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reg_PMIC_WRAP.h

reg_PMIC_WRAP.h 19 KB
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  1. /* Copyright Statement:
    2. 

  2.  *
    3. 

  3.  * This software/firmware and related documentation ("MediaTek Software") are
    4. 

  4.  * protected under relevant copyright laws. The information contained herein is
    5. 

  5.  * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
    6. 

  6.  * the prior written permission of MediaTek inc. and/or its licensors, any
    7. 

  7.  * reproduction, modification, use or disclosure of MediaTek Software, and
    8. 

  8.  * information contained herein, in whole or in part, shall be strictly
    9. 

  9.  * prohibited.
    10. 

  10.  *
    11. 

  11.  * MediaTek Inc. (C) 2016. All rights reserved.
    12. 

  12.  *
    13. 

  13.  * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
    14. 

  14.  * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
    15. 

  15.  * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
    16. 

  16.  * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
    17. 

  17.  * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
    18. 

  18.  * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
    19. 

  19.  * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
    20. 

  20.  * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
    21. 

  21.  * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
    22. 

  22.  * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
    23. 

  23.  * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
    24. 

  24.  * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
    25. 

  25.  * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
    26. 

  26.  * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
    27. 

  27.  * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
    28. 

  28.  * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
    29. 

  29.  * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
    30. 

  30.  * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
    31. 

  31.  * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
    32. 

  32.  *
    33. 

  33.  * The following software/firmware and/or related documentation ("MediaTek
    34. 

  34.  * Software") have been modified by MediaTek Inc. All revisions are subject to
    35. 

  35.  * any receiver's applicable license agreements with MediaTek Inc.
    36. 

  36.  */
    37. 

  37. #ifndef __PMIC_WRAP_REGS_H__
    38. 

  38. #define __PMIC_WRAP_REGS_H__
    39. 

  39. 

  40. #define PMIC_WRAP_MUX_SEL	((UINT32P)(PMIC_WRAP_BASE+0x0))
    41. 

  41. #define PMIC_WRAP_WRAP_EN	((UINT32P)(PMIC_WRAP_BASE+0x4))
    42. 

  42. #define PMIC_WRAP_DIO_EN	((UINT32P)(PMIC_WRAP_BASE+0x8))
    43. 

  43. #define PMIC_WRAP_SI_SAMPLE_CTRL	((UINT32P)(PMIC_WRAP_BASE+0xC))
    44. 

  44. #define PMIC_WRAP_SI_SAMPLE_CTRL_ULPOSC	((UINT32P)(PMIC_WRAP_BASE+0x10))
    45. 

  45. #define PMIC_WRAP_RDDMY	((UINT32P)(PMIC_WRAP_BASE+0x14))
    46. 

  46. #define PMIC_WRAP_CSHEXT_WRITE	((UINT32P)(PMIC_WRAP_BASE+0x18))
    47. 

  47. #define PMIC_WRAP_CSHEXT_READ	((UINT32P)(PMIC_WRAP_BASE+0x1C))
    48. 

  48. #define PMIC_WRAP_CSLEXT_WRITE	((UINT32P)(PMIC_WRAP_BASE+0x20))
    49. 

  49. #define PMIC_WRAP_CSLEXT_READ	((UINT32P)(PMIC_WRAP_BASE+0x24))
    50. 

  50. #define PMIC_WRAP_EXT_CK_WRITE	((UINT32P)(PMIC_WRAP_BASE+0x28))
    51. 

  51. #define PMIC_WRAP_EXT_CK_READ	((UINT32P)(PMIC_WRAP_BASE+0x2C))
    52. 

  52. #define PMIC_WRAP_STAUPD_CTRL	((UINT32P)(PMIC_WRAP_BASE+0x30))
    53. 

  53. #define PMIC_WRAP_STAUPD_GRPEN	((UINT32P)(PMIC_WRAP_BASE+0x34))
    54. 

  54. #define PMIC_WRAP_EINT_STA0_ADR	((UINT32P)(PMIC_WRAP_BASE+0x38))
    55. 

  55. #define PMIC_WRAP_EINT_STA1_ADR	((UINT32P)(PMIC_WRAP_BASE+0x3C))
    56. 

  56. #define PMIC_WRAP_EINT_STA	((UINT32P)(PMIC_WRAP_BASE+0x40))
    57. 

  57. #define PMIC_WRAP_EINT_CLR	((UINT32P)(PMIC_WRAP_BASE+0x44))
    58. 

  58. #define PMIC_WRAP_EINT_CTRL	((UINT32P)(PMIC_WRAP_BASE+0x48))
    59. 

  59. #define PMIC_WRAP_STAUPD_MAN_TRIG	((UINT32P)(PMIC_WRAP_BASE+0x4C))
    60. 

  60. #define PMIC_WRAP_STAUPD_STA	((UINT32P)(PMIC_WRAP_BASE+0x50))
    61. 

  61. #define PMIC_WRAP_WRAP_STA	((UINT32P)(PMIC_WRAP_BASE+0x54))
    62. 

  62. #define PMIC_WRAP_HARB_INIT	((UINT32P)(PMIC_WRAP_BASE+0x58))
    63. 

  63. #define PMIC_WRAP_HARB_HPRIO	((UINT32P)(PMIC_WRAP_BASE+0x5C))
    64. 

  64. #define PMIC_WRAP_HPRIO_ARB_EN	((UINT32P)(PMIC_WRAP_BASE+0x60))
    65. 

  65. #define PMIC_WRAP_HARB_STA0	((UINT32P)(PMIC_WRAP_BASE+0x64))
    66. 

  66. #define PMIC_WRAP_HARB_STA1	((UINT32P)(PMIC_WRAP_BASE+0x68))
    67. 

  67. #define PMIC_WRAP_HARB_STA2	((UINT32P)(PMIC_WRAP_BASE+0x6C))
    68. 

  68. #define PMIC_WRAP_MAN_EN	((UINT32P)(PMIC_WRAP_BASE+0x70))
    69. 

  69. #define PMIC_WRAP_MAN_CMD	((UINT32P)(PMIC_WRAP_BASE+0x74))
    70. 

  70. #define PMIC_WRAP_MAN_RDATA	((UINT32P)(PMIC_WRAP_BASE+0x78))
    71. 

  71. #define PMIC_WRAP_MAN_VLDCLR	((UINT32P)(PMIC_WRAP_BASE+0x7C))
    72. 

  72. #define PMIC_WRAP_WACS0_EN	((UINT32P)(PMIC_WRAP_BASE+0x80))
    73. 

  73. #define PMIC_WRAP_INIT_DONE0	((UINT32P)(PMIC_WRAP_BASE+0x84))
    74. 

  74. #define PMIC_WRAP_WACS1_EN	((UINT32P)(PMIC_WRAP_BASE+0x88))
    75. 

  75. #define PMIC_WRAP_INIT_DONE1	((UINT32P)(PMIC_WRAP_BASE+0x8C))
    76. 

  76. #define PMIC_WRAP_WACS2_EN	((UINT32P)(PMIC_WRAP_BASE+0x90))
    77. 

  77. #define PMIC_WRAP_INIT_DONE2	((UINT32P)(PMIC_WRAP_BASE+0x94))
    78. 

  78. #define PMIC_WRAP_WACS3_EN	((UINT32P)(PMIC_WRAP_BASE+0x98))
    79. 

  79. #define PMIC_WRAP_INIT_DONE3	((UINT32P)(PMIC_WRAP_BASE+0x9C))
    80. 

  80. #define PMIC_WRAP_WACS_P2P_EN	((UINT32P)(PMIC_WRAP_BASE+0xA0))
    81. 

  81. #define PMIC_WRAP_INIT_DONE_P2P	((UINT32P)(PMIC_WRAP_BASE+0xA4))
    82. 

  82. #define PMIC_WRAP_WACS_MD32_EN	((UINT32P)(PMIC_WRAP_BASE+0xA8))
    83. 

  83. #define PMIC_WRAP_INIT_DONE_MD32	((UINT32P)(PMIC_WRAP_BASE+0xAC))
    84. 

  84. #define PMIC_WRAP_INT0_EN	((UINT32P)(PMIC_WRAP_BASE+0xB0))
    85. 

  85. #define PMIC_WRAP_INT0_FLG_RAW	((UINT32P)(PMIC_WRAP_BASE+0xB4))
    86. 

  86. #define PMIC_WRAP_INT0_FLG	((UINT32P)(PMIC_WRAP_BASE+0xB8))
    87. 

  87. #define PMIC_WRAP_INT0_CLR	((UINT32P)(PMIC_WRAP_BASE+0xBC))
    88. 

  88. #define PMIC_WRAP_INT1_EN	((UINT32P)(PMIC_WRAP_BASE+0xC0))
    89. 

  89. #define PMIC_WRAP_INT1_FLG_RAW	((UINT32P)(PMIC_WRAP_BASE+0xC4))
    90. 

  90. #define PMIC_WRAP_INT1_FLG	((UINT32P)(PMIC_WRAP_BASE+0xC8))
    91. 

  91. #define PMIC_WRAP_INT1_CLR	((UINT32P)(PMIC_WRAP_BASE+0xCC))
    92. 

  92. #define PMIC_WRAP_SIG_ADR	((UINT32P)(PMIC_WRAP_BASE+0xD0))
    93. 

  93. #define PMIC_WRAP_SIG_MODE	((UINT32P)(PMIC_WRAP_BASE+0xD4))
    94. 

  94. #define PMIC_WRAP_SIG_VALUE	((UINT32P)(PMIC_WRAP_BASE+0xD8))
    95. 

  95. #define PMIC_WRAP_SIG_ERRVAL	((UINT32P)(PMIC_WRAP_BASE+0xDC))
    96. 

  96. #define PMIC_WRAP_CRC_EN	((UINT32P)(PMIC_WRAP_BASE+0xE0))
    97. 

  97. #define PMIC_WRAP_TIMER_EN	((UINT32P)(PMIC_WRAP_BASE+0xE4))
    98. 

  98. #define PMIC_WRAP_TIMER_STA	((UINT32P)(PMIC_WRAP_BASE+0xE8))
    99. 

  99. #define PMIC_WRAP_WDT_UNIT	((UINT32P)(PMIC_WRAP_BASE+0xEC))
    100. 

  100. #define PMIC_WRAP_WDT_SRC_EN_0	((UINT32P)(PMIC_WRAP_BASE+0xF0))
    101. 

  101. #define PMIC_WRAP_WDT_SRC_EN_1	((UINT32P)(PMIC_WRAP_BASE+0xF4))
    102. 

  102. #define PMIC_WRAP_WDT_FLG_0	((UINT32P)(PMIC_WRAP_BASE+0xF8))
    103. 

  103. #define PMIC_WRAP_WDT_FLG_1	((UINT32P)(PMIC_WRAP_BASE+0xFC))
    104. 

  104. #define PMIC_WRAP_DEBUG_INT_SEL	((UINT32P)(PMIC_WRAP_BASE+0x100))
    105. 

  105. #define PMIC_WRAP_DVFS_ADR0	((UINT32P)(PMIC_WRAP_BASE+0x104))
    106. 

  106. #define PMIC_WRAP_DVFS_WDATA0	((UINT32P)(PMIC_WRAP_BASE+0x108))
    107. 

  107. #define PMIC_WRAP_DVFS_ADR1	((UINT32P)(PMIC_WRAP_BASE+0x10C))
    108. 

  108. #define PMIC_WRAP_DVFS_WDATA1	((UINT32P)(PMIC_WRAP_BASE+0x110))
    109. 

  109. #define PMIC_WRAP_DVFS_ADR2	((UINT32P)(PMIC_WRAP_BASE+0x114))
    110. 

  110. #define PMIC_WRAP_DVFS_WDATA2	((UINT32P)(PMIC_WRAP_BASE+0x118))
    111. 

  111. #define PMIC_WRAP_DVFS_ADR3	((UINT32P)(PMIC_WRAP_BASE+0x11C))
    112. 

  112. #define PMIC_WRAP_DVFS_WDATA3	((UINT32P)(PMIC_WRAP_BASE+0x120))
    113. 

  113. #define PMIC_WRAP_DVFS_ADR4	((UINT32P)(PMIC_WRAP_BASE+0x124))
    114. 

  114. #define PMIC_WRAP_DVFS_WDATA4	((UINT32P)(PMIC_WRAP_BASE+0x128))
    115. 

  115. #define PMIC_WRAP_DVFS_ADR5	((UINT32P)(PMIC_WRAP_BASE+0x12C))
    116. 

  116. #define PMIC_WRAP_DVFS_WDATA5	((UINT32P)(PMIC_WRAP_BASE+0x130))
    117. 

  117. #define PMIC_WRAP_DVFS_ADR6	((UINT32P)(PMIC_WRAP_BASE+0x134))
    118. 

  118. #define PMIC_WRAP_DVFS_WDATA6	((UINT32P)(PMIC_WRAP_BASE+0x138))
    119. 

  119. #define PMIC_WRAP_DVFS_ADR7	((UINT32P)(PMIC_WRAP_BASE+0x13C))
    120. 

  120. #define PMIC_WRAP_DVFS_WDATA7	((UINT32P)(PMIC_WRAP_BASE+0x140))
    121. 

  121. #define PMIC_WRAP_DVFS_ADR8	((UINT32P)(PMIC_WRAP_BASE+0x144))
    122. 

  122. #define PMIC_WRAP_DVFS_WDATA8	((UINT32P)(PMIC_WRAP_BASE+0x148))
    123. 

  123. #define PMIC_WRAP_DVFS_ADR9	((UINT32P)(PMIC_WRAP_BASE+0x14C))
    124. 

  124. #define PMIC_WRAP_DVFS_WDATA9	((UINT32P)(PMIC_WRAP_BASE+0x150))
    125. 

  125. #define PMIC_WRAP_DVFS_ADR10	((UINT32P)(PMIC_WRAP_BASE+0x154))
    126. 

  126. #define PMIC_WRAP_DVFS_WDATA10	((UINT32P)(PMIC_WRAP_BASE+0x158))
    127. 

  127. #define PMIC_WRAP_DVFS_ADR11	((UINT32P)(PMIC_WRAP_BASE+0x15C))
    128. 

  128. #define PMIC_WRAP_DVFS_WDATA11	((UINT32P)(PMIC_WRAP_BASE+0x160))
    129. 

  129. #define PMIC_WRAP_DVFS_ADR12	((UINT32P)(PMIC_WRAP_BASE+0x164))
    130. 

  130. #define PMIC_WRAP_DVFS_WDATA12	((UINT32P)(PMIC_WRAP_BASE+0x168))
    131. 

  131. #define PMIC_WRAP_DVFS_ADR13	((UINT32P)(PMIC_WRAP_BASE+0x16C))
    132. 

  132. #define PMIC_WRAP_DVFS_WDATA13	((UINT32P)(PMIC_WRAP_BASE+0x170))
    133. 

  133. #define PMIC_WRAP_DVFS_ADR14	((UINT32P)(PMIC_WRAP_BASE+0x174))
    134. 

  134. #define PMIC_WRAP_DVFS_WDATA14	((UINT32P)(PMIC_WRAP_BASE+0x178))
    135. 

  135. #define PMIC_WRAP_DVFS_ADR15	((UINT32P)(PMIC_WRAP_BASE+0x17C))
    136. 

  136. #define PMIC_WRAP_DVFS_WDATA15	((UINT32P)(PMIC_WRAP_BASE+0x180))
    137. 

  137. #define PMIC_WRAP_DCXO_ENABLE	((UINT32P)(PMIC_WRAP_BASE+0x184))
    138. 

  138. #define PMIC_WRAP_DCXO_CONN_ADR0	((UINT32P)(PMIC_WRAP_BASE+0x188))
    139. 

  139. #define PMIC_WRAP_DCXO_CONN_WDATA0	((UINT32P)(PMIC_WRAP_BASE+0x18C))
    140. 

  140. #define PMIC_WRAP_DCXO_CONN_ADR1	((UINT32P)(PMIC_WRAP_BASE+0x190))
    141. 

  141. #define PMIC_WRAP_DCXO_CONN_WDATA1	((UINT32P)(PMIC_WRAP_BASE+0x194))
    142. 

  142. #define PMIC_WRAP_DCXO_NFC_ADR0	((UINT32P)(PMIC_WRAP_BASE+0x198))
    143. 

  143. #define PMIC_WRAP_DCXO_NFC_WDATA0	((UINT32P)(PMIC_WRAP_BASE+0x19C))
    144. 

  144. #define PMIC_WRAP_DCXO_NFC_ADR1	((UINT32P)(PMIC_WRAP_BASE+0x1A0))
    145. 

  145. #define PMIC_WRAP_DCXO_NFC_WDATA1	((UINT32P)(PMIC_WRAP_BASE+0x1A4))
    146. 

  146. #define PMIC_WRAP_SPMINF_STA_0	((UINT32P)(PMIC_WRAP_BASE+0x1A8))
    147. 

  147. #define PMIC_WRAP_SPMINF_STA_1	((UINT32P)(PMIC_WRAP_BASE+0x1AC))
    148. 

  148. #define PMIC_WRAP_SPMINF_BACKUP_STA	((UINT32P)(PMIC_WRAP_BASE+0x1B0))
    149. 

  149. #define PMIC_WRAP_SCPINF_STA	((UINT32P)(PMIC_WRAP_BASE+0x1B4))
    150. 

  150. #define PMIC_WRAP_CIPHER_KEY_SEL	((UINT32P)(PMIC_WRAP_BASE+0x1B8))
    151. 

  151. #define PMIC_WRAP_CIPHER_IV_SEL	((UINT32P)(PMIC_WRAP_BASE+0x1BC))
    152. 

  152. #define PMIC_WRAP_CIPHER_EN	((UINT32P)(PMIC_WRAP_BASE+0x1C0))
    153. 

  153. #define PMIC_WRAP_CIPHER_RDY	((UINT32P)(PMIC_WRAP_BASE+0x1C4))
    154. 

  154. #define PMIC_WRAP_CIPHER_MODE	((UINT32P)(PMIC_WRAP_BASE+0x1C8))
    155. 

  155. #define PMIC_WRAP_CIPHER_SWRST	((UINT32P)(PMIC_WRAP_BASE+0x1CC))
    156. 

  156. #define PMIC_WRAP_DCM_EN	((UINT32P)(PMIC_WRAP_BASE+0x1D0))
    157. 

  157. #define PMIC_WRAP_DCM_SPI_DBC_PRD	((UINT32P)(PMIC_WRAP_BASE+0x1D4))
    158. 

  158. #define PMIC_WRAP_DCM_DBC_PRD	((UINT32P)(PMIC_WRAP_BASE+0x1D8))
    159. 

  159. #define PMIC_WRAP_INT_GPS_AUXADC_CMD_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x1DC))
    160. 

  160. #define PMIC_WRAP_INT_GPS_AUXADC_CMD	((UINT32P)(PMIC_WRAP_BASE+0x1E0))
    161. 

  161. #define PMIC_WRAP_INT_GPS_AUXADC_RDATA_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x1E4))
    162. 

  162. #define PMIC_WRAP_EXT_GPS_AUXADC_RDATA_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x1E8))
    163. 

  163. #define PMIC_WRAP_GPSINF_0_STA	((UINT32P)(PMIC_WRAP_BASE+0x1EC))
    164. 

  164. #define PMIC_WRAP_GPSINF_1_STA	((UINT32P)(PMIC_WRAP_BASE+0x1F0))
    165. 

  165. #define PMIC_WRAP_MD_ADCINF_CTRL	((UINT32P)(PMIC_WRAP_BASE+0x1F4))
    166. 

  166. #define PMIC_WRAP_MD_AUXADC_RDATA_LATEST_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x1F8))
    167. 

  167. #define PMIC_WRAP_MD_AUXADC_RDATA_WP_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x1FC))
    168. 

  168. #define PMIC_WRAP_MD_AUXADC_RDATA_0_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x200))
    169. 

  169. #define PMIC_WRAP_MD_AUXADC_RDATA_1_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x204))
    170. 

  170. #define PMIC_WRAP_MD_AUXADC_RDATA_2_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x208))
    171. 

  171. #define PMIC_WRAP_MD_AUXADC_RDATA_3_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x20C))
    172. 

  172. #define PMIC_WRAP_MD_AUXADC_RDATA_4_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x210))
    173. 

  173. #define PMIC_WRAP_MD_AUXADC_RDATA_5_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x214))
    174. 

  174. #define PMIC_WRAP_MD_AUXADC_RDATA_6_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x218))
    175. 

  175. #define PMIC_WRAP_MD_AUXADC_RDATA_7_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x21C))
    176. 

  176. #define PMIC_WRAP_MD_AUXADC_RDATA_8_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x220))
    177. 

  177. #define PMIC_WRAP_MD_AUXADC_RDATA_9_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x224))
    178. 

  178. #define PMIC_WRAP_MD_AUXADC_RDATA_10_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x228))
    179. 

  179. #define PMIC_WRAP_MD_AUXADC_RDATA_11_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x22C))
    180. 

  180. #define PMIC_WRAP_MD_AUXADC_RDATA_12_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x230))
    181. 

  181. #define PMIC_WRAP_MD_AUXADC_RDATA_13_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x234))
    182. 

  182. #define PMIC_WRAP_MD_AUXADC_RDATA_14_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x238))
    183. 

  183. #define PMIC_WRAP_MD_AUXADC_RDATA_15_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x23C))
    184. 

  184. #define PMIC_WRAP_MD_AUXADC_RDATA_16_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x240))
    185. 

  185. #define PMIC_WRAP_MD_AUXADC_RDATA_17_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x244))
    186. 

  186. #define PMIC_WRAP_MD_AUXADC_RDATA_18_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x248))
    187. 

  187. #define PMIC_WRAP_MD_AUXADC_RDATA_19_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x24C))
    188. 

  188. #define PMIC_WRAP_MD_AUXADC_RDATA_20_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x250))
    189. 

  189. #define PMIC_WRAP_MD_AUXADC_RDATA_21_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x254))
    190. 

  190. #define PMIC_WRAP_MD_AUXADC_RDATA_22_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x258))
    191. 

  191. #define PMIC_WRAP_MD_AUXADC_RDATA_23_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x25C))
    192. 

  192. #define PMIC_WRAP_MD_AUXADC_RDATA_24_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x260))
    193. 

  193. #define PMIC_WRAP_MD_AUXADC_RDATA_25_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x264))
    194. 

  194. #define PMIC_WRAP_MD_AUXADC_RDATA_26_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x268))
    195. 

  195. #define PMIC_WRAP_MD_AUXADC_RDATA_27_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x26C))
    196. 

  196. #define PMIC_WRAP_MD_AUXADC_RDATA_28_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x270))
    197. 

  197. #define PMIC_WRAP_MD_AUXADC_RDATA_29_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x274))
    198. 

  198. #define PMIC_WRAP_MD_AUXADC_RDATA_30_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x278))
    199. 

  199. #define PMIC_WRAP_MD_AUXADC_RDATA_31_ADDR	((UINT32P)(PMIC_WRAP_BASE+0x27C))
    200. 

  200. #define PMIC_WRAP_MD_ADCINF_0_STA_0	((UINT32P)(PMIC_WRAP_BASE+0x280))
    201. 

  201. #define PMIC_WRAP_MD_ADCINF_0_STA_1	((UINT32P)(PMIC_WRAP_BASE+0x284))
    202. 

  202. #define PMIC_WRAP_MD_ADCINF_1_STA_0	((UINT32P)(PMIC_WRAP_BASE+0x288))
    203. 

  203. #define PMIC_WRAP_MD_ADCINF_1_STA_1	((UINT32P)(PMIC_WRAP_BASE+0x28C))
    204. 

  204. #define PMIC_WRAP_SWRST	((UINT32P)(PMIC_WRAP_BASE+0x290))
    205. 

  205. #define PMIC_WRAP_SPM_SLEEP_GATING_CTRL	((UINT32P)(PMIC_WRAP_BASE+0x294))
    206. 

  206. #define PMIC_WRAP_SCP_SLEEP_GATING_CTRL	((UINT32P)(PMIC_WRAP_BASE+0x298))
    207. 

  207. #define PMIC_WRAP_PRIORITY_USER_SEL_0	((UINT32P)(PMIC_WRAP_BASE+0x29C))
    208. 

  208. #define PMIC_WRAP_PRIORITY_USER_SEL_1	((UINT32P)(PMIC_WRAP_BASE+0x2A0))
    209. 

  209. #define PMIC_WRAP_PRIORITY_USER_SEL_2	((UINT32P)(PMIC_WRAP_BASE+0x2A4))
    210. 

  210. #define PMIC_WRAP_PRIORITY_USER_SEL_3	((UINT32P)(PMIC_WRAP_BASE+0x2A8))
    211. 

  211. #define PMIC_WRAP_PRIORITY_USER_SEL_4	((UINT32P)(PMIC_WRAP_BASE+0x2AC))
    212. 

  212. #define PMIC_WRAP_ARBITER_OUT_SEL_0	((UINT32P)(PMIC_WRAP_BASE+0x2B0))
    213. 

  213. #define PMIC_WRAP_ARBITER_OUT_SEL_1	((UINT32P)(PMIC_WRAP_BASE+0x2B4))
    214. 

  214. #define PMIC_WRAP_ARBITER_OUT_SEL_2	((UINT32P)(PMIC_WRAP_BASE+0x2B8))
    215. 

  215. #define PMIC_WRAP_ARBITER_OUT_SEL_3	((UINT32P)(PMIC_WRAP_BASE+0x2BC))
    216. 

  216. #define PMIC_WRAP_ARBITER_OUT_SEL_4	((UINT32P)(PMIC_WRAP_BASE+0x2C0))
    217. 

  217. #define PMIC_WRAP_STARV_COUNTER_0	((UINT32P)(PMIC_WRAP_BASE+0x2C4))
    218. 

  218. #define PMIC_WRAP_STARV_COUNTER_1	((UINT32P)(PMIC_WRAP_BASE+0x2C8))
    219. 

  219. #define PMIC_WRAP_STARV_COUNTER_2	((UINT32P)(PMIC_WRAP_BASE+0x2CC))
    220. 

  220. #define PMIC_WRAP_STARV_COUNTER_3	((UINT32P)(PMIC_WRAP_BASE+0x2D0))
    221. 

  221. #define PMIC_WRAP_STARV_COUNTER_4	((UINT32P)(PMIC_WRAP_BASE+0x2D4))
    222. 

  222. #define PMIC_WRAP_STARV_COUNTER_5	((UINT32P)(PMIC_WRAP_BASE+0x2D8))
    223. 

  223. #define PMIC_WRAP_STARV_COUNTER_6	((UINT32P)(PMIC_WRAP_BASE+0x2DC))
    224. 

  224. #define PMIC_WRAP_STARV_COUNTER_7	((UINT32P)(PMIC_WRAP_BASE+0x2E0))
    225. 

  225. #define PMIC_WRAP_STARV_COUNTER_8	((UINT32P)(PMIC_WRAP_BASE+0x2E4))
    226. 

  226. #define PMIC_WRAP_STARV_COUNTER_9	((UINT32P)(PMIC_WRAP_BASE+0x2E8))
    227. 

  227. #define PMIC_WRAP_STARV_COUNTER_10	((UINT32P)(PMIC_WRAP_BASE+0x2EC))
    228. 

  228. #define PMIC_WRAP_STARV_COUNTER_11	((UINT32P)(PMIC_WRAP_BASE+0x2F0))
    229. 

  229. #define PMIC_WRAP_STARV_COUNTER_12	((UINT32P)(PMIC_WRAP_BASE+0x2F4))
    230. 

  230. #define PMIC_WRAP_STARV_COUNTER_13	((UINT32P)(PMIC_WRAP_BASE+0x2F8))
    231. 

  231. #define PMIC_WRAP_STARV_COUNTER_14	((UINT32P)(PMIC_WRAP_BASE+0x2FC))
    232. 

  232. #define PMIC_WRAP_STARV_COUNTER_15	((UINT32P)(PMIC_WRAP_BASE+0x300))
    233. 

  233. #define PMIC_WRAP_STARV_COUNTER_16	((UINT32P)(PMIC_WRAP_BASE+0x304))
    234. 

  234. #define PMIC_WRAP_STARV_COUNTER_0_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x308))
    235. 

  235. #define PMIC_WRAP_STARV_COUNTER_1_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x30C))
    236. 

  236. #define PMIC_WRAP_STARV_COUNTER_2_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x310))
    237. 

  237. #define PMIC_WRAP_STARV_COUNTER_3_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x314))
    238. 

  238. #define PMIC_WRAP_STARV_COUNTER_4_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x318))
    239. 

  239. #define PMIC_WRAP_STARV_COUNTER_5_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x31C))
    240. 

  240. #define PMIC_WRAP_STARV_COUNTER_6_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x320))
    241. 

  241. #define PMIC_WRAP_STARV_COUNTER_7_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x324))
    242. 

  242. #define PMIC_WRAP_STARV_COUNTER_8_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x328))
    243. 

  243. #define PMIC_WRAP_STARV_COUNTER_9_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x32C))
    244. 

  244. #define PMIC_WRAP_STARV_COUNTER_10_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x330))
    245. 

  245. #define PMIC_WRAP_STARV_COUNTER_11_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x334))
    246. 

  246. #define PMIC_WRAP_STARV_COUNTER_12_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x338))
    247. 

  247. #define PMIC_WRAP_STARV_COUNTER_13_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x33C))
    248. 

  248. #define PMIC_WRAP_STARV_COUNTER_14_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x340))
    249. 

  249. #define PMIC_WRAP_STARV_COUNTER_15_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x344))
    250. 

  250. #define PMIC_WRAP_STARV_COUNTER_16_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x348))
    251. 

  251. #define PMIC_WRAP_STARV_COUNTER_CLR	((UINT32P)(PMIC_WRAP_BASE+0x34C))
    252. 

  252. #define PMIC_WRAP_STARV_PRIO_STATUS	((UINT32P)(PMIC_WRAP_BASE+0x350))
    253. 

  253. #define PMIC_WRAP_MONITOR_CTRL_0	((UINT32P)(PMIC_WRAP_BASE+0x354))
    254. 

  254. #define PMIC_WRAP_MONITOR_CTRL_1	((UINT32P)(PMIC_WRAP_BASE+0x358))
    255. 

  255. #define PMIC_WRAP_MONITOR_CTRL_2	((UINT32P)(PMIC_WRAP_BASE+0x35C))
    256. 

  256. #define PMIC_WRAP_MONITOR_CTRL_3	((UINT32P)(PMIC_WRAP_BASE+0x360))
    257. 

  257. #define PMIC_WRAP_CHANNEL_SEQUENCE_0	((UINT32P)(PMIC_WRAP_BASE+0x364))
    258. 

  258. #define PMIC_WRAP_CHANNEL_SEQUENCE_1	((UINT32P)(PMIC_WRAP_BASE+0x368))
    259. 

  259. #define PMIC_WRAP_CHANNEL_SEQUENCE_2	((UINT32P)(PMIC_WRAP_BASE+0x36C))
    260. 

  260. #define PMIC_WRAP_CHANNEL_SEQUENCE_3	((UINT32P)(PMIC_WRAP_BASE+0x370))
    261. 

  261. #define PMIC_WRAP_CMD_SEQUENCE_0	((UINT32P)(PMIC_WRAP_BASE+0x374))
    262. 

  262. #define PMIC_WRAP_CMD_SEQUENCE_1	((UINT32P)(PMIC_WRAP_BASE+0x378))
    263. 

  263. #define PMIC_WRAP_CMD_SEQUENCE_2	((UINT32P)(PMIC_WRAP_BASE+0x37C))
    264. 

  264. #define PMIC_WRAP_CMD_SEQUENCE_3	((UINT32P)(PMIC_WRAP_BASE+0x380))
    265. 

  265. #define PMIC_WRAP_CMD_SEQUENCE_4	((UINT32P)(PMIC_WRAP_BASE+0x384))
    266. 

  266. #define PMIC_WRAP_CMD_SEQUENCE_5	((UINT32P)(PMIC_WRAP_BASE+0x388))
    267. 

  267. #define PMIC_WRAP_CMD_SEQUENCE_6	((UINT32P)(PMIC_WRAP_BASE+0x38C))
    268. 

  268. #define PMIC_WRAP_CMD_SEQUENCE_7	((UINT32P)(PMIC_WRAP_BASE+0x390))
    269. 

  269. #define PMIC_WRAP_WDATA_SEQUENCE_0	((UINT32P)(PMIC_WRAP_BASE+0x394))
    270. 

  270. #define PMIC_WRAP_WDATA_SEQUENCE_1	((UINT32P)(PMIC_WRAP_BASE+0x398))
    271. 

  271. #define PMIC_WRAP_WDATA_SEQUENCE_2	((UINT32P)(PMIC_WRAP_BASE+0x39C))
    272. 

  272. #define PMIC_WRAP_WDATA_SEQUENCE_3	((UINT32P)(PMIC_WRAP_BASE+0x3A0))
    273. 

  273. #define PMIC_WRAP_WDATA_SEQUENCE_4	((UINT32P)(PMIC_WRAP_BASE+0x3A4))
    274. 

  274. #define PMIC_WRAP_WDATA_SEQUENCE_5	((UINT32P)(PMIC_WRAP_BASE+0x3A8))
    275. 

  275. #define PMIC_WRAP_WDATA_SEQUENCE_6	((UINT32P)(PMIC_WRAP_BASE+0x3AC))
    276. 

  276. #define PMIC_WRAP_WDATA_SEQUENCE_7	((UINT32P)(PMIC_WRAP_BASE+0x3B0))
    277. 

  277. #define PMIC_WRAP_DEBUG_SW_DRIVER_0	((UINT32P)(PMIC_WRAP_BASE+0x3B4))
    278. 

  278. #define PMIC_WRAP_DEBUG_SW_DRIVER_1	((UINT32P)(PMIC_WRAP_BASE+0x3B8))
    279. 

  279. #define PMIC_WRAP_DEBUG_SW_DRIVER_2	((UINT32P)(PMIC_WRAP_BASE+0x3BC))
    280. 

  280. #define PMIC_WRAP_DEBUG_SW_DRIVER_3	((UINT32P)(PMIC_WRAP_BASE+0x3C0))
    281. 

  281. #define PMIC_WRAP_DEBUG_SW_DRIVER_4	((UINT32P)(PMIC_WRAP_BASE+0x3C4))
    282. 

  282. #define PMIC_WRAP_DEBUG_SW_DRIVER_5	((UINT32P)(PMIC_WRAP_BASE+0x3C8))
    283. 

  283. #define PMIC_WRAP_BWC_OPTIONS	((UINT32P)(PMIC_WRAP_BASE+0x3CC))
    284. 

  284. #define PMIC_WRAP_RESERVED	((UINT32P)(PMIC_WRAP_BASE+0x3D0))
    285. 

  285. #define PMIC_WRAP_WACS0_CMD	((UINT32P)(PMIC_WRAP_BASE+0xC00))
    286. 

  286. #define PMIC_WRAP_WACS0_RDATA	((UINT32P)(PMIC_WRAP_BASE+0xC04))
    287. 

  287. #define PMIC_WRAP_WACS0_VLDCLR	((UINT32P)(PMIC_WRAP_BASE+0xC08))
    288. 

  288. #define PMIC_WRAP_WACS1_CMD	((UINT32P)(PMIC_WRAP_BASE+0xC10))
    289. 

  289. #define PMIC_WRAP_WACS1_RDATA	((UINT32P)(PMIC_WRAP_BASE+0xC14))
    290. 

  290. #define PMIC_WRAP_WACS1_VLDCLR	((UINT32P)(PMIC_WRAP_BASE+0xC18))
    291. 

  291. #define PMIC_WRAP_WACS2_CMD	((UINT32P)(PMIC_WRAP_BASE+0xC20))
    292. 

  292. #define PMIC_WRAP_WACS2_RDATA	((UINT32P)(PMIC_WRAP_BASE+0xC24))
    293. 

  293. #define PMIC_WRAP_WACS2_VLDCLR	((UINT32P)(PMIC_WRAP_BASE+0xC28))
    294. 

  294. #define PMIC_WRAP_WACS3_CMD	((UINT32P)(PMIC_WRAP_BASE+0xC30))
    295. 

  295. #define PMIC_WRAP_WACS3_RDATA	((UINT32P)(PMIC_WRAP_BASE+0xC34))
    296. 

  296. #define PMIC_WRAP_WACS3_VLDCLR	((UINT32P)(PMIC_WRAP_BASE+0xC38))
    297. 

  297. 

  298. #endif //__PMIC_WRAP_REGS_H__
    299. 

  299.