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ddp_reg_pq.h

ddp_reg_pq.h 22 KB
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  1. /* Copyright Statement:
    2. 

  2. *
    3. 

  3. * This software/firmware and related documentation ("MediaTek Software") are
    4. 

  4. * protected under relevant copyright laws. The information contained herein
    5. 

  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
    6. 

  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
    7. 

  7. * any reproduction, modification, use or disclosure of MediaTek Software,
    8. 

  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
    9. 

  9. */
    10. 

  10. /* MediaTek Inc. (C) 2015. All rights reserved.
    11. 

  11. *
    12. 

  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
    13. 

  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
    14. 

  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
    15. 

  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
    16. 

  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
    17. 

  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
    18. 

  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
    19. 

  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
    20. 

  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
    21. 

  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
    22. 

  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
    23. 

  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
    24. 

  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
    25. 

  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
    26. 

  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
    27. 

  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
    28. 

  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
    29. 

  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
    30. 

  30. */
    31. 

  31. 

  32. 

  33. #ifndef _DDP_REG_PQ_H_
    34. 

  34. #define _DDP_REG_PQ_H_
    35. 

  35. 

  36. /*******************************/
    37. 

  37. /* field definition */
    38. 

  38. /* ------------------------------------------------------------- */
    39. 

  39. /* AAL */
    40. 

  40. #define DISP_AAL_EN                             (DISPSYS_AAL0_BASE + 0x000)
    41. 

  41. #define DISP_AAL_RESET                          (DISPSYS_AAL0_BASE + 0x004)
    42. 

  42. #define DISP_AAL_INTEN                          (DISPSYS_AAL0_BASE + 0x008)
    43. 

  43. #define DISP_AAL_INTSTA                         (DISPSYS_AAL0_BASE + 0x00c)
    44. 

  44. #define DISP_AAL_STATUS                         (DISPSYS_AAL0_BASE + 0x010)
    45. 

  45. #define DISP_AAL_CFG                            (DISPSYS_AAL0_BASE + 0x020)
    46. 

  46. #define DISP_AAL_IN_CNT                         (DISPSYS_AAL0_BASE + 0x024)
    47. 

  47. #define DISP_AAL_OUT_CNT                        (DISPSYS_AAL0_BASE + 0x028)
    48. 

  48. #define DISP_AAL_CHKSUM                         (DISPSYS_AAL0_BASE + 0x02c)
    49. 

  49. #define DISP_AAL_SIZE                           (DISPSYS_AAL0_BASE + 0x030)
    50. 

  50. #define DISP_AAL_SHADOW_CTL                     (DISPSYS_AAL0_BASE + 0x0B0)
    51. 

  51. #define DISP_AAL_DUMMY_REG                      (DISPSYS_AAL0_BASE + 0x0c0)
    52. 

  52. #define DISP_AAL_MAX_HIST_CONFIG_00             (DISPSYS_AAL0_BASE + 0x204)
    53. 

  53. #define DISP_AAL_CABC_00                        (DISPSYS_AAL0_BASE + 0x20c)
    54. 

  54. #define DISP_AAL_CABC_02                        (DISPSYS_AAL0_BASE + 0x214)
    55. 

  55. #define DISP_AAL_CABC_04                        (DISPSYS_AAL0_BASE + 0x21c)
    56. 

  56. #define DISP_AAL_STATUS_00                      (DISPSYS_AAL0_BASE + 0x224)
    57. 

  57. /* 00 ~ 32: max histogram */
    58. 

  58. #define DISP_AAL_STATUS_32                      (DISPSYS_AAL0_BASE + 0x2a4)
    59. 

  59. /* bit 8: dre_gain_force_en */
    60. 

  60. #define DISP_AAL_DRE_GAIN_FILTER_00             (DISPSYS_AAL0_BASE + 0x354)
    61. 

  61. #define DISP_AAL_DRE_FLT_FORCE(idx)             (DISPSYS_AAL0_BASE + 0x358 + (idx) * 4)
    62. 

  62. #define DISP_AAL_DRE_CRV_CAL_00                 (DISPSYS_AAL0_BASE + 0x344)
    63. 

  63. #define DISP_AAL_DRE_MAPPING_00                 (DISPSYS_AAL0_BASE + 0x3b0)
    64. 

  64. #define DISP_AAL_CABC_GAINLMT_TBL(idx)          (DISPSYS_AAL0_BASE + 0x40c + (idx) * 4)
    65. 

  65. /* DRE 3.0 */
    66. 

  66. #define DISP_AAL_OUTPUT_SIZE                    (DISPSYS_AAL0_BASE + 0x4d8)
    67. 

  67. 

  68. #define DISP_PWM_EN_OFF                         (0x00)
    69. 

  69. #define DISP_PWM_RST_RX                         (0x04)
    70. 

  70. #define DISP_PWM_COMMIT_OFF                     (0x0C)
    71. 

  71. #define DISP_PWM_CON_0_OFF                      (0x18)
    72. 

  72. #define DISP_PWM_CON_1_OFF                      (0x1C)
    73. 

  73. #define DISP_PWM_DEBUG                          (0x80)
    74. 

  74. 

  75. 

  76. /* field definition */
    77. 

  77. /* ------------------------------------------------------------- */
    78. 

  78. /* COLOR */
    79. 

  79. #define CFG_MAIN_FLD_M_REG_RESET                 REG_FLD(1, 31)
    80. 

  80. #define CFG_MAIN_FLD_M_DISP_RESET                REG_FLD(1, 30)
    81. 

  81. #define CFG_MAIN_FLD_COLOR_DBUF_EN               REG_FLD(1, 29)
    82. 

  82. #define CFG_MAIN_FLD_C_PP_CM_DBG_SEL             REG_FLD(4, 16)
    83. 

  83. #define CFG_MAIN_FLD_SEQ_SEL                     REG_FLD(1, 13)
    84. 

  84. #define CFG_MAIN_FLD_ALLBP                       REG_FLD(1, 7)
    85. 

  85. #define CFG_MAIN_FLD_HEBP                        REG_FLD(1, 4)
    86. 

  86. #define CFG_MAIN_FLD_SEBP                        REG_FLD(1, 3)
    87. 

  87. #define CFG_MAIN_FLD_YEBP                        REG_FLD(1, 2)
    88. 

  88. #define CFG_MAIN_FLD_P2CBP                       REG_FLD(1, 1)
    89. 

  89. #define CFG_MAIN_FLD_C2PBP                       REG_FLD(1, 0)
    90. 

  90. #define START_FLD_DISP_COLOR_START               REG_FLD(1, 0)
    91. 

  91. 

  92. #define DISP_COLOR_CFG_MAIN             (DISPSYS_COLOR0_BASE+0x400)
    93. 

  93. #define DISP_COLOR_PXL_CNT_MAIN         (DISPSYS_COLOR0_BASE+0x404)
    94. 

  94. #define DISP_COLOR_LINE_CNT_MAIN        (DISPSYS_COLOR0_BASE+0x408)
    95. 

  95. #define DISP_COLOR_WIN_X_MAIN           (DISPSYS_COLOR0_BASE+0x40C)
    96. 

  96. #define DISP_COLOR_WIN_Y_MAIN           (DISPSYS_COLOR0_BASE+0x410)
    97. 

  97. #define DISP_COLOR_TIMING_DETECTION_0   (DISPSYS_COLOR0_BASE+0x418)
    98. 

  98. #define DISP_COLOR_TIMING_DETECTION_1   (DISPSYS_COLOR0_BASE+0x41c)
    99. 

  99. #define DISP_COLOR_DBG_CFG_MAIN         (DISPSYS_COLOR0_BASE+0x420)
    100. 

  100. #define DISP_COLOR_C_BOOST_MAIN         (DISPSYS_COLOR0_BASE+0x428)
    101. 

  101. #define DISP_COLOR_C_BOOST_MAIN_2       (DISPSYS_COLOR0_BASE+0x42C)
    102. 

  102. #define DISP_COLOR_LUMA_ADJ             (DISPSYS_COLOR0_BASE+0x430)
    103. 

  103. #define DISP_COLOR_G_PIC_ADJ_MAIN_1     (DISPSYS_COLOR0_BASE+0x434)
    104. 

  104. #define DISP_COLOR_G_PIC_ADJ_MAIN_2     (DISPSYS_COLOR0_BASE+0x438)
    105. 

  105. #define DISP_COLOR_POS_MAIN             (DISPSYS_COLOR0_BASE+0x484)
    106. 

  106. #define DISP_COLOR_INK_DATA_MAIN        (DISPSYS_COLOR0_BASE+0x488)
    107. 

  107. #define DISP_COLOR_INK_DATA_MAIN_CR     (DISPSYS_COLOR0_BASE+0x48c)
    108. 

  108. #define DISP_COLOR_CAP_IN_DATA_MAIN     (DISPSYS_COLOR0_BASE+0x490)
    109. 

  109. #define DISP_COLOR_CAP_IN_DATA_MAIN_CR  (DISPSYS_COLOR0_BASE+0x494)
    110. 

  110. #define DISP_COLOR_CAP_OUT_DATA_MAIN    (DISPSYS_COLOR0_BASE+0x498)
    111. 

  111. #define DISP_COLOR_CAP_OUT_DATA_MAIN_CR (DISPSYS_COLOR0_BASE+0x49c)
    112. 

  112. #define DISP_COLOR_Y_SLOPE_1_0_MAIN     (DISPSYS_COLOR0_BASE+0x4A0)
    113. 

  113. #define DISP_COLOR_LOCAL_HUE_CD_0       (DISPSYS_COLOR0_BASE+0x620)
    114. 

  114. #define DISP_COLOR_TWO_D_WINDOW_1       (DISPSYS_COLOR0_BASE+0x740)
    115. 

  115. #define DISP_COLOR_TWO_D_W1_RESULT      (DISPSYS_COLOR0_BASE+0x74C)
    116. 

  116. #define DISP_COLOR_SAT_HIST_X_CFG_MAIN  (DISPSYS_COLOR0_BASE+0x768)
    117. 

  117. #define DISP_COLOR_SAT_HIST_Y_CFG_MAIN  (DISPSYS_COLOR0_BASE+0x76c)
    118. 

  118. #define DISP_COLOR_BWS_2                (DISPSYS_COLOR0_BASE+0x79c)
    119. 

  119. #define DISP_COLOR_CRC_0                (DISPSYS_COLOR0_BASE+0x7e0)
    120. 

  120. #define DISP_COLOR_PART_SAT_GAIN1_0     (DISPSYS_COLOR0_BASE+0x7FC)
    121. 

  121. #define DISP_COLOR_PART_SAT_GAIN1_1     (DISPSYS_COLOR0_BASE+0x800)
    122. 

  122. #define DISP_COLOR_PART_SAT_GAIN1_2     (DISPSYS_COLOR0_BASE+0x804)
    123. 

  123. #define DISP_COLOR_PART_SAT_GAIN1_3     (DISPSYS_COLOR0_BASE+0x808)
    124. 

  124. #define DISP_COLOR_PART_SAT_GAIN1_4     (DISPSYS_COLOR0_BASE+0x80C)
    125. 

  125. #define DISP_COLOR_PART_SAT_GAIN2_0     (DISPSYS_COLOR0_BASE+0x810)
    126. 

  126. #define DISP_COLOR_PART_SAT_GAIN2_1     (DISPSYS_COLOR0_BASE+0x814)
    127. 

  127. #define DISP_COLOR_PART_SAT_GAIN2_2     (DISPSYS_COLOR0_BASE+0x818)
    128. 

  128. #define DISP_COLOR_PART_SAT_GAIN2_3	    (DISPSYS_COLOR0_BASE+0x81C)
    129. 

  129. #define DISP_COLOR_PART_SAT_GAIN2_4     (DISPSYS_COLOR0_BASE+0x820)
    130. 

  130. #define DISP_COLOR_PART_SAT_GAIN3_0     (DISPSYS_COLOR0_BASE+0x824)
    131. 

  131. #define DISP_COLOR_PART_SAT_GAIN3_1     (DISPSYS_COLOR0_BASE+0x828)
    132. 

  132. #define DISP_COLOR_PART_SAT_GAIN3_2     (DISPSYS_COLOR0_BASE+0x82C)
    133. 

  133. #define DISP_COLOR_PART_SAT_GAIN3_3     (DISPSYS_COLOR0_BASE+0x830)
    134. 

  134. #define DISP_COLOR_PART_SAT_GAIN3_4     (DISPSYS_COLOR0_BASE+0x834)
    135. 

  135. #define DISP_COLOR_PART_SAT_POINT1_0    (DISPSYS_COLOR0_BASE+0x838)
    136. 

  136. #define DISP_COLOR_PART_SAT_POINT1_1    (DISPSYS_COLOR0_BASE+0x83C)
    137. 

  137. #define DISP_COLOR_PART_SAT_POINT1_2    (DISPSYS_COLOR0_BASE+0x840)
    138. 

  138. #define DISP_COLOR_PART_SAT_POINT1_3    (DISPSYS_COLOR0_BASE+0x844)
    139. 

  139. #define DISP_COLOR_PART_SAT_POINT1_4    (DISPSYS_COLOR0_BASE+0x848)
    140. 

  140. #define DISP_COLOR_PART_SAT_POINT2_0    (DISPSYS_COLOR0_BASE+0x84C)
    141. 

  141. #define DISP_COLOR_PART_SAT_POINT2_1    (DISPSYS_COLOR0_BASE+0x850)
    142. 

  142. #define DISP_COLOR_PART_SAT_POINT2_2    (DISPSYS_COLOR0_BASE+0x854)
    143. 

  143. #define DISP_COLOR_PART_SAT_POINT2_3    (DISPSYS_COLOR0_BASE+0x858)
    144. 

  144. #define DISP_COLOR_PART_SAT_POINT2_4    (DISPSYS_COLOR0_BASE+0x85C)
    145. 

  145. 

  146. #define DISP_COLOR_START                (DISPSYS_COLOR0_BASE+0xC00)
    147. 

  147. #define DISP_COLOR_INTEN                (DISPSYS_COLOR0_BASE+0xC04)
    148. 

  148. #define DISP_COLOR_OUT_SEL              (DISPSYS_COLOR0_BASE+0xC08)
    149. 

  149. #define DISP_COLOR_FRAME_DONE_DEL       (DISPSYS_COLOR0_BASE+0xC10)
    150. 

  150. #define DISP_COLOR_CRC                  (DISPSYS_COLOR0_BASE+0xC14)
    151. 

  151. #define DISP_COLOR_SW_SCRATCH           (DISPSYS_COLOR0_BASE+0xC18)
    152. 

  152. #define DISP_COLOR_CK_ON                (DISPSYS_COLOR0_BASE+0xC28)
    153. 

  153. #define DISP_COLOR_INTERNAL_IP_WIDTH    (DISPSYS_COLOR0_BASE+0xC50)
    154. 

  154. #define DISP_COLOR_INTERNAL_IP_HEIGHT   (DISPSYS_COLOR0_BASE+0xC54)
    155. 

  155. #define DISP_COLOR_CM1_EN               (DISPSYS_COLOR0_BASE+0xC60)
    156. 

  156. #define DISP_COLOR_CM2_EN               (DISPSYS_COLOR0_BASE+0xCA0)
    157. 

  157. #define DISP_COLOR_SHADOW_CTRL          (DISPSYS_COLOR0_BASE+0xCB0)
    158. 

  158. #define DISP_COLOR_R0_CRC               (DISPSYS_COLOR0_BASE+0xCF0)
    159. 

  159. #define DISP_COLOR_S_GAIN_BY_Y0_0       (DISPSYS_COLOR0_BASE+0xCF4)
    160. 

  160. #define DISP_COLOR_S_GAIN_BY_Y0_1       (DISPSYS_COLOR0_BASE+0xCF8)
    161. 

  161. #define DISP_COLOR_S_GAIN_BY_Y0_2       (DISPSYS_COLOR0_BASE+0xCFC)
    162. 

  162. #define DISP_COLOR_S_GAIN_BY_Y0_3       (DISPSYS_COLOR0_BASE+0xD00)
    163. 

  163. #define DISP_COLOR_S_GAIN_BY_Y0_4       (DISPSYS_COLOR0_BASE+0xD04)
    164. 

  164. #define DISP_COLOR_S_GAIN_BY_Y64_0      (DISPSYS_COLOR0_BASE+0xD08)
    165. 

  165. #define DISP_COLOR_S_GAIN_BY_Y64_1      (DISPSYS_COLOR0_BASE+0xD0C)
    166. 

  166. #define DISP_COLOR_S_GAIN_BY_Y64_2      (DISPSYS_COLOR0_BASE+0xD10)
    167. 

  167. #define DISP_COLOR_S_GAIN_BY_Y64_3      (DISPSYS_COLOR0_BASE+0xD14)
    168. 

  168. #define DISP_COLOR_S_GAIN_BY_Y64_4      (DISPSYS_COLOR0_BASE+0xD18)
    169. 

  169. #define DISP_COLOR_S_GAIN_BY_Y128_0     (DISPSYS_COLOR0_BASE+0xD1C)
    170. 

  170. #define DISP_COLOR_S_GAIN_BY_Y128_1     (DISPSYS_COLOR0_BASE+0xD20)
    171. 

  171. #define DISP_COLOR_S_GAIN_BY_Y128_2     (DISPSYS_COLOR0_BASE+0xD24)
    172. 

  172. #define DISP_COLOR_S_GAIN_BY_Y128_3     (DISPSYS_COLOR0_BASE+0xD28)
    173. 

  173. #define DISP_COLOR_S_GAIN_BY_Y128_4     (DISPSYS_COLOR0_BASE+0xD2C)
    174. 

  174. #define DISP_COLOR_S_GAIN_BY_Y192_0     (DISPSYS_COLOR0_BASE+0xD30)
    175. 

  175. #define DISP_COLOR_S_GAIN_BY_Y192_1     (DISPSYS_COLOR0_BASE+0xD34)
    176. 

  176. #define DISP_COLOR_S_GAIN_BY_Y192_2     (DISPSYS_COLOR0_BASE+0xD38)
    177. 

  177. #define DISP_COLOR_S_GAIN_BY_Y192_3     (DISPSYS_COLOR0_BASE+0xD3C)
    178. 

  178. #define DISP_COLOR_S_GAIN_BY_Y192_4     (DISPSYS_COLOR0_BASE+0xD40)
    179. 

  179. #define DISP_COLOR_S_GAIN_BY_Y256_0     (DISPSYS_COLOR0_BASE+0xD44)
    180. 

  180. #define DISP_COLOR_S_GAIN_BY_Y256_1     (DISPSYS_COLOR0_BASE+0xD48)
    181. 

  181. #define DISP_COLOR_S_GAIN_BY_Y256_2     (DISPSYS_COLOR0_BASE+0xD4C)
    182. 

  182. #define DISP_COLOR_S_GAIN_BY_Y256_3     (DISPSYS_COLOR0_BASE+0xD50)
    183. 

  183. #define DISP_COLOR_S_GAIN_BY_Y256_4     (DISPSYS_COLOR0_BASE+0xD54)
    184. 

  184. #define DISP_COLOR_LSP_1                (DISPSYS_COLOR0_BASE+0xD58)
    185. 

  185. #define DISP_COLOR_LSP_2                (DISPSYS_COLOR0_BASE+0xD5C)
    186. 

  186. 

  187. 

  188. 

  189. /* SMI_LARB0 */
    190. 

  190. #define DISP_REG_SMI_LARB0_NON_SEC_CON (DISPSYS_SMI_LARB0_BASE+0x380)
    191. 

  191. #define DISP_REG_SMI_LARB0_SEC_CON (DISPSYS_SMI_LARB0_BASE+0xf80)
    192. 

  192. /* SMI_LARB1 */
    193. 

  193. #define DISP_REG_SMI_LARB1_NON_SEC_CON (DISPSYS_SMI_LARB1_BASE+0x380)
    194. 

  194. #define DISP_REG_SMI_LARB1_SEC_CON (DISPSYS_SMI_LARB1_BASE+0xf80)
    195. 

  195. #define REG_FLD_MMU_EN										   REG_FLD(1, 0)
    196. 

  196. 

  197. 

  198. /* field definition */
    199. 

  199. /* ------------------------------------------------------------- */
    200. 

  200. /* CCORR */
    201. 

  201. #define DISP_REG_CCORR_EN                                    (DISPSYS_CCORR0_BASE + 0x000)
    202. 

  202. #define DISP_REG_CCORR_RESET                                 (DISPSYS_CCORR0_BASE + 0x004)
    203. 

  203. #define DISP_REG_CCORR_INTEN                                 (DISPSYS_CCORR0_BASE + 0x008)
    204. 

  204. #define DISP_REG_CCORR_INTSTA                                (DISPSYS_CCORR0_BASE + 0x00c)
    205. 

  205. #define DISP_REG_CCORR_STATUS                                (DISPSYS_CCORR0_BASE + 0x010)
    206. 

  206. #define DISP_REG_CCORR_CFG                                   (DISPSYS_CCORR0_BASE + 0x020)
    207. 

  207. #define DISP_REG_CCORR_IN_CNT                                (DISPSYS_CCORR0_BASE + 0x024)
    208. 

  208. #define DISP_REG_CCORR_OUT_CNT                               (DISPSYS_CCORR0_BASE + 0x028)
    209. 

  209. #define DISP_REG_CCORR_CHKSUM                                (DISPSYS_CCORR0_BASE + 0x02c)
    210. 

  210. #define DISP_REG_CCORR_SIZE                                  (DISPSYS_CCORR0_BASE + 0x030)
    211. 

  211. #define DISP_REG_CCORR_COEF_0                                (DISPSYS_CCORR0_BASE + 0x080)
    212. 

  212. #define DISP_REG_CCORR_SHADOW                                (DISPSYS_CCORR0_BASE + 0x0a0)
    213. 

  213. #define DISP_REG_CCORR_DUMMY_REG                             (DISPSYS_CCORR0_BASE + 0x0c0)
    214. 

  214. 

  215. #define CCORR_SIZE_FLD_HSIZE                                  REG_FLD(13, 16)
    216. 

  216. #define CCORR_SIZE_FLD_VSIZE                                  REG_FLD(13, 0)
    217. 

  217. #define CCORR_CFG_FLD_CHKSUM_SEL                              REG_FLD(3, 29)
    218. 

  218. #define CCORR_CFG_FLD_CHKSUM_EN                               REG_FLD(1, 28)
    219. 

  219. #define CCORR_CFG_FLD_CCORR_GAMMA_OFF                         REG_FLD(1, 2)
    220. 

  220. #define CCORR_CFG_FLD_CCORR_ENGINE_EN                         REG_FLD(1, 1)
    221. 

  221. /* field definition */
    222. 

  222. /* ------------------------------------------------------------- */
    223. 

  223. /* GAMMA */
    224. 

  224. #define DISP_REG_GAMMA_EN								(DISPSYS_GAMMA0_BASE + 0x000)
    225. 

  225. #define DISP_REG_GAMMA_RESET							(DISPSYS_GAMMA0_BASE + 0x004)
    226. 

  226. #define DISP_REG_GAMMA_INTEN							(DISPSYS_GAMMA0_BASE + 0x008)
    227. 

  227. #define DISP_REG_GAMMA_INTSTA							(DISPSYS_GAMMA0_BASE + 0x00c)
    228. 

  228. #define DISP_REG_GAMMA_STATUS						    (DISPSYS_GAMMA0_BASE + 0x010)
    229. 

  229. #define DISP_REG_GAMMA_CFG							    (DISPSYS_GAMMA0_BASE + 0x020)
    230. 

  230. #define DISP_REG_GAMMA_INPUT_COUNT					    (DISPSYS_GAMMA0_BASE + 0x024)
    231. 

  231. #define DISP_REG_GAMMA_OUTPUT_COUNT					    (DISPSYS_GAMMA0_BASE + 0x028)
    232. 

  232. #define DISP_REG_GAMMA_CHKSUM						    (DISPSYS_GAMMA0_BASE + 0x02c)
    233. 

  233. #define DISP_REG_GAMMA_SIZE							    (DISPSYS_GAMMA0_BASE + 0x030)
    234. 

  234. #define DISP_REG_GAMMA_DEBUG						    (DISPSYS_GAMMA0_BASE + 0x034)
    235. 

  235. #define DISP_REG_GAMMA_DUMMY_REG					    (DISPSYS_GAMMA0_BASE + 0x0c0)
    236. 

  236. #define DISP_REG_GAMMA_LUT							    (DISPSYS_GAMMA0_BASE + 0x700)
    237. 

  237. 

  238. #define EN_FLD_GAMMA_EN                         REG_FLD(1, 0)
    239. 

  239. #define RESET_FLD_GAMMA_RESET                   REG_FLD(1, 0)
    240. 

  240. #define INTEN_FLD_OF_END_INT_EN                 REG_FLD(1, 1)
    241. 

  241. #define INTEN_FLD_IF_END_INT_EN                 REG_FLD(1, 0)
    242. 

  242. #define INTSTA_FLD_OF_END_INT                   REG_FLD(1, 1)
    243. 

  243. #define INTSTA_FLD_IF_END_INT                   REG_FLD(1, 0)
    244. 

  244. #define STATUS_FLD_IN_VALID				REG_FLD(1, 7)
    245. 

  245. #define STATUS_FLD_IN_READY				REG_FLD(1, 6)
    246. 

  246. #define STATUS_FLD_OUT_VALID	                REG_FLD(1, 5)
    247. 

  247. #define STATUS_FLD_OUT_READY	                REG_FLD(1, 4)
    248. 

  248. #define STATUS_FLD_OF_UNFINISH	                REG_FLD(1, 1)
    249. 

  249. #define STATUS_FLD_IF_UNFINISH	                REG_FLD(1, 0)
    250. 

  250. #define CFG_FLD_CHKSUM_SEL				REG_FLD(2, 29)
    251. 

  251. #define CFG_FLD_CHKSUM_EN				REG_FLD(1, 28)
    252. 

  252. #define CFG_FLD_CCORR_GAMMA_OFF                 REG_FLD(1, 5)
    253. 

  253. #define CFG_FLD_CCORR_EN			            REG_FLD(1, 4)
    254. 

  254. #define CFG_FLD_DITHER_EN			            REG_FLD(1, 2)
    255. 

  255. #define CFG_FLD_GAMMA_LUT_EN			REG_FLD(1, 1)
    256. 

  256. #define CFG_FLD_RELAY_MODE				REG_FLD(1, 0)
    257. 

  257. #define INPUT_COUNT_FLD_INP_LINE_CNT			REG_FLD(13, 16)
    258. 

  258. #define INPUT_COUNT_FLD_INP_PIX_CNT			REG_FLD(13, 0)
    259. 

  259. #define OUTPUT_COUNT_FLD_OUTP_LINE_CNT			REG_FLD(13, 16)
    260. 

  260. #define OUTPUT_COUNT_FLD_OUTP_PIX_CNT			REG_FLD(13, 0)
    261. 

  261. #define CHKSUM_FLD_CHKSUM						REG_FLD(30, 0)
    262. 

  262. #define SIZE_FLD_HSIZE							REG_FLD(13, 16)
    263. 

  263. #define SIZE_FLD_VSIZE							REG_FLD(13, 0)
    264. 

  264. #define CCORR_0_FLD_CCORR_C00					REG_FLD(12, 16)
    265. 

  265. #define CCORR_0_FLD_CCORR_C01					REG_FLD(12, 0)
    266. 

  266. #define CCORR_1_FLD_CCORR_C02					REG_FLD(12, 16)
    267. 

  267. #define CCORR_1_FLD_CCORR_C10					REG_FLD(12, 0)
    268. 

  268. #define CCORR_2_FLD_CCORR_C11					REG_FLD(12, 16)
    269. 

  269. #define CCORR_2_FLD_CCORR_C12					REG_FLD(12, 0)
    270. 

  270. #define CCORR_3_FLD_CCORR_C20					REG_FLD(12, 16)
    271. 

  271. #define CCORR_3_FLD_CCORR_C21					REG_FLD(12, 0)
    272. 

  272. #define CCORR_4_FLD_CCORR_C22					REG_FLD(12, 16)
    273. 

  273. #define DUMMY_REG_FLD_DUMMY_REG					REG_FLD(32, 0)
    274. 

  274. #define DITHER_0_FLD_CRC_CLR					REG_FLD(1, 24)
    275. 

  275. #define DITHER_0_FLD_CRC_START					REG_FLD(1, 20)
    276. 

  276. #define DITHER_0_FLD_CRC_CEN					REG_FLD(1, 16)
    277. 

  277. #define DITHER_0_FLD_FRAME_DONE_DEL				REG_FLD(8, 8)
    278. 

  278. #define DITHER_0_FLD_OUT_SEL					REG_FLD(1, 4)
    279. 

  279. #define DITHER_5_FLD_W_DEMO						REG_FLD(16, 0)
    280. 

  280. #define DITHER_6_FLD_WRAP_MODE					REG_FLD(1, 16)
    281. 

  281. #define DITHER_6_FLD_LEFT_EN					REG_FLD(2, 14)
    282. 

  282. #define DITHER_6_FLD_FPHASE_R					REG_FLD(1, 13)
    283. 

  283. #define DITHER_6_FLD_FPHASE_EN					REG_FLD(1, 12)
    284. 

  284. #define DITHER_6_FLD_FPHASE						REG_FLD(6, 4)
    285. 

  285. #define DITHER_6_FLD_ROUND_EN					REG_FLD(1, 3)
    286. 

  286. #define DITHER_6_FLD_RDITHER_EN					REG_FLD(1, 2)
    287. 

  287. #define DITHER_6_FLD_LFSR_EN					REG_FLD(1, 1)
    288. 

  288. #define DITHER_6_FLD_EDITHER_EN					REG_FLD(1, 0)
    289. 

  289. #define DITHER_7_FLD_DRMOD_B					REG_FLD(2, 8)
    290. 

  290. #define DITHER_7_FLD_DRMOD_G					REG_FLD(2, 4)
    291. 

  291. #define DITHER_7_FLD_DRMOD_R					REG_FLD(2, 0)
    292. 

  292. #define GAMMA_DITHER_8_FLD_INK_DATA_R			REG_FLD(12, 16)
    293. 

  293. #define DITHER_8_FLD_INK						REG_FLD(1, 0)
    294. 

  294. #define GAMMA_DITHER_9_FLD_INK_DATA_B			REG_FLD(12, 16)
    295. 

  295. #define GAMMA_DITHER_9_FLD_INK_DATA_G			REG_FLD(12, 0)
    296. 

  296. #define DITHER_10_FLD_FPHASE_BIT				REG_FLD(3, 8)
    297. 

  297. #define DITHER_10_FLD_FPHASE_SEL				REG_FLD(2, 4)
    298. 

  298. #define DITHER_10_FLD_FPHASE_CTRL				REG_FLD(2, 0)
    299. 

  299. #define DITHER_11_FLD_SUB_B						REG_FLD(2, 12)
    300. 

  300. #define DITHER_11_FLD_SUB_G						REG_FLD(2, 8)
    301. 

  301. #define DITHER_11_FLD_SUB_R						REG_FLD(2, 4)
    302. 

  302. #define DITHER_11_FLD_SUBPIX_EN					REG_FLD(1, 0)
    303. 

  303. #define DITHER_12_FLD_H_ACTIVE					REG_FLD(16, 16)
    304. 

  304. #define DITHER_12_FLD_TABLE_EN					REG_FLD(2, 4)
    305. 

  305. #define DITHER_12_FLD_LSB_OFF					REG_FLD(1, 0)
    306. 

  306. #define DITHER_13_FLD_RSHIFT_B					REG_FLD(3, 8)
    307. 

  307. #define DITHER_13_FLD_RSHIFT_G					REG_FLD(3, 4)
    308. 

  308. #define DITHER_13_FLD_RSHIFT_R					REG_FLD(3, 0)
    309. 

  309. #define DITHER_14_FLD_DEBUG_MODE				REG_FLD(2, 8)
    310. 

  310. #define DITHER_14_FLD_DIFF_SHIFT				REG_FLD(3, 4)
    311. 

  311. #define DITHER_14_FLD_TESTPIN_EN				REG_FLD(1, 0)
    312. 

  312. #define DITHER_15_FLD_LSB_ERR_SHIFT_R			REG_FLD(3, 28)
    313. 

  313. #define DITHER_15_FLD_LSB_OVFLW_BIT_R			REG_FLD(3, 24)
    314. 

  314. #define DITHER_15_FLD_LSB_ADD_LSHIFT_R			REG_FLD(3, 20)
    315. 

  315. #define DITHER_15_FLD_LSB_INPUT_RSHIFT_R		REG_FLD(3, 16)
    316. 

  316. #define DITHER_15_FLD_LSB_NEW_BIT_MODE			REG_FLD(1, 0)
    317. 

  317. #define DITHER_16_FLD_LSB_ERR_SHIFT_B			REG_FLD(3, 28)
    318. 

  318. #define DITHER_16_FLD_OVFLW_BIT_B				REG_FLD(3, 24)
    319. 

  319. #define DITHER_16_FLD_ADD_LSHIFT_B				REG_FLD(3, 20)
    320. 

  320. #define DITHER_16_FLD_INPUT_RSHIFT_B			REG_FLD(3, 16)
    321. 

  321. #define DITHER_16_FLD_LSB_ERR_SHIFT_G			REG_FLD(3, 12)
    322. 

  322. #define DITHER_16_FLD_OVFLW_BIT_G				REG_FLD(3, 8)
    323. 

  323. #define DITHER_16_FLD_ADD_LSHIFT_G				REG_FLD(3, 4)
    324. 

  324. #define DITHER_16_FLD_INPUT_RSHIFT_G				REG_FLD(3, 0)
    325. 

  325. #define DITHER_17_FLD_CRC_RDY					REG_FLD(1, 16)
    326. 

  326. #define DITHER_17_FLD_CRC_OUT					REG_FLD(16, 0)
    327. 

  327. #define LUT_FLD_GAMMA_LUT_R					REG_FLD(10, 20)
    328. 

  328. #define LUT_FLD_GAMMA_LUT_G					REG_FLD(10, 10)
    329. 

  329. #define LUT_FLD_GAMMA_LUT_B					REG_FLD(10, 0)
    330. 

  330. 

  331. /* ------------------------------------------------------------- */
    332. 

  332. /* Dither */
    333. 

  333. #define DISP_REG_DITHER_EN                                        (DISPSYS_DITHER0_BASE + 0x000)
    334. 

  334. #define DISP_REG_DITHER_RESET                                     (DISPSYS_DITHER0_BASE + 0x004)
    335. 

  335. #define DISP_REG_DITHER_INTEN                                     (DISPSYS_DITHER0_BASE + 0x008)
    336. 

  336. #define DISP_REG_DITHER_INTSTA                                    (DISPSYS_DITHER0_BASE + 0x00c)
    337. 

  337. #define DISP_REG_DITHER_STATUS                                    (DISPSYS_DITHER0_BASE + 0x010)
    338. 

  338. #define DISP_REG_DITHER_CFG                                       (DISPSYS_DITHER0_BASE + 0x020)
    339. 

  339. #define DISP_REG_DITHER_IN_CNT                                    (DISPSYS_DITHER0_BASE + 0x024)
    340. 

  340. #define DISP_REG_DITHER_OUT_CNT                                   (DISPSYS_DITHER0_BASE + 0x028)
    341. 

  341. #define DISP_REG_DITHER_CHKSUM                                    (DISPSYS_DITHER0_BASE + 0x02c)
    342. 

  342. #define DISP_REG_DITHER_SIZE                                      (DISPSYS_DITHER0_BASE + 0x030)
    343. 

  343. #define DISP_REG_DITHER_DUMMY_REG                                 (DISPSYS_DITHER0_BASE + 0x0c0)
    344. 

  344. #define DISP_REG_DITHER_0                                         (DISPSYS_DITHER0_BASE + 0x100)
    345. 

  345. #define DISP_REG_DITHER_5                                         (DISPSYS_DITHER0_BASE + 0x114)
    346. 

  346. #define DISP_REG_DITHER_6                                         (DISPSYS_DITHER0_BASE + 0x118)
    347. 

  347. #define DISP_REG_DITHER_7                                         (DISPSYS_DITHER0_BASE + 0x11c)
    348. 

  348. #define DISP_REG_DITHER_8                                         (DISPSYS_DITHER0_BASE + 0x120)
    349. 

  349. #define DISP_REG_DITHER_9                                         (DISPSYS_DITHER0_BASE + 0x124)
    350. 

  350. #define DISP_REG_DITHER_10                                        (DISPSYS_DITHER0_BASE + 0x128)
    351. 

  351. #define DISP_REG_DITHER_11                                        (DISPSYS_DITHER0_BASE + 0x12c)
    352. 

  352. #define DISP_REG_DITHER_12                                        (DISPSYS_DITHER0_BASE + 0x130)
    353. 

  353. #define DISP_REG_DITHER_13                                        (DISPSYS_DITHER0_BASE + 0x134)
    354. 

  354. #define DISP_REG_DITHER_14                                        (DISPSYS_DITHER0_BASE + 0x138)
    355. 

  355. #define DISP_REG_DITHER_15                                        (DISPSYS_DITHER0_BASE + 0x13c)
    356. 

  356. #define DISP_REG_DITHER_16                                        (DISPSYS_DITHER0_BASE + 0x140)
    357. 

  357. #define DISP_REG_DITHER_17                                        (DISPSYS_DITHER0_BASE + 0x144)
    358. 

  358. 

  359. #define DITHER_CFG_FLD_CHKSUM_SEL				REG_FLD(2, 29)
    360. 

  360. #define DITHER_CFG_FLD_CHKSUM_EN				REG_FLD(1, 28)
    361. 

  361. #define DITHER_CFG_FLD_DITHER_ENGINE_EN				REG_FLD(1, 1)
    362. 

  362. #define DITHER_CFG_FLD_RELAY_MODE				REG_FLD(1, 0)
    363. 

  363. #define DITHER_SIZE_FLD_HSIZE					REG_FLD(13, 16)
    364. 

  364. #define DITHER_SIZE_FLD_VSIZE					REG_FLD(13, 0)
    365. 

  365. 

  366. #endif /* _DDP_REG_PQ_H_ */
    367.