mtk-lk/target/k57pv1_dm_2g_hdp/cust_msdc.c

/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2015. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#include "cust_msdc.h"
#include "msdc.h"


struct msdc_cust msdc_cap[MSDC_MAX_NUM] = {
	{
		MSDC50_CLKSRC_DEFAULT, /* host clock source          */
		MSDC_SMPL_RISING,   /* command latch edge            */
		MSDC_SMPL_RISING,   /* data latch edge               */
		MSDC_DRVN_GEAR3,    /* clock pad driving             */
		MSDC_DRVN_GEAR3,    /* command pad driving           */
		MSDC_DRVN_GEAR3,    /* data pad driving              */
		MSDC_DRVN_GEAR3,    /* rst pad driving               */
		MSDC_DRVN_GEAR1,    /* ds pad driving                */
		MSDC_DRVN_DONT_CARE,/* clock pad driving on 1.8V     */
		MSDC_DRVN_DONT_CARE,/* command pad driving on 1.8V   */
		MSDC_DRVN_DONT_CARE,/* data pad driving on 1.8V      */
		8,                  /* data pins                     */
		0,                  /* data address offset           */
#if defined(MMC_MSDC_DRV_CTP)
		MSDC_HIGHSPEED | MSDC_HS200 | MSDC_RST_PIN_EN | MSDC_DDR | MSDC_HS400
#else
		MSDC_HIGHSPEED | MSDC_DDR
#endif
	}

#if (defined(MMC_MSDC_DRV_CTP) && !defined(FPGA_PLATFORM))
	,
	{
		MSDC30_CLKSRC_DEFAULT, /* host clock source          */
		MSDC_SMPL_RISING,   /* command latch edge            */
		MSDC_SMPL_RISING,   /* data latch edge               */
		MSDC_DRVN_GEAR4,    /* clock pad driving             */
		MSDC_DRVN_GEAR3,    /* command pad driving           */
		MSDC_DRVN_GEAR3,    /* data pad driving              */
		MSDC_DRVN_DONT_CARE,/* no need for not-emmc card     */
		MSDC_DRVN_DONT_CARE,/* no need for not-emmc card     */
		MSDC_DRVN_GEAR3,    /* clock pad driving on 1.8V     */
		MSDC_DRVN_GEAR3,    /* command pad driving on 1.8V   */
		MSDC_DRVN_GEAR3,    /* data pad driving on 1.8V      */
		4,                  /* data pins                     */
		0,                  /* data address offset           */

		/* hardware capability flags     */
		MSDC_HIGHSPEED | MSDC_UHS1 | MSDC_DDR //|MSDC_UHS1|MSDC_SDIO_IRQ|MSDC_DDR
	}
	,
	{
		MSDC30_CLKSRC_DEFAULT, /* host clock source          */
		MSDC_SMPL_RISING,   /* command latch edge            */
		MSDC_SMPL_RISING,   /* data latch edge               */
		MSDC_DRVN_GEAR1,    /* clock pad driving             */
		MSDC_DRVN_GEAR1,    /* command pad driving           */
		MSDC_DRVN_GEAR1,    /* data pad driving              */
		MSDC_DRVN_DONT_CARE,/* no need for not-emmc card     */
		MSDC_DRVN_DONT_CARE,/* no need for not-emmc card     */
		MSDC_DRVN_GEAR1,    /* clock pad driving on 1.8V     */
		MSDC_DRVN_GEAR1,    /* command pad driving on 1.8V   */
		MSDC_DRVN_GEAR1 ,   /* data pad driving on 1.8V      */
		4,                  /* data pins                     */
		0,                  /* data address offset           */

		/* hardware capability flags     */
		MSDC_HIGHSPEED | MSDC_UHS1 | MSDC_DDR //|MSDC_UHS1|MSDC_SDIO_IRQ|MSDC_DDR
	}
#endif
};