primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. //#include<linux/timer.h>
  44. #define DDP_LK_BOOT
  45. #ifndef HZ
  46. #define HZ 100
  47. #endif
  48. #ifdef DDP_LK_BOOT
  49. typedef void * cmdqRecHandle;
  50. #endif
  51. #define ALIGN_TO(x, n) \
  52. (((x) + ((n) - 1)) & ~((n) - 1))
  53. int primary_display_use_cmdq = CMDQ_DISABLE;
  54. int primary_display_use_m4u = 1;
  55. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  56. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  57. static UINT32 disp_fb_pages = 3; ///double buffer
  58. static UINT32 display_init;
  59. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  60. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  61. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  62. extern void video_printf(const char *fmt, ...);
  63. extern void disp_path_clock_on(char *str);
  64. typedef struct _disp_dfo_item {
  65. char name[32];
  66. int value;
  67. } disp_dfo_item_t;
  68. static disp_dfo_item_t disp_dfo_setting[] = {
  69. {"LCM_FAKE_WIDTH", 0},
  70. {"LCM_FAKE_HEIGHT", 0},
  71. {"DISP_DEBUG_SWITCH", 0}
  72. };
  73. typedef struct {
  74. int state;
  75. int need_trigger_overlay;
  76. DISP_PRIMARY_PATH_MODE mode;
  77. unsigned int last_vsync_tick;
  78. #ifndef DDP_LK_BOOT
  79. struct mutex lock;
  80. #endif
  81. disp_lcm_handle * plcm;
  82. cmdqRecHandle cmdq_handle_config;
  83. cmdqRecHandle cmdq_handle_trigger;
  84. disp_path_handle dpmgr_handle;
  85. disp_path_handle ovl2mem_path_handle;
  86. } display_primary_path_context;
  87. #define pgc _get_context()
  88. static display_primary_path_context* _get_context(void)
  89. {
  90. static int is_context_inited = 0;
  91. static display_primary_path_context g_context;
  92. if (!is_context_inited) {
  93. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  94. is_context_inited = 1;
  95. }
  96. return &g_context;
  97. }
  98. static void _primary_path_lock(void)
  99. {
  100. #ifndef DDP_LK_BOOT
  101. disp_sw_mutex_lock(&(pgc->lock));
  102. #endif
  103. }
  104. static void _primary_path_unlock(void)
  105. {
  106. #ifndef DDP_LK_BOOT
  107. disp_sw_mutex_unlock(&(pgc->lock));
  108. #endif
  109. }
  110. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  111. {
  112. if (plcm == NULL) {
  113. DISPERR("plcm is null\n");
  114. return DISP_MODULE_UNKNOWN;
  115. }
  116. if (plcm->params->type == LCM_TYPE_DSI) {
  117. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  118. return DISP_MODULE_DSI0;
  119. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  120. return DISP_MODULE_DSI1;
  121. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  122. return DISP_MODULE_DSIDUAL;
  123. } else {
  124. return DISP_MODULE_DSI0;
  125. }
  126. } else if (plcm->params->type == LCM_TYPE_DPI) {
  127. return DISP_MODULE_UNKNOWN;
  128. } else {
  129. DISPERR("can't find primary path dst module\n");
  130. return DISP_MODULE_UNKNOWN;
  131. }
  132. }
  133. static int _build_path_direct_link(void)
  134. {
  135. int ret = 0;
  136. DISP_MODULE_ENUM dst_module = 0;
  137. DISPFUNC();
  138. pgc->mode = DIRECT_LINK_MODE;
  139. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  140. if (pgc->dpmgr_handle) {
  141. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  142. } else {
  143. DISPCHECK("dpmgr create path FAIL\n");
  144. return -1;
  145. }
  146. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  147. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  148. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  149. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  150. return ret;
  151. }
  152. static int _build_path_decouple(void)
  153. {
  154. return 0;
  155. }
  156. static int _build_path_single_layer(void)
  157. {
  158. return 0;
  159. }
  160. static int _build_path_debug_rdma1_dsi0(void)
  161. {
  162. return 0;
  163. }
  164. static void _build_cmdq_trigger_loop(void)
  165. {
  166. #ifndef DDP_LK_BOOT
  167. int ret = 0;
  168. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  169. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  170. cmdqRecReset(pgc->cmdq_handle_trigger);
  171. if (primary_display_is_video_mode()) {
  172. // wait and clear stream_done
  173. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  174. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  175. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  176. } else {
  177. // only in DSI Command mode we need to wait these
  178. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  179. // no internal te on fpga now.
  180. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  181. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  182. // block config threads, we'll about to update frame
  183. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  184. // only in DSI command mode we need to enable mutex explicitly
  185. // WRITE mutex enable
  186. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  187. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  188. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  189. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  190. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  191. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  192. // polling DSI idle
  193. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  194. // polling wdma frame done
  195. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  196. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  197. /*********************/
  198. /***build cmdq finished***/
  199. /*********************/
  200. // TODO:
  201. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  202. // RUN forever!!!!
  203. BUG_ON(ret < 0);
  204. }
  205. #endif
  206. }
  207. static void _start_cmdq_trigger_loop(void)
  208. {
  209. #ifndef DDP_LK_BOOT
  210. int ret = 0;
  211. // this should be called only once because trigger loop will nevet stop
  212. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  213. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  214. #endif
  215. }
  216. static void _set_cmdq_config_handle_dirty(void)
  217. {
  218. #ifndef DDP_LK_BOOT
  219. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  220. cmdqRecFlush(pgc->cmdq_handle_config);
  221. #endif
  222. }
  223. static void _reset_cmdq_config_handle(void)
  224. {
  225. #ifndef DDP_LK_BOOT
  226. cmdqRecReset(pgc->cmdq_handle_config);
  227. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  228. #endif
  229. }
  230. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  231. {
  232. if (src && dst) {
  233. dst->inputFormat = src->fmt;
  234. dst->address = src->addr;
  235. dst->width = src->src_w;
  236. dst->height = src->src_h;
  237. dst->pitch = src->src_pitch;
  238. return 0;
  239. } else {
  240. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  241. return -1;
  242. }
  243. }
  244. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  245. {
  246. if (src && dst) {
  247. dst->layer = src->layer;
  248. dst->layer_en = src->layer_en;
  249. dst->fmt = src->fmt;
  250. dst->addr = src->addr;
  251. dst->vaddr = src->vaddr;
  252. dst->src_x = src->src_x;
  253. dst->src_y = src->src_y;
  254. dst->src_w = src->src_w;
  255. dst->src_h = src->src_h;
  256. dst->src_pitch = src->src_pitch;
  257. dst->dst_x = src->dst_x;
  258. dst->dst_y = src->dst_y;
  259. dst->dst_w = src->dst_w;
  260. dst->dst_h = src->dst_h;
  261. dst->keyEn = src->keyEn;
  262. dst->key = src->key;
  263. dst->aen = src->aen;
  264. dst->alpha = src->alpha;
  265. dst->isDirty = src->isDirty;
  266. dst->buff_idx = src->buff_idx;
  267. dst->identity = src->identity;
  268. dst->connected_type = src->connected_type;
  269. dst->security = src->security;
  270. return 0;
  271. } else {
  272. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  273. return -1;
  274. }
  275. }
  276. void _dump_lcm_info_by_video_printf(void)
  277. {
  278. LCM_DRIVER *l = NULL;
  279. LCM_PARAMS *p = NULL;
  280. disp_lcm_handle *plcm = pgc->plcm;
  281. if (plcm == NULL) {
  282. DISPERR("plcm is null\n");
  283. return;
  284. }
  285. l = plcm->drv;
  286. p = plcm->params;
  287. if (l && p) {
  288. video_printf("[LCM], name: %s\n", l->name);
  289. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  290. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  291. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  292. switch (p->lcm_if) {
  293. case LCM_INTERFACE_DSI0:
  294. video_printf("[LCM] interface: DSI0\n");
  295. break;
  296. case LCM_INTERFACE_DSI1:
  297. video_printf("[LCM] interface: DSI1\n");
  298. break;
  299. case LCM_INTERFACE_DPI0:
  300. video_printf("[LCM] interface: DPI0\n");
  301. break;
  302. case LCM_INTERFACE_DPI1:
  303. video_printf("[LCM] interface: DPI1\n");
  304. break;
  305. case LCM_INTERFACE_DBI0:
  306. video_printf("[LCM] interface: DBI0\n");
  307. break;
  308. default:
  309. video_printf("[LCM] interface: unknown\n");
  310. break;
  311. }
  312. switch (p->type) {
  313. case LCM_TYPE_DBI:
  314. video_printf("[LCM] Type: DBI\n");
  315. break;
  316. case LCM_TYPE_DSI:
  317. video_printf("[LCM] Type: DSI\n");
  318. break;
  319. case LCM_TYPE_DPI:
  320. video_printf("[LCM] Type: DPI\n");
  321. break;
  322. default:
  323. video_printf("[LCM] TYPE: unknown\n");
  324. break;
  325. }
  326. if (p->type == LCM_TYPE_DSI) {
  327. switch (p->dsi.mode) {
  328. case CMD_MODE:
  329. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  330. break;
  331. case SYNC_PULSE_VDO_MODE:
  332. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  333. break;
  334. case SYNC_EVENT_VDO_MODE:
  335. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  336. break;
  337. case BURST_VDO_MODE:
  338. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  339. break;
  340. default:
  341. video_printf("[LCM] DSI Mode: Unknown\n");
  342. break;
  343. }
  344. }
  345. if (p->type == LCM_TYPE_DSI) {
  346. video_printf("[LCM] LANE_NUM: %d, data_format: (%d,%d,%d,%d)\n", p->dsi.LANE_NUM,
  347. p->dsi.data_format.color_order, p->dsi.data_format.format,
  348. p->dsi.data_format.padding, p->dsi.data_format.trans_seq);
  349. #ifdef MY_TODO
  350. #error
  351. #endif
  352. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  353. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  354. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  355. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  356. }
  357. }
  358. return;
  359. }
  360. unsigned int mt_disp_parse_dfo_setting(void)
  361. {
  362. unsigned int i, j=0 ;
  363. char tmp[11];
  364. char *buffer = NULL;
  365. char *ptr = NULL;
  366. buffer = (char *)get_env("DFO");
  367. DISPMSG("env buffer = %s\n", buffer);
  368. if (buffer != NULL) {
  369. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  370. j = 0;
  371. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  372. ptr = strstr(buffer, disp_dfo_setting[i].name);
  373. if (ptr == NULL) continue;
  374. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  375. do {} while ((*ptr++) != ',');
  376. do {tmp[j++] = *ptr++;}
  377. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  378. disp_dfo_setting[i].value = atoi((const char*)tmp);
  379. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  380. }
  381. } else {
  382. DISPMSG("env buffer = NULL\n");
  383. }
  384. return 0;
  385. }
  386. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  387. {
  388. char *disp_name;
  389. int disp_value;
  390. unsigned int i = 0;
  391. if (string == NULL)
  392. return -1;
  393. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  394. disp_name = disp_dfo_setting[i].name;
  395. disp_value = disp_dfo_setting[i].value;
  396. if (!strcmp(disp_name, string)) {
  397. *value = disp_value;
  398. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  399. return 0;
  400. }
  401. }
  402. return 0;
  403. }
  404. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  405. int primary_display_is_lcm_connected(void)
  406. {
  407. return pgc->plcm->is_connected;
  408. }
  409. const char* primary_display_get_lcm_name(void)
  410. {
  411. return disp_lcm_get_name(pgc->plcm);
  412. }
  413. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  414. {
  415. if (pgc->plcm) {
  416. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  417. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  418. // otherwise we will have a panic in lk(root cause unknown).
  419. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  420. DISPERR("Invalid resolution: %dx%d\n", width, height);
  421. return -1;
  422. }
  423. if (primary_display_is_video_mode()) {
  424. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  425. return -1;
  426. }
  427. pgc->plcm->params->width = width;
  428. pgc->plcm->params->height = height;
  429. return 0;
  430. } else {
  431. return -1;
  432. }
  433. }
  434. int primary_display_init(char *lcm_name)
  435. {
  436. DISPFUNC();
  437. DISP_STATUS ret = DISP_STATUS_OK;
  438. LCM_PARAMS *lcm_param = NULL;
  439. dpmgr_init();
  440. #ifndef DDP_LK_BOOT
  441. mutex_init(&(pgc->lock));
  442. #endif
  443. _primary_path_lock();
  444. if (pgc->plcm == NULL)
  445. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  446. if (pgc->plcm == NULL) {
  447. DISPCHECK("disp_lcm_probe returns null\n");
  448. ret = DISP_STATUS_ERROR;
  449. goto done;
  450. } else {
  451. DISPCHECK("disp_lcm_probe SUCCESS\n");
  452. }
  453. lcm_param = disp_lcm_get_params(pgc->plcm);
  454. if (lcm_param == NULL) {
  455. DISPERR("get lcm params FAILED\n");
  456. ret = DISP_STATUS_ERROR;
  457. goto done;
  458. }
  459. if (primary_display_mode == DIRECT_LINK_MODE) {
  460. _build_path_direct_link();
  461. DISPCHECK("primary display is DIRECT LINK MODE\n");
  462. } else if (primary_display_mode == DECOUPLE_MODE) {
  463. _build_path_decouple();
  464. DISPCHECK("primary display is DECOUPLE MODE\n");
  465. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  466. _build_path_single_layer();
  467. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  468. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  469. _build_path_debug_rdma1_dsi0();
  470. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  471. } else {
  472. DISPCHECK("primary display mode is WRONG\n");
  473. }
  474. _build_cmdq_trigger_loop();
  475. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  476. _start_cmdq_trigger_loop();
  477. DISPCHECK("primary display START cmdq trigger loop finished\n");
  478. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  479. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  480. disp_ddp_path_config data_config;
  481. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  482. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  483. data_config.dst_w = disp_lcm_width(pgc->plcm);
  484. data_config.dst_h = disp_lcm_height(pgc->plcm);
  485. if (lcm_param->type == LCM_TYPE_DSI) {
  486. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  487. data_config.lcm_bpp = 24;
  488. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  489. data_config.lcm_bpp = 16;
  490. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  491. data_config.lcm_bpp = 18;
  492. } else if (lcm_param->type == LCM_TYPE_DPI) {
  493. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  494. data_config.lcm_bpp = 24;
  495. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  496. data_config.lcm_bpp = 16;
  497. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  498. data_config.lcm_bpp = 18;
  499. }
  500. data_config.dst_dirty = 1;
  501. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  502. ret = disp_lcm_init(pgc->plcm);
  503. if (primary_display_is_video_mode()) {
  504. if (lcm_param->dsi.lfr_enable == 1) {
  505. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  506. } else {
  507. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  508. }
  509. } else {
  510. }
  511. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  512. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  513. pgc->state = 1;
  514. display_init = 1;
  515. done:
  516. _primary_path_unlock();
  517. return ret;
  518. }
  519. // register rdma done event
  520. int primary_display_wait_for_idle(void)
  521. {
  522. DISP_STATUS ret = DISP_STATUS_OK;
  523. DISPFUNC();
  524. _primary_path_lock();
  525. _primary_path_unlock();
  526. return ret;
  527. }
  528. int primary_display_wait_for_dump(void)
  529. {
  530. return 0;
  531. }
  532. static long int get_current_time_us(void)
  533. {
  534. return get_timer(0);
  535. }
  536. int priamry_display_wait_for_vsync(void)
  537. {
  538. int ret = 0;
  539. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  540. if (ret == -2) {
  541. DISPCHECK("vsync for primary display path not enabled yet\n");
  542. return -1;
  543. }
  544. // pgc->last_vsync_tick = get_current_time_us();
  545. pgc->last_vsync_tick = 0;
  546. return 0;
  547. }
  548. int primary_display_suspend(void)
  549. {
  550. DISP_STATUS ret = DISP_STATUS_OK;
  551. if (display_init == 0) {
  552. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  553. return -1;
  554. }
  555. DISPFUNC();
  556. _primary_path_lock();
  557. disp_lcm_suspend(pgc->plcm);
  558. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  559. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  560. #ifndef DDP_LK_BOOT
  561. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  562. #endif
  563. pgc->state = 0;
  564. _primary_path_unlock();
  565. return ret;
  566. }
  567. int primary_display_resume(void)
  568. {
  569. DISP_STATUS ret = DISP_STATUS_OK;
  570. DISPFUNC();
  571. _primary_path_lock();
  572. disp_path_clock_on("Primary Display Path");
  573. pgc->state = 1;
  574. _primary_path_unlock();
  575. return ret;
  576. }
  577. int primary_display_is_alive(void)
  578. {
  579. unsigned int temp = 0;
  580. DISPFUNC();
  581. _primary_path_lock();
  582. temp = pgc->state;
  583. _primary_path_unlock();
  584. return temp;
  585. }
  586. int primary_display_is_sleepd(void)
  587. {
  588. unsigned int temp = 0;
  589. DISPFUNC();
  590. _primary_path_lock();
  591. temp = !pgc->state;
  592. _primary_path_unlock();
  593. return temp;
  594. }
  595. #ifdef MTK_ROUND_CORNER_SUPPORT
  596. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  597. {
  598. if (pgc->plcm == NULL) {
  599. return NULL;
  600. }
  601. if (pgc->plcm->params) {
  602. return &(pgc->plcm->params->round_corner_params);
  603. } else {
  604. DISPERR("lcm_params is null!\n");
  605. return NULL;
  606. }
  607. }
  608. int disp_get_round_corner_size(void)
  609. {
  610. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  611. int pitch = DISP_GetScreenWidth();
  612. int size = 0;
  613. if (corner_params) {
  614. if (corner_params->round_corner_en) {
  615. if (corner_params->full_content)
  616. size = (corner_params->h + corner_params->h_bot) * pitch * 2;
  617. else
  618. size = corner_params->h * pitch * 2 * 2;
  619. } else
  620. DISPERR("corner_params is null!\n");
  621. }
  622. return size;
  623. }
  624. #endif
  625. int primary_display_get_width(void)
  626. {
  627. if (pgc->plcm == NULL) {
  628. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  629. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  630. if (pgc->plcm == NULL)
  631. return 0;
  632. }
  633. if (pgc->plcm->params) {
  634. return pgc->plcm->params->width;
  635. } else {
  636. DISPERR("lcm_params is null!\n");
  637. return 0;
  638. }
  639. }
  640. int primary_display_get_height(void)
  641. {
  642. if (pgc->plcm == NULL) {
  643. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  644. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  645. if (pgc->plcm == NULL)
  646. return 0;
  647. }
  648. if (pgc->plcm->params) {
  649. return pgc->plcm->params->height;
  650. } else {
  651. DISPERR("lcm_params is null!\n");
  652. return 0;
  653. }
  654. }
  655. int primary_display_get_bpp(void)
  656. {
  657. return 32;
  658. }
  659. int primary_display_get_info(void *dispif_info)
  660. {
  661. #if 0
  662. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  663. switch (pgc->lcm_param->type) {
  664. case LCM_TYPE_DBI: {
  665. dispif_info->displayType = DISPIF_TYPE_DBI;
  666. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  667. dispif_info->isHwVsyncAvailable = 1;
  668. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  669. break;
  670. }
  671. case LCM_TYPE_DPI: {
  672. dispif_info->displayType = DISPIF_TYPE_DPI0;
  673. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  674. dispif_info->isHwVsyncAvailable = 1;
  675. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  676. break;
  677. }
  678. case LCM_TYPE_DSI: {
  679. dispif_info->displayType = DISPIF_TYPE_DSI0;
  680. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  681. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  682. dispif_info->isHwVsyncAvailable = 1;
  683. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  684. } else {
  685. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  686. dispif_info->isHwVsyncAvailable = 1;
  687. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  688. }
  689. break;
  690. }
  691. default:
  692. break;
  693. }
  694. #ifdef MY_TODO
  695. #error
  696. if (disp_if_drv->get_panel_color_format()) {
  697. switch (disp_if_drv->get_panel_color_format()) {
  698. case PANEL_COLOR_FORMAT_RGB565:
  699. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  700. case PANEL_COLOR_FORMAT_RGB666:
  701. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  702. case PANEL_COLOR_FORMAT_RGB888:
  703. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  704. default:
  705. break;
  706. }
  707. }
  708. #endif
  709. dispif_info->displayWidth = primary_display_get_width();
  710. dispif_info->displayHeight = primary_display_get_height();
  711. #ifdef MY_TODO
  712. #error
  713. dispif_info->vsyncFPS = lcd_fps;
  714. #endif
  715. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  716. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  717. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  718. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  719. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  720. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  721. } else {
  722. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  723. }
  724. dispif_info->isConnected = 1;
  725. #ifdef MY_TODO
  726. #error
  727. {
  728. LCM_PARAMS lcm_params_temp;
  729. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  730. if (lcm_drv) {
  731. lcm_drv->get_params(&lcm_params_temp);
  732. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  733. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  734. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  735. } else {
  736. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  737. }
  738. }
  739. #endif
  740. #endif
  741. return 0;
  742. }
  743. int primary_display_get_pages(void)
  744. {
  745. return 3;
  746. }
  747. int primary_display_config_output()
  748. {
  749. return 0;
  750. }
  751. int primary_display_diagnose(void)
  752. {
  753. int ret = 0;
  754. dpmgr_check_status(pgc->dpmgr_handle);
  755. return ret;
  756. }
  757. int primary_display_trigger(int blocking)
  758. {
  759. int ret = 0;
  760. DISPFUNC();
  761. int x=0, y=0;
  762. int width = 0, height =0;
  763. x = disp_lcm_x(pgc->plcm);
  764. y = disp_lcm_y(pgc->plcm);
  765. width = disp_lcm_width(pgc->plcm);
  766. height = disp_lcm_height(pgc->plcm);
  767. _primary_path_lock();
  768. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  769. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  770. if (primary_display_is_video_mode()) {
  771. _primary_path_unlock();
  772. return 0;
  773. }
  774. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  775. }
  776. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  777. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  778. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  779. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  780. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  781. }
  782. //_set_cmdq_config_handle_dirty();
  783. //_reset_cmdq_config_handle();
  784. //if(blocking)
  785. {
  786. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  787. }
  788. } else if (pgc->mode == DECOUPLE_MODE) {
  789. DISPCHECK("trigger mode: DECOUPLE\n");
  790. if (pgc->need_trigger_overlay) {
  791. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  792. if (blocking) {
  793. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  794. }
  795. } else {
  796. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  797. // this request of trigger should be called by AAL or ovl2mem done event
  798. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  799. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  800. }
  801. _set_cmdq_config_handle_dirty();
  802. _reset_cmdq_config_handle();
  803. if (blocking) {
  804. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  805. }
  806. }
  807. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  808. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  809. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  810. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  811. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  812. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  813. }
  814. if (blocking) {
  815. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  816. }
  817. } else {
  818. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  819. }
  820. _primary_path_unlock();
  821. //primary_display_diagnose();
  822. return ret;
  823. }
  824. int primary_display_config_input(disp_input_config* input)
  825. {
  826. int ret = 0;
  827. DISPFUNC();
  828. disp_ddp_path_config data_config;
  829. // all dirty should be cleared in dpmgr_path_get_last_config()
  830. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  831. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  832. data_config.dst_dirty = 0;
  833. data_config.ovl_dirty = 0;
  834. data_config.rdma_dirty = 0;
  835. data_config.wdma_dirty = 0;
  836. _primary_path_lock();
  837. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  838. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  839. if (primary_display_is_video_mode()) {
  840. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  841. }
  842. }
  843. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  844. data_config.ovl_dirty = 1;
  845. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  846. // this is used for decouple mode, to indicate whether we need to trigger ovl
  847. pgc->need_trigger_overlay = 1;
  848. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  849. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  850. data_config.rdma_dirty= 1;
  851. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  852. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  853. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  854. data_config.rdma_dirty= 1;
  855. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  856. // TODO: should use wait_event_timeout_or_idle
  857. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  858. }
  859. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  860. } else {
  861. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  862. }
  863. _primary_path_unlock();
  864. return ret;
  865. }
  866. int primary_display_is_video_mode(void)
  867. {
  868. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  869. return disp_lcm_is_video_mode(pgc->plcm);
  870. }
  871. int primary_display_get_vsync_interval(void)
  872. {
  873. int ret = 0;
  874. unsigned int time0 = 0;
  875. unsigned int time1 = 0;
  876. unsigned int lcd_time = 0;
  877. if (pgc->plcm->is_connected == false)
  878. goto fail;
  879. pgc->plcm->is_connected = false;
  880. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  881. if (ret <= 0)
  882. goto fail;
  883. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  884. if (ret <= 0)
  885. goto fail;
  886. // because we are polling irq status, so the first event should be ignored
  887. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  888. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  889. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  890. if (ret <= 0)
  891. goto fail;
  892. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  893. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  894. if (ret > 0) {
  895. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  896. } else
  897. goto fail;
  898. lcd_time = (time1 - time0)/2;
  899. pgc->plcm->is_connected = true;
  900. if (0 != lcd_time)
  901. return (100000000/lcd_time);
  902. else
  903. return (6000);
  904. fail:
  905. DISPERR("wait event fail\n");
  906. return 0;
  907. }
  908. int primary_display_setbacklight(unsigned int level)
  909. {
  910. DISPMSG("lk %s level=%d\n",__func__,level);
  911. int ret=0;
  912. if (pgc->dpmgr_handle == NULL) {
  913. DISPCHECK("lk set backlight early!\n");
  914. return 0;
  915. }
  916. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  917. DISPCHECK("primary display path is busy\n");
  918. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  919. DISPCHECK("wait frame done ret:%d\n", ret);
  920. }
  921. disp_lcm_set_backlight(pgc->plcm,level);
  922. return 0;
  923. }
  924. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  925. /***********************/
  926. /*****Legacy DISP API*****/
  927. /***********************/
  928. UINT32 DISP_GetScreenWidth(void)
  929. {
  930. return primary_display_get_width();
  931. }
  932. UINT32 DISP_GetScreenHeight(void)
  933. {
  934. return primary_display_get_height();
  935. }
  936. UINT32 DISP_GetActiveHeight(void)
  937. {
  938. if (pgc->plcm == NULL) {
  939. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  940. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  941. if (pgc->plcm == NULL)return 0;
  942. }
  943. if (pgc->plcm->params) {
  944. return pgc->plcm->params->physical_height;
  945. } else {
  946. DISPERR("lcm_params is null!\n");
  947. return 0;
  948. }
  949. }
  950. UINT32 DISP_GetActiveWidth(void)
  951. {
  952. if (pgc->plcm == NULL) {
  953. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  954. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  955. if (pgc->plcm == NULL)return 0;
  956. }
  957. if (pgc->plcm->params) {
  958. return pgc->plcm->params->physical_width;
  959. } else {
  960. DISPERR("lcm_params is null!\n");
  961. return 0;
  962. }
  963. }
  964. int primary_display_capture_framebuffer(unsigned int *pbuf)
  965. {
  966. return 0;
  967. }
  968. UINT32 DISP_GetPanelBPP(void)
  969. {
  970. #if 0
  971. PANEL_COLOR_FORMAT fmt;
  972. disp_drv_init_context();
  973. if (disp_if_drv->get_panel_color_format == NULL) {
  974. return DISP_STATUS_NOT_IMPLEMENTED;
  975. }
  976. fmt = disp_if_drv->get_panel_color_format();
  977. switch (fmt) {
  978. case PANEL_COLOR_FORMAT_RGB332:
  979. return 8;
  980. case PANEL_COLOR_FORMAT_RGB444:
  981. return 12;
  982. case PANEL_COLOR_FORMAT_RGB565:
  983. return 16;
  984. case PANEL_COLOR_FORMAT_RGB666:
  985. return 18;
  986. case PANEL_COLOR_FORMAT_RGB888:
  987. return 24;
  988. default:
  989. return 0;
  990. }
  991. #endif
  992. return 0;
  993. }
  994. UINT32 DISP_GetScreenBpp(void)
  995. {
  996. return disp_fb_bpp;
  997. }
  998. UINT32 DISP_GetPages(void)
  999. {
  1000. return disp_fb_pages; // Double Buffers
  1001. }
  1002. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1003. #define DAL_BPP (2)
  1004. #define DAL_WIDTH (DISP_GetScreenWidth())
  1005. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1006. UINT32 DAL_GetLayerSize(void)
  1007. {
  1008. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1009. }
  1010. UINT32 DISP_GetFBRamSize(void)
  1011. {
  1012. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1013. }
  1014. unsigned int DISP_GetVRamSize(void)
  1015. {
  1016. static UINT32 vramSize = 0;
  1017. unsigned int fb_ram_size =0;
  1018. //FB RAM(n blocks)+(Assert layer size)
  1019. if (0 == vramSize) {
  1020. vramSize = DISP_GetFBRamSize();
  1021. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1022. fb_ram_size = vramSize;
  1023. vramSize += DAL_GetLayerSize();
  1024. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1025. #ifdef MTK_ROUND_CORNER_SUPPORT
  1026. fb_ram_size = vramSize;
  1027. vramSize += disp_get_round_corner_size();
  1028. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1029. #endif
  1030. #if 0
  1031. if (g_is_64bit_kernel) {
  1032. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1033. } else {
  1034. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1035. }
  1036. #else
  1037. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1038. #endif
  1039. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1040. }
  1041. return vramSize;
  1042. }