primary_display.c 36 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/ddp_path.h>
  43. #include <platform/disp_lcm.h>
  44. #include <dev/mrdump.h>
  45. #include <platform/ram_console.h>
  46. //#include<linux/timer.h>
  47. #define DDP_LK_BOOT
  48. #ifndef HZ
  49. #define HZ 100
  50. #endif
  51. #define LCM_MAX_WIDTH 1920
  52. #define LCM_MAX_HEIGHT 1080
  53. #ifdef DDP_LK_BOOT
  54. typedef void * cmdqRecHandle;
  55. #endif
  56. #define ALIGN_TO(x, n) \
  57. (((x) + ((n) - 1)) & ~((n) - 1))
  58. int primary_display_use_cmdq = CMDQ_DISABLE;
  59. int primary_display_use_m4u = 1;
  60. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  61. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  62. static UINT32 disp_fb_pages = 3; ///double buffer
  63. static UINT32 display_init;
  64. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  65. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  66. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  67. extern void video_printf(const char *fmt, ...);
  68. extern void disp_path_clock_on(char *str);
  69. typedef struct _disp_dfo_item {
  70. char name[32];
  71. int value;
  72. } disp_dfo_item_t;
  73. static disp_dfo_item_t disp_dfo_setting[] = {
  74. {"LCM_FAKE_WIDTH", 0},
  75. {"LCM_FAKE_HEIGHT", 0},
  76. {"DISP_DEBUG_SWITCH", 0}
  77. };
  78. typedef struct {
  79. int state;
  80. int need_trigger_overlay;
  81. DISP_PRIMARY_PATH_MODE mode;
  82. unsigned int last_vsync_tick;
  83. #ifndef DDP_LK_BOOT
  84. struct mutex lock;
  85. #endif
  86. disp_lcm_handle * plcm;
  87. cmdqRecHandle cmdq_handle_config;
  88. cmdqRecHandle cmdq_handle_trigger;
  89. disp_path_handle dpmgr_handle;
  90. disp_path_handle ovl2mem_path_handle;
  91. } display_primary_path_context;
  92. #define pgc _get_context()
  93. static display_primary_path_context* _get_context(void)
  94. {
  95. static int is_context_inited = 0;
  96. static display_primary_path_context g_context;
  97. if (!is_context_inited) {
  98. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  99. is_context_inited = 1;
  100. }
  101. return &g_context;
  102. }
  103. static void _primary_path_lock(void)
  104. {
  105. #ifndef DDP_LK_BOOT
  106. disp_sw_mutex_lock(&(pgc->lock));
  107. #endif
  108. }
  109. static void _primary_path_unlock(void)
  110. {
  111. #ifndef DDP_LK_BOOT
  112. disp_sw_mutex_unlock(&(pgc->lock));
  113. #endif
  114. }
  115. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  116. {
  117. if (plcm == NULL) {
  118. DISPERR("plcm is null\n");
  119. return DISP_MODULE_UNKNOWN;
  120. }
  121. if (plcm->params->type == LCM_TYPE_DSI) {
  122. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  123. return DISP_MODULE_DSI0;
  124. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  125. return DISP_MODULE_DSI1;
  126. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  127. return DISP_MODULE_DSIDUAL;
  128. } else {
  129. return DISP_MODULE_DSI0;
  130. }
  131. } else if (plcm->params->type == LCM_TYPE_DPI) {
  132. return DISP_MODULE_UNKNOWN;
  133. } else {
  134. DISPERR("can't find primary path dst module\n");
  135. return DISP_MODULE_UNKNOWN;
  136. }
  137. }
  138. static int _build_path_direct_link(void)
  139. {
  140. int ret = 0;
  141. DISP_MODULE_ENUM dst_module = 0;
  142. DISPFUNC();
  143. pgc->mode = DIRECT_LINK_MODE;
  144. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  145. if (pgc->dpmgr_handle) {
  146. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  147. } else {
  148. DISPCHECK("dpmgr create path FAIL\n");
  149. return -1;
  150. }
  151. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  152. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  153. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  154. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  155. return ret;
  156. }
  157. static int _build_path_decouple(void)
  158. {
  159. return 0;
  160. }
  161. static int _build_path_single_layer(void)
  162. {
  163. return 0;
  164. }
  165. static int _build_path_debug_rdma1_dsi0(void)
  166. {
  167. return 0;
  168. }
  169. static void _build_cmdq_trigger_loop(void)
  170. {
  171. #ifndef DDP_LK_BOOT
  172. int ret = 0;
  173. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  174. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  175. cmdqRecReset(pgc->cmdq_handle_trigger);
  176. if (primary_display_is_video_mode()) {
  177. // wait and clear stream_done
  178. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  179. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  180. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  181. } else {
  182. // only in DSI Command mode we need to wait these
  183. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  184. // no internal te on fpga now.
  185. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  186. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  187. // block config threads, we'll about to update frame
  188. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  189. // only in DSI command mode we need to enable mutex explicitly
  190. // WRITE mutex enable
  191. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  192. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  193. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  194. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  195. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  196. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  197. // polling DSI idle
  198. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  199. // polling wdma frame done
  200. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  201. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  202. /*********************/
  203. /***build cmdq finished***/
  204. /*********************/
  205. // TODO:
  206. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  207. // RUN forever!!!!
  208. BUG_ON(ret < 0);
  209. }
  210. #endif
  211. }
  212. static void _start_cmdq_trigger_loop(void)
  213. {
  214. #ifndef DDP_LK_BOOT
  215. int ret = 0;
  216. // this should be called only once because trigger loop will nevet stop
  217. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  218. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  219. #endif
  220. }
  221. static void _set_cmdq_config_handle_dirty(void)
  222. {
  223. #ifndef DDP_LK_BOOT
  224. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  225. cmdqRecFlush(pgc->cmdq_handle_config);
  226. #endif
  227. }
  228. static void _reset_cmdq_config_handle(void)
  229. {
  230. #ifndef DDP_LK_BOOT
  231. cmdqRecReset(pgc->cmdq_handle_config);
  232. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  233. #endif
  234. }
  235. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  236. {
  237. if (src && dst) {
  238. dst->inputFormat = src->fmt;
  239. dst->address = src->addr;
  240. dst->width = src->src_w;
  241. dst->height = src->src_h;
  242. dst->pitch = src->src_pitch;
  243. return 0;
  244. } else {
  245. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  246. return -1;
  247. }
  248. }
  249. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  250. {
  251. if (src && dst) {
  252. dst->layer = src->layer;
  253. dst->layer_en = src->layer_en;
  254. dst->fmt = src->fmt;
  255. dst->addr = src->addr;
  256. dst->vaddr = src->vaddr;
  257. dst->src_x = src->src_x;
  258. dst->src_y = src->src_y;
  259. dst->src_w = src->src_w;
  260. dst->src_h = src->src_h;
  261. dst->src_pitch = src->src_pitch;
  262. dst->dst_x = src->dst_x;
  263. dst->dst_y = src->dst_y;
  264. dst->dst_w = src->dst_w;
  265. dst->dst_h = src->dst_h;
  266. dst->keyEn = src->keyEn;
  267. dst->key = src->key;
  268. dst->aen = src->aen;
  269. dst->alpha = src->alpha;
  270. dst->isDirty = src->isDirty;
  271. dst->buff_idx = src->buff_idx;
  272. dst->identity = src->identity;
  273. dst->connected_type = src->connected_type;
  274. dst->security = src->security;
  275. return 0;
  276. } else {
  277. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  278. return -1;
  279. }
  280. }
  281. void _dump_lcm_info_by_video_printf(void)
  282. {
  283. LCM_DRIVER *l = NULL;
  284. LCM_PARAMS *p = NULL;
  285. disp_lcm_handle *plcm = pgc->plcm;
  286. if (plcm == NULL) {
  287. DISPERR("plcm is null\n");
  288. return;
  289. }
  290. l = plcm->drv;
  291. p = plcm->params;
  292. if (l && p) {
  293. video_printf("[LCM], name: %s\n", l->name);
  294. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  295. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  296. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  297. switch (p->lcm_if) {
  298. case LCM_INTERFACE_DSI0:
  299. video_printf("[LCM] interface: DSI0\n");
  300. break;
  301. case LCM_INTERFACE_DSI1:
  302. video_printf("[LCM] interface: DSI1\n");
  303. break;
  304. case LCM_INTERFACE_DPI0:
  305. video_printf("[LCM] interface: DPI0\n");
  306. break;
  307. case LCM_INTERFACE_DPI1:
  308. video_printf("[LCM] interface: DPI1\n");
  309. break;
  310. case LCM_INTERFACE_DBI0:
  311. video_printf("[LCM] interface: DBI0\n");
  312. break;
  313. default:
  314. video_printf("[LCM] interface: unknown\n");
  315. break;
  316. }
  317. switch (p->type) {
  318. case LCM_TYPE_DBI:
  319. video_printf("[LCM] Type: DBI\n");
  320. break;
  321. case LCM_TYPE_DSI:
  322. video_printf("[LCM] Type: DSI\n");
  323. break;
  324. case LCM_TYPE_DPI:
  325. video_printf("[LCM] Type: DPI\n");
  326. break;
  327. default:
  328. video_printf("[LCM] TYPE: unknown\n");
  329. break;
  330. }
  331. if (p->type == LCM_TYPE_DSI) {
  332. switch (p->dsi.mode) {
  333. case CMD_MODE:
  334. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  335. break;
  336. case SYNC_PULSE_VDO_MODE:
  337. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  338. break;
  339. case SYNC_EVENT_VDO_MODE:
  340. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  341. break;
  342. case BURST_VDO_MODE:
  343. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  344. break;
  345. default:
  346. video_printf("[LCM] DSI Mode: Unknown\n");
  347. break;
  348. }
  349. }
  350. if (p->type == LCM_TYPE_DSI) {
  351. video_printf("[LCM] LANE_NUM: %d, data_format: (%d,%d,%d,%d)\n", p->dsi.LANE_NUM,
  352. p->dsi.data_format.color_order, p->dsi.data_format.format,
  353. p->dsi.data_format.padding, p->dsi.data_format.trans_seq);
  354. #ifdef MY_TODO
  355. #error
  356. #endif
  357. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  358. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  359. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  360. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  361. }
  362. }
  363. return;
  364. }
  365. unsigned int mt_disp_parse_dfo_setting(void)
  366. {
  367. unsigned int i, j=0 ;
  368. char tmp[11];
  369. char *buffer = NULL;
  370. char *ptr = NULL;
  371. buffer = (char *)get_env("DFO");
  372. DISPMSG("env buffer = %s\n", buffer);
  373. if (buffer != NULL) {
  374. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  375. j = 0;
  376. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  377. ptr = strstr(buffer, disp_dfo_setting[i].name);
  378. if (ptr == NULL) continue;
  379. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  380. do {} while ((*ptr++) != ',');
  381. do {tmp[j++] = *ptr++;}
  382. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  383. disp_dfo_setting[i].value = atoi((const char*)tmp);
  384. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  385. }
  386. } else {
  387. DISPMSG("env buffer = NULL\n");
  388. }
  389. return 0;
  390. }
  391. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  392. {
  393. char *disp_name;
  394. int disp_value;
  395. unsigned int i = 0;
  396. if (string == NULL)
  397. return -1;
  398. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  399. disp_name = disp_dfo_setting[i].name;
  400. disp_value = disp_dfo_setting[i].value;
  401. if (!strcmp(disp_name, string)) {
  402. *value = disp_value;
  403. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  404. return 0;
  405. }
  406. }
  407. return 0;
  408. }
  409. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  410. int primary_display_is_lcm_connected(void)
  411. {
  412. return pgc->plcm->is_connected;
  413. }
  414. const char* primary_display_get_lcm_name(void)
  415. {
  416. return disp_lcm_get_name(pgc->plcm);
  417. }
  418. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  419. {
  420. if (pgc->plcm) {
  421. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  422. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  423. // otherwise we will have a panic in lk(root cause unknown).
  424. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  425. DISPERR("Invalid resolution: %dx%d\n", width, height);
  426. return -1;
  427. }
  428. if (primary_display_is_video_mode()) {
  429. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  430. return -1;
  431. }
  432. pgc->plcm->params->width = width;
  433. pgc->plcm->params->height = height;
  434. return 0;
  435. } else {
  436. return -1;
  437. }
  438. }
  439. int primary_display_init(char *lcm_name)
  440. {
  441. DISPFUNC();
  442. DISP_STATUS ret = DISP_STATUS_OK;
  443. LCM_PARAMS *lcm_param = NULL;
  444. dpmgr_init();
  445. #ifndef DDP_LK_BOOT
  446. mutex_init(&(pgc->lock));
  447. #endif
  448. _primary_path_lock();
  449. if (pgc->plcm == NULL)
  450. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  451. if (pgc->plcm == NULL) {
  452. DISPCHECK("disp_lcm_probe returns null\n");
  453. ret = DISP_STATUS_ERROR;
  454. goto done;
  455. } else {
  456. DISPCHECK("disp_lcm_probe SUCCESS\n");
  457. }
  458. lcm_param = disp_lcm_get_params(pgc->plcm);
  459. if (lcm_param == NULL) {
  460. DISPERR("get lcm params FAILED\n");
  461. ret = DISP_STATUS_ERROR;
  462. goto done;
  463. }
  464. /* insert DSC if needed */
  465. if (lcm_param->dsi.dsc_enable == 1)
  466. primary_disp_module_list_insert_dsc();
  467. if (primary_display_mode == DIRECT_LINK_MODE) {
  468. _build_path_direct_link();
  469. DISPCHECK("primary display is DIRECT LINK MODE\n");
  470. } else if (primary_display_mode == DECOUPLE_MODE) {
  471. _build_path_decouple();
  472. DISPCHECK("primary display is DECOUPLE MODE\n");
  473. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  474. _build_path_single_layer();
  475. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  476. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  477. _build_path_debug_rdma1_dsi0();
  478. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  479. } else {
  480. DISPCHECK("primary display mode is WRONG\n");
  481. }
  482. _build_cmdq_trigger_loop();
  483. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  484. _start_cmdq_trigger_loop();
  485. DISPCHECK("primary display START cmdq trigger loop finished\n");
  486. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  487. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  488. disp_ddp_path_config data_config;
  489. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  490. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  491. #if defined(MTK_ROUND_CORNER_SUPPORT) && defined(DISP_HW_RC)
  492. memcpy(&(data_config.round_corner_params), &(lcm_param->round_corner_params), sizeof(LCM_ROUND_CORNER));
  493. #endif
  494. data_config.dst_w = disp_lcm_width(pgc->plcm);
  495. data_config.dst_h = disp_lcm_height(pgc->plcm);
  496. if (lcm_param->type == LCM_TYPE_DSI) {
  497. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  498. data_config.lcm_bpp = 24;
  499. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  500. data_config.lcm_bpp = 16;
  501. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  502. data_config.lcm_bpp = 18;
  503. } else if (lcm_param->type == LCM_TYPE_DPI) {
  504. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  505. data_config.lcm_bpp = 24;
  506. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  507. data_config.lcm_bpp = 16;
  508. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  509. data_config.lcm_bpp = 18;
  510. }
  511. data_config.dst_dirty = 1;
  512. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  513. ret = disp_lcm_init(pgc->plcm);
  514. if (primary_display_is_video_mode()) {
  515. if (lcm_param->dsi.lfr_enable == 1) {
  516. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  517. } else {
  518. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  519. }
  520. } else {
  521. }
  522. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  523. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  524. pgc->state = 1;
  525. display_init = 1;
  526. done:
  527. _primary_path_unlock();
  528. return ret;
  529. }
  530. // register rdma done event
  531. int primary_display_wait_for_idle(void)
  532. {
  533. DISP_STATUS ret = DISP_STATUS_OK;
  534. DISPFUNC();
  535. _primary_path_lock();
  536. _primary_path_unlock();
  537. return ret;
  538. }
  539. int primary_display_wait_for_dump(void)
  540. {
  541. return 0;
  542. }
  543. static long int get_current_time_us(void)
  544. {
  545. return get_timer(0);
  546. }
  547. int priamry_display_wait_for_vsync(void)
  548. {
  549. int ret = 0;
  550. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  551. if (ret == -2) {
  552. DISPCHECK("vsync for primary display path not enabled yet\n");
  553. return -1;
  554. }
  555. // pgc->last_vsync_tick = get_current_time_us();
  556. pgc->last_vsync_tick = 0;
  557. return 0;
  558. }
  559. int primary_display_suspend(void)
  560. {
  561. DISP_STATUS ret = DISP_STATUS_OK;
  562. if (display_init == 0) {
  563. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  564. return -1;
  565. }
  566. DISPFUNC();
  567. _primary_path_lock();
  568. disp_lcm_suspend(pgc->plcm);
  569. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  570. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  571. #ifndef DDP_LK_BOOT
  572. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  573. #endif
  574. pgc->state = 0;
  575. _primary_path_unlock();
  576. return ret;
  577. }
  578. int primary_display_resume(void)
  579. {
  580. DISP_STATUS ret = DISP_STATUS_OK;
  581. DISPFUNC();
  582. _primary_path_lock();
  583. disp_path_clock_on("Primary Display Path");
  584. pgc->state = 1;
  585. _primary_path_unlock();
  586. return ret;
  587. }
  588. int primary_display_is_alive(void)
  589. {
  590. unsigned int temp = 0;
  591. DISPFUNC();
  592. _primary_path_lock();
  593. temp = pgc->state;
  594. _primary_path_unlock();
  595. return temp;
  596. }
  597. int primary_display_is_sleepd(void)
  598. {
  599. unsigned int temp = 0;
  600. DISPFUNC();
  601. _primary_path_lock();
  602. temp = !pgc->state;
  603. _primary_path_unlock();
  604. return temp;
  605. }
  606. #if defined(MTK_ROUND_CORNER_SUPPORT) && !defined(DISP_HW_RC)
  607. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  608. {
  609. if (pgc->plcm == NULL) {
  610. return NULL;
  611. }
  612. if (pgc->plcm->params) {
  613. return &(pgc->plcm->params->round_corner_params);
  614. } else {
  615. DISPERR("lcm_params is null!\n");
  616. return NULL;
  617. }
  618. }
  619. int disp_get_round_corner_size(void)
  620. {
  621. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  622. int pitch = DISP_GetScreenWidth();
  623. int size = 0;
  624. if (corner_params) {
  625. if (corner_params->round_corner_en) {
  626. if (corner_params->full_content)
  627. size = (corner_params->h + corner_params->h_bot) * pitch * 2;
  628. else
  629. size = corner_params->h * pitch * 2 * 2;
  630. } else
  631. DISPERR("corner_params is null!\n");
  632. }
  633. return size;
  634. }
  635. #endif
  636. int primary_display_get_width(void)
  637. {
  638. if (pgc->plcm == NULL) {
  639. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  640. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  641. if (pgc->plcm == NULL)
  642. return 0;
  643. }
  644. if (pgc->plcm->params) {
  645. return pgc->plcm->params->width;
  646. } else {
  647. DISPERR("lcm_params is null!\n");
  648. return 0;
  649. }
  650. }
  651. int primary_display_get_height(void)
  652. {
  653. if (pgc->plcm == NULL) {
  654. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  655. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  656. if (pgc->plcm == NULL)
  657. return 0;
  658. }
  659. if (pgc->plcm->params) {
  660. return pgc->plcm->params->height;
  661. } else {
  662. DISPERR("lcm_params is null!\n");
  663. return 0;
  664. }
  665. }
  666. int primary_display_get_bpp(void)
  667. {
  668. return 32;
  669. }
  670. int primary_display_get_info(void *dispif_info)
  671. {
  672. #if 0
  673. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  674. switch (pgc->lcm_param->type) {
  675. case LCM_TYPE_DBI: {
  676. dispif_info->displayType = DISPIF_TYPE_DBI;
  677. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  678. dispif_info->isHwVsyncAvailable = 1;
  679. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  680. break;
  681. }
  682. case LCM_TYPE_DPI: {
  683. dispif_info->displayType = DISPIF_TYPE_DPI0;
  684. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  685. dispif_info->isHwVsyncAvailable = 1;
  686. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  687. break;
  688. }
  689. case LCM_TYPE_DSI: {
  690. dispif_info->displayType = DISPIF_TYPE_DSI0;
  691. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  692. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  693. dispif_info->isHwVsyncAvailable = 1;
  694. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  695. } else {
  696. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  697. dispif_info->isHwVsyncAvailable = 1;
  698. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  699. }
  700. break;
  701. }
  702. default:
  703. break;
  704. }
  705. #ifdef MY_TODO
  706. #error
  707. if (disp_if_drv->get_panel_color_format()) {
  708. switch (disp_if_drv->get_panel_color_format()) {
  709. case PANEL_COLOR_FORMAT_RGB565:
  710. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  711. case PANEL_COLOR_FORMAT_RGB666:
  712. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  713. case PANEL_COLOR_FORMAT_RGB888:
  714. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  715. default:
  716. break;
  717. }
  718. }
  719. #endif
  720. dispif_info->displayWidth = primary_display_get_width();
  721. dispif_info->displayHeight = primary_display_get_height();
  722. #ifdef MY_TODO
  723. #error
  724. dispif_info->vsyncFPS = lcd_fps;
  725. #endif
  726. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  727. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  728. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  729. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  730. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  731. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  732. } else {
  733. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  734. }
  735. dispif_info->isConnected = 1;
  736. #ifdef MY_TODO
  737. #error
  738. {
  739. LCM_PARAMS lcm_params_temp;
  740. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  741. if (lcm_drv) {
  742. lcm_drv->get_params(&lcm_params_temp);
  743. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  744. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  745. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  746. } else {
  747. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  748. }
  749. }
  750. #endif
  751. #endif
  752. return 0;
  753. }
  754. int primary_display_get_pages(void)
  755. {
  756. return 3;
  757. }
  758. int primary_display_config_output()
  759. {
  760. return 0;
  761. }
  762. int primary_display_diagnose(void)
  763. {
  764. int ret = 0;
  765. dpmgr_check_status(pgc->dpmgr_handle);
  766. return ret;
  767. }
  768. int __primary_display_trigger(int blocking, bool logo)
  769. {
  770. int ret = 0;
  771. DISPFUNC();
  772. int x=0, y=0;
  773. int width = 0, height =0;
  774. x = disp_lcm_x(pgc->plcm);
  775. y = disp_lcm_y(pgc->plcm);
  776. width = disp_lcm_width(pgc->plcm);
  777. height = disp_lcm_height(pgc->plcm);
  778. _primary_path_lock();
  779. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  780. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  781. if (primary_display_is_video_mode()) {
  782. #ifdef MTK_LOGO_RUNTIME_SWITCH
  783. if (logo) {
  784. DSI0_WaitNotBusyAfterTrigger(DISP_MODULE_DSI0);
  785. dpmgr_path_switch_layer(pgc->dpmgr_handle, 0, 1, primary_display_use_cmdq);
  786. DISPCHECK("switch on layer0\n");
  787. }
  788. #endif
  789. _primary_path_unlock();
  790. return 0;
  791. }
  792. #if 0
  793. /* do not use RDMA frame done status because it would not be clear
  794. * in the last trigger...
  795. */
  796. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  797. #else
  798. DSI0_WaitNotBusyAfterTrigger(DISP_MODULE_DSI0);
  799. #endif
  800. }
  801. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  802. #ifdef MTK_LOGO_RUNTIME_SWITCH
  803. if (logo) {
  804. dpmgr_path_switch_layer(pgc->dpmgr_handle, 0, 1, primary_display_use_cmdq);
  805. DISPCHECK("switch on layer0\n");
  806. }
  807. #endif
  808. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  809. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  810. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  811. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  812. }
  813. //_set_cmdq_config_handle_dirty();
  814. //_reset_cmdq_config_handle();
  815. //if(blocking)
  816. {
  817. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  818. }
  819. } else if (pgc->mode == DECOUPLE_MODE) {
  820. DISPCHECK("trigger mode: DECOUPLE\n");
  821. if (pgc->need_trigger_overlay) {
  822. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  823. if (blocking) {
  824. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  825. }
  826. } else {
  827. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  828. // this request of trigger should be called by AAL or ovl2mem done event
  829. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  830. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  831. }
  832. _set_cmdq_config_handle_dirty();
  833. _reset_cmdq_config_handle();
  834. if (blocking) {
  835. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  836. }
  837. }
  838. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  839. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  840. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  841. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  842. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  843. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  844. }
  845. if (blocking) {
  846. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  847. }
  848. } else {
  849. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  850. }
  851. _primary_path_unlock();
  852. //primary_display_diagnose();
  853. return ret;
  854. }
  855. int primary_display_trigger(int blocking)
  856. {
  857. return __primary_display_trigger(blocking, false);
  858. }
  859. int primary_display_config_input(disp_input_config* input)
  860. {
  861. int ret = 0;
  862. DISPFUNC();
  863. disp_ddp_path_config data_config;
  864. // all dirty should be cleared in dpmgr_path_get_last_config()
  865. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  866. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  867. data_config.dst_dirty = 0;
  868. data_config.ovl_dirty = 0;
  869. data_config.rdma_dirty = 0;
  870. data_config.wdma_dirty = 0;
  871. _primary_path_lock();
  872. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  873. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  874. if (primary_display_is_video_mode()) {
  875. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  876. }
  877. }
  878. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  879. data_config.ovl_dirty = 1;
  880. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  881. // this is used for decouple mode, to indicate whether we need to trigger ovl
  882. pgc->need_trigger_overlay = 1;
  883. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  884. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  885. data_config.rdma_dirty= 1;
  886. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  887. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  888. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  889. data_config.rdma_dirty= 1;
  890. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  891. // TODO: should use wait_event_timeout_or_idle
  892. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  893. }
  894. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  895. } else {
  896. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  897. }
  898. _primary_path_unlock();
  899. return ret;
  900. }
  901. int primary_display_is_video_mode(void)
  902. {
  903. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  904. return disp_lcm_is_video_mode(pgc->plcm);
  905. }
  906. int primary_display_get_vsync_interval(void)
  907. {
  908. int ret = 0;
  909. unsigned int time0 = 0;
  910. unsigned int time1 = 0;
  911. unsigned int lcd_time = 0;
  912. if (pgc->plcm->is_connected == false)
  913. goto fail;
  914. if (pgc->plcm->is_connected == false)
  915. goto fail;
  916. pgc->plcm->is_connected = false;
  917. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  918. if (ret <= 0)
  919. goto fail;
  920. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  921. if (ret <= 0)
  922. goto fail;
  923. // because we are polling irq status, so the first event should be ignored
  924. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  925. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  926. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  927. if (ret <= 0)
  928. goto fail;
  929. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  930. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  931. if (ret > 0) {
  932. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  933. } else
  934. goto fail;
  935. lcd_time = (time1 - time0)/2;
  936. pgc->plcm->is_connected = true;
  937. if (0 != lcd_time)
  938. return (100000000/lcd_time);
  939. else
  940. return (6000);
  941. fail:
  942. DISPERR("wait event fail\n");
  943. return 0;
  944. }
  945. int primary_display_setbacklight(unsigned int level)
  946. {
  947. DISPMSG("lk %s level=%d\n",__func__,level);
  948. int ret=0;
  949. if (pgc->dpmgr_handle == NULL) {
  950. DISPCHECK("lk set backlight early!\n");
  951. return 0;
  952. }
  953. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  954. DISPCHECK("primary display path is busy\n");
  955. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  956. DISPCHECK("wait frame done ret:%d\n", ret);
  957. }
  958. disp_lcm_set_backlight(pgc->plcm,level);
  959. return 0;
  960. }
  961. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  962. /***********************/
  963. /*****Legacy DISP API*****/
  964. /***********************/
  965. UINT32 DISP_GetScreenWidth(void)
  966. {
  967. #ifndef MACH_FPGA_NO_DISPLAY
  968. return primary_display_get_width();
  969. #else
  970. return LCM_MAX_WIDTH;
  971. #endif
  972. }
  973. UINT32 DISP_GetScreenHeight(void)
  974. {
  975. #ifndef MACH_FPGA_NO_DISPLAY
  976. if (mrdump_check_enable() <= MRDUMP_ALWAYS_ENABLE &&
  977. current_is_abnormal_boot())
  978. return primary_display_get_height()/8;
  979. else
  980. return primary_display_get_height();
  981. #else
  982. return LCM_MAX_HEIGHT;
  983. #endif
  984. }
  985. UINT32 DISP_GetActiveHeight(void)
  986. {
  987. if (pgc->plcm == NULL) {
  988. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  989. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  990. if (pgc->plcm == NULL)return 0;
  991. }
  992. if (pgc->plcm->params) {
  993. return pgc->plcm->params->physical_height;
  994. } else {
  995. DISPERR("lcm_params is null!\n");
  996. return 0;
  997. }
  998. }
  999. UINT32 DISP_GetActiveWidth(void)
  1000. {
  1001. if (pgc->plcm == NULL) {
  1002. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  1003. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  1004. if (pgc->plcm == NULL)return 0;
  1005. }
  1006. if (pgc->plcm->params) {
  1007. return pgc->plcm->params->physical_width;
  1008. } else {
  1009. DISPERR("lcm_params is null!\n");
  1010. return 0;
  1011. }
  1012. }
  1013. int primary_display_capture_framebuffer(unsigned int *pbuf)
  1014. {
  1015. return 0;
  1016. }
  1017. UINT32 DISP_GetPanelBPP(void)
  1018. {
  1019. #if 0
  1020. PANEL_COLOR_FORMAT fmt;
  1021. disp_drv_init_context();
  1022. if (disp_if_drv->get_panel_color_format == NULL) {
  1023. return DISP_STATUS_NOT_IMPLEMENTED;
  1024. }
  1025. fmt = disp_if_drv->get_panel_color_format();
  1026. switch (fmt) {
  1027. case PANEL_COLOR_FORMAT_RGB332:
  1028. return 8;
  1029. case PANEL_COLOR_FORMAT_RGB444:
  1030. return 12;
  1031. case PANEL_COLOR_FORMAT_RGB565:
  1032. return 16;
  1033. case PANEL_COLOR_FORMAT_RGB666:
  1034. return 18;
  1035. case PANEL_COLOR_FORMAT_RGB888:
  1036. return 24;
  1037. default:
  1038. return 0;
  1039. }
  1040. #endif
  1041. return 0;
  1042. }
  1043. UINT32 DISP_GetScreenBpp(void)
  1044. {
  1045. return disp_fb_bpp;
  1046. }
  1047. UINT32 DISP_GetPages(void)
  1048. {
  1049. return disp_fb_pages; // Double Buffers
  1050. }
  1051. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1052. //#define DAL_BPP (2)
  1053. //#define DAL_WIDTH (DISP_GetScreenWidth())
  1054. //#define DAL_HEIGHT (DISP_GetScreenHeight())
  1055. UINT32 DISP_GetFBRamSize(void)
  1056. {
  1057. UINT32 display_height = 0;
  1058. #ifndef MACH_FPGA_NO_DISPLAY
  1059. display_height = primary_display_get_height();
  1060. #else
  1061. display_height = LCM_MAX_HEIGHT;
  1062. #endif
  1063. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(display_height, MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1064. }
  1065. unsigned int DISP_GetVRamSize(void)
  1066. {
  1067. static UINT32 vramSize = 0;
  1068. unsigned int fb_ram_size =0;
  1069. //FB RAM(n blocks)+(Assert layer size)
  1070. if (0 == vramSize) {
  1071. vramSize = DISP_GetFBRamSize();
  1072. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1073. fb_ram_size = vramSize;
  1074. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1075. #if defined(MTK_ROUND_CORNER_SUPPORT) && !defined(DISP_HW_RC)
  1076. fb_ram_size = vramSize;
  1077. vramSize += disp_get_round_corner_size();
  1078. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1079. #endif
  1080. #if 0
  1081. if (g_is_64bit_kernel) {
  1082. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1083. } else {
  1084. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1085. }
  1086. #else
  1087. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1088. #endif
  1089. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1090. }
  1091. return vramSize;
  1092. }
  1093. /*for MRDUMP buffer*/
  1094. UINT32 DISP_GetMBRamSize(void)
  1095. {
  1096. static UINT32 mramSize = 0;
  1097. UINT32 width = 0;
  1098. UINT32 height = 0;
  1099. UINT32 bpp = 0;
  1100. if (0 == mramSize){
  1101. width = ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT);
  1102. if (mrdump_check_enable() <= MRDUMP_ALWAYS_ENABLE && current_is_abnormal_boot())
  1103. height = ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT);
  1104. else
  1105. height = ALIGN_TO(DISP_GetScreenHeight() / 8, MTK_FB_ALIGNMENT);
  1106. bpp = (DISP_GetScreenBpp() + 7) >> 3;
  1107. mramSize = width * height * bpp;
  1108. DISPDBG("^^ DISP_GetMBRamSize: %d, %d, %d\n", width, height, bpp);
  1109. }
  1110. DISPDBG("^^ DISP_GetMBRamSize: %u bytes\n", mramSize);
  1111. return mramSize;
  1112. }