mtk-lk/platform/mt6768/include/platform/mt6355_hw.h

/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2015. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#ifndef _LK_MT_UPMU_SW_MT6355_H_
#define _LK_MT_UPMU_SW_MT6355_H_

#define MT6355_PMIC_REG_BASE (0x0000)

#define MT6355_HWCID                            ((unsigned int)(MT6355_PMIC_REG_BASE+0x0000))
#define MT6355_SWCID                            ((unsigned int)(MT6355_PMIC_REG_BASE+0x0002))
#define MT6355_TOP_CON                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0200))
#define MT6355_TEST_OUT                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0202))
#define MT6355_TEST_CON0                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x0204))
#define MT6355_TEST_CON1                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x0206))
#define MT6355_TESTMODE_SW                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0208))
#define MT6355_PGDEBSTATUS0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x020A))
#define MT6355_PGDEBSTATU1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x020C))
#define MT6355_PGSTATUS0                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x020E))
#define MT6355_PGSTATUS1                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x0210))
#define MT6355_PSOCSTATUS                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0212))
#define MT6355_THERMALSTATUS                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0214))
#define MT6355_TOPSTATUS                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x0216))
#define MT6355_TDSEL_CON                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x0218))
#define MT6355_RDSEL_CON                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x021A))
#define MT6355_SMT_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x021C))
#define MT6355_SMT_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x021E))
#define MT6355_DRV_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0220))
#define MT6355_DRV_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0222))
#define MT6355_DRV_CON2                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0224))
#define MT6355_DRV_CON3                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0226))
#define MT6355_FILTER_CON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0228))
#define MT6355_FILTER_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x022A))
#define MT6355_TOP_STATUS                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x022C))
#define MT6355_TOP_STATUS_SET                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x022E))
#define MT6355_TOP_STATUS_CLR                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0230))
#define MT6355_TOP_SPI_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0232))
#define MT6355_TOP_SPI_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0234))
#define MT6355_TOP_TRAP                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0236))
#define MT6355_TOP_CKPDN_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0400))
#define MT6355_TOP_CKPDN_CON0_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0402))
#define MT6355_TOP_CKPDN_CON0_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0404))
#define MT6355_TOP_CKPDN_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0406))
#define MT6355_TOP_CKPDN_CON1_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0408))
#define MT6355_TOP_CKPDN_CON1_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x040A))
#define MT6355_TOP_CKPDN_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x040C))
#define MT6355_TOP_CKPDN_CON2_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x040E))
#define MT6355_TOP_CKPDN_CON2_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0410))
#define MT6355_TOP_CKPDN_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0412))
#define MT6355_TOP_CKPDN_CON3_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0414))
#define MT6355_TOP_CKPDN_CON3_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0416))
#define MT6355_TOP_CKPDN_CON4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0418))
#define MT6355_TOP_CKPDN_CON4_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x041A))
#define MT6355_TOP_CKPDN_CON4_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x041C))
#define MT6355_TOP_CKSEL_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x041E))
#define MT6355_TOP_CKSEL_CON0_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0420))
#define MT6355_TOP_CKSEL_CON0_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0422))
#define MT6355_TOP_CKSEL_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0424))
#define MT6355_TOP_CKSEL_CON2_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0426))
#define MT6355_TOP_CKSEL_CON2_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0428))
#define MT6355_TOP_CKDIVSEL_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x042A))
#define MT6355_TOP_CKDIVSEL_CON0_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x042C))
#define MT6355_TOP_CKDIVSEL_CON0_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x042E))
#define MT6355_TOP_CKHWEN_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0430))
#define MT6355_TOP_CKHWEN_CON0_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x0432))
#define MT6355_TOP_CKHWEN_CON0_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x0434))
#define MT6355_TOP_CKHWEN_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0436))
#define MT6355_TOP_CKHWEN_CON1_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x0438))
#define MT6355_TOP_CKHWEN_CON1_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x043A))
#define MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0     ((unsigned int)(MT6355_PMIC_REG_BASE+0x043C))
#define MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0_SET ((unsigned int)(MT6355_PMIC_REG_BASE+0x043E))
#define MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0_CLR ((unsigned int)(MT6355_PMIC_REG_BASE+0x0440))
#define MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0442))
#define MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1_SET ((unsigned int)(MT6355_PMIC_REG_BASE+0x0444))
#define MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1_CLR ((unsigned int)(MT6355_PMIC_REG_BASE+0x0446))
#define MT6355_TOP_CKTST_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0448))
#define MT6355_TOP_CKTST_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x044A))
#define MT6355_TOP_CLKSQ                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x044C))
#define MT6355_TOP_CLKSQ_SET                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x044E))
#define MT6355_TOP_CLKSQ_CLR                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0450))
#define MT6355_TOP_CLKSQ_RTC                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0452))
#define MT6355_TOP_CLKSQ_RTC_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0454))
#define MT6355_TOP_CLKSQ_RTC_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0456))
#define MT6355_TOP_CLK_TRIM                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0458))
#define MT6355_TOP_CLK_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x045A))
#define MT6355_TOP_CLK_CON0_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x045C))
#define MT6355_TOP_CLK_CON0_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x045E))
#define MT6355_TOP_CLK_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0460))
#define MT6355_TOP_CLK_CON1_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0462))
#define MT6355_TOP_CLK_CON1_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0464))
#define MT6355_TOP_CLK_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0466))
#define MT6355_TOP_RST_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0600))
#define MT6355_TOP_RST_CON0_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0602))
#define MT6355_TOP_RST_CON0_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0604))
#define MT6355_TOP_RST_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0606))
#define MT6355_TOP_RST_CON1_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0608))
#define MT6355_TOP_RST_CON1_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x060A))
#define MT6355_TOP_RST_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x060C))
#define MT6355_TOP_RST_MISC                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x060E))
#define MT6355_TOP_RST_MISC_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0610))
#define MT6355_TOP_RST_MISC_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0612))
#define MT6355_TOP_RST_STATUS                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0614))
#define MT6355_TOP_RST_STATUS_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0616))
#define MT6355_TOP_RST_STATUS_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0618))
#define MT6355_TOP_RST_RSV_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x061A))
#define MT6355_TOP_RST_RSV_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x061C))
#define MT6355_TOP_RST_BANK_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x061E))
#define MT6355_TOP_RST_BANK_CON0_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x0620))
#define MT6355_TOP_RST_BANK_CON0_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x0622))
#define MT6355_TOP_RST_BANK_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0624))
#define MT6355_TOP_RST_BANK_CON1_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x0626))
#define MT6355_TOP_RST_BANK_CON1_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x0628))
#define MT6355_INT_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0800))
#define MT6355_INT_CON0_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0802))
#define MT6355_INT_CON0_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0804))
#define MT6355_INT_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0806))
#define MT6355_INT_CON1_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0808))
#define MT6355_INT_CON1_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x080A))
#define MT6355_INT_CON2                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x080C))
#define MT6355_INT_CON2_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x080E))
#define MT6355_INT_CON2_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0810))
#define MT6355_INT_CON3                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0812))
#define MT6355_INT_CON3_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0814))
#define MT6355_INT_CON3_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0816))
#define MT6355_INT_CON4                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0818))
#define MT6355_INT_CON4_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x081A))
#define MT6355_INT_CON4_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x081C))
#define MT6355_INT_CON5                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x081E))
#define MT6355_INT_CON5_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0820))
#define MT6355_INT_CON5_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0822))
#define MT6355_INT_CON6                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0824))
#define MT6355_INT_CON6_SET                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0826))
#define MT6355_INT_CON6_CLR                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0828))
#define MT6355_INT_MASK_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x082A))
#define MT6355_INT_MASK_CON0_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x082C))
#define MT6355_INT_MASK_CON0_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x082E))
#define MT6355_INT_MASK_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0830))
#define MT6355_INT_MASK_CON1_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0832))
#define MT6355_INT_MASK_CON1_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0834))
#define MT6355_INT_MASK_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0836))
#define MT6355_INT_MASK_CON2_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0838))
#define MT6355_INT_MASK_CON2_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x083A))
#define MT6355_INT_MASK_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x083C))
#define MT6355_INT_MASK_CON3_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x083E))
#define MT6355_INT_MASK_CON3_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0840))
#define MT6355_INT_MASK_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0842))
#define MT6355_INT_MASK_CON4_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0844))
#define MT6355_INT_MASK_CON4_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0846))
#define MT6355_INT_MASK_CON5                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0848))
#define MT6355_INT_MASK_CON5_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x084A))
#define MT6355_INT_MASK_CON5_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x084C))
#define MT6355_INT_MASK_CON6                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x084E))
#define MT6355_INT_MASK_CON6_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0850))
#define MT6355_INT_MASK_CON6_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0852))
#define MT6355_INT_STATUS0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0854))
#define MT6355_INT_STATUS1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0856))
#define MT6355_INT_STATUS2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0858))
#define MT6355_INT_STATUS3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x085A))
#define MT6355_INT_STATUS4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x085C))
#define MT6355_INT_STATUS5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x085E))
#define MT6355_INT_STATUS6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0860))
#define MT6355_INT_RAW_STATUS0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0862))
#define MT6355_INT_RAW_STATUS1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0864))
#define MT6355_INT_RAW_STATUS2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0866))
#define MT6355_INT_RAW_STATUS3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0868))
#define MT6355_INT_RAW_STATUS4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x086A))
#define MT6355_INT_RAW_STATUS5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x086C))
#define MT6355_INT_RAW_STATUS6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x086E))
#define MT6355_INT_MISC_CON                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0870))
#define MT6355_INT_MISC_CON_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0872))
#define MT6355_INT_MISC_CON_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0874))
#define MT6355_INT_EINT_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0876))
#define MT6355_INT_EINT_CON0_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0878))
#define MT6355_INT_EINT_CON0_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x087A))
#define MT6355_INT_EINT_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x087C))
#define MT6355_INT_EINT_CON1_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x087E))
#define MT6355_INT_EINT_CON1_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0880))
#define MT6355_INT_EINT_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0882))
#define MT6355_INT_EINT_CON2_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0884))
#define MT6355_INT_EINT_CON2_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0886))
#define MT6355_INT_EINT_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0888))
#define MT6355_INT_EINT_CON3_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x088A))
#define MT6355_INT_EINT_CON3_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x088C))
#define MT6355_INT_EINT_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x088E))
#define MT6355_INT_EINT_CON4_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0890))
#define MT6355_INT_EINT_CON4_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0892))
#define MT6355_FQMTR_CON0                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0A00))
#define MT6355_FQMTR_CON1                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0A02))
#define MT6355_FQMTR_CON2                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0A04))
#define MT6355_RG_SPI_CON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C00))
#define MT6355_DEW_DIO_EN                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C02))
#define MT6355_DEW_READ_TEST                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C04))
#define MT6355_DEW_WRITE_TEST                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C06))
#define MT6355_DEW_CRC_SWRST                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C08))
#define MT6355_DEW_CRC_EN                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C0A))
#define MT6355_DEW_CRC_VAL                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C0C))
#define MT6355_DEW_DBG_MON_SEL                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C0E))
#define MT6355_DEW_CIPHER_KEY_SEL               ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C10))
#define MT6355_DEW_CIPHER_IV_SEL                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C12))
#define MT6355_DEW_CIPHER_EN                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C14))
#define MT6355_DEW_CIPHER_RDY                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C16))
#define MT6355_DEW_CIPHER_MODE                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C18))
#define MT6355_DEW_CIPHER_SWRST                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C1A))
#define MT6355_DEW_RDDMY_NO                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C1C))
#define MT6355_INT_TYPE_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C1E))
#define MT6355_INT_TYPE_CON0_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C20))
#define MT6355_INT_TYPE_CON0_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C22))
#define MT6355_INT_TYPE_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C24))
#define MT6355_INT_TYPE_CON1_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C26))
#define MT6355_INT_TYPE_CON1_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C28))
#define MT6355_INT_TYPE_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C2A))
#define MT6355_INT_TYPE_CON2_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C2C))
#define MT6355_INT_TYPE_CON2_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C2E))
#define MT6355_INT_TYPE_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C30))
#define MT6355_INT_TYPE_CON3_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C32))
#define MT6355_INT_TYPE_CON3_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C34))
#define MT6355_INT_TYPE_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C36))
#define MT6355_INT_TYPE_CON4_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C38))
#define MT6355_INT_TYPE_CON4_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C3A))
#define MT6355_INT_TYPE_CON5                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C3C))
#define MT6355_INT_TYPE_CON5_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C3E))
#define MT6355_INT_TYPE_CON5_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C40))
#define MT6355_INT_TYPE_CON6                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C42))
#define MT6355_INT_TYPE_CON6_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C44))
#define MT6355_INT_TYPE_CON6_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C46))
#define MT6355_INT_STA                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C48))
#define MT6355_RG_SPI_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C4A))
#define MT6355_RG_SPI_CON2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C4C))
#define MT6355_RG_SPI_CON3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C4E))
#define MT6355_RG_SPI_CON4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C50))
#define MT6355_RG_SPI_CON5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C52))
#define MT6355_RG_SPI_CON6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C54))
#define MT6355_RG_SPI_CON7                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C56))
#define MT6355_RG_SPI_CON8                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C58))
#define MT6355_RG_SPI_CON9                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C5A))
#define MT6355_RG_SPI_CON10                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C5C))
#define MT6355_RG_SPI_CON11                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C5E))
#define MT6355_RG_SPI_CON12                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C60))
#define MT6355_RG_SPI_CON13                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x0C62))
#define MT6355_STRUP_CON0                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E00))
#define MT6355_STRUP_CON1                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E02))
#define MT6355_STRUP_CON2                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E04))
#define MT6355_STRUP_CON3                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E06))
#define MT6355_STRUP_CON4                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E08))
#define MT6355_STRUP_CON5                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E0A))
#define MT6355_STRUP_CON6                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E0C))
#define MT6355_STRUP_CON7                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E0E))
#define MT6355_STRUP_CON8                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E10))
#define MT6355_STRUP_CON9                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E12))
#define MT6355_STRUP_CON10                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E14))
#define MT6355_STRUP_CON11                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E16))
#define MT6355_STRUP_CON12                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E18))
#define MT6355_STRUP_CON13                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E1A))
#define MT6355_STRUP_CON14                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E1C))
#define MT6355_STRUP_CON15                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E1E))
#define MT6355_STRUP_CON16                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E20))
#define MT6355_STRUP_CON17                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E22))
#define MT6355_STRUP_CON18                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E24))
#define MT6355_STRUP_CON19                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E26))
#define MT6355_STRUP_CON20                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E28))
#define MT6355_STRUP_ANA_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E2A))
#define MT6355_STRUP_ANA_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E2C))
#define MT6355_PPCCTL0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E2E))
#define MT6355_PPCCTL1                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E30))
#define MT6355_PPCCTL2                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E32))
#define MT6355_PPCCFG0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E34))
#define MT6355_PPCTST0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E36))
#define MT6355_PPCRSV0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E38))
#define MT6355_BWDTCTL0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E3A))
#define MT6355_CPSWKEY                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E3C))
#define MT6355_CPSCFG0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E3E))
#define MT6355_CPSCFG1                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E40))
#define MT6355_CPSPSA0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E42))
#define MT6355_CPSPSA1                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E44))
#define MT6355_CPSPSA2                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E46))
#define MT6355_CPSPSA3                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E48))
#define MT6355_CPSPSA4                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E4A))
#define MT6355_CPSPSA5                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E4C))
#define MT6355_CPSPSA6                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E4E))
#define MT6355_CPSPSA7                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E50))
#define MT6355_CPSPSA8                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E52))
#define MT6355_CPSPSA9                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E54))
#define MT6355_CPSPSA10                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E56))
#define MT6355_CPSPSA11                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E58))
#define MT6355_CPSDSA0                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E5A))
#define MT6355_CPSDSA1                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E5C))
#define MT6355_CPSDSA2                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E5E))
#define MT6355_CPSDSA3                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E60))
#define MT6355_CPSDSA4                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E62))
#define MT6355_CPSDSA5                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E64))
#define MT6355_CPSDSA6                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E66))
#define MT6355_CPSDSA7                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E68))
#define MT6355_CPSDSA8                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E6A))
#define MT6355_CPSDSA9                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E6C))
#define MT6355_CPSDSA10                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E6E))
#define MT6355_CPSDSA11                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E70))
#define MT6355_PORFLAG                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E72))
#define MT6355_PONSTS                           ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E74))
#define MT6355_POFFSTS                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E76))
#define MT6355_PSTSCTL                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x0E78))
#define MT6355_BUCK_ALL_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1000))
#define MT6355_BUCK_STB_CON                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1002))
#define MT6355_BUCK_SLP_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1004))
#define MT6355_BUCK_SLP_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1006))
#define MT6355_BUCK_SLP_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1008))
#define MT6355_BUCK_MINFREQ_CON                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x100A))
#define MT6355_BUCK_OC_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x100C))
#define MT6355_BUCK_OC_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x100E))
#define MT6355_BUCK_K_CON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1010))
#define MT6355_BUCK_K_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1012))
#define MT6355_BUCK_K_CON2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1014))
#define MT6355_BUCK_K_CON3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1016))
#define MT6355_BUCK_VOW_CON                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1018))
#define MT6355_BUCK_VPROC11_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x101A))
#define MT6355_BUCK_VPROC11_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x101C))
#define MT6355_BUCK_VPROC11_CON2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x101E))
#define MT6355_BUCK_VPROC11_CFG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1020))
#define MT6355_BUCK_VPROC11_CFG1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1022))
#define MT6355_BUCK_VPROC11_OP_EN               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1024))
#define MT6355_BUCK_VPROC11_OP_EN_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1026))
#define MT6355_BUCK_VPROC11_OP_EN_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1028))
#define MT6355_BUCK_VPROC11_OP_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x102A))
#define MT6355_BUCK_VPROC11_OP_CFG_SET          ((unsigned int)(MT6355_PMIC_REG_BASE+0x102C))
#define MT6355_BUCK_VPROC11_OP_CFG_CLR          ((unsigned int)(MT6355_PMIC_REG_BASE+0x102E))
#define MT6355_BUCK_VPROC11_SP_CON              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1030))
#define MT6355_BUCK_VPROC11_SP_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1032))
#define MT6355_BUCK_VPROC11_OC_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1034))
#define MT6355_BUCK_VPROC11_DBG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1036))
#define MT6355_BUCK_VPROC11_DBG1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1038))
#define MT6355_BUCK_VPROC11_DBG2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x103A))
#define MT6355_BUCK_VPROC12_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x103C))
#define MT6355_BUCK_VPROC12_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x103E))
#define MT6355_BUCK_VPROC12_CON2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1040))
#define MT6355_BUCK_VPROC12_CFG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1042))
#define MT6355_BUCK_VPROC12_CFG1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1044))
#define MT6355_BUCK_VPROC12_OP_EN               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1046))
#define MT6355_BUCK_VPROC12_OP_EN_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1048))
#define MT6355_BUCK_VPROC12_OP_EN_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x104A))
#define MT6355_BUCK_VPROC12_OP_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x104C))
#define MT6355_BUCK_VPROC12_OP_CFG_SET          ((unsigned int)(MT6355_PMIC_REG_BASE+0x104E))
#define MT6355_BUCK_VPROC12_OP_CFG_CLR          ((unsigned int)(MT6355_PMIC_REG_BASE+0x1050))
#define MT6355_BUCK_VPROC12_SP_CON              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1052))
#define MT6355_BUCK_VPROC12_SP_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1054))
#define MT6355_BUCK_VPROC12_OC_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1056))
#define MT6355_BUCK_VPROC12_DBG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1058))
#define MT6355_BUCK_VPROC12_DBG1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x105A))
#define MT6355_BUCK_VPROC12_DBG2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x105C))
#define MT6355_BUCK_VCORE_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x105E))
#define MT6355_BUCK_VCORE_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1060))
#define MT6355_BUCK_VCORE_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1062))
#define MT6355_BUCK_VCORE_CFG0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1064))
#define MT6355_BUCK_VCORE_CFG1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1066))
#define MT6355_BUCK_VCORE_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1068))
#define MT6355_BUCK_VCORE_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x106A))
#define MT6355_BUCK_VCORE_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x106C))
#define MT6355_BUCK_VCORE_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x106E))
#define MT6355_BUCK_VCORE_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1070))
#define MT6355_BUCK_VCORE_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1072))
#define MT6355_BUCK_VCORE_SP_CON                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1074))
#define MT6355_BUCK_VCORE_SP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1076))
#define MT6355_BUCK_VCORE_OC_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1078))
#define MT6355_BUCK_VCORE_DBG0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x107A))
#define MT6355_BUCK_VCORE_DBG1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x107C))
#define MT6355_BUCK_VCORE_DBG2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x107E))
#define MT6355_BUCK_VCORE_SSHUB_CON             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1080))
#define MT6355_BUCK_VGPU_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1082))
#define MT6355_BUCK_VGPU_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1084))
#define MT6355_BUCK_VGPU_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1086))
#define MT6355_BUCK_VGPU_CFG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1088))
#define MT6355_BUCK_VGPU_CFG1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x108A))
#define MT6355_BUCK_VGPU_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x108C))
#define MT6355_BUCK_VGPU_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x108E))
#define MT6355_BUCK_VGPU_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1090))
#define MT6355_BUCK_VGPU_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1092))
#define MT6355_BUCK_VGPU_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1094))
#define MT6355_BUCK_VGPU_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1096))
#define MT6355_BUCK_VGPU_SP_CON                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1098))
#define MT6355_BUCK_VGPU_SP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x109A))
#define MT6355_BUCK_VGPU_OC_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x109C))
#define MT6355_BUCK_VGPU_DBG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x109E))
#define MT6355_BUCK_VGPU_DBG1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x10A0))
#define MT6355_BUCK_VGPU_DBG2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x10A2))
#define MT6355_BUCK_VDRAM1_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10A4))
#define MT6355_BUCK_VDRAM1_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10A6))
#define MT6355_BUCK_VDRAM1_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10A8))
#define MT6355_BUCK_VDRAM1_CFG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10AA))
#define MT6355_BUCK_VDRAM1_CFG1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10AC))
#define MT6355_BUCK_VDRAM1_OP_EN                ((unsigned int)(MT6355_PMIC_REG_BASE+0x10AE))
#define MT6355_BUCK_VDRAM1_OP_EN_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x10B0))
#define MT6355_BUCK_VDRAM1_OP_EN_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x10B2))
#define MT6355_BUCK_VDRAM1_OP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10B4))
#define MT6355_BUCK_VDRAM1_OP_CFG_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x10B6))
#define MT6355_BUCK_VDRAM1_OP_CFG_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x10B8))
#define MT6355_BUCK_VDRAM1_SP_CON               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10BA))
#define MT6355_BUCK_VDRAM1_SP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10BC))
#define MT6355_BUCK_VDRAM1_OC_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10BE))
#define MT6355_BUCK_VDRAM1_DBG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10C0))
#define MT6355_BUCK_VDRAM1_DBG1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10C2))
#define MT6355_BUCK_VDRAM1_DBG2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10C4))
#define MT6355_BUCK_VDRAM2_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10C6))
#define MT6355_BUCK_VDRAM2_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10C8))
#define MT6355_BUCK_VDRAM2_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10CA))
#define MT6355_BUCK_VDRAM2_CFG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10CC))
#define MT6355_BUCK_VDRAM2_CFG1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10CE))
#define MT6355_BUCK_VDRAM2_OP_EN                ((unsigned int)(MT6355_PMIC_REG_BASE+0x10D0))
#define MT6355_BUCK_VDRAM2_OP_EN_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x10D2))
#define MT6355_BUCK_VDRAM2_OP_EN_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x10D4))
#define MT6355_BUCK_VDRAM2_OP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10D6))
#define MT6355_BUCK_VDRAM2_OP_CFG_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x10D8))
#define MT6355_BUCK_VDRAM2_OP_CFG_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x10DA))
#define MT6355_BUCK_VDRAM2_SP_CON               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10DC))
#define MT6355_BUCK_VDRAM2_SP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10DE))
#define MT6355_BUCK_VDRAM2_OC_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10E0))
#define MT6355_BUCK_VDRAM2_DBG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10E2))
#define MT6355_BUCK_VDRAM2_DBG1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10E4))
#define MT6355_BUCK_VDRAM2_DBG2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10E6))
#define MT6355_BUCK_VMODEM_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10E8))
#define MT6355_BUCK_VMODEM_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10EA))
#define MT6355_BUCK_VMODEM_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10EC))
#define MT6355_BUCK_VMODEM_CFG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10EE))
#define MT6355_BUCK_VMODEM_CFG1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x10F0))
#define MT6355_BUCK_VMODEM_OP_EN                ((unsigned int)(MT6355_PMIC_REG_BASE+0x10F2))
#define MT6355_BUCK_VMODEM_OP_EN_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x10F4))
#define MT6355_BUCK_VMODEM_OP_EN_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x10F6))
#define MT6355_BUCK_VMODEM_OP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10F8))
#define MT6355_BUCK_VMODEM_OP_CFG_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x10FA))
#define MT6355_BUCK_VMODEM_OP_CFG_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x10FC))
#define MT6355_BUCK_VMODEM_SP_CON               ((unsigned int)(MT6355_PMIC_REG_BASE+0x10FE))
#define MT6355_BUCK_VMODEM_SP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1100))
#define MT6355_BUCK_VMODEM_OC_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1102))
#define MT6355_BUCK_VMODEM_DBG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1104))
#define MT6355_BUCK_VMODEM_DBG1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1106))
#define MT6355_BUCK_VMODEM_DBG2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1108))
#define MT6355_BUCK_VMODEM_DLC_CON0             ((unsigned int)(MT6355_PMIC_REG_BASE+0x110A))
#define MT6355_BUCK_VMODEM_DLC_CON1             ((unsigned int)(MT6355_PMIC_REG_BASE+0x110C))
#define MT6355_BUCK_VMODEM_DLC_CON2             ((unsigned int)(MT6355_PMIC_REG_BASE+0x110E))
#define MT6355_BUCK_VMODEM_DLC_CON3             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1110))
#define MT6355_BUCK_VS1_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1112))
#define MT6355_BUCK_VS1_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1114))
#define MT6355_BUCK_VS1_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1116))
#define MT6355_BUCK_VS1_CFG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1118))
#define MT6355_BUCK_VS1_CFG1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x111A))
#define MT6355_BUCK_VS1_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x111C))
#define MT6355_BUCK_VS1_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x111E))
#define MT6355_BUCK_VS1_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1120))
#define MT6355_BUCK_VS1_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1122))
#define MT6355_BUCK_VS1_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1124))
#define MT6355_BUCK_VS1_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1126))
#define MT6355_BUCK_VS1_SP_CON                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1128))
#define MT6355_BUCK_VS1_SP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x112A))
#define MT6355_BUCK_VS1_OC_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x112C))
#define MT6355_BUCK_VS1_DBG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x112E))
#define MT6355_BUCK_VS1_DBG1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1130))
#define MT6355_BUCK_VS1_DBG2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1132))
#define MT6355_BUCK_VS1_VOTER                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1134))
#define MT6355_BUCK_VS1_VOTER_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1136))
#define MT6355_BUCK_VS1_VOTER_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1138))
#define MT6355_BUCK_VS1_VOTER_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x113A))
#define MT6355_BUCK_VS2_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x113C))
#define MT6355_BUCK_VS2_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x113E))
#define MT6355_BUCK_VS2_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1140))
#define MT6355_BUCK_VS2_CFG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1142))
#define MT6355_BUCK_VS2_CFG1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1144))
#define MT6355_BUCK_VS2_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1146))
#define MT6355_BUCK_VS2_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1148))
#define MT6355_BUCK_VS2_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x114A))
#define MT6355_BUCK_VS2_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x114C))
#define MT6355_BUCK_VS2_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x114E))
#define MT6355_BUCK_VS2_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1150))
#define MT6355_BUCK_VS2_SP_CON                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1152))
#define MT6355_BUCK_VS2_SP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1154))
#define MT6355_BUCK_VS2_OC_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1156))
#define MT6355_BUCK_VS2_DBG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1158))
#define MT6355_BUCK_VS2_DBG1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x115A))
#define MT6355_BUCK_VS2_DBG2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x115C))
#define MT6355_BUCK_VS2_VOTER                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x115E))
#define MT6355_BUCK_VS2_VOTER_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1160))
#define MT6355_BUCK_VS2_VOTER_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1162))
#define MT6355_BUCK_VS2_VOTER_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1164))
#define MT6355_BUCK_VPA_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1166))
#define MT6355_BUCK_VPA_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1168))
#define MT6355_BUCK_VPA_CFG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x116A))
#define MT6355_BUCK_VPA_CFG1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x116C))
#define MT6355_BUCK_VPA_OC_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x116E))
#define MT6355_BUCK_VPA_DBG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1170))
#define MT6355_BUCK_VPA_DBG1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1172))
#define MT6355_BUCK_VPA_DBG2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1174))
#define MT6355_BUCK_VPA_DLC_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1176))
#define MT6355_BUCK_VPA_DLC_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1178))
#define MT6355_BUCK_VPA_DLC_CON2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x117A))
#define MT6355_BUCK_VPA_MSFG_CON0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x117C))
#define MT6355_BUCK_VPA_MSFG_CON1               ((unsigned int)(MT6355_PMIC_REG_BASE+0x117E))
#define MT6355_BUCK_VPA_MSFG_RRATE0             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1180))
#define MT6355_BUCK_VPA_MSFG_RRATE1             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1182))
#define MT6355_BUCK_VPA_MSFG_RRATE2             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1184))
#define MT6355_BUCK_VPA_MSFG_RTHD0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1186))
#define MT6355_BUCK_VPA_MSFG_RTHD1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1188))
#define MT6355_BUCK_VPA_MSFG_RTHD2              ((unsigned int)(MT6355_PMIC_REG_BASE+0x118A))
#define MT6355_BUCK_VPA_MSFG_FRATE0             ((unsigned int)(MT6355_PMIC_REG_BASE+0x118C))
#define MT6355_BUCK_VPA_MSFG_FRATE1             ((unsigned int)(MT6355_PMIC_REG_BASE+0x118E))
#define MT6355_BUCK_VPA_MSFG_FRATE2             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1190))
#define MT6355_BUCK_VPA_MSFG_FTHD0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1192))
#define MT6355_BUCK_VPA_MSFG_FTHD1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1194))
#define MT6355_BUCK_VPA_MSFG_FTHD2              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1196))
#define MT6355_SMPS_ANA_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1200))
#define MT6355_SMPS_ANA_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1202))
#define MT6355_SMPS_ANA_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1204))
#define MT6355_SMPS_ANA_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1206))
#define MT6355_SMPS_ANA_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1208))
#define MT6355_SMPS_ANA_CON5                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x120A))
#define MT6355_SMPS_ANA_CON6                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x120C))
#define MT6355_SMPS_ANA_CON7                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x120E))
#define MT6355_SMPS_ANA_CON8                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1210))
#define MT6355_SMPS_ANA_CON9                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1212))
#define MT6355_SMPS_ANA_CON10                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1214))
#define MT6355_SMPS_ANA_CON11                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1216))
#define MT6355_SMPS_ANA_CON12                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1218))
#define MT6355_SMPS_ANA_CON13                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x121A))
#define MT6355_SMPS_ANA_CON14                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x121C))
#define MT6355_SMPS_ANA_CON15                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x121E))
#define MT6355_VPROC_ANA_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1220))
#define MT6355_VPROC_ANA_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1222))
#define MT6355_VPROC_ANA_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1224))
#define MT6355_VPROC_ANA_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1226))
#define MT6355_VPROC_ANA_CON4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1228))
#define MT6355_VPROC_ANA_CON5                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x122A))
#define MT6355_VPROC_ANA_CON6                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x122C))
#define MT6355_VPROC_ANA_CON7                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x122E))
#define MT6355_VPROC_ANA_CON8                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1230))
#define MT6355_VPROC_ANA_CON9                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1232))
#define MT6355_VPROC_ANA_CON10                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1234))
#define MT6355_VPROC_ANA_CON11                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1236))
#define MT6355_VPROC_ANA_CON12                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1238))
#define MT6355_VPROC_ANA_CON13                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x123A))
#define MT6355_VPROC_ANA_CON14                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x123C))
#define MT6355_VPROC_ANA_CON15                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x123E))
#define MT6355_VPROC_ANA_CON16                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1240))
#define MT6355_VCORE_VGPU_ANA_CON0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1242))
#define MT6355_VCORE_VGPU_ANA_CON1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1244))
#define MT6355_VCORE_VGPU_ANA_CON2              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1246))
#define MT6355_VCORE_VGPU_ANA_CON3              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1248))
#define MT6355_VCORE_VGPU_ANA_CON4              ((unsigned int)(MT6355_PMIC_REG_BASE+0x124A))
#define MT6355_VCORE_VGPU_ANA_CON5              ((unsigned int)(MT6355_PMIC_REG_BASE+0x124C))
#define MT6355_VCORE_VGPU_ANA_CON6              ((unsigned int)(MT6355_PMIC_REG_BASE+0x124E))
#define MT6355_VCORE_VGPU_ANA_CON7              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1250))
#define MT6355_VCORE_VGPU_ANA_CON8              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1252))
#define MT6355_VCORE_VGPU_ANA_CON9              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1254))
#define MT6355_VCORE_VGPU_ANA_CON10             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1256))
#define MT6355_VCORE_VGPU_ANA_CON11             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1258))
#define MT6355_VCORE_VGPU_ANA_CON12             ((unsigned int)(MT6355_PMIC_REG_BASE+0x125A))
#define MT6355_VCORE_VGPU_ANA_CON13             ((unsigned int)(MT6355_PMIC_REG_BASE+0x125C))
#define MT6355_VCORE_VGPU_ANA_CON14             ((unsigned int)(MT6355_PMIC_REG_BASE+0x125E))
#define MT6355_VCORE_VGPU_ANA_CON15             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1260))
#define MT6355_VCORE_VGPU_ANA_CON16             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1262))
#define MT6355_VDRAM1_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1264))
#define MT6355_VDRAM1_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1266))
#define MT6355_VDRAM1_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1268))
#define MT6355_VDRAM1_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x126A))
#define MT6355_VDRAM1_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x126C))
#define MT6355_VDRAM1_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x126E))
#define MT6355_VDRAM1_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1270))
#define MT6355_VDRAM1_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1272))
#define MT6355_VDRAM2_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1274))
#define MT6355_VDRAM2_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1276))
#define MT6355_VDRAM2_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1278))
#define MT6355_VDRAM2_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x127A))
#define MT6355_VDRAM2_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x127C))
#define MT6355_VDRAM2_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x127E))
#define MT6355_VDRAM2_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1280))
#define MT6355_VDRAM2_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1282))
#define MT6355_VMODEM_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1284))
#define MT6355_VMODEM_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1286))
#define MT6355_VMODEM_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1288))
#define MT6355_VMODEM_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x128A))
#define MT6355_VMODEM_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x128C))
#define MT6355_VMODEM_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x128E))
#define MT6355_VMODEM_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1290))
#define MT6355_VMODEM_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1292))
#define MT6355_VMODEM_ANA_CON8                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1294))
#define MT6355_VMODEM_ANA_CON9                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1296))
#define MT6355_VS1_ANA_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1298))
#define MT6355_VS1_ANA_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x129A))
#define MT6355_VS1_ANA_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x129C))
#define MT6355_VS1_ANA_CON3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x129E))
#define MT6355_VS1_ANA_CON4                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12A0))
#define MT6355_VS1_ANA_CON5                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12A2))
#define MT6355_VS1_ANA_CON6                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12A4))
#define MT6355_VS2_ANA_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12A6))
#define MT6355_VS2_ANA_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12A8))
#define MT6355_VS2_ANA_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12AA))
#define MT6355_VS2_ANA_CON3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12AC))
#define MT6355_VS2_ANA_CON4                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12AE))
#define MT6355_VS2_ANA_CON5                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12B0))
#define MT6355_VS2_ANA_CON6                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12B2))
#define MT6355_VPA_ANA_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12B4))
#define MT6355_VPA_ANA_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12B6))
#define MT6355_VPA_ANA_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12B8))
#define MT6355_VPA_ANA_CON3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12BA))
#define MT6355_VPA_ANA_CON4                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12BC))
#define MT6355_VPA_ANA_CON5                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x12BE))
#define MT6355_WDTDBG_CON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1400))
#define MT6355_WDTDBG_MON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1402))
#define MT6355_WDTDBG_MON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1404))
#define MT6355_WDTDBG_MON2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1406))
#define MT6355_WDTDBG_MON3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1408))
#define MT6355_WDTDBG_MON4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x140A))
#define MT6355_WDTDBG_MON5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x140C))
#define MT6355_WDTDBG_MON6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x140E))
#define MT6355_LDO_VIO28_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1600))
#define MT6355_LDO_VIO28_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1602))
#define MT6355_LDO_VIO28_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1604))
#define MT6355_LDO_VIO28_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1606))
#define MT6355_LDO_VIO28_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1608))
#define MT6355_LDO_VIO28_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x160A))
#define MT6355_LDO_VIO28_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x160C))
#define MT6355_LDO_VIO28_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x160E))
#define MT6355_LDO_VIO28_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1610))
#define MT6355_LDO_VIO28_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1612))
#define MT6355_LDO_VIO18_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1614))
#define MT6355_LDO_VIO18_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1616))
#define MT6355_LDO_VIO18_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1618))
#define MT6355_LDO_VIO18_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x161A))
#define MT6355_LDO_VIO18_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x161C))
#define MT6355_LDO_VIO18_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x161E))
#define MT6355_LDO_VIO18_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1620))
#define MT6355_LDO_VIO18_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1622))
#define MT6355_LDO_VIO18_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1624))
#define MT6355_LDO_VIO18_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1626))
#define MT6355_LDO_VUFS18_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1628))
#define MT6355_LDO_VUFS18_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x162A))
#define MT6355_LDO_VUFS18_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x162C))
#define MT6355_LDO_VUFS18_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x162E))
#define MT6355_LDO_VUFS18_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1630))
#define MT6355_LDO_VUFS18_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1632))
#define MT6355_LDO_VUFS18_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1634))
#define MT6355_LDO_VUFS18_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1636))
#define MT6355_LDO_VUFS18_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1638))
#define MT6355_LDO_VUFS18_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x163A))
#define MT6355_LDO_VA10_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x163C))
#define MT6355_LDO_VA10_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x163E))
#define MT6355_LDO_VA10_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1640))
#define MT6355_LDO_VA10_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1642))
#define MT6355_LDO_VA10_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1644))
#define MT6355_LDO_VA10_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1646))
#define MT6355_LDO_VA10_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1648))
#define MT6355_LDO_VA10_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x164A))
#define MT6355_LDO_VA10_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x164C))
#define MT6355_LDO_VA10_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x164E))
#define MT6355_LDO_VA10_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1650))
#define MT6355_LDO_VA12_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1652))
#define MT6355_LDO_VA12_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1654))
#define MT6355_LDO_VA12_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1656))
#define MT6355_LDO_VA12_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1658))
#define MT6355_LDO_VA12_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x165A))
#define MT6355_LDO_VA12_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x165C))
#define MT6355_LDO_VA12_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x165E))
#define MT6355_LDO_VA12_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1660))
#define MT6355_LDO_VA12_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1662))
#define MT6355_LDO_VA12_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1664))
#define MT6355_LDO_VA18_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1666))
#define MT6355_LDO_VA18_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1668))
#define MT6355_LDO_VA18_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x166A))
#define MT6355_LDO_VA18_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x166C))
#define MT6355_LDO_VA18_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x166E))
#define MT6355_LDO_VA18_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1670))
#define MT6355_LDO_VA18_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1672))
#define MT6355_LDO_VA18_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1674))
#define MT6355_LDO_VA18_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1676))
#define MT6355_LDO_VA18_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1678))
#define MT6355_LDO_VUSB33_CON0_0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x167A))
#define MT6355_LDO_VUSB33_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x167C))
#define MT6355_LDO_VUSB33_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x167E))
#define MT6355_LDO_VUSB33_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1680))
#define MT6355_LDO_VUSB33_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1682))
#define MT6355_LDO_VUSB33_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1684))
#define MT6355_LDO_VUSB33_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1686))
#define MT6355_LDO_VUSB33_CON0_1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1688))
#define MT6355_LDO_VUSB33_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x168A))
#define MT6355_LDO_VUSB33_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x168C))
#define MT6355_LDO_VUSB33_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x168E))
#define MT6355_LDO_VEMC_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1690))
#define MT6355_LDO_VEMC_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1692))
#define MT6355_LDO_VEMC_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1694))
#define MT6355_LDO_VEMC_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1696))
#define MT6355_LDO_VEMC_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1698))
#define MT6355_LDO_VEMC_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x169A))
#define MT6355_LDO_VEMC_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x169C))
#define MT6355_LDO_VEMC_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x169E))
#define MT6355_LDO_VEMC_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x16A0))
#define MT6355_LDO_VEMC_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x16A2))
#define MT6355_LDO_VXO22_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16A4))
#define MT6355_LDO_VXO22_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x16A6))
#define MT6355_LDO_VXO22_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16A8))
#define MT6355_LDO_VXO22_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16AA))
#define MT6355_LDO_VXO22_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x16AC))
#define MT6355_LDO_VXO22_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16AE))
#define MT6355_LDO_VXO22_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16B0))
#define MT6355_LDO_VXO22_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16B2))
#define MT6355_LDO_VXO22_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16B4))
#define MT6355_LDO_VXO22_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16B6))
#define MT6355_LDO_VXO18_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16B8))
#define MT6355_LDO_VXO18_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x16BA))
#define MT6355_LDO_VXO18_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16BC))
#define MT6355_LDO_VXO18_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16BE))
#define MT6355_LDO_VXO18_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x16C0))
#define MT6355_LDO_VXO18_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16C2))
#define MT6355_LDO_VXO18_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16C4))
#define MT6355_LDO_VXO18_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16C6))
#define MT6355_LDO_VXO18_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16C8))
#define MT6355_LDO_VXO18_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16CA))
#define MT6355_LDO_VSIM1_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16CC))
#define MT6355_LDO_VSIM1_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x16CE))
#define MT6355_LDO_VSIM1_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16D0))
#define MT6355_LDO_VSIM1_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16D2))
#define MT6355_LDO_VSIM1_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x16D4))
#define MT6355_LDO_VSIM1_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16D6))
#define MT6355_LDO_VSIM1_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16D8))
#define MT6355_LDO_VSIM1_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16DA))
#define MT6355_LDO_VSIM1_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16DC))
#define MT6355_LDO_VSIM1_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16DE))
#define MT6355_LDO_VSIM2_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16E0))
#define MT6355_LDO_VSIM2_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x16E2))
#define MT6355_LDO_VSIM2_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16E4))
#define MT6355_LDO_VSIM2_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x16E6))
#define MT6355_LDO_VSIM2_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x16E8))
#define MT6355_LDO_VSIM2_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16EA))
#define MT6355_LDO_VSIM2_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16EC))
#define MT6355_LDO_VSIM2_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16EE))
#define MT6355_LDO_VSIM2_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16F0))
#define MT6355_LDO_VSIM2_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x16F2))
#define MT6355_LDO_VCAMD1_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x16F4))
#define MT6355_LDO_VCAMD1_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x16F6))
#define MT6355_LDO_VCAMD1_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16F8))
#define MT6355_LDO_VCAMD1_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x16FA))
#define MT6355_LDO_VCAMD1_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x16FC))
#define MT6355_LDO_VCAMD1_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x16FE))
#define MT6355_LDO_VCAMD1_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1700))
#define MT6355_LDO_VCAMD1_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1702))
#define MT6355_LDO_VCAMD1_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1704))
#define MT6355_LDO_VCAMD1_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1706))
#define MT6355_LDO_VCAMD2_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1708))
#define MT6355_LDO_VCAMD2_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x170A))
#define MT6355_LDO_VCAMD2_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x170C))
#define MT6355_LDO_VCAMD2_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x170E))
#define MT6355_LDO_VCAMD2_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1710))
#define MT6355_LDO_VCAMD2_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1712))
#define MT6355_LDO_VCAMD2_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1714))
#define MT6355_LDO_VCAMD2_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1716))
#define MT6355_LDO_VCAMD2_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1718))
#define MT6355_LDO_VCAMD2_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x171A))
#define MT6355_LDO_VCAMIO_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x171C))
#define MT6355_LDO_VCAMIO_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x171E))
#define MT6355_LDO_VCAMIO_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1720))
#define MT6355_LDO_VCAMIO_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1722))
#define MT6355_LDO_VCAMIO_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1724))
#define MT6355_LDO_VCAMIO_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1726))
#define MT6355_LDO_VCAMIO_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1728))
#define MT6355_LDO_VCAMIO_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x172A))
#define MT6355_LDO_VCAMIO_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x172C))
#define MT6355_LDO_VCAMIO_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x172E))
#define MT6355_LDO_VMIPI_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1730))
#define MT6355_LDO_VMIPI_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1732))
#define MT6355_LDO_VMIPI_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1734))
#define MT6355_LDO_VMIPI_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1736))
#define MT6355_LDO_VMIPI_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1738))
#define MT6355_LDO_VMIPI_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x173A))
#define MT6355_LDO_VMIPI_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x173C))
#define MT6355_LDO_VMIPI_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x173E))
#define MT6355_LDO_VMIPI_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1740))
#define MT6355_LDO_VMIPI_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1742))
#define MT6355_LDO_VGP_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1744))
#define MT6355_LDO_VGP_OP_EN                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1746))
#define MT6355_LDO_VGP_OP_EN_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1748))
#define MT6355_LDO_VGP_OP_EN_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x174A))
#define MT6355_LDO_VGP_OP_CFG                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x174C))
#define MT6355_LDO_VGP_OP_CFG_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x174E))
#define MT6355_LDO_VGP_OP_CFG_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1750))
#define MT6355_LDO_VGP_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1752))
#define MT6355_LDO_VGP_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1754))
#define MT6355_LDO_VGP_CON3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1756))
#define MT6355_LDO_VCN33_CON0_BT                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1758))
#define MT6355_LDO_VCN33_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x175A))
#define MT6355_LDO_VCN33_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x175C))
#define MT6355_LDO_VCN33_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x175E))
#define MT6355_LDO_VCN33_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1760))
#define MT6355_LDO_VCN33_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1762))
#define MT6355_LDO_VCN33_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1764))
#define MT6355_LDO_VCN33_CON0_WIFI              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1766))
#define MT6355_LDO_VCN33_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1768))
#define MT6355_LDO_VCN33_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x176A))
#define MT6355_LDO_VCN33_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x176C))
#define MT6355_LDO_VCN18_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x176E))
#define MT6355_LDO_VCN18_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1770))
#define MT6355_LDO_VCN18_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1772))
#define MT6355_LDO_VCN18_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1774))
#define MT6355_LDO_VCN18_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1776))
#define MT6355_LDO_VCN18_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1778))
#define MT6355_LDO_VCN18_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x177A))
#define MT6355_LDO_VCN18_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x177C))
#define MT6355_LDO_VCN18_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x177E))
#define MT6355_LDO_VCN18_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1780))
#define MT6355_LDO_VCN28_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1782))
#define MT6355_LDO_VCN28_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1784))
#define MT6355_LDO_VCN28_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1786))
#define MT6355_LDO_VCN28_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1788))
#define MT6355_LDO_VCN28_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x178A))
#define MT6355_LDO_VCN28_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x178C))
#define MT6355_LDO_VCN28_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x178E))
#define MT6355_LDO_VCN28_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1790))
#define MT6355_LDO_VCN28_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1792))
#define MT6355_LDO_VCN28_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1794))
#define MT6355_LDO_VBIF28_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1796))
#define MT6355_LDO_VBIF28_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1798))
#define MT6355_LDO_VBIF28_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x179A))
#define MT6355_LDO_VBIF28_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x179C))
#define MT6355_LDO_VBIF28_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x179E))
#define MT6355_LDO_VBIF28_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x17A0))
#define MT6355_LDO_VBIF28_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x17A2))
#define MT6355_LDO_VBIF28_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17A4))
#define MT6355_LDO_VBIF28_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17A6))
#define MT6355_LDO_VBIF28_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17A8))
#define MT6355_LDO_VTCXO24_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x17AA))
#define MT6355_LDO_VTCXO24_OP_EN                ((unsigned int)(MT6355_PMIC_REG_BASE+0x17AC))
#define MT6355_LDO_VTCXO24_OP_EN_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x17AE))
#define MT6355_LDO_VTCXO24_OP_EN_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x17B0))
#define MT6355_LDO_VTCXO24_OP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x17B2))
#define MT6355_LDO_VTCXO24_OP_CFG_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x17B4))
#define MT6355_LDO_VTCXO24_OP_CFG_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x17B6))
#define MT6355_LDO_VTCXO24_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x17B8))
#define MT6355_LDO_VTCXO24_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x17BA))
#define MT6355_LDO_VTCXO24_CON3                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x17BC))
#define MT6355_LDO_VLDO28_CON0_AF               ((unsigned int)(MT6355_PMIC_REG_BASE+0x17BE))
#define MT6355_LDO_VLDO28_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x17C0))
#define MT6355_LDO_VLDO28_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x17C2))
#define MT6355_LDO_VLDO28_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x17C4))
#define MT6355_LDO_VLDO28_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x17C6))
#define MT6355_LDO_VLDO28_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x17C8))
#define MT6355_LDO_VLDO28_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x17CA))
#define MT6355_LDO_VLDO28_CON0_TP               ((unsigned int)(MT6355_PMIC_REG_BASE+0x17CC))
#define MT6355_LDO_VLDO28_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17CE))
#define MT6355_LDO_VLDO28_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17D0))
#define MT6355_LDO_VLDO28_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17D2))
#define MT6355_LDO_VGP2_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x17D4))
#define MT6355_LDO_VGP2_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x17D6))
#define MT6355_LDO_VGP2_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x17D8))
#define MT6355_LDO_VGP2_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x17DA))
#define MT6355_LDO_VGP2_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x17DC))
#define MT6355_LDO_VGP2_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x17DE))
#define MT6355_LDO_VGP2_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x17E0))
#define MT6355_LDO_VGP2_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x17E2))
#define MT6355_LDO_VGP2_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x17E4))
#define MT6355_LDO_VGP2_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x17E6))
#define MT6355_LDO_VFE28_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1800))
#define MT6355_LDO_VFE28_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1802))
#define MT6355_LDO_VFE28_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1804))
#define MT6355_LDO_VFE28_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1806))
#define MT6355_LDO_VFE28_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1808))
#define MT6355_LDO_VFE28_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x180A))
#define MT6355_LDO_VFE28_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x180C))
#define MT6355_LDO_VFE28_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x180E))
#define MT6355_LDO_VFE28_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1810))
#define MT6355_LDO_VFE28_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1812))
#define MT6355_LDO_VMCH_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1814))
#define MT6355_LDO_VMCH_OP_EN                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1816))
#define MT6355_LDO_VMCH_OP_EN_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1818))
#define MT6355_LDO_VMCH_OP_EN_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x181A))
#define MT6355_LDO_VMCH_OP_CFG                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x181C))
#define MT6355_LDO_VMCH_OP_CFG_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x181E))
#define MT6355_LDO_VMCH_OP_CFG_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1820))
#define MT6355_LDO_VMCH_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1822))
#define MT6355_LDO_VMCH_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1824))
#define MT6355_LDO_VMCH_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1826))
#define MT6355_LDO_VMC_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1828))
#define MT6355_LDO_VMC_OP_EN                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x182A))
#define MT6355_LDO_VMC_OP_EN_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x182C))
#define MT6355_LDO_VMC_OP_EN_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x182E))
#define MT6355_LDO_VMC_OP_CFG                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1830))
#define MT6355_LDO_VMC_OP_CFG_SET               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1832))
#define MT6355_LDO_VMC_OP_CFG_CLR               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1834))
#define MT6355_LDO_VMC_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1836))
#define MT6355_LDO_VMC_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1838))
#define MT6355_LDO_VMC_CON3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x183A))
#define MT6355_LDO_VRF18_1_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x183C))
#define MT6355_LDO_VRF18_1_OP_EN                ((unsigned int)(MT6355_PMIC_REG_BASE+0x183E))
#define MT6355_LDO_VRF18_1_OP_EN_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1840))
#define MT6355_LDO_VRF18_1_OP_EN_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1842))
#define MT6355_LDO_VRF18_1_OP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1844))
#define MT6355_LDO_VRF18_1_OP_CFG_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1846))
#define MT6355_LDO_VRF18_1_OP_CFG_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1848))
#define MT6355_LDO_VRF18_1_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x184A))
#define MT6355_LDO_VRF18_1_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x184C))
#define MT6355_LDO_VRF18_1_CON3                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x184E))
#define MT6355_LDO_VRF18_2_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1850))
#define MT6355_LDO_VRF18_2_OP_EN                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1852))
#define MT6355_LDO_VRF18_2_OP_EN_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1854))
#define MT6355_LDO_VRF18_2_OP_EN_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1856))
#define MT6355_LDO_VRF18_2_OP_CFG               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1858))
#define MT6355_LDO_VRF18_2_OP_CFG_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x185A))
#define MT6355_LDO_VRF18_2_OP_CFG_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x185C))
#define MT6355_LDO_VRF18_2_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x185E))
#define MT6355_LDO_VRF18_2_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1860))
#define MT6355_LDO_VRF18_2_CON3                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1862))
#define MT6355_LDO_VRF12_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1864))
#define MT6355_LDO_VRF12_OP_EN                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1866))
#define MT6355_LDO_VRF12_OP_EN_SET              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1868))
#define MT6355_LDO_VRF12_OP_EN_CLR              ((unsigned int)(MT6355_PMIC_REG_BASE+0x186A))
#define MT6355_LDO_VRF12_OP_CFG                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x186C))
#define MT6355_LDO_VRF12_OP_CFG_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x186E))
#define MT6355_LDO_VRF12_OP_CFG_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1870))
#define MT6355_LDO_VRF12_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1872))
#define MT6355_LDO_VRF12_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1874))
#define MT6355_LDO_VRF12_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1876))
#define MT6355_LDO_VCAMA1_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1878))
#define MT6355_LDO_VCAMA1_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x187A))
#define MT6355_LDO_VCAMA1_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x187C))
#define MT6355_LDO_VCAMA1_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x187E))
#define MT6355_LDO_VCAMA1_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1880))
#define MT6355_LDO_VCAMA1_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1882))
#define MT6355_LDO_VCAMA1_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1884))
#define MT6355_LDO_VCAMA1_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1886))
#define MT6355_LDO_VCAMA1_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1888))
#define MT6355_LDO_VCAMA1_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x188A))
#define MT6355_LDO_VCAMA2_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x188C))
#define MT6355_LDO_VCAMA2_OP_EN                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x188E))
#define MT6355_LDO_VCAMA2_OP_EN_SET             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1890))
#define MT6355_LDO_VCAMA2_OP_EN_CLR             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1892))
#define MT6355_LDO_VCAMA2_OP_CFG                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1894))
#define MT6355_LDO_VCAMA2_OP_CFG_SET            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1896))
#define MT6355_LDO_VCAMA2_OP_CFG_CLR            ((unsigned int)(MT6355_PMIC_REG_BASE+0x1898))
#define MT6355_LDO_VCAMA2_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x189A))
#define MT6355_LDO_VCAMA2_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x189C))
#define MT6355_LDO_VCAMA2_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x189E))
#define MT6355_LDO_OCFB0                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x18A0))
#define MT6355_VRTC_CON0                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x18A2))
#define MT6355_LDO_RSV_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x18A4))
#define MT6355_LDO_RSV_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x18A6))
#define MT6355_LDO_VSRAM_PROC_CON0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18A8))
#define MT6355_LDO_VSRAM_PROC_CON1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18AA))
#define MT6355_LDO_VSRAM_PROC_CON2              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18AC))
#define MT6355_LDO_VSRAM_PROC_CFG0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18AE))
#define MT6355_LDO_VSRAM_PROC_CFG1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18B0))
#define MT6355_LDO_VSRAM_PROC_OP_EN             ((unsigned int)(MT6355_PMIC_REG_BASE+0x18B2))
#define MT6355_LDO_VSRAM_PROC_OP_EN_SET         ((unsigned int)(MT6355_PMIC_REG_BASE+0x18B4))
#define MT6355_LDO_VSRAM_PROC_OP_EN_CLR         ((unsigned int)(MT6355_PMIC_REG_BASE+0x18B6))
#define MT6355_LDO_VSRAM_PROC_OP_CFG            ((unsigned int)(MT6355_PMIC_REG_BASE+0x18B8))
#define MT6355_LDO_VSRAM_PROC_OP_CFG_SET        ((unsigned int)(MT6355_PMIC_REG_BASE+0x18BA))
#define MT6355_LDO_VSRAM_PROC_OP_CFG_CLR        ((unsigned int)(MT6355_PMIC_REG_BASE+0x18BC))
#define MT6355_LDO_VSRAM_PROC_CON3              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18BE))
#define MT6355_LDO_VSRAM_PROC_CON4              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18C0))
#define MT6355_LDO_VSRAM_PROC_CON5              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18C2))
#define MT6355_LDO_VSRAM_PROC_DBG0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18C4))
#define MT6355_LDO_VSRAM_PROC_DBG1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18C6))
#define MT6355_LDO_VSRAM_CORE_CON0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18C8))
#define MT6355_LDO_VSRAM_CORE_CON1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18CA))
#define MT6355_LDO_VSRAM_CORE_CON2              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18CC))
#define MT6355_LDO_VSRAM_CORE_CFG0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18CE))
#define MT6355_LDO_VSRAM_CORE_CFG1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18D0))
#define MT6355_LDO_VSRAM_CORE_OP_EN             ((unsigned int)(MT6355_PMIC_REG_BASE+0x18D2))
#define MT6355_LDO_VSRAM_CORE_OP_EN_SET         ((unsigned int)(MT6355_PMIC_REG_BASE+0x18D4))
#define MT6355_LDO_VSRAM_CORE_OP_EN_CLR         ((unsigned int)(MT6355_PMIC_REG_BASE+0x18D6))
#define MT6355_LDO_VSRAM_CORE_OP_CFG            ((unsigned int)(MT6355_PMIC_REG_BASE+0x18D8))
#define MT6355_LDO_VSRAM_CORE_OP_CFG_SET        ((unsigned int)(MT6355_PMIC_REG_BASE+0x18DA))
#define MT6355_LDO_VSRAM_CORE_OP_CFG_CLR        ((unsigned int)(MT6355_PMIC_REG_BASE+0x18DC))
#define MT6355_LDO_VSRAM_CORE_CON3              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18DE))
#define MT6355_LDO_VSRAM_CORE_CON4              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18E0))
#define MT6355_LDO_VSRAM_CORE_CON5              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18E2))
#define MT6355_LDO_VSRAM_CORE_DBG0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18E4))
#define MT6355_LDO_VSRAM_CORE_DBG1              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18E6))
#define MT6355_LDO_VSRAM_GPU_CON0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x18E8))
#define MT6355_LDO_VSRAM_GPU_CON1               ((unsigned int)(MT6355_PMIC_REG_BASE+0x18EA))
#define MT6355_LDO_VSRAM_GPU_CON2               ((unsigned int)(MT6355_PMIC_REG_BASE+0x18EC))
#define MT6355_LDO_VSRAM_GPU_CFG0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x18EE))
#define MT6355_LDO_VSRAM_GPU_CFG1               ((unsigned int)(MT6355_PMIC_REG_BASE+0x18F0))
#define MT6355_LDO_VSRAM_GPU_OP_EN              ((unsigned int)(MT6355_PMIC_REG_BASE+0x18F2))
#define MT6355_LDO_VSRAM_GPU_OP_EN_SET          ((unsigned int)(MT6355_PMIC_REG_BASE+0x18F4))
#define MT6355_LDO_VSRAM_GPU_OP_EN_CLR          ((unsigned int)(MT6355_PMIC_REG_BASE+0x18F6))
#define MT6355_LDO_VSRAM_GPU_OP_CFG             ((unsigned int)(MT6355_PMIC_REG_BASE+0x18F8))
#define MT6355_LDO_VSRAM_GPU_OP_CFG_SET         ((unsigned int)(MT6355_PMIC_REG_BASE+0x18FA))
#define MT6355_LDO_VSRAM_GPU_OP_CFG_CLR         ((unsigned int)(MT6355_PMIC_REG_BASE+0x18FC))
#define MT6355_LDO_VSRAM_GPU_CON3               ((unsigned int)(MT6355_PMIC_REG_BASE+0x18FE))
#define MT6355_LDO_VSRAM_GPU_CON4               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1900))
#define MT6355_LDO_VSRAM_GPU_CON5               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1902))
#define MT6355_LDO_VSRAM_GPU_DBG0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1904))
#define MT6355_LDO_VSRAM_GPU_DBG1               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1906))
#define MT6355_LDO_VSRAM_MD_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1908))
#define MT6355_LDO_VSRAM_MD_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x190A))
#define MT6355_LDO_VSRAM_MD_CON2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x190C))
#define MT6355_LDO_VSRAM_MD_CFG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x190E))
#define MT6355_LDO_VSRAM_MD_CFG1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1910))
#define MT6355_LDO_VSRAM_MD_OP_EN               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1912))
#define MT6355_LDO_VSRAM_MD_OP_EN_SET           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1914))
#define MT6355_LDO_VSRAM_MD_OP_EN_CLR           ((unsigned int)(MT6355_PMIC_REG_BASE+0x1916))
#define MT6355_LDO_VSRAM_MD_OP_CFG              ((unsigned int)(MT6355_PMIC_REG_BASE+0x1918))
#define MT6355_LDO_VSRAM_MD_OP_CFG_SET          ((unsigned int)(MT6355_PMIC_REG_BASE+0x191A))
#define MT6355_LDO_VSRAM_MD_OP_CFG_CLR          ((unsigned int)(MT6355_PMIC_REG_BASE+0x191C))
#define MT6355_LDO_VSRAM_MD_CON3                ((unsigned int)(MT6355_PMIC_REG_BASE+0x191E))
#define MT6355_LDO_VSRAM_MD_CON4                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1920))
#define MT6355_LDO_VSRAM_MD_CON5                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1922))
#define MT6355_LDO_VSRAM_MD_DBG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1924))
#define MT6355_LDO_VSRAM_MD_DBG1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1926))
#define MT6355_LDO_TRACKING_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1928))
#define MT6355_LDO_TRACKING_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x192A))
#define MT6355_LDO_TRACKING_CON2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x192C))
#define MT6355_LDO_TRACKING_CON3                ((unsigned int)(MT6355_PMIC_REG_BASE+0x192E))
#define MT6355_LDO_DCM                          ((unsigned int)(MT6355_PMIC_REG_BASE+0x1930))
#define MT6355_LDO_VIO28_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1932))
#define MT6355_LDO_VIO18_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1934))
#define MT6355_LDO_VUFS18_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1936))
#define MT6355_LDO_VA10_CG0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1938))
#define MT6355_LDO_VA12_CG0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x193A))
#define MT6355_LDO_VSRAM_PROC_CG0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x193C))
#define MT6355_LDO_VSRAM_CORE_CG0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x193E))
#define MT6355_LDO_VSRAM_GPU_CG0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1940))
#define MT6355_LDO_VSRAM_MD_CG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1942))
#define MT6355_LDO_VA18_CG0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1944))
#define MT6355_LDO_VUSB33_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1946))
#define MT6355_LDO_VEMC_CG0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1948))
#define MT6355_LDO_VXO22_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x194A))
#define MT6355_LDO_VXO18_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x194C))
#define MT6355_LDO_VSIM1_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x194E))
#define MT6355_LDO_VSIM2_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1950))
#define MT6355_LDO_VCAMD1_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1952))
#define MT6355_LDO_VCAMD2_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1954))
#define MT6355_LDO_VCAMIO_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1956))
#define MT6355_LDO_VMIPI_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1958))
#define MT6355_LDO_VGP_CG0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x195A))
#define MT6355_LDO_VCN33_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x195C))
#define MT6355_LDO_VCN18_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x195E))
#define MT6355_LDO_VCN28_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1960))
#define MT6355_LDO_VGP2_CG0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1962))
#define MT6355_LDO_VBIF28_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1964))
#define MT6355_LDO_VFE28_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1966))
#define MT6355_LDO_VMCH_CG0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1968))
#define MT6355_LDO_VMC_CG0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x196A))
#define MT6355_LDO_VRF18_1_CG0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x196C))
#define MT6355_LDO_VRF18_2_CG0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x196E))
#define MT6355_LDO_VTCXO24_CG0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1970))
#define MT6355_LDO_VLDO28_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1972))
#define MT6355_LDO_VRF12_CG0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1974))
#define MT6355_LDO_VCAMA1_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1976))
#define MT6355_LDO_VCAMA2_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1978))
#define MT6355_LDO_VSRAM_PROC_SP                ((unsigned int)(MT6355_PMIC_REG_BASE+0x197A))
#define MT6355_LDO_VSRAM_GPU_SP                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x197C))
#define MT6355_LDO_VSRAM_MD_SP                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x197E))
#define MT6355_LDO_VSRAM_CORE_SP                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1980))
#define MT6355_LDO_VSRAM_CORE_SSHUB             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1982))
#define MT6355_LDO_LP_PROTECTION                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1984))
#define MT6355_LDO_DUMMY_LOAD_GATED             ((unsigned int)(MT6355_PMIC_REG_BASE+0x1986))
#define MT6355_LDO_VSRAM_PROC_R2R_PDN_DIS       ((unsigned int)(MT6355_PMIC_REG_BASE+0x1988))
#define MT6355_LDO_VSRAM_CORE_R2R_PDN_DIS       ((unsigned int)(MT6355_PMIC_REG_BASE+0x198A))
#define MT6355_LDO_VSRAM_GPU_R2R_PDN_DIS        ((unsigned int)(MT6355_PMIC_REG_BASE+0x198C))
#define MT6355_LDO_VSRAM_MD_R2R_PDN_DIS         ((unsigned int)(MT6355_PMIC_REG_BASE+0x198E))
#define MT6355_ALDO_ANA_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A00))
#define MT6355_ALDO_ANA_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A02))
#define MT6355_ALDO_ANA_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A04))
#define MT6355_ALDO_ANA_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A06))
#define MT6355_ALDO_ANA_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A08))
#define MT6355_ALDO_ANA_CON5                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A0A))
#define MT6355_ALDO_ANA_CON6                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A0C))
#define MT6355_ALDO_ANA_CON7                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A0E))
#define MT6355_ALDO_ANA_CON8                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A10))
#define MT6355_ALDO_ANA_CON9                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A12))
#define MT6355_ALDO_ANA_CON10                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A14))
#define MT6355_ALDO_ANA_CON11                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A16))
#define MT6355_ALDO_ANA_CON12                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A18))
#define MT6355_ALDO_ANA_CON13                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A1A))
#define MT6355_ALDO_ANA_CON14                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A1C))
#define MT6355_ALDO_ANA_CON15                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A1E))
#define MT6355_ALDO_ANA_CON16                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A20))
#define MT6355_ALDO_ANA_CON17                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A22))
#define MT6355_ALDO_ANA_CON18                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A24))
#define MT6355_ALDO_ANA_CON19                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A26))
#define MT6355_DLDO_ANA_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A28))
#define MT6355_DLDO_ANA_CON1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A2A))
#define MT6355_DLDO_ANA_CON2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A2C))
#define MT6355_DLDO_ANA_CON3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A2E))
#define MT6355_DLDO_ANA_CON4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A30))
#define MT6355_DLDO_ANA_CON5                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A32))
#define MT6355_DLDO_ANA_CON6                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A34))
#define MT6355_DLDO_ANA_CON7                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A36))
#define MT6355_DLDO_ANA_CON8                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A38))
#define MT6355_DLDO_ANA_CON9                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A3A))
#define MT6355_DLDO_ANA_CON10                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A3C))
#define MT6355_DLDO_ANA_CON11                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A3E))
#define MT6355_DLDO_ANA_CON12                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A40))
#define MT6355_DLDO_ANA_CON13                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A42))
#define MT6355_DLDO_ANA_CON14                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A44))
#define MT6355_DLDO_ANA_CON15                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A46))
#define MT6355_DLDO_ANA_CON16                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A48))
#define MT6355_DLDO_ANA_CON17                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A4A))
#define MT6355_SLDO20_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A4C))
#define MT6355_SLDO20_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A4E))
#define MT6355_SLDO20_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A50))
#define MT6355_SLDO20_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A52))
#define MT6355_SLDO20_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A54))
#define MT6355_SLDO20_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A56))
#define MT6355_SLDO20_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A58))
#define MT6355_SLDO20_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A5A))
#define MT6355_SLDO20_ANA_CON8                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A5C))
#define MT6355_SLDO20_ANA_CON9                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A5E))
#define MT6355_SLDO20_ANA_CON10                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A60))
#define MT6355_SLDO20_ANA_CON11                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A62))
#define MT6355_SLDO20_ANA_CON12                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A64))
#define MT6355_SLDO20_ANA_CON13                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A66))
#define MT6355_SLDO20_ANA_CON14                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A68))
#define MT6355_SLDO20_ANA_CON15                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A6A))
#define MT6355_SLDO14_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A6C))
#define MT6355_SLDO14_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A6E))
#define MT6355_SLDO14_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A70))
#define MT6355_SLDO14_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A72))
#define MT6355_SLDO14_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A74))
#define MT6355_SLDO14_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A76))
#define MT6355_SLDO14_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A78))
#define MT6355_SLDO14_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A7A))
#define MT6355_SLDO14_ANA_CON8                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A7C))
#define MT6355_SLDO14_ANA_CON9                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A7E))
#define MT6355_SLDO14_ANA_CON10                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A80))
#define MT6355_SLDO14_ANA_CON11                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A82))
#define MT6355_SLDO14_ANA_CON12                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1A84))
#define MT6355_ACCDET_CON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C00))
#define MT6355_ACCDET_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C02))
#define MT6355_ACCDET_CON2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C04))
#define MT6355_ACCDET_CON3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C06))
#define MT6355_ACCDET_CON4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C08))
#define MT6355_ACCDET_CON5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C0A))
#define MT6355_ACCDET_CON6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C0C))
#define MT6355_ACCDET_CON7                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C0E))
#define MT6355_ACCDET_CON8                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C10))
#define MT6355_ACCDET_CON9                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C12))
#define MT6355_ACCDET_CON10                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C14))
#define MT6355_ACCDET_CON11                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C16))
#define MT6355_ACCDET_CON12                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C18))
#define MT6355_ACCDET_CON13                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C1A))
#define MT6355_ACCDET_CON14                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C1C))
#define MT6355_ACCDET_CON15                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C1E))
#define MT6355_ACCDET_CON16                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C20))
#define MT6355_ACCDET_CON17                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C22))
#define MT6355_ACCDET_CON18                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C24))
#define MT6355_ACCDET_CON19                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C26))
#define MT6355_ACCDET_CON20                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C28))
#define MT6355_ACCDET_CON21                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C2A))
#define MT6355_ACCDET_CON22                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C2C))
#define MT6355_ACCDET_CON23                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C2E))
#define MT6355_ACCDET_CON24                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1C30))
#define MT6355_OTP_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E00))
#define MT6355_OTP_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E02))
#define MT6355_OTP_CON2                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E04))
#define MT6355_OTP_CON3                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E06))
#define MT6355_OTP_CON4                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E08))
#define MT6355_OTP_CON5                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E0A))
#define MT6355_OTP_CON6                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E0C))
#define MT6355_OTP_CON7                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E0E))
#define MT6355_OTP_CON8                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E10))
#define MT6355_OTP_CON9                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E12))
#define MT6355_OTP_CON10                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E14))
#define MT6355_OTP_CON11                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E16))
#define MT6355_OTP_CON12                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E18))
#define MT6355_OTP_CON13                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E1A))
#define MT6355_OTP_CON14                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E1C))
#define MT6355_OTP_DOUT_0_15                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E1E))
#define MT6355_OTP_DOUT_16_31                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E20))
#define MT6355_OTP_DOUT_32_47                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E22))
#define MT6355_OTP_DOUT_48_63                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E24))
#define MT6355_OTP_DOUT_64_79                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E26))
#define MT6355_OTP_DOUT_80_95                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E28))
#define MT6355_OTP_DOUT_96_111                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E2A))
#define MT6355_OTP_DOUT_112_127                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E2C))
#define MT6355_OTP_DOUT_128_143                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E2E))
#define MT6355_OTP_DOUT_144_159                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E30))
#define MT6355_OTP_DOUT_160_175                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E32))
#define MT6355_OTP_DOUT_176_191                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E34))
#define MT6355_OTP_DOUT_192_207                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E36))
#define MT6355_OTP_DOUT_208_223                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E38))
#define MT6355_OTP_DOUT_224_239                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E3A))
#define MT6355_OTP_DOUT_240_255                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E3C))
#define MT6355_OTP_DOUT_256_271                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E3E))
#define MT6355_OTP_DOUT_272_287                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E40))
#define MT6355_OTP_DOUT_288_303                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E42))
#define MT6355_OTP_DOUT_304_319                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E44))
#define MT6355_OTP_DOUT_320_335                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E46))
#define MT6355_OTP_DOUT_336_351                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E48))
#define MT6355_OTP_DOUT_352_367                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E4A))
#define MT6355_OTP_DOUT_368_383                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E4C))
#define MT6355_OTP_DOUT_384_399                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E4E))
#define MT6355_OTP_DOUT_400_415                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E50))
#define MT6355_OTP_DOUT_416_431                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E52))
#define MT6355_OTP_DOUT_432_447                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E54))
#define MT6355_OTP_DOUT_448_463                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E56))
#define MT6355_OTP_DOUT_464_479                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E58))
#define MT6355_OTP_DOUT_480_495                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E5A))
#define MT6355_OTP_DOUT_496_511                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E5C))
#define MT6355_OTP_DOUT_512_527                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E5E))
#define MT6355_OTP_DOUT_528_543                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E60))
#define MT6355_OTP_DOUT_544_559                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E62))
#define MT6355_OTP_DOUT_560_575                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E64))
#define MT6355_OTP_DOUT_576_591                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E66))
#define MT6355_OTP_DOUT_592_607                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E68))
#define MT6355_OTP_DOUT_608_623                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E6A))
#define MT6355_OTP_DOUT_624_639                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E6C))
#define MT6355_OTP_DOUT_640_655                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E6E))
#define MT6355_OTP_DOUT_656_671                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E70))
#define MT6355_OTP_DOUT_672_687                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E72))
#define MT6355_OTP_DOUT_688_703                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E74))
#define MT6355_OTP_DOUT_704_719                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E76))
#define MT6355_OTP_DOUT_720_735                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E78))
#define MT6355_OTP_DOUT_736_751                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E7A))
#define MT6355_OTP_DOUT_752_767                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E7C))
#define MT6355_OTP_DOUT_768_783                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E7E))
#define MT6355_OTP_DOUT_784_799                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E80))
#define MT6355_OTP_DOUT_800_815                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E82))
#define MT6355_OTP_DOUT_816_831                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E84))
#define MT6355_OTP_DOUT_832_847                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E86))
#define MT6355_OTP_DOUT_848_863                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E88))
#define MT6355_OTP_DOUT_864_879                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E8A))
#define MT6355_OTP_DOUT_880_895                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E8C))
#define MT6355_OTP_DOUT_896_911                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E8E))
#define MT6355_OTP_DOUT_912_927                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E90))
#define MT6355_OTP_DOUT_928_943                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E92))
#define MT6355_OTP_DOUT_944_959                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E94))
#define MT6355_OTP_DOUT_960_975                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E96))
#define MT6355_OTP_DOUT_976_991                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E98))
#define MT6355_OTP_DOUT_992_1007                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E9A))
#define MT6355_OTP_DOUT_1008_1023               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E9C))
#define MT6355_OTP_DOUT_1024_1039               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1E9E))
#define MT6355_OTP_DOUT_1040_1055               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EA0))
#define MT6355_OTP_DOUT_1056_1071               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EA2))
#define MT6355_OTP_DOUT_1072_1087               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EA4))
#define MT6355_OTP_DOUT_1088_1103               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EA6))
#define MT6355_OTP_DOUT_1104_1119               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EA8))
#define MT6355_OTP_DOUT_1120_1135               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EAA))
#define MT6355_OTP_DOUT_1136_1151               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EAC))
#define MT6355_OTP_DOUT_1152_1167               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EAE))
#define MT6355_OTP_DOUT_1168_1183               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EB0))
#define MT6355_OTP_DOUT_1184_1199               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EB2))
#define MT6355_OTP_DOUT_1200_1215               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EB4))
#define MT6355_OTP_DOUT_1216_1231               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EB6))
#define MT6355_OTP_DOUT_1232_1247               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EB8))
#define MT6355_OTP_DOUT_1248_1263               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EBA))
#define MT6355_OTP_DOUT_1264_1279               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EBC))
#define MT6355_OTP_DOUT_1280_1295               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EBE))
#define MT6355_OTP_DOUT_1296_1311               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EC0))
#define MT6355_OTP_DOUT_1312_1327               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EC2))
#define MT6355_OTP_DOUT_1328_1343               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EC4))
#define MT6355_OTP_DOUT_1344_1359               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EC6))
#define MT6355_OTP_DOUT_1360_1375               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EC8))
#define MT6355_OTP_DOUT_1376_1391               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ECA))
#define MT6355_OTP_DOUT_1392_1407               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ECC))
#define MT6355_OTP_DOUT_1408_1423               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ECE))
#define MT6355_OTP_DOUT_1424_1439               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ED0))
#define MT6355_OTP_DOUT_1440_1455               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ED2))
#define MT6355_OTP_DOUT_1456_1471               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ED4))
#define MT6355_OTP_DOUT_1472_1487               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ED6))
#define MT6355_OTP_DOUT_1488_1503               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1ED8))
#define MT6355_OTP_DOUT_1504_1519               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EDA))
#define MT6355_OTP_DOUT_1520_1535               ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EDC))
#define MT6355_OTP_VAL_0_15                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EDE))
#define MT6355_OTP_VAL_16_31                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EE0))
#define MT6355_OTP_VAL_32_47                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EE2))
#define MT6355_OTP_VAL_48_63                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EE4))
#define MT6355_OTP_VAL_64_79                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EE6))
#define MT6355_OTP_VAL_80_95                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EE8))
#define MT6355_OTP_VAL_96_111                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EEA))
#define MT6355_OTP_VAL_112_127                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EEC))
#define MT6355_OTP_VAL_128_143                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EEE))
#define MT6355_OTP_VAL_144_159                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EF0))
#define MT6355_OTP_VAL_160_175                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EF2))
#define MT6355_OTP_VAL_176_191                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EF4))
#define MT6355_OTP_VAL_192_207                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EF6))
#define MT6355_OTP_VAL_208_223                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EF8))
#define MT6355_OTP_VAL_224_239                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EFA))
#define MT6355_OTP_VAL_240_255                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EFC))
#define MT6355_OTP_VAL_256_271                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1EFE))
#define MT6355_OTP_VAL_272_287                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F00))
#define MT6355_OTP_VAL_288_303                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F02))
#define MT6355_OTP_VAL_304_319                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F04))
#define MT6355_OTP_VAL_320_335                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F06))
#define MT6355_OTP_VAL_336_351                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F08))
#define MT6355_OTP_VAL_352_367                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F0A))
#define MT6355_OTP_VAL_368_383                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F0C))
#define MT6355_OTP_VAL_384_399                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F0E))
#define MT6355_OTP_VAL_400_415                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F10))
#define MT6355_OTP_VAL_416_431                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F12))
#define MT6355_OTP_VAL_432_447                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F14))
#define MT6355_OTP_VAL_448_463                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F16))
#define MT6355_OTP_VAL_464_479                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F18))
#define MT6355_OTP_VAL_480_495                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F1A))
#define MT6355_OTP_VAL_496_511                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F1C))
#define MT6355_OTP_VAL_512_527                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F1E))
#define MT6355_OTP_VAL_528_543                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F20))
#define MT6355_OTP_VAL_544_559                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F22))
#define MT6355_OTP_VAL_560_575                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F24))
#define MT6355_OTP_VAL_576_591                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F26))
#define MT6355_OTP_VAL_592_607                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F28))
#define MT6355_OTP_VAL_608_623                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F2A))
#define MT6355_OTP_VAL_624_639                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F2C))
#define MT6355_OTP_VAL_640_655                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F2E))
#define MT6355_OTP_VAL_656_671                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F30))
#define MT6355_OTP_VAL_672_687                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F32))
#define MT6355_OTP_VAL_688_703                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F34))
#define MT6355_OTP_VAL_704_719                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F36))
#define MT6355_OTP_VAL_720_735                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F38))
#define MT6355_OTP_VAL_736_751                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F3A))
#define MT6355_OTP_VAL_752_767                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F3C))
#define MT6355_OTP_VAL_768_783                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F3E))
#define MT6355_OTP_VAL_784_799                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F40))
#define MT6355_OTP_VAL_800_815                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F42))
#define MT6355_OTP_VAL_816_831                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F44))
#define MT6355_OTP_VAL_832_847                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F46))
#define MT6355_OTP_VAL_848_863                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F48))
#define MT6355_OTP_VAL_864_879                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F4A))
#define MT6355_OTP_VAL_880_895                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F4C))
#define MT6355_OTP_VAL_896_911                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F4E))
#define MT6355_OTP_VAL_912_927                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F50))
#define MT6355_OTP_VAL_928_943                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F52))
#define MT6355_OTP_VAL_944_959                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F54))
#define MT6355_OTP_VAL_960_975                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F56))
#define MT6355_OTP_VAL_976_991                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F58))
#define MT6355_OTP_VAL_992_1007                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F5A))
#define MT6355_OTP_VAL_1008_1023                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F5C))
#define MT6355_OTP_VAL_1024_1039                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F5E))
#define MT6355_OTP_VAL_1040_1055                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F60))
#define MT6355_OTP_VAL_1056_1071                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F62))
#define MT6355_OTP_VAL_1072_1087                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F64))
#define MT6355_OTP_VAL_1088_1103                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F66))
#define MT6355_OTP_VAL_1104_1119                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F68))
#define MT6355_OTP_VAL_1120_1135                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F6A))
#define MT6355_OTP_VAL_1136_1151                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F6C))
#define MT6355_OTP_VAL_1152_1167                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F6E))
#define MT6355_OTP_VAL_1168_1183                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F70))
#define MT6355_OTP_VAL_1184_1199                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F72))
#define MT6355_OTP_VAL_1200_1215                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F74))
#define MT6355_OTP_VAL_1216_1231                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F76))
#define MT6355_OTP_VAL_1232_1247                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F78))
#define MT6355_OTP_VAL_1248_1263                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F7A))
#define MT6355_OTP_VAL_1264_1279                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F7C))
#define MT6355_OTP_VAL_1280_1295                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F7E))
#define MT6355_OTP_VAL_1296_1311                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F80))
#define MT6355_OTP_VAL_1312_1327                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F82))
#define MT6355_OTP_VAL_1328_1343                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F84))
#define MT6355_OTP_VAL_1344_1359                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F86))
#define MT6355_OTP_VAL_1360_1375                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F88))
#define MT6355_OTP_VAL_1376_1391                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F8A))
#define MT6355_OTP_VAL_1392_1407                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F8C))
#define MT6355_OTP_VAL_1408_1423                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F8E))
#define MT6355_OTP_VAL_1424_1439                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F90))
#define MT6355_OTP_VAL_1440_1455                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F92))
#define MT6355_OTP_VAL_1456_1471                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F94))
#define MT6355_OTP_VAL_1472_1487                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F96))
#define MT6355_OTP_VAL_1488_1503                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F98))
#define MT6355_OTP_VAL_1504_1519                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F9A))
#define MT6355_OTP_VAL_1520_1535                ((unsigned int)(MT6355_PMIC_REG_BASE+0x1F9C))
#define MT6355_DCXO_CW00                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2000))
#define MT6355_DCXO_CW00_SET                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x2002))
#define MT6355_DCXO_CW00_CLR                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x2004))
#define MT6355_DCXO_CW01                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2006))
#define MT6355_DCXO_CW02                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2008))
#define MT6355_DCXO_CW03                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x200A))
#define MT6355_DCXO_CW04                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x200C))
#define MT6355_DCXO_CW05                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x200E))
#define MT6355_DCXO_CW06                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2010))
#define MT6355_DCXO_CW07                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2012))
#define MT6355_DCXO_CW08                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2014))
#define MT6355_DCXO_CW09                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2016))
#define MT6355_DCXO_CW10                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2018))
#define MT6355_DCXO_CW11                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x201A))
#define MT6355_DCXO_CW11_SET                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x201C))
#define MT6355_DCXO_CW11_CLR                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x201E))
#define MT6355_DCXO_CW12                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2020))
#define MT6355_DCXO_CW13                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2022))
#define MT6355_DCXO_CW14                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2024))
#define MT6355_DCXO_CW15                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2026))
#define MT6355_DCXO_CW16                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2028))
#define MT6355_DCXO_CW17                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x202A))
#define MT6355_DCXO_CW18                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x202C))
#define MT6355_DCXO_CW19                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x202E))
#define MT6355_DCXO_CW20                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2030))
#define MT6355_DCXO_CW21                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2032))
#define MT6355_DCXO_CW22                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2034))
#define MT6355_CHR_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2200))
#define MT6355_CHR_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2202))
#define MT6355_CHR_CON2                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2204))
#define MT6355_CHR_CON3                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2206))
#define MT6355_CHR_CON4                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2208))
#define MT6355_CHR_CON5                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x220A))
#define MT6355_CHR_CON6                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x220C))
#define MT6355_CHR_CON7                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x220E))
#define MT6355_PCHR_VREF_ANA_DA0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x2210))
#define MT6355_PCHR_VREF_ANA_CON0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x2212))
#define MT6355_PCHR_VREF_ANA_CON1               ((unsigned int)(MT6355_PMIC_REG_BASE+0x2214))
#define MT6355_PCHR_VREF_ANA_CON2               ((unsigned int)(MT6355_PMIC_REG_BASE+0x2216))
#define MT6355_PCHR_VREF_ANA_CON3               ((unsigned int)(MT6355_PMIC_REG_BASE+0x2218))
#define MT6355_GPIO_DIR0                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2400))
#define MT6355_GPIO_DIR0_SET                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x2402))
#define MT6355_GPIO_DIR0_CLR                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x2404))
#define MT6355_GPIO_PULLEN0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2406))
#define MT6355_GPIO_PULLEN0_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x2408))
#define MT6355_GPIO_PULLEN0_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x240A))
#define MT6355_GPIO_PULLSEL0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x240C))
#define MT6355_GPIO_PULLSEL0_SET                ((unsigned int)(MT6355_PMIC_REG_BASE+0x240E))
#define MT6355_GPIO_PULLSEL0_CLR                ((unsigned int)(MT6355_PMIC_REG_BASE+0x2410))
#define MT6355_GPIO_DINV0                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x2412))
#define MT6355_GPIO_DINV0_SET                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2414))
#define MT6355_GPIO_DINV0_CLR                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2416))
#define MT6355_GPIO_DOUT0                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x2418))
#define MT6355_GPIO_DOUT0_SET                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x241A))
#define MT6355_GPIO_DOUT0_CLR                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x241C))
#define MT6355_GPIO_PI0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x241E))
#define MT6355_GPIO_POE0                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2420))
#define MT6355_GPIO_MODE0                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x2422))
#define MT6355_GPIO_MODE0_SET                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2424))
#define MT6355_GPIO_MODE0_CLR                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2426))
#define MT6355_GPIO_MODE1                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x2428))
#define MT6355_GPIO_MODE1_SET                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x242A))
#define MT6355_GPIO_MODE1_CLR                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x242C))
#define MT6355_GPIO_MODE2                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x242E))
#define MT6355_GPIO_MODE2_SET                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2430))
#define MT6355_GPIO_MODE2_CLR                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2432))
#define MT6355_GPIO_RSV                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2434))
#define MT6355_RTC_SEC_DUMMY_CON0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x2600))
#define MT6355_RTC_DUMMY_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2800))
#define MT6355_EOSC_CALI_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2A00))
#define MT6355_EOSC_CALI_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x2A02))
#define MT6355_RTC_MIX_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2A04))
#define MT6355_RTC_MIX_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2A06))
#define MT6355_RTC_MIX_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2A08))
#define MT6355_VRTC_PWM_CON0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x2C00))
#define MT6355_BIF_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E00))
#define MT6355_BIF_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E02))
#define MT6355_BIF_CON2                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E04))
#define MT6355_BIF_CON3                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E06))
#define MT6355_BIF_CON4                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E08))
#define MT6355_BIF_CON5                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E0A))
#define MT6355_BIF_CON6                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E0C))
#define MT6355_BIF_CON7                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E0E))
#define MT6355_BIF_CON8                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E10))
#define MT6355_BIF_CON9                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E12))
#define MT6355_BIF_CON10                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E14))
#define MT6355_BIF_CON11                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E16))
#define MT6355_BIF_CON12                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E18))
#define MT6355_BIF_CON13                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E1A))
#define MT6355_BIF_CON14                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E1C))
#define MT6355_BIF_CON15                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E1E))
#define MT6355_BIF_CON16                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E20))
#define MT6355_BIF_CON17                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E22))
#define MT6355_BIF_CON18                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E24))
#define MT6355_BIF_CON19                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E26))
#define MT6355_BIF_CON20                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E28))
#define MT6355_BIF_CON21                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E2A))
#define MT6355_BIF_CON22                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E2C))
#define MT6355_BIF_CON23                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E2E))
#define MT6355_BIF_CON24                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E30))
#define MT6355_BIF_CON25                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E32))
#define MT6355_BIF_CON26                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E34))
#define MT6355_BIF_CON27                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E36))
#define MT6355_BIF_CON28                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E38))
#define MT6355_BIF_CON29                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E3A))
#define MT6355_BIF_CON30                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E3C))
#define MT6355_BIF_CON31                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E3E))
#define MT6355_BIF_CON32                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E40))
#define MT6355_BIF_CON33                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E42))
#define MT6355_BIF_CON34                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E44))
#define MT6355_BIF_CON35                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E46))
#define MT6355_BIF_CON36                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E48))
#define MT6355_BIF_CON37                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E4A))
#define MT6355_BIF_CON38                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E4C))
#define MT6355_BIF_CON39                        ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E4E))
#define MT6355_BIF_BAT_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E50))
#define MT6355_BIF_BAT_CON1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E52))
#define MT6355_BIF_BAT_CON2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E54))
#define MT6355_BIF_BAT_CON3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E56))
#define MT6355_BIF_ANA_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x2E58))
#define MT6355_FGADC_CON0                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x3000))
#define MT6355_FGADC_CON1                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x3002))
#define MT6355_FGADC_CON2                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x3004))
#define MT6355_FGADC_CON3                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x3006))
#define MT6355_FGADC_CON4                       ((unsigned int)(MT6355_PMIC_REG_BASE+0x3008))
#define MT6355_FGADC_RST_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x300A))
#define MT6355_FGADC_R_CON0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x300C))
#define MT6355_FGADC_CUR_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x300E))
#define MT6355_FGADC_CUR_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3010))
#define MT6355_FGADC_CUR_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3012))
#define MT6355_FGADC_CUR_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3014))
#define MT6355_FGADC_CAR_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3016))
#define MT6355_FGADC_CAR_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3018))
#define MT6355_FGADC_CAR_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x301A))
#define MT6355_FGADC_CAR_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x301C))
#define MT6355_FGADC_CAR_CON4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x301E))
#define MT6355_FGADC_CAR_CON5                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3020))
#define MT6355_FGADC_CAR_CON6                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3022))
#define MT6355_FGADC_CAR_CON7                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3024))
#define MT6355_FGADC_CAR_CON8                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3026))
#define MT6355_FGADC_CAR_CON9                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3028))
#define MT6355_FGADC_NCAR_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x302A))
#define MT6355_FGADC_NCAR_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x302C))
#define MT6355_FGADC_NCAR_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x302E))
#define MT6355_FGADC_NCAR_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3030))
#define MT6355_FGADC_IAVG_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3032))
#define MT6355_FGADC_IAVG_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3034))
#define MT6355_FGADC_IAVG_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3036))
#define MT6355_FGADC_IAVG_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3038))
#define MT6355_FGADC_IAVG_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x303A))
#define MT6355_FGADC_IAVG_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x303C))
#define MT6355_FGADC_NTER_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x303E))
#define MT6355_FGADC_NTER_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3040))
#define MT6355_FGADC_NTER_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3042))
#define MT6355_FGADC_NTER_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3044))
#define MT6355_FGADC_OFFSET_CON0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3046))
#define MT6355_FGADC_OFFSET_CON1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3048))
#define MT6355_FGADC_GAIN_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x304A))
#define MT6355_FGADC_SON_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x304C))
#define MT6355_FGADC_SON_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x304E))
#define MT6355_FGADC_SON_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3050))
#define MT6355_FGADC_SON_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3052))
#define MT6355_FGADC_SOFF_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3054))
#define MT6355_FGADC_SOFF_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3056))
#define MT6355_FGADC_SOFF_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3058))
#define MT6355_FGADC_SOFF_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x305A))
#define MT6355_FGADC_SOFF_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x305C))
#define MT6355_FGADC_PWR_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x305E))
#define MT6355_FGADC_PWR_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3060))
#define MT6355_FGADC_ZCV_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3062))
#define MT6355_FGADC_ZCV_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3064))
#define MT6355_FGADC_ZCV_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3066))
#define MT6355_FGADC_ZCV_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3068))
#define MT6355_FGADC_ZCV_CON4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x306A))
#define MT6355_FGADC_ZCV_CON5                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x306C))
#define MT6355_FGADC_ANA_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x306E))
#define MT6355_FGADC_ANA_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3070))
#define MT6355_FGADC_TEST_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3072))
#define MT6355_FGADC_RSV_CON0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3074))
#define MT6355_FGADC_RSV_CON1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3076))
#define MT6355_FGADC_RSV_CON2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3078))
#define MT6355_FGADC_RSV_CON3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x307A))
#define MT6355_SYSTEM_INFO_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x307C))
#define MT6355_SYSTEM_INFO_CON1                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x307E))
#define MT6355_SYSTEM_INFO_CON2                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3080))
#define MT6355_SYSTEM_INFO_CON3                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3082))
#define MT6355_SYSTEM_INFO_CON4                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3084))
#define MT6355_FGADC_EFUSE_CON0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3086))
#define MT6355_AUXADC_ADC0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3200))
#define MT6355_AUXADC_ADC1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3202))
#define MT6355_AUXADC_ADC2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3204))
#define MT6355_AUXADC_ADC3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3206))
#define MT6355_AUXADC_ADC4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3208))
#define MT6355_AUXADC_ADC5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x320A))
#define MT6355_AUXADC_ADC6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x320C))
#define MT6355_AUXADC_ADC7                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x320E))
#define MT6355_AUXADC_ADC8                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3210))
#define MT6355_AUXADC_ADC9                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3212))
#define MT6355_AUXADC_ADC10                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3214))
#define MT6355_AUXADC_ADC11                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3216))
#define MT6355_AUXADC_ADC12                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3218))
#define MT6355_AUXADC_ADC13                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x321A))
#define MT6355_AUXADC_ADC14                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x321C))
#define MT6355_AUXADC_ADC15                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x321E))
#define MT6355_AUXADC_ADC16                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3220))
#define MT6355_AUXADC_ADC17                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3222))
#define MT6355_AUXADC_ADC18                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3224))
#define MT6355_AUXADC_ADC19                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3226))
#define MT6355_AUXADC_ADC20                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3228))
#define MT6355_AUXADC_ADC21                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x322A))
#define MT6355_AUXADC_ADC22                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x322C))
#define MT6355_AUXADC_ADC23                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x322E))
#define MT6355_AUXADC_ADC24                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3230))
#define MT6355_AUXADC_ADC25                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3232))
#define MT6355_AUXADC_ADC26                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3234))
#define MT6355_AUXADC_ADC27                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3236))
#define MT6355_AUXADC_ADC28                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3238))
#define MT6355_AUXADC_ADC29                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x323A))
#define MT6355_AUXADC_ADC30                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x323C))
#define MT6355_AUXADC_ADC31                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x323E))
#define MT6355_AUXADC_ADC32                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3240))
#define MT6355_AUXADC_ADC33                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3242))
#define MT6355_AUXADC_ADC34                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3244))
#define MT6355_AUXADC_ADC35                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3246))
#define MT6355_AUXADC_ADC36                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3248))
#define MT6355_AUXADC_ADC37                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x324A))
#define MT6355_AUXADC_ADC38                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x324C))
#define MT6355_AUXADC_ADC39                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x324E))
#define MT6355_AUXADC_ADC40                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3250))
#define MT6355_AUXADC_ADC41                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3252))
#define MT6355_AUXADC_ADC42                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3254))
#define MT6355_AUXADC_ADC43                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3256))
#define MT6355_AUXADC_ADC44                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3258))
#define MT6355_AUXADC_BUF0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x325A))
#define MT6355_AUXADC_BUF1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x325C))
#define MT6355_AUXADC_BUF2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x325E))
#define MT6355_AUXADC_BUF3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3260))
#define MT6355_AUXADC_BUF4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3262))
#define MT6355_AUXADC_BUF5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3264))
#define MT6355_AUXADC_BUF6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3266))
#define MT6355_AUXADC_BUF7                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3268))
#define MT6355_AUXADC_BUF8                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x326A))
#define MT6355_AUXADC_BUF9                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x326C))
#define MT6355_AUXADC_BUF10                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x326E))
#define MT6355_AUXADC_BUF11                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3270))
#define MT6355_AUXADC_BUF12                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3272))
#define MT6355_AUXADC_BUF13                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3274))
#define MT6355_AUXADC_BUF14                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3276))
#define MT6355_AUXADC_BUF15                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3278))
#define MT6355_AUXADC_BUF16                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x327A))
#define MT6355_AUXADC_BUF17                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x327C))
#define MT6355_AUXADC_BUF18                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x327E))
#define MT6355_AUXADC_BUF19                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3280))
#define MT6355_AUXADC_BUF20                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3282))
#define MT6355_AUXADC_BUF21                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3284))
#define MT6355_AUXADC_BUF22                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3286))
#define MT6355_AUXADC_BUF23                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3288))
#define MT6355_AUXADC_BUF24                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x328A))
#define MT6355_AUXADC_BUF25                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x328C))
#define MT6355_AUXADC_BUF26                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x328E))
#define MT6355_AUXADC_BUF27                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3290))
#define MT6355_AUXADC_BUF28                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3292))
#define MT6355_AUXADC_BUF29                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3294))
#define MT6355_AUXADC_BUF30                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3296))
#define MT6355_AUXADC_BUF31                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3298))
#define MT6355_AUXADC_STA0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x329A))
#define MT6355_AUXADC_STA1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x329C))
#define MT6355_AUXADC_STA2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x329E))
#define MT6355_AUXADC_RQST0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32A0))
#define MT6355_AUXADC_RQST0_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x32A2))
#define MT6355_AUXADC_RQST0_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x32A4))
#define MT6355_AUXADC_RQST1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32A6))
#define MT6355_AUXADC_RQST1_SET                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x32A8))
#define MT6355_AUXADC_RQST1_CLR                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x32AA))
#define MT6355_AUXADC_CON0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32AC))
#define MT6355_AUXADC_CON0_SET                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x32AE))
#define MT6355_AUXADC_CON0_CLR                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x32B0))
#define MT6355_AUXADC_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32B2))
#define MT6355_AUXADC_CON2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32B4))
#define MT6355_AUXADC_CON3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32B6))
#define MT6355_AUXADC_CON4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32B8))
#define MT6355_AUXADC_CON5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32BA))
#define MT6355_AUXADC_CON6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32BC))
#define MT6355_AUXADC_CON7                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32BE))
#define MT6355_AUXADC_CON8                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32C0))
#define MT6355_AUXADC_CON9                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32C2))
#define MT6355_AUXADC_CON10                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32C4))
#define MT6355_AUXADC_CON11                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32C6))
#define MT6355_AUXADC_CON12                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32C8))
#define MT6355_AUXADC_CON13                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32CA))
#define MT6355_AUXADC_CON14                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32CC))
#define MT6355_AUXADC_CON15                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32CE))
#define MT6355_AUXADC_CON16                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32D0))
#define MT6355_AUXADC_CON17                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32D2))
#define MT6355_AUXADC_CON18                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32D4))
#define MT6355_AUXADC_CON19                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32D6))
#define MT6355_AUXADC_CON20                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32D8))
#define MT6355_AUXADC_CON21                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32DA))
#define MT6355_AUXADC_CON22                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32DC))
#define MT6355_AUXADC_CON23                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32DE))
#define MT6355_AUXADC_AUTORPT0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x32E0))
#define MT6355_AUXADC_LBAT0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32E2))
#define MT6355_AUXADC_LBAT1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32E4))
#define MT6355_AUXADC_LBAT2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32E6))
#define MT6355_AUXADC_LBAT3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32E8))
#define MT6355_AUXADC_LBAT4                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32EA))
#define MT6355_AUXADC_LBAT5                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32EC))
#define MT6355_AUXADC_LBAT6                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x32EE))
#define MT6355_AUXADC_ACCDET                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x32F0))
#define MT6355_AUXADC_THR0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32F2))
#define MT6355_AUXADC_THR1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32F4))
#define MT6355_AUXADC_THR2                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32F6))
#define MT6355_AUXADC_THR3                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32F8))
#define MT6355_AUXADC_THR4                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32FA))
#define MT6355_AUXADC_THR5                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32FC))
#define MT6355_AUXADC_THR6                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x32FE))
#define MT6355_AUXADC_EFUSE0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3300))
#define MT6355_AUXADC_EFUSE1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3302))
#define MT6355_AUXADC_EFUSE2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3304))
#define MT6355_AUXADC_EFUSE3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3306))
#define MT6355_AUXADC_EFUSE4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3308))
#define MT6355_AUXADC_EFUSE5                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x330A))
#define MT6355_AUXADC_DBG0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x330C))
#define MT6355_AUXADC_IMP0                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x330E))
#define MT6355_AUXADC_IMP1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3310))
#define MT6355_AUXADC_BAT_TEMP_0                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3312))
#define MT6355_AUXADC_BAT_TEMP_1                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3314))
#define MT6355_AUXADC_BAT_TEMP_2                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3316))
#define MT6355_AUXADC_BAT_TEMP_3                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3318))
#define MT6355_AUXADC_BAT_TEMP_4                ((unsigned int)(MT6355_PMIC_REG_BASE+0x331A))
#define MT6355_AUXADC_BAT_TEMP_5                ((unsigned int)(MT6355_PMIC_REG_BASE+0x331C))
#define MT6355_AUXADC_BAT_TEMP_6                ((unsigned int)(MT6355_PMIC_REG_BASE+0x331E))
#define MT6355_AUXADC_BAT_TEMP_7                ((unsigned int)(MT6355_PMIC_REG_BASE+0x3320))
#define MT6355_AUXADC_LBAT2_1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3322))
#define MT6355_AUXADC_LBAT2_2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3324))
#define MT6355_AUXADC_LBAT2_3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3326))
#define MT6355_AUXADC_LBAT2_4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3328))
#define MT6355_AUXADC_LBAT2_5                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x332A))
#define MT6355_AUXADC_LBAT2_6                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x332C))
#define MT6355_AUXADC_LBAT2_7                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x332E))
#define MT6355_AUXADC_MDBG_0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3330))
#define MT6355_AUXADC_MDBG_1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3332))
#define MT6355_AUXADC_MDBG_2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3334))
#define MT6355_AUXADC_MDRT_0                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3336))
#define MT6355_AUXADC_MDRT_1                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x3338))
#define MT6355_AUXADC_MDRT_2                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x333A))
#define MT6355_AUXADC_MDRT_3                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x333C))
#define MT6355_AUXADC_MDRT_4                    ((unsigned int)(MT6355_PMIC_REG_BASE+0x333E))
#define MT6355_AUXADC_JEITA_0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3340))
#define MT6355_AUXADC_JEITA_1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3342))
#define MT6355_AUXADC_JEITA_2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3344))
#define MT6355_AUXADC_JEITA_3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3346))
#define MT6355_AUXADC_JEITA_4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3348))
#define MT6355_AUXADC_JEITA_5                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x334A))
#define MT6355_AUXADC_DCXO_MDRT_0               ((unsigned int)(MT6355_PMIC_REG_BASE+0x334C))
#define MT6355_AUXADC_DCXO_MDRT_1               ((unsigned int)(MT6355_PMIC_REG_BASE+0x334E))
#define MT6355_AUXADC_DCXO_MDRT_2               ((unsigned int)(MT6355_PMIC_REG_BASE+0x3350))
#define MT6355_AUXADC_NAG_0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3352))
#define MT6355_AUXADC_NAG_1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3354))
#define MT6355_AUXADC_NAG_2                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3356))
#define MT6355_AUXADC_NAG_3                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3358))
#define MT6355_AUXADC_NAG_4                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x335A))
#define MT6355_AUXADC_NAG_5                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x335C))
#define MT6355_AUXADC_NAG_6                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x335E))
#define MT6355_AUXADC_NAG_7                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3360))
#define MT6355_AUXADC_NAG_8                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x3362))
#define MT6355_AUXADC_EFUSE_1                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3364))
#define MT6355_AUXADC_EFUSE_2                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3366))
#define MT6355_AUXADC_EFUSE_3                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3368))
#define MT6355_AUXADC_EFUSE_4                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x336A))
#define MT6355_AUXADC_RSV_1                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x336C))
#define MT6355_AUXADC_ANA_0                     ((unsigned int)(MT6355_PMIC_REG_BASE+0x336E))
#define MT6355_AUXADC_IMP_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3370))
#define MT6355_AUXADC_LBAT_CG0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3372))
#define MT6355_AUXADC_THR_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x3374))
#define MT6355_AUXADC_BAT_TEMP_CG0              ((unsigned int)(MT6355_PMIC_REG_BASE+0x3376))
#define MT6355_AUXADC_LBAT2_CG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3378))
#define MT6355_AUXADC_JEITA_CG0                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x337A))
#define MT6355_AUXADC_NAG_CG0                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x337C))
#define MT6355_AUXADC_PRI_NEW                   ((unsigned int)(MT6355_PMIC_REG_BASE+0x337E))
#define MT6355_DRIVER_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3400))
#define MT6355_DRIVER_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3402))
#define MT6355_ISINK0_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3404))
#define MT6355_ISINK1_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3406))
#define MT6355_ISINK2_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x3408))
#define MT6355_ISINK3_CON1                      ((unsigned int)(MT6355_PMIC_REG_BASE+0x340A))
#define MT6355_ISINK_ANA1_SMPL                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x340C))
#define MT6355_ISINK_EN_CTRL_SMPL               ((unsigned int)(MT6355_PMIC_REG_BASE+0x340E))
#define MT6355_AUDDEC_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3600))
#define MT6355_AUDDEC_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3602))
#define MT6355_AUDDEC_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3604))
#define MT6355_AUDDEC_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3606))
#define MT6355_AUDDEC_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3608))
#define MT6355_AUDDEC_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x360A))
#define MT6355_AUDDEC_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x360C))
#define MT6355_AUDDEC_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x360E))
#define MT6355_AUDDEC_ANA_CON8                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3610))
#define MT6355_AUDDEC_ANA_CON9                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3612))
#define MT6355_AUDDEC_ANA_CON10                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3614))
#define MT6355_AUDDEC_ANA_CON11                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3616))
#define MT6355_AUDDEC_ANA_CON12                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3618))
#define MT6355_AUDDEC_ANA_CON13                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x361A))
#define MT6355_AUDDEC_ANA_CON14                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x361C))
#define MT6355_AUDENC_ANA_CON0                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x361E))
#define MT6355_AUDENC_ANA_CON1                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3620))
#define MT6355_AUDENC_ANA_CON2                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3622))
#define MT6355_AUDENC_ANA_CON3                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3624))
#define MT6355_AUDENC_ANA_CON4                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3626))
#define MT6355_AUDENC_ANA_CON5                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3628))
#define MT6355_AUDENC_ANA_CON6                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x362A))
#define MT6355_AUDENC_ANA_CON7                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x362C))
#define MT6355_AUDENC_ANA_CON8                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x362E))
#define MT6355_AUDENC_ANA_CON9                  ((unsigned int)(MT6355_PMIC_REG_BASE+0x3630))
#define MT6355_AUDENC_ANA_CON10                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3632))
#define MT6355_AUDENC_ANA_CON11                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3634))
#define MT6355_AUDENC_ANA_CON12                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3636))
#define MT6355_AUDENC_ANA_CON13                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x3638))
#define MT6355_AUDENC_ANA_CON14                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x363A))
#define MT6355_AUDENC_ANA_CON15                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x363C))
#define MT6355_AUDENC_ANA_CON16                 ((unsigned int)(MT6355_PMIC_REG_BASE+0x363E))
#define MT6355_ZCD_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x3800))
#define MT6355_ZCD_CON1                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x3802))
#define MT6355_ZCD_CON2                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x3804))
#define MT6355_ZCD_CON3                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x3806))
#define MT6355_ZCD_CON4                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x3808))
#define MT6355_ZCD_CON5                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x380A))
#define MT6355_RSV_CON0                         ((unsigned int)(MT6355_PMIC_REG_BASE+0x3A00))
/*--mask is HEX;  shift is Integer--*/
#define PMIC_HWCID_ADDR                                  MT6355_HWCID
#define PMIC_HWCID_MASK                                  0xFFFF
#define PMIC_HWCID_SHIFT                                 0
#define PMIC_SWCID_ADDR                                  MT6355_SWCID
#define PMIC_SWCID_MASK                                  0xFFFF
#define PMIC_SWCID_SHIFT                                 0
#define PMIC_RG_SRCLKEN_IN0_EN_ADDR                      MT6355_TOP_CON
#define PMIC_RG_SRCLKEN_IN0_EN_MASK                      0x1
#define PMIC_RG_SRCLKEN_IN0_EN_SHIFT                     0
#define PMIC_RG_SRCLKEN_IN1_EN_ADDR                      MT6355_TOP_CON
#define PMIC_RG_SRCLKEN_IN1_EN_MASK                      0x1
#define PMIC_RG_SRCLKEN_IN1_EN_SHIFT                     1
#define PMIC_RG_OSC_SEL_ADDR                             MT6355_TOP_CON
#define PMIC_RG_OSC_SEL_MASK                             0x1
#define PMIC_RG_OSC_SEL_SHIFT                            4
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR                 MT6355_TOP_CON
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK                 0x1
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT                5
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR                 MT6355_TOP_CON
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK                 0x1
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT                6
#define PMIC_RG_OSC_SEL_HW_MODE_ADDR                     MT6355_TOP_CON
#define PMIC_RG_OSC_SEL_HW_MODE_MASK                     0x1
#define PMIC_RG_OSC_SEL_HW_MODE_SHIFT                    7
#define PMIC_RG_SRCLKEN_IN_SYNC_EN_ADDR                  MT6355_TOP_CON
#define PMIC_RG_SRCLKEN_IN_SYNC_EN_MASK                  0x1
#define PMIC_RG_SRCLKEN_IN_SYNC_EN_SHIFT                 8
#define PMIC_RG_OSC_EN_AUTO_OFF_ADDR                     MT6355_TOP_CON
#define PMIC_RG_OSC_EN_AUTO_OFF_MASK                     0x1
#define PMIC_RG_OSC_EN_AUTO_OFF_SHIFT                    9
#define PMIC_TEST_OUT_ADDR                               MT6355_TEST_OUT
#define PMIC_TEST_OUT_MASK                               0xFF
#define PMIC_TEST_OUT_SHIFT                              0
#define PMIC_RG_MON_FLAG_SEL_ADDR                        MT6355_TEST_CON0
#define PMIC_RG_MON_FLAG_SEL_MASK                        0xFF
#define PMIC_RG_MON_FLAG_SEL_SHIFT                       0
#define PMIC_RG_MON_GRP_SEL_ADDR                         MT6355_TEST_CON0
#define PMIC_RG_MON_GRP_SEL_MASK                         0x1F
#define PMIC_RG_MON_GRP_SEL_SHIFT                        8
#define PMIC_RG_NANDTREE_MODE_ADDR                       MT6355_TEST_CON1
#define PMIC_RG_NANDTREE_MODE_MASK                       0x1
#define PMIC_RG_NANDTREE_MODE_SHIFT                      0
#define PMIC_RG_TEST_AUXADC_ADDR                         MT6355_TEST_CON1
#define PMIC_RG_TEST_AUXADC_MASK                         0x1
#define PMIC_RG_TEST_AUXADC_SHIFT                        1
#define PMIC_RG_EFUSE_MODE_ADDR                          MT6355_TEST_CON1
#define PMIC_RG_EFUSE_MODE_MASK                          0x1
#define PMIC_RG_EFUSE_MODE_SHIFT                         2
#define PMIC_RG_TEST_STRUP_ADDR                          MT6355_TEST_CON1
#define PMIC_RG_TEST_STRUP_MASK                          0x1
#define PMIC_RG_TEST_STRUP_SHIFT                         3
#define PMIC_TESTMODE_SW_ADDR                            MT6355_TESTMODE_SW
#define PMIC_TESTMODE_SW_MASK                            0x1
#define PMIC_TESTMODE_SW_SHIFT                           0
#define PMIC_VA12_PG_DEB_ADDR                            MT6355_PGDEBSTATUS0
#define PMIC_VA12_PG_DEB_MASK                            0x1
#define PMIC_VA12_PG_DEB_SHIFT                           0
#define PMIC_VA10_PG_DEB_ADDR                            MT6355_PGDEBSTATUS0
#define PMIC_VA10_PG_DEB_MASK                            0x1
#define PMIC_VA10_PG_DEB_SHIFT                           1
#define PMIC_VSRAM_GPU_PG_DEB_ADDR                       MT6355_PGDEBSTATUS0
#define PMIC_VSRAM_GPU_PG_DEB_MASK                       0x1
#define PMIC_VSRAM_GPU_PG_DEB_SHIFT                      2
#define PMIC_VSRAM_MD_PG_DEB_ADDR                        MT6355_PGDEBSTATUS0
#define PMIC_VSRAM_MD_PG_DEB_MASK                        0x1
#define PMIC_VSRAM_MD_PG_DEB_SHIFT                       3
#define PMIC_VSRAM_CORE_PG_DEB_ADDR                      MT6355_PGDEBSTATUS0
#define PMIC_VSRAM_CORE_PG_DEB_MASK                      0x1
#define PMIC_VSRAM_CORE_PG_DEB_SHIFT                     4
#define PMIC_VA18_PG_DEB_ADDR                            MT6355_PGDEBSTATUS0
#define PMIC_VA18_PG_DEB_MASK                            0x1
#define PMIC_VA18_PG_DEB_SHIFT                           5
#define PMIC_BUCK_RSV_PG_DEB_ADDR                        MT6355_PGDEBSTATUS0
#define PMIC_BUCK_RSV_PG_DEB_MASK                        0x1
#define PMIC_BUCK_RSV_PG_DEB_SHIFT                       6
#define PMIC_VDRAM2_PG_DEB_ADDR                          MT6355_PGDEBSTATUS0
#define PMIC_VDRAM2_PG_DEB_MASK                          0x1
#define PMIC_VDRAM2_PG_DEB_SHIFT                         7
#define PMIC_VDRAM1_PG_DEB_ADDR                          MT6355_PGDEBSTATUS0
#define PMIC_VDRAM1_PG_DEB_MASK                          0x1
#define PMIC_VDRAM1_PG_DEB_SHIFT                         8
#define PMIC_VPROC12_PG_DEB_ADDR                         MT6355_PGDEBSTATUS0
#define PMIC_VPROC12_PG_DEB_MASK                         0x1
#define PMIC_VPROC12_PG_DEB_SHIFT                        9
#define PMIC_VPROC11_PG_DEB_ADDR                         MT6355_PGDEBSTATUS0
#define PMIC_VPROC11_PG_DEB_MASK                         0x1
#define PMIC_VPROC11_PG_DEB_SHIFT                        10
#define PMIC_VS1_PG_DEB_ADDR                             MT6355_PGDEBSTATUS0
#define PMIC_VS1_PG_DEB_MASK                             0x1
#define PMIC_VS1_PG_DEB_SHIFT                            11
#define PMIC_VMODEM_PG_DEB_ADDR                          MT6355_PGDEBSTATUS0
#define PMIC_VMODEM_PG_DEB_MASK                          0x1
#define PMIC_VMODEM_PG_DEB_SHIFT                         12
#define PMIC_VGPU_PG_DEB_ADDR                            MT6355_PGDEBSTATUS0
#define PMIC_VGPU_PG_DEB_MASK                            0x1
#define PMIC_VGPU_PG_DEB_SHIFT                           13
#define PMIC_VCORE_PG_DEB_ADDR                           MT6355_PGDEBSTATUS0
#define PMIC_VCORE_PG_DEB_MASK                           0x1
#define PMIC_VCORE_PG_DEB_SHIFT                          14
#define PMIC_VS2_PG_DEB_ADDR                             MT6355_PGDEBSTATUS0
#define PMIC_VS2_PG_DEB_MASK                             0x1
#define PMIC_VS2_PG_DEB_SHIFT                            15
#define PMIC_EXT_PMIC_PG_DEB_ADDR                        MT6355_PGDEBSTATU1
#define PMIC_EXT_PMIC_PG_DEB_MASK                        0x1
#define PMIC_EXT_PMIC_PG_DEB_SHIFT                       7
#define PMIC_VXO18_PG_DEB_ADDR                           MT6355_PGDEBSTATU1
#define PMIC_VXO18_PG_DEB_MASK                           0x1
#define PMIC_VXO18_PG_DEB_SHIFT                          8
#define PMIC_VXO22_PG_DEB_ADDR                           MT6355_PGDEBSTATU1
#define PMIC_VXO22_PG_DEB_MASK                           0x1
#define PMIC_VXO22_PG_DEB_SHIFT                          9
#define PMIC_VUSB33_PG_DEB_ADDR                          MT6355_PGDEBSTATU1
#define PMIC_VUSB33_PG_DEB_MASK                          0x1
#define PMIC_VUSB33_PG_DEB_SHIFT                         10
#define PMIC_VSRAM_PROC_PG_DEB_ADDR                      MT6355_PGDEBSTATU1
#define PMIC_VSRAM_PROC_PG_DEB_MASK                      0x1
#define PMIC_VSRAM_PROC_PG_DEB_SHIFT                     11
#define PMIC_VIO28_PG_DEB_ADDR                           MT6355_PGDEBSTATU1
#define PMIC_VIO28_PG_DEB_MASK                           0x1
#define PMIC_VIO28_PG_DEB_SHIFT                          12
#define PMIC_VUFS18_PG_DEB_ADDR                          MT6355_PGDEBSTATU1
#define PMIC_VUFS18_PG_DEB_MASK                          0x1
#define PMIC_VUFS18_PG_DEB_SHIFT                         13
#define PMIC_VEMC_PG_DEB_ADDR                            MT6355_PGDEBSTATU1
#define PMIC_VEMC_PG_DEB_MASK                            0x1
#define PMIC_VEMC_PG_DEB_SHIFT                           14
#define PMIC_VIO18_PG_DEB_ADDR                           MT6355_PGDEBSTATU1
#define PMIC_VIO18_PG_DEB_MASK                           0x1
#define PMIC_VIO18_PG_DEB_SHIFT                          15
#define PMIC_STRUP_VA12_PG_STATUS_ADDR                   MT6355_PGSTATUS0
#define PMIC_STRUP_VA12_PG_STATUS_MASK                   0x1
#define PMIC_STRUP_VA12_PG_STATUS_SHIFT                  0
#define PMIC_STRUP_VA10_PG_STATUS_ADDR                   MT6355_PGSTATUS0
#define PMIC_STRUP_VA10_PG_STATUS_MASK                   0x1
#define PMIC_STRUP_VA10_PG_STATUS_SHIFT                  1
#define PMIC_STRUP_VSRAM_GPU_PG_STATUS_ADDR              MT6355_PGSTATUS0
#define PMIC_STRUP_VSRAM_GPU_PG_STATUS_MASK              0x1
#define PMIC_STRUP_VSRAM_GPU_PG_STATUS_SHIFT             2
#define PMIC_STRUP_VSRAM_MD_PG_STATUS_ADDR               MT6355_PGSTATUS0
#define PMIC_STRUP_VSRAM_MD_PG_STATUS_MASK               0x1
#define PMIC_STRUP_VSRAM_MD_PG_STATUS_SHIFT              3
#define PMIC_STRUP_VSRAM_CORE_PG_STATUS_ADDR             MT6355_PGSTATUS0
#define PMIC_STRUP_VSRAM_CORE_PG_STATUS_MASK             0x1
#define PMIC_STRUP_VSRAM_CORE_PG_STATUS_SHIFT            4
#define PMIC_STRUP_VA18_PG_STATUS_ADDR                   MT6355_PGSTATUS0
#define PMIC_STRUP_VA18_PG_STATUS_MASK                   0x1
#define PMIC_STRUP_VA18_PG_STATUS_SHIFT                  5
#define PMIC_STRUP_BUCK_RSV_PG_STATUS_ADDR               MT6355_PGSTATUS0
#define PMIC_STRUP_BUCK_RSV_PG_STATUS_MASK               0x1
#define PMIC_STRUP_BUCK_RSV_PG_STATUS_SHIFT              6
#define PMIC_STRUP_VDRAM2_PG_STATUS_ADDR                 MT6355_PGSTATUS0
#define PMIC_STRUP_VDRAM2_PG_STATUS_MASK                 0x1
#define PMIC_STRUP_VDRAM2_PG_STATUS_SHIFT                7
#define PMIC_STRUP_VDRAM1_PG_STATUS_ADDR                 MT6355_PGSTATUS0
#define PMIC_STRUP_VDRAM1_PG_STATUS_MASK                 0x1
#define PMIC_STRUP_VDRAM1_PG_STATUS_SHIFT                8
#define PMIC_STRUP_VPROC12_PG_STATUS_ADDR                MT6355_PGSTATUS0
#define PMIC_STRUP_VPROC12_PG_STATUS_MASK                0x1
#define PMIC_STRUP_VPROC12_PG_STATUS_SHIFT               9
#define PMIC_STRUP_VPROC11_PG_STATUS_ADDR                MT6355_PGSTATUS0
#define PMIC_STRUP_VPROC11_PG_STATUS_MASK                0x1
#define PMIC_STRUP_VPROC11_PG_STATUS_SHIFT               10
#define PMIC_STRUP_VS1_PG_STATUS_ADDR                    MT6355_PGSTATUS0
#define PMIC_STRUP_VS1_PG_STATUS_MASK                    0x1
#define PMIC_STRUP_VS1_PG_STATUS_SHIFT                   11
#define PMIC_STRUP_VMODEM_PG_STATUS_ADDR                 MT6355_PGSTATUS0
#define PMIC_STRUP_VMODEM_PG_STATUS_MASK                 0x1
#define PMIC_STRUP_VMODEM_PG_STATUS_SHIFT                12
#define PMIC_STRUP_VGPU_PG_STATUS_ADDR                   MT6355_PGSTATUS0
#define PMIC_STRUP_VGPU_PG_STATUS_MASK                   0x1
#define PMIC_STRUP_VGPU_PG_STATUS_SHIFT                  13
#define PMIC_STRUP_VCORE_PG_STATUS_ADDR                  MT6355_PGSTATUS0
#define PMIC_STRUP_VCORE_PG_STATUS_MASK                  0x1
#define PMIC_STRUP_VCORE_PG_STATUS_SHIFT                 14
#define PMIC_STRUP_VS2_PG_STATUS_ADDR                    MT6355_PGSTATUS0
#define PMIC_STRUP_VS2_PG_STATUS_MASK                    0x1
#define PMIC_STRUP_VS2_PG_STATUS_SHIFT                   15
#define PMIC_STRUP_EXT_PMIC_PG_STATUS_ADDR               MT6355_PGSTATUS1
#define PMIC_STRUP_EXT_PMIC_PG_STATUS_MASK               0x1
#define PMIC_STRUP_EXT_PMIC_PG_STATUS_SHIFT              7
#define PMIC_STRUP_VXO18_PG_STATUS_ADDR                  MT6355_PGSTATUS1
#define PMIC_STRUP_VXO18_PG_STATUS_MASK                  0x1
#define PMIC_STRUP_VXO18_PG_STATUS_SHIFT                 8
#define PMIC_STRUP_VXO22_PG_STATUS_ADDR                  MT6355_PGSTATUS1
#define PMIC_STRUP_VXO22_PG_STATUS_MASK                  0x1
#define PMIC_STRUP_VXO22_PG_STATUS_SHIFT                 9
#define PMIC_STRUP_VUSB33_PG_STATUS_ADDR                 MT6355_PGSTATUS1
#define PMIC_STRUP_VUSB33_PG_STATUS_MASK                 0x1
#define PMIC_STRUP_VUSB33_PG_STATUS_SHIFT                10
#define PMIC_STRUP_VSRAM_PROC_PG_STATUS_ADDR             MT6355_PGSTATUS1
#define PMIC_STRUP_VSRAM_PROC_PG_STATUS_MASK             0x1
#define PMIC_STRUP_VSRAM_PROC_PG_STATUS_SHIFT            11
#define PMIC_STRUP_VIO28_PG_STATUS_ADDR                  MT6355_PGSTATUS1
#define PMIC_STRUP_VIO28_PG_STATUS_MASK                  0x1
#define PMIC_STRUP_VIO28_PG_STATUS_SHIFT                 12
#define PMIC_STRUP_VUFS18_PG_STATUS_ADDR                 MT6355_PGSTATUS1
#define PMIC_STRUP_VUFS18_PG_STATUS_MASK                 0x1
#define PMIC_STRUP_VUFS18_PG_STATUS_SHIFT                13
#define PMIC_STRUP_VEMC_PG_STATUS_ADDR                   MT6355_PGSTATUS1
#define PMIC_STRUP_VEMC_PG_STATUS_MASK                   0x1
#define PMIC_STRUP_VEMC_PG_STATUS_SHIFT                  14
#define PMIC_STRUP_VIO18_PG_STATUS_ADDR                  MT6355_PGSTATUS1
#define PMIC_STRUP_VIO18_PG_STATUS_MASK                  0x1
#define PMIC_STRUP_VIO18_PG_STATUS_SHIFT                 15
#define PMIC_STRUP_BUCK_RSV_OC_STATUS_ADDR               MT6355_PSOCSTATUS
#define PMIC_STRUP_BUCK_RSV_OC_STATUS_MASK               0x1
#define PMIC_STRUP_BUCK_RSV_OC_STATUS_SHIFT              6
#define PMIC_STRUP_VDRAM2_OC_STATUS_ADDR                 MT6355_PSOCSTATUS
#define PMIC_STRUP_VDRAM2_OC_STATUS_MASK                 0x1
#define PMIC_STRUP_VDRAM2_OC_STATUS_SHIFT                7
#define PMIC_STRUP_VDRAM1_OC_STATUS_ADDR                 MT6355_PSOCSTATUS
#define PMIC_STRUP_VDRAM1_OC_STATUS_MASK                 0x1
#define PMIC_STRUP_VDRAM1_OC_STATUS_SHIFT                8
#define PMIC_STRUP_VPROC12_OC_STATUS_ADDR                MT6355_PSOCSTATUS
#define PMIC_STRUP_VPROC12_OC_STATUS_MASK                0x1
#define PMIC_STRUP_VPROC12_OC_STATUS_SHIFT               9
#define PMIC_STRUP_VPROC11_OC_STATUS_ADDR                MT6355_PSOCSTATUS
#define PMIC_STRUP_VPROC11_OC_STATUS_MASK                0x1
#define PMIC_STRUP_VPROC11_OC_STATUS_SHIFT               10
#define PMIC_STRUP_VS1_OC_STATUS_ADDR                    MT6355_PSOCSTATUS
#define PMIC_STRUP_VS1_OC_STATUS_MASK                    0x1
#define PMIC_STRUP_VS1_OC_STATUS_SHIFT                   11
#define PMIC_STRUP_VMODEM_OC_STATUS_ADDR                 MT6355_PSOCSTATUS
#define PMIC_STRUP_VMODEM_OC_STATUS_MASK                 0x1
#define PMIC_STRUP_VMODEM_OC_STATUS_SHIFT                12
#define PMIC_STRUP_VGPU_OC_STATUS_ADDR                   MT6355_PSOCSTATUS
#define PMIC_STRUP_VGPU_OC_STATUS_MASK                   0x1
#define PMIC_STRUP_VGPU_OC_STATUS_SHIFT                  13
#define PMIC_STRUP_VCORE_OC_STATUS_ADDR                  MT6355_PSOCSTATUS
#define PMIC_STRUP_VCORE_OC_STATUS_MASK                  0x1
#define PMIC_STRUP_VCORE_OC_STATUS_SHIFT                 14
#define PMIC_STRUP_VS2_OC_STATUS_ADDR                    MT6355_PSOCSTATUS
#define PMIC_STRUP_VS2_OC_STATUS_MASK                    0x1
#define PMIC_STRUP_VS2_OC_STATUS_SHIFT                   15
#define PMIC_PMU_THERMAL_DEB_ADDR                        MT6355_THERMALSTATUS
#define PMIC_PMU_THERMAL_DEB_MASK                        0x1
#define PMIC_PMU_THERMAL_DEB_SHIFT                       14
#define PMIC_STRUP_THERMAL_STATUS_ADDR                   MT6355_THERMALSTATUS
#define PMIC_STRUP_THERMAL_STATUS_MASK                   0x1
#define PMIC_STRUP_THERMAL_STATUS_SHIFT                  15
#define PMIC_PMU_TEST_MODE_SCAN_ADDR                     MT6355_TOPSTATUS
#define PMIC_PMU_TEST_MODE_SCAN_MASK                     0x1
#define PMIC_PMU_TEST_MODE_SCAN_SHIFT                    0
#define PMIC_PWRKEY_DEB_ADDR                             MT6355_TOPSTATUS
#define PMIC_PWRKEY_DEB_MASK                             0x1
#define PMIC_PWRKEY_DEB_SHIFT                            1
#define PMIC_HOMEKEY_DEB_ADDR                            MT6355_TOPSTATUS
#define PMIC_HOMEKEY_DEB_MASK                            0x1
#define PMIC_HOMEKEY_DEB_SHIFT                           2
#define PMIC_RTC_XTAL_DET_DONE_ADDR                      MT6355_TOPSTATUS
#define PMIC_RTC_XTAL_DET_DONE_MASK                      0x1
#define PMIC_RTC_XTAL_DET_DONE_SHIFT                     6
#define PMIC_XOSC32_ENB_DET_ADDR                         MT6355_TOPSTATUS
#define PMIC_XOSC32_ENB_DET_MASK                         0x1
#define PMIC_XOSC32_ENB_DET_SHIFT                        7
#define PMIC_RTC_XTAL_DET_RSV_ADDR                       MT6355_TOPSTATUS
#define PMIC_RTC_XTAL_DET_RSV_MASK                       0xF
#define PMIC_RTC_XTAL_DET_RSV_SHIFT                      8
#define PMIC_RG_PMU_TDSEL_ADDR                           MT6355_TDSEL_CON
#define PMIC_RG_PMU_TDSEL_MASK                           0x1
#define PMIC_RG_PMU_TDSEL_SHIFT                          0
#define PMIC_RG_SPI_TDSEL_ADDR                           MT6355_TDSEL_CON
#define PMIC_RG_SPI_TDSEL_MASK                           0x1
#define PMIC_RG_SPI_TDSEL_SHIFT                          1
#define PMIC_RG_AUD_TDSEL_ADDR                           MT6355_TDSEL_CON
#define PMIC_RG_AUD_TDSEL_MASK                           0x1
#define PMIC_RG_AUD_TDSEL_SHIFT                          2
#define PMIC_RG_E32CAL_TDSEL_ADDR                        MT6355_TDSEL_CON
#define PMIC_RG_E32CAL_TDSEL_MASK                        0x1
#define PMIC_RG_E32CAL_TDSEL_SHIFT                       3
#define PMIC_RG_PMU_RDSEL_ADDR                           MT6355_RDSEL_CON
#define PMIC_RG_PMU_RDSEL_MASK                           0x1
#define PMIC_RG_PMU_RDSEL_SHIFT                          0
#define PMIC_RG_SPI_RDSEL_ADDR                           MT6355_RDSEL_CON
#define PMIC_RG_SPI_RDSEL_MASK                           0x1
#define PMIC_RG_SPI_RDSEL_SHIFT                          1
#define PMIC_RG_AUD_RDSEL_ADDR                           MT6355_RDSEL_CON
#define PMIC_RG_AUD_RDSEL_MASK                           0x1
#define PMIC_RG_AUD_RDSEL_SHIFT                          2
#define PMIC_RG_E32CAL_RDSEL_ADDR                        MT6355_RDSEL_CON
#define PMIC_RG_E32CAL_RDSEL_MASK                        0x1
#define PMIC_RG_E32CAL_RDSEL_SHIFT                       3
#define PMIC_RG_SMT_WDTRSTB_IN_ADDR                      MT6355_SMT_CON0
#define PMIC_RG_SMT_WDTRSTB_IN_MASK                      0x1
#define PMIC_RG_SMT_WDTRSTB_IN_SHIFT                     0
#define PMIC_RG_SMT_HOMEKEY_ADDR                         MT6355_SMT_CON0
#define PMIC_RG_SMT_HOMEKEY_MASK                         0x1
#define PMIC_RG_SMT_HOMEKEY_SHIFT                        1
#define PMIC_RG_SMT_SRCLKEN_IN0_ADDR                     MT6355_SMT_CON0
#define PMIC_RG_SMT_SRCLKEN_IN0_MASK                     0x1
#define PMIC_RG_SMT_SRCLKEN_IN0_SHIFT                    2
#define PMIC_RG_SMT_SRCLKEN_IN1_ADDR                     MT6355_SMT_CON0
#define PMIC_RG_SMT_SRCLKEN_IN1_MASK                     0x1
#define PMIC_RG_SMT_SRCLKEN_IN1_SHIFT                    3
#define PMIC_RG_SMT_RTC_32K1V8_0_ADDR                    MT6355_SMT_CON0
#define PMIC_RG_SMT_RTC_32K1V8_0_MASK                    0x1
#define PMIC_RG_SMT_RTC_32K1V8_0_SHIFT                   4
#define PMIC_RG_SMT_RTC_32K1V8_1_ADDR                    MT6355_SMT_CON0
#define PMIC_RG_SMT_RTC_32K1V8_1_MASK                    0x1
#define PMIC_RG_SMT_RTC_32K1V8_1_SHIFT                   5
#define PMIC_RG_SMT_SCP_VREQ_VAO_ADDR                    MT6355_SMT_CON0
#define PMIC_RG_SMT_SCP_VREQ_VAO_MASK                    0x1
#define PMIC_RG_SMT_SCP_VREQ_VAO_SHIFT                   6
#define PMIC_RG_SMT_SPI_CLK_ADDR                         MT6355_SMT_CON1
#define PMIC_RG_SMT_SPI_CLK_MASK                         0x1
#define PMIC_RG_SMT_SPI_CLK_SHIFT                        0
#define PMIC_RG_SMT_SPI_CSN_ADDR                         MT6355_SMT_CON1
#define PMIC_RG_SMT_SPI_CSN_MASK                         0x1
#define PMIC_RG_SMT_SPI_CSN_SHIFT                        1
#define PMIC_RG_SMT_SPI_MOSI_ADDR                        MT6355_SMT_CON1
#define PMIC_RG_SMT_SPI_MOSI_MASK                        0x1
#define PMIC_RG_SMT_SPI_MOSI_SHIFT                       2
#define PMIC_RG_SMT_SPI_MISO_ADDR                        MT6355_SMT_CON1
#define PMIC_RG_SMT_SPI_MISO_MASK                        0x1
#define PMIC_RG_SMT_SPI_MISO_SHIFT                       3
#define PMIC_RG_SMT_AUD_CLK_ADDR                         MT6355_SMT_CON1
#define PMIC_RG_SMT_AUD_CLK_MASK                         0x1
#define PMIC_RG_SMT_AUD_CLK_SHIFT                        4
#define PMIC_RG_SMT_AUD_DAT_MOSI_ADDR                    MT6355_SMT_CON1
#define PMIC_RG_SMT_AUD_DAT_MOSI_MASK                    0x1
#define PMIC_RG_SMT_AUD_DAT_MOSI_SHIFT                   5
#define PMIC_RG_SMT_AUD_DAT_MISO_ADDR                    MT6355_SMT_CON1
#define PMIC_RG_SMT_AUD_DAT_MISO_MASK                    0x1
#define PMIC_RG_SMT_AUD_DAT_MISO_SHIFT                   6
#define PMIC_RG_SMT_VOW_CLK_MISO_ADDR                    MT6355_SMT_CON1
#define PMIC_RG_SMT_VOW_CLK_MISO_MASK                    0x1
#define PMIC_RG_SMT_VOW_CLK_MISO_SHIFT                   7
#define PMIC_RG_OCTL_SRCLKEN_IN0_ADDR                    MT6355_DRV_CON0
#define PMIC_RG_OCTL_SRCLKEN_IN0_MASK                    0xF
#define PMIC_RG_OCTL_SRCLKEN_IN0_SHIFT                   0
#define PMIC_RG_OCTL_SRCLKEN_IN1_ADDR                    MT6355_DRV_CON0
#define PMIC_RG_OCTL_SRCLKEN_IN1_MASK                    0xF
#define PMIC_RG_OCTL_SRCLKEN_IN1_SHIFT                   4
#define PMIC_RG_OCTL_RTC_32K1V8_0_ADDR                   MT6355_DRV_CON0
#define PMIC_RG_OCTL_RTC_32K1V8_0_MASK                   0xF
#define PMIC_RG_OCTL_RTC_32K1V8_0_SHIFT                  8
#define PMIC_RG_OCTL_RTC_32K1V8_1_ADDR                   MT6355_DRV_CON0
#define PMIC_RG_OCTL_RTC_32K1V8_1_MASK                   0xF
#define PMIC_RG_OCTL_RTC_32K1V8_1_SHIFT                  12
#define PMIC_RG_OCTL_SPI_CLK_ADDR                        MT6355_DRV_CON1
#define PMIC_RG_OCTL_SPI_CLK_MASK                        0xF
#define PMIC_RG_OCTL_SPI_CLK_SHIFT                       0
#define PMIC_RG_OCTL_SPI_CSN_ADDR                        MT6355_DRV_CON1
#define PMIC_RG_OCTL_SPI_CSN_MASK                        0xF
#define PMIC_RG_OCTL_SPI_CSN_SHIFT                       4
#define PMIC_RG_OCTL_SPI_MOSI_ADDR                       MT6355_DRV_CON1
#define PMIC_RG_OCTL_SPI_MOSI_MASK                       0xF
#define PMIC_RG_OCTL_SPI_MOSI_SHIFT                      8
#define PMIC_RG_OCTL_SPI_MISO_ADDR                       MT6355_DRV_CON1
#define PMIC_RG_OCTL_SPI_MISO_MASK                       0xF
#define PMIC_RG_OCTL_SPI_MISO_SHIFT                      12
#define PMIC_RG_OCTL_AUD_CLK_ADDR                        MT6355_DRV_CON2
#define PMIC_RG_OCTL_AUD_CLK_MASK                        0xF
#define PMIC_RG_OCTL_AUD_CLK_SHIFT                       0
#define PMIC_RG_OCTL_AUD_DAT_MOSI_ADDR                   MT6355_DRV_CON2
#define PMIC_RG_OCTL_AUD_DAT_MOSI_MASK                   0xF
#define PMIC_RG_OCTL_AUD_DAT_MOSI_SHIFT                  4
#define PMIC_RG_OCTL_AUD_DAT_MISO_ADDR                   MT6355_DRV_CON2
#define PMIC_RG_OCTL_AUD_DAT_MISO_MASK                   0xF
#define PMIC_RG_OCTL_AUD_DAT_MISO_SHIFT                  8
#define PMIC_RG_OCTL_VOW_CLK_MISO_ADDR                   MT6355_DRV_CON2
#define PMIC_RG_OCTL_VOW_CLK_MISO_MASK                   0xF
#define PMIC_RG_OCTL_VOW_CLK_MISO_SHIFT                  12
#define PMIC_RG_OCTL_HOMEKEY_ADDR                        MT6355_DRV_CON3
#define PMIC_RG_OCTL_HOMEKEY_MASK                        0xF
#define PMIC_RG_OCTL_HOMEKEY_SHIFT                       0
#define PMIC_RG_OCTL_SCP_VREQ_VAO_ADDR                   MT6355_DRV_CON3
#define PMIC_RG_OCTL_SCP_VREQ_VAO_MASK                   0xF
#define PMIC_RG_OCTL_SCP_VREQ_VAO_SHIFT                  4
#define PMIC_RG_SPI_CLK_FILTER_EN_ADDR                   MT6355_FILTER_CON0
#define PMIC_RG_SPI_CLK_FILTER_EN_MASK                   0x1
#define PMIC_RG_SPI_CLK_FILTER_EN_SHIFT                  0
#define PMIC_RG_SPI_CSN_FILTER_EN_ADDR                   MT6355_FILTER_CON0
#define PMIC_RG_SPI_CSN_FILTER_EN_MASK                   0x1
#define PMIC_RG_SPI_CSN_FILTER_EN_SHIFT                  1
#define PMIC_RG_SPI_MOSI_FILTER_EN_ADDR                  MT6355_FILTER_CON0
#define PMIC_RG_SPI_MOSI_FILTER_EN_MASK                  0x1
#define PMIC_RG_SPI_MOSI_FILTER_EN_SHIFT                 2
#define PMIC_RG_SPI_MISO_FILTER_EN_ADDR                  MT6355_FILTER_CON0
#define PMIC_RG_SPI_MISO_FILTER_EN_MASK                  0x1
#define PMIC_RG_SPI_MISO_FILTER_EN_SHIFT                 3
#define PMIC_RG_AUD_CLK_FILTER_EN_ADDR                   MT6355_FILTER_CON0
#define PMIC_RG_AUD_CLK_FILTER_EN_MASK                   0x1
#define PMIC_RG_AUD_CLK_FILTER_EN_SHIFT                  4
#define PMIC_RG_AUD_DAT_MOSI_FILTER_EN_ADDR              MT6355_FILTER_CON0
#define PMIC_RG_AUD_DAT_MOSI_FILTER_EN_MASK              0x1
#define PMIC_RG_AUD_DAT_MOSI_FILTER_EN_SHIFT             5
#define PMIC_RG_AUD_DAT_MISO_FILTER_EN_ADDR              MT6355_FILTER_CON0
#define PMIC_RG_AUD_DAT_MISO_FILTER_EN_MASK              0x1
#define PMIC_RG_AUD_DAT_MISO_FILTER_EN_SHIFT             6
#define PMIC_RG_VOW_CLK_MISO_FILTER_EN_ADDR              MT6355_FILTER_CON0
#define PMIC_RG_VOW_CLK_MISO_FILTER_EN_MASK              0x1
#define PMIC_RG_VOW_CLK_MISO_FILTER_EN_SHIFT             7
#define PMIC_RG_WDTRSTB_IN_FILTER_EN_ADDR                MT6355_FILTER_CON0
#define PMIC_RG_WDTRSTB_IN_FILTER_EN_MASK                0x1
#define PMIC_RG_WDTRSTB_IN_FILTER_EN_SHIFT               8
#define PMIC_RG_HOMEKEY_FILTER_EN_ADDR                   MT6355_FILTER_CON0
#define PMIC_RG_HOMEKEY_FILTER_EN_MASK                   0x1
#define PMIC_RG_HOMEKEY_FILTER_EN_SHIFT                  9
#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_ADDR               MT6355_FILTER_CON0
#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_MASK               0x1
#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_SHIFT              10
#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_ADDR               MT6355_FILTER_CON0
#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_MASK               0x1
#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_SHIFT              11
#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_ADDR              MT6355_FILTER_CON0
#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_MASK              0x1
#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_SHIFT             12
#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_ADDR              MT6355_FILTER_CON0
#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_MASK              0x1
#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_SHIFT             13
#define PMIC_RG_SCP_VREQ_VAO_FILTER_EN_ADDR              MT6355_FILTER_CON0
#define PMIC_RG_SCP_VREQ_VAO_FILTER_EN_MASK              0x1
#define PMIC_RG_SCP_VREQ_VAO_FILTER_EN_SHIFT             14
#define PMIC_RG_SPI_CLK_RCSEL_ADDR                       MT6355_FILTER_CON1
#define PMIC_RG_SPI_CLK_RCSEL_MASK                       0x1
#define PMIC_RG_SPI_CLK_RCSEL_SHIFT                      0
#define PMIC_RG_SPI_CSN_RCSEL_ADDR                       MT6355_FILTER_CON1
#define PMIC_RG_SPI_CSN_RCSEL_MASK                       0x1
#define PMIC_RG_SPI_CSN_RCSEL_SHIFT                      1
#define PMIC_RG_SPI_MOSI_RCSEL_ADDR                      MT6355_FILTER_CON1
#define PMIC_RG_SPI_MOSI_RCSEL_MASK                      0x1
#define PMIC_RG_SPI_MOSI_RCSEL_SHIFT                     2
#define PMIC_RG_SPI_MISO_RCSEL_ADDR                      MT6355_FILTER_CON1
#define PMIC_RG_SPI_MISO_RCSEL_MASK                      0x1
#define PMIC_RG_SPI_MISO_RCSEL_SHIFT                     3
#define PMIC_RG_AUD_CLK_RCSEL_ADDR                       MT6355_FILTER_CON1
#define PMIC_RG_AUD_CLK_RCSEL_MASK                       0x1
#define PMIC_RG_AUD_CLK_RCSEL_SHIFT                      4
#define PMIC_RG_AUD_DAT_MOSI_RCSEL_ADDR                  MT6355_FILTER_CON1
#define PMIC_RG_AUD_DAT_MOSI_RCSEL_MASK                  0x1
#define PMIC_RG_AUD_DAT_MOSI_RCSEL_SHIFT                 5
#define PMIC_RG_AUD_DAT_MISO_RCSEL_ADDR                  MT6355_FILTER_CON1
#define PMIC_RG_AUD_DAT_MISO_RCSEL_MASK                  0x1
#define PMIC_RG_AUD_DAT_MISO_RCSEL_SHIFT                 6
#define PMIC_RG_VOW_CLK_MISO_RCSEL_ADDR                  MT6355_FILTER_CON1
#define PMIC_RG_VOW_CLK_MISO_RCSEL_MASK                  0x1
#define PMIC_RG_VOW_CLK_MISO_RCSEL_SHIFT                 7
#define PMIC_RG_WDTRSTB_IN_RCSEL_ADDR                    MT6355_FILTER_CON1
#define PMIC_RG_WDTRSTB_IN_RCSEL_MASK                    0x1
#define PMIC_RG_WDTRSTB_IN_RCSEL_SHIFT                   8
#define PMIC_RG_HOMEKEY_RCSEL_ADDR                       MT6355_FILTER_CON1
#define PMIC_RG_HOMEKEY_RCSEL_MASK                       0x1
#define PMIC_RG_HOMEKEY_RCSEL_SHIFT                      9
#define PMIC_RG_SRCLKEN_IN0_RCSEL_ADDR                   MT6355_FILTER_CON1
#define PMIC_RG_SRCLKEN_IN0_RCSEL_MASK                   0x1
#define PMIC_RG_SRCLKEN_IN0_RCSEL_SHIFT                  10
#define PMIC_RG_SRCLKEN_IN1_RCSEL_ADDR                   MT6355_FILTER_CON1
#define PMIC_RG_SRCLKEN_IN1_RCSEL_MASK                   0x1
#define PMIC_RG_SRCLKEN_IN1_RCSEL_SHIFT                  11
#define PMIC_RG_RTC32K_1V8_0_RCSEL_ADDR                  MT6355_FILTER_CON1
#define PMIC_RG_RTC32K_1V8_0_RCSEL_MASK                  0x1
#define PMIC_RG_RTC32K_1V8_0_RCSEL_SHIFT                 12
#define PMIC_RG_RTC32K_1V8_1_RCSEL_ADDR                  MT6355_FILTER_CON1
#define PMIC_RG_RTC32K_1V8_1_RCSEL_MASK                  0x1
#define PMIC_RG_RTC32K_1V8_1_RCSEL_SHIFT                 13
#define PMIC_RG_SCP_VREQ_VAO_RCSEL_ADDR                  MT6355_FILTER_CON1
#define PMIC_RG_SCP_VREQ_VAO_RCSEL_MASK                  0x1
#define PMIC_RG_SCP_VREQ_VAO_RCSEL_SHIFT                 14
#define PMIC_TOP_STATUS_ADDR                             MT6355_TOP_STATUS
#define PMIC_TOP_STATUS_MASK                             0xF
#define PMIC_TOP_STATUS_SHIFT                            0
#define PMIC_TOP_STATUS_SET_ADDR                         MT6355_TOP_STATUS_SET
#define PMIC_TOP_STATUS_SET_MASK                         0x3
#define PMIC_TOP_STATUS_SET_SHIFT                        0
#define PMIC_TOP_STATUS_CLR_ADDR                         MT6355_TOP_STATUS_CLR
#define PMIC_TOP_STATUS_CLR_MASK                         0x3
#define PMIC_TOP_STATUS_CLR_SHIFT                        0
#define PMIC_RG_SRCLKEN_IN2_EN_ADDR                      MT6355_TOP_SPI_CON0
#define PMIC_RG_SRCLKEN_IN2_EN_MASK                      0x1
#define PMIC_RG_SRCLKEN_IN2_EN_SHIFT                     0
#define PMIC_RG_SRCLKEN_IN3_EN_ADDR                      MT6355_TOP_SPI_CON1
#define PMIC_RG_SRCLKEN_IN3_EN_MASK                      0x1
#define PMIC_RG_SRCLKEN_IN3_EN_SHIFT                     0
#define PMIC_VM_MODE_ADDR                                MT6355_TOP_TRAP
#define PMIC_VM_MODE_MASK                                0x3
#define PMIC_VM_MODE_SHIFT                               0
#define PMIC_RG_G_SMPS_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON0
#define PMIC_RG_G_SMPS_CK_PDN_MASK                       0x1
#define PMIC_RG_G_SMPS_CK_PDN_SHIFT                      0
#define PMIC_RG_G_SMPS_TEST_CK_PDN_ADDR                  MT6355_TOP_CKPDN_CON0
#define PMIC_RG_G_SMPS_TEST_CK_PDN_MASK                  0x1
#define PMIC_RG_G_SMPS_TEST_CK_PDN_SHIFT                 1
#define PMIC_RG_INTRP_CK_PDN_ADDR                        MT6355_TOP_CKPDN_CON0
#define PMIC_RG_INTRP_CK_PDN_MASK                        0x1
#define PMIC_RG_INTRP_CK_PDN_SHIFT                       2
#define PMIC_RG_INTRP_PRE_OC_CK_PDN_ADDR                 MT6355_TOP_CKPDN_CON0
#define PMIC_RG_INTRP_PRE_OC_CK_PDN_MASK                 0x1
#define PMIC_RG_INTRP_PRE_OC_CK_PDN_SHIFT                3
#define PMIC_RG_G_BIF_1M_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON0
#define PMIC_RG_G_BIF_1M_CK_PDN_MASK                     0x1
#define PMIC_RG_G_BIF_1M_CK_PDN_SHIFT                    4
#define PMIC_RG_BIF_X1_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON0
#define PMIC_RG_BIF_X1_CK_PDN_MASK                       0x1
#define PMIC_RG_BIF_X1_CK_PDN_SHIFT                      5
#define PMIC_RG_BIF_X4_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON0
#define PMIC_RG_BIF_X4_CK_PDN_MASK                       0x1
#define PMIC_RG_BIF_X4_CK_PDN_SHIFT                      6
#define PMIC_RG_BIF_X72_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON0
#define PMIC_RG_BIF_X72_CK_PDN_MASK                      0x1
#define PMIC_RG_BIF_X72_CK_PDN_SHIFT                     7
#define PMIC_RG_AUXADC_AO_1M_CK_PDN_ADDR                 MT6355_TOP_CKPDN_CON0
#define PMIC_RG_AUXADC_AO_1M_CK_PDN_MASK                 0x1
#define PMIC_RG_AUXADC_AO_1M_CK_PDN_SHIFT                8
#define PMIC_RG_AUXADC_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON0
#define PMIC_RG_AUXADC_CK_PDN_MASK                       0x1
#define PMIC_RG_AUXADC_CK_PDN_SHIFT                      9
#define PMIC_RG_AUXADC_RNG_CK_PDN_ADDR                   MT6355_TOP_CKPDN_CON0
#define PMIC_RG_AUXADC_RNG_CK_PDN_MASK                   0x1
#define PMIC_RG_AUXADC_RNG_CK_PDN_SHIFT                  10
#define PMIC_RG_AUXADC_1M_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON0
#define PMIC_RG_AUXADC_1M_CK_PDN_MASK                    0x1
#define PMIC_RG_AUXADC_1M_CK_PDN_SHIFT                   11
#define PMIC_RG_DRV_32K_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON0
#define PMIC_RG_DRV_32K_CK_PDN_MASK                      0x1
#define PMIC_RG_DRV_32K_CK_PDN_SHIFT                     12
#define PMIC_RG_TOP_CKPDN_CON0_RSV_ADDR                  MT6355_TOP_CKPDN_CON0
#define PMIC_RG_TOP_CKPDN_CON0_RSV_MASK                  0x7
#define PMIC_RG_TOP_CKPDN_CON0_RSV_SHIFT                 13
#define PMIC_TOP_CKPDN_CON0_SET_ADDR                     MT6355_TOP_CKPDN_CON0_SET
#define PMIC_TOP_CKPDN_CON0_SET_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON0_SET_SHIFT                    0
#define PMIC_TOP_CKPDN_CON0_CLR_ADDR                     MT6355_TOP_CKPDN_CON0_CLR
#define PMIC_TOP_CKPDN_CON0_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON0_CLR_SHIFT                    0
#define PMIC_RG_BUCK_9M_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BUCK_9M_CK_PDN_MASK                      0x1
#define PMIC_RG_BUCK_9M_CK_PDN_SHIFT                     0
#define PMIC_RG_BUCK_1M_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BUCK_1M_CK_PDN_MASK                      0x1
#define PMIC_RG_BUCK_1M_CK_PDN_SHIFT                     1
#define PMIC_RG_BUCK_18M_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BUCK_18M_CK_PDN_MASK                     0x1
#define PMIC_RG_BUCK_18M_CK_PDN_SHIFT                    2
#define PMIC_RG_BUCK_32K_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BUCK_32K_CK_PDN_MASK                     0x1
#define PMIC_RG_BUCK_32K_CK_PDN_SHIFT                    3
#define PMIC_RG_LDO_9M_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON1
#define PMIC_RG_LDO_9M_CK_PDN_MASK                       0x1
#define PMIC_RG_LDO_9M_CK_PDN_SHIFT                      4
#define PMIC_RG_LDO_1M_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON1
#define PMIC_RG_LDO_1M_CK_PDN_MASK                       0x1
#define PMIC_RG_LDO_1M_CK_PDN_SHIFT                      5
#define PMIC_RG_RSV0_CK_PDN_ADDR                         MT6355_TOP_CKPDN_CON1
#define PMIC_RG_RSV0_CK_PDN_MASK                         0x1
#define PMIC_RG_RSV0_CK_PDN_SHIFT                        6
#define PMIC_RG_BUCK_ANA_CLK_PDN_ADDR                    MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BUCK_ANA_CLK_PDN_MASK                    0x1
#define PMIC_RG_BUCK_ANA_CLK_PDN_SHIFT                   7
#define PMIC_RG_TRIM_75K_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON1
#define PMIC_RG_TRIM_75K_CK_PDN_MASK                     0x1
#define PMIC_RG_TRIM_75K_CK_PDN_SHIFT                    8
#define PMIC_RG_CHDET_75K_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON1
#define PMIC_RG_CHDET_75K_CK_PDN_MASK                    0x1
#define PMIC_RG_CHDET_75K_CK_PDN_SHIFT                   9
#define PMIC_RG_SPI_CK_PDN_ADDR                          MT6355_TOP_CKPDN_CON1
#define PMIC_RG_SPI_CK_PDN_MASK                          0x1
#define PMIC_RG_SPI_CK_PDN_SHIFT                         10
#define PMIC_RG_REG_CK_PDN_ADDR                          MT6355_TOP_CKPDN_CON1
#define PMIC_RG_REG_CK_PDN_MASK                          0x1
#define PMIC_RG_REG_CK_PDN_SHIFT                         11
#define PMIC_RG_BGR_TEST_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BGR_TEST_CK_PDN_MASK                     0x1
#define PMIC_RG_BGR_TEST_CK_PDN_SHIFT                    12
#define PMIC_RG_FQMTR_32K_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON1
#define PMIC_RG_FQMTR_32K_CK_PDN_MASK                    0x1
#define PMIC_RG_FQMTR_32K_CK_PDN_SHIFT                   13
#define PMIC_RG_FQMTR_CK_PDN_ADDR                        MT6355_TOP_CKPDN_CON1
#define PMIC_RG_FQMTR_CK_PDN_MASK                        0x1
#define PMIC_RG_FQMTR_CK_PDN_SHIFT                       14
#define PMIC_RG_BUCK_ANA_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON1
#define PMIC_RG_BUCK_ANA_CK_PDN_MASK                     0x1
#define PMIC_RG_BUCK_ANA_CK_PDN_SHIFT                    15
#define PMIC_TOP_CKPDN_CON1_SET_ADDR                     MT6355_TOP_CKPDN_CON1_SET
#define PMIC_TOP_CKPDN_CON1_SET_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON1_SET_SHIFT                    0
#define PMIC_TOP_CKPDN_CON1_CLR_ADDR                     MT6355_TOP_CKPDN_CON1_CLR
#define PMIC_TOP_CKPDN_CON1_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON1_CLR_SHIFT                    0
#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_ADDR               MT6355_TOP_CKPDN_CON2
#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_MASK               0x1
#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_SHIFT              0
#define PMIC_RG_RTC_EOSC32_CK_PDN_ADDR                   MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC_EOSC32_CK_PDN_MASK                   0x1
#define PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT                  1
#define PMIC_RG_RTC_SEC_32K_CK_PDN_ADDR                  MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC_SEC_32K_CK_PDN_MASK                  0x1
#define PMIC_RG_RTC_SEC_32K_CK_PDN_SHIFT                 2
#define PMIC_RG_RTC_MCLK_PDN_ADDR                        MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC_MCLK_PDN_MASK                        0x1
#define PMIC_RG_RTC_MCLK_PDN_SHIFT                       4
#define PMIC_RG_RTC_32K_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC_32K_CK_PDN_MASK                      0x1
#define PMIC_RG_RTC_32K_CK_PDN_SHIFT                     5
#define PMIC_RG_RTC_26M_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC_26M_CK_PDN_MASK                      0x1
#define PMIC_RG_RTC_26M_CK_PDN_SHIFT                     6
#define PMIC_RG_FGADC_FT_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON2
#define PMIC_RG_FGADC_FT_CK_PDN_MASK                     0x1
#define PMIC_RG_FGADC_FT_CK_PDN_SHIFT                    7
#define PMIC_RG_FGADC_DIG_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON2
#define PMIC_RG_FGADC_DIG_CK_PDN_MASK                    0x1
#define PMIC_RG_FGADC_DIG_CK_PDN_SHIFT                   8
#define PMIC_RG_FGADC_ANA_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON2
#define PMIC_RG_FGADC_ANA_CK_PDN_MASK                    0x1
#define PMIC_RG_FGADC_ANA_CK_PDN_SHIFT                   9
#define PMIC_RG_STRUP_32K_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON2
#define PMIC_RG_STRUP_32K_CK_PDN_MASK                    0x1
#define PMIC_RG_STRUP_32K_CK_PDN_SHIFT                   10
#define PMIC_RG_STRUP_75K_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON2
#define PMIC_RG_STRUP_75K_CK_PDN_MASK                    0x1
#define PMIC_RG_STRUP_75K_CK_PDN_SHIFT                   11
#define PMIC_RG_RTC32K_1V8_0_O_PDN_ADDR                  MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC32K_1V8_0_O_PDN_MASK                  0x1
#define PMIC_RG_RTC32K_1V8_0_O_PDN_SHIFT                 12
#define PMIC_RG_RTC32K_1V8_1_O_PDN_ADDR                  MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC32K_1V8_1_O_PDN_MASK                  0x1
#define PMIC_RG_RTC32K_1V8_1_O_PDN_SHIFT                 13
#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_ADDR                MT6355_TOP_CKPDN_CON2
#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_MASK                0x1
#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_SHIFT               14
#define PMIC_RG_SMPS_CK_DIV_PDN_ADDR                     MT6355_TOP_CKPDN_CON2
#define PMIC_RG_SMPS_CK_DIV_PDN_MASK                     0x1
#define PMIC_RG_SMPS_CK_DIV_PDN_SHIFT                    15
#define PMIC_TOP_CKPDN_CON2_SET_ADDR                     MT6355_TOP_CKPDN_CON2_SET
#define PMIC_TOP_CKPDN_CON2_SET_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON2_SET_SHIFT                    0
#define PMIC_TOP_CKPDN_CON2_CLR_ADDR                     MT6355_TOP_CKPDN_CON2_CLR
#define PMIC_TOP_CKPDN_CON2_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON2_CLR_SHIFT                    0
#define PMIC_RG_BATON_75K_CK_PDN_ADDR                    MT6355_TOP_CKPDN_CON3
#define PMIC_RG_BATON_75K_CK_PDN_MASK                    0x1
#define PMIC_RG_BATON_75K_CK_PDN_SHIFT                   0
#define PMIC_RG_EFUSE_CK_PDN_ADDR                        MT6355_TOP_CKPDN_CON3
#define PMIC_RG_EFUSE_CK_PDN_MASK                        0x1
#define PMIC_RG_EFUSE_CK_PDN_SHIFT                       1
#define PMIC_RG_ACCDET_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON3
#define PMIC_RG_ACCDET_CK_PDN_MASK                       0x1
#define PMIC_RG_ACCDET_CK_PDN_SHIFT                      2
#define PMIC_RG_AUD_CK_PDN_ADDR                          MT6355_TOP_CKPDN_CON3
#define PMIC_RG_AUD_CK_PDN_MASK                          0x1
#define PMIC_RG_AUD_CK_PDN_SHIFT                         3
#define PMIC_RG_AUDIF_CK_PDN_ADDR                        MT6355_TOP_CKPDN_CON3
#define PMIC_RG_AUDIF_CK_PDN_MASK                        0x1
#define PMIC_RG_AUDIF_CK_PDN_SHIFT                       4
#define PMIC_RG_VOW32K_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON3
#define PMIC_RG_VOW32K_CK_PDN_MASK                       0x1
#define PMIC_RG_VOW32K_CK_PDN_SHIFT                      5
#define PMIC_RG_VOW12M_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON3
#define PMIC_RG_VOW12M_CK_PDN_MASK                       0x1
#define PMIC_RG_VOW12M_CK_PDN_SHIFT                      6
#define PMIC_RG_ZCD13M_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON3
#define PMIC_RG_ZCD13M_CK_PDN_MASK                       0x1
#define PMIC_RG_ZCD13M_CK_PDN_SHIFT                      7
#define PMIC_RG_RTC_SEC_MCLK_PDN_ADDR                    MT6355_TOP_CKPDN_CON3
#define PMIC_RG_RTC_SEC_MCLK_PDN_MASK                    0x1
#define PMIC_RG_RTC_SEC_MCLK_PDN_SHIFT                   8
#define PMIC_RG_AUXADC_32K_CK_PDN_ADDR                   MT6355_TOP_CKPDN_CON3
#define PMIC_RG_AUXADC_32K_CK_PDN_MASK                   0x1
#define PMIC_RG_AUXADC_32K_CK_PDN_SHIFT                  9
#define PMIC_RG_EINT_32K_CK_PDN_ADDR                     MT6355_TOP_CKPDN_CON3
#define PMIC_RG_EINT_32K_CK_PDN_MASK                     0x1
#define PMIC_RG_EINT_32K_CK_PDN_SHIFT                    10
#define PMIC_RG_TOP_CKPDN_CON3_RSV_ADDR                  MT6355_TOP_CKPDN_CON3
#define PMIC_RG_TOP_CKPDN_CON3_RSV_MASK                  0x1F
#define PMIC_RG_TOP_CKPDN_CON3_RSV_SHIFT                 11
#define PMIC_TOP_CKPDN_CON3_SET_ADDR                     MT6355_TOP_CKPDN_CON3_SET
#define PMIC_TOP_CKPDN_CON3_SET_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON3_SET_SHIFT                    0
#define PMIC_TOP_CKPDN_CON3_CLR_ADDR                     MT6355_TOP_CKPDN_CON3_CLR
#define PMIC_TOP_CKPDN_CON3_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON3_CLR_SHIFT                    0
#define PMIC_RG_RTCDET_CK_PDN_ADDR                       MT6355_TOP_CKPDN_CON4
#define PMIC_RG_RTCDET_CK_PDN_MASK                       0x1
#define PMIC_RG_RTCDET_CK_PDN_SHIFT                      0
#define PMIC_RG_RTC_75K_CK_PDN_ADDR                      MT6355_TOP_CKPDN_CON4
#define PMIC_RG_RTC_75K_CK_PDN_MASK                      0x1
#define PMIC_RG_RTC_75K_CK_PDN_SHIFT                     1
#define PMIC_TOP_CKPDN_CON4_SET_ADDR                     MT6355_TOP_CKPDN_CON4_SET
#define PMIC_TOP_CKPDN_CON4_SET_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON4_SET_SHIFT                    0
#define PMIC_TOP_CKPDN_CON4_CLR_ADDR                     MT6355_TOP_CKPDN_CON4_CLR
#define PMIC_TOP_CKPDN_CON4_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKPDN_CON4_CLR_SHIFT                    0
#define PMIC_RG_FQMTR_CK_CKSEL_ADDR                      MT6355_TOP_CKSEL_CON0
#define PMIC_RG_FQMTR_CK_CKSEL_MASK                      0x7
#define PMIC_RG_FQMTR_CK_CKSEL_SHIFT                     0
#define PMIC_RG_75K_32K_SEL_ADDR                         MT6355_TOP_CKSEL_CON0
#define PMIC_RG_75K_32K_SEL_MASK                         0x1
#define PMIC_RG_75K_32K_SEL_SHIFT                        3
#define PMIC_RG_FGADC_ANA_CK_CKSEL_ADDR                  MT6355_TOP_CKSEL_CON0
#define PMIC_RG_FGADC_ANA_CK_CKSEL_MASK                  0x1
#define PMIC_RG_FGADC_ANA_CK_CKSEL_SHIFT                 4
#define PMIC_RG_BGR_TEST_CK_CKSEL_ADDR                   MT6355_TOP_CKSEL_CON0
#define PMIC_RG_BGR_TEST_CK_CKSEL_MASK                   0x1
#define PMIC_RG_BGR_TEST_CK_CKSEL_SHIFT                  5
#define PMIC_RG_AUD_CK_CKSEL_ADDR                        MT6355_TOP_CKSEL_CON0
#define PMIC_RG_AUD_CK_CKSEL_MASK                        0x1
#define PMIC_RG_AUD_CK_CKSEL_SHIFT                       6
#define PMIC_RG_AUDIF_CK_CKSEL_ADDR                      MT6355_TOP_CKSEL_CON0
#define PMIC_RG_AUDIF_CK_CKSEL_MASK                      0x1
#define PMIC_RG_AUDIF_CK_CKSEL_SHIFT                     7
#define PMIC_RG_TOP_CKSEL_CON0_RSV_ADDR                  MT6355_TOP_CKSEL_CON0
#define PMIC_RG_TOP_CKSEL_CON0_RSV_MASK                  0xFF
#define PMIC_RG_TOP_CKSEL_CON0_RSV_SHIFT                 8
#define PMIC_TOP_CKSEL_CON0_SET_ADDR                     MT6355_TOP_CKSEL_CON0_SET
#define PMIC_TOP_CKSEL_CON0_SET_MASK                     0xFFFF
#define PMIC_TOP_CKSEL_CON0_SET_SHIFT                    0
#define PMIC_TOP_CKSEL_CON0_CLR_ADDR                     MT6355_TOP_CKSEL_CON0_CLR
#define PMIC_TOP_CKSEL_CON0_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKSEL_CON0_CLR_SHIFT                    0
#define PMIC_RG_SRCVOLTEN_SW_ADDR                        MT6355_TOP_CKSEL_CON2
#define PMIC_RG_SRCVOLTEN_SW_MASK                        0x1
#define PMIC_RG_SRCVOLTEN_SW_SHIFT                       0
#define PMIC_RG_BUCK_OSC_SEL_SW_ADDR                     MT6355_TOP_CKSEL_CON2
#define PMIC_RG_BUCK_OSC_SEL_SW_MASK                     0x1
#define PMIC_RG_BUCK_OSC_SEL_SW_SHIFT                    2
#define PMIC_RG_VOWEN_SW_ADDR                            MT6355_TOP_CKSEL_CON2
#define PMIC_RG_VOWEN_SW_MASK                            0x1
#define PMIC_RG_VOWEN_SW_SHIFT                           3
#define PMIC_RG_SRCVOLTEN_MODE_ADDR                      MT6355_TOP_CKSEL_CON2
#define PMIC_RG_SRCVOLTEN_MODE_MASK                      0x1
#define PMIC_RG_SRCVOLTEN_MODE_SHIFT                     4
#define PMIC_RG_BUCK_OSC_SEL_MODE_ADDR                   MT6355_TOP_CKSEL_CON2
#define PMIC_RG_BUCK_OSC_SEL_MODE_MASK                   0x1
#define PMIC_RG_BUCK_OSC_SEL_MODE_SHIFT                  6
#define PMIC_RG_VOWEN_MODE_ADDR                          MT6355_TOP_CKSEL_CON2
#define PMIC_RG_VOWEN_MODE_MASK                          0x1
#define PMIC_RG_VOWEN_MODE_SHIFT                         7
#define PMIC_RG_TOP_CKSEL_CON2_RSV_ADDR                  MT6355_TOP_CKSEL_CON2
#define PMIC_RG_TOP_CKSEL_CON2_RSV_MASK                  0xFF
#define PMIC_RG_TOP_CKSEL_CON2_RSV_SHIFT                 8
#define PMIC_TOP_CKSEL_CON2_SET_ADDR                     MT6355_TOP_CKSEL_CON2_SET
#define PMIC_TOP_CKSEL_CON2_SET_MASK                     0xFFFF
#define PMIC_TOP_CKSEL_CON2_SET_SHIFT                    0
#define PMIC_TOP_CKSEL_CON2_CLR_ADDR                     MT6355_TOP_CKSEL_CON2_CLR
#define PMIC_TOP_CKSEL_CON2_CLR_MASK                     0xFFFF
#define PMIC_TOP_CKSEL_CON2_CLR_SHIFT                    0
#define PMIC_RG_AUXADC_CK_DIVSEL_ADDR                    MT6355_TOP_CKDIVSEL_CON0
#define PMIC_RG_AUXADC_CK_DIVSEL_MASK                    0x3
#define PMIC_RG_AUXADC_CK_DIVSEL_SHIFT                   0
#define PMIC_RG_LDO_9M_CK_DIVSEL_ADDR                    MT6355_TOP_CKDIVSEL_CON0
#define PMIC_RG_LDO_9M_CK_DIVSEL_MASK                    0x1
#define PMIC_RG_LDO_9M_CK_DIVSEL_SHIFT                   2
#define PMIC_RG_BUCK_9M_CK_DIVSEL_ADDR                   MT6355_TOP_CKDIVSEL_CON0
#define PMIC_RG_BUCK_9M_CK_DIVSEL_MASK                   0x1
#define PMIC_RG_BUCK_9M_CK_DIVSEL_SHIFT                  3
#define PMIC_RG_BIF_X4_CK_DIVSEL_ADDR                    MT6355_TOP_CKDIVSEL_CON0
#define PMIC_RG_BIF_X4_CK_DIVSEL_MASK                    0x7
#define PMIC_RG_BIF_X4_CK_DIVSEL_SHIFT                   4
#define PMIC_RG_REG_CK_DIVSEL_ADDR                       MT6355_TOP_CKDIVSEL_CON0
#define PMIC_RG_REG_CK_DIVSEL_MASK                       0x3
#define PMIC_RG_REG_CK_DIVSEL_SHIFT                      8
#define PMIC_TOP_CKDIVSEL_CON0_RSV_ADDR                  MT6355_TOP_CKDIVSEL_CON0
#define PMIC_TOP_CKDIVSEL_CON0_RSV_MASK                  0x3F
#define PMIC_TOP_CKDIVSEL_CON0_RSV_SHIFT                 10
#define PMIC_TOP_CKDIVSEL_CON0_SET_ADDR                  MT6355_TOP_CKDIVSEL_CON0_SET
#define PMIC_TOP_CKDIVSEL_CON0_SET_MASK                  0xFFFF
#define PMIC_TOP_CKDIVSEL_CON0_SET_SHIFT                 0
#define PMIC_TOP_CKDIVSEL_CON0_CLR_ADDR                  MT6355_TOP_CKDIVSEL_CON0_CLR
#define PMIC_TOP_CKDIVSEL_CON0_CLR_MASK                  0xFFFF
#define PMIC_TOP_CKDIVSEL_CON0_CLR_SHIFT                 0
#define PMIC_RG_G_SMPS_CK_PDN_HWEN_ADDR                  MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_G_SMPS_CK_PDN_HWEN_MASK                  0x1
#define PMIC_RG_G_SMPS_CK_PDN_HWEN_SHIFT                 0
#define PMIC_RG_SMPS_PD_1M_CK_PDN_HWEN_ADDR              MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_SMPS_PD_1M_CK_PDN_HWEN_MASK              0x1
#define PMIC_RG_SMPS_PD_1M_CK_PDN_HWEN_SHIFT             1
#define PMIC_RG_AUXADC_CK_PDN_HWEN_ADDR                  MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_AUXADC_CK_PDN_HWEN_MASK                  0x1
#define PMIC_RG_AUXADC_CK_PDN_HWEN_SHIFT                 2
#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_ADDR              MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_MASK              0x1
#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_SHIFT             3
#define PMIC_RG_BIF_X4_CK_PDN_HWEN_ADDR                  MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_BIF_X4_CK_PDN_HWEN_MASK                  0x1
#define PMIC_RG_BIF_X4_CK_PDN_HWEN_SHIFT                 4
#define PMIC_RG_BIF_X72_CK_PDN_HWEN_ADDR                 MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_BIF_X72_CK_PDN_HWEN_MASK                 0x1
#define PMIC_RG_BIF_X72_CK_PDN_HWEN_SHIFT                5
#define PMIC_RG_RTC_26M_CK_PDN_HWEN_ADDR                 MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_26M_CK_PDN_HWEN_MASK                 0x1
#define PMIC_RG_RTC_26M_CK_PDN_HWEN_SHIFT                6
#define PMIC_RG_REG_CK_PDN_HWEN_ADDR                     MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_REG_CK_PDN_HWEN_MASK                     0x1
#define PMIC_RG_REG_CK_PDN_HWEN_SHIFT                    7
#define PMIC_RG_RTC_MCLK_PDN_HWEN_ADDR                   MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_MCLK_PDN_HWEN_MASK                   0x1
#define PMIC_RG_RTC_MCLK_PDN_HWEN_SHIFT                  8
#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_ADDR             MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_MASK             0x1
#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_SHIFT            9
#define PMIC_RG_EFUSE_CK_PDN_HWEN_ADDR                   MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_EFUSE_CK_PDN_HWEN_MASK                   0x1
#define PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT                  10
#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_ADDR               MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_MASK               0x1
#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_SHIFT              11
#define PMIC_RG_AUXADC_32K_CK_PDN_HWEN_ADDR              MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_AUXADC_32K_CK_PDN_HWEN_MASK              0x1
#define PMIC_RG_AUXADC_32K_CK_PDN_HWEN_SHIFT             12
#define PMIC_RG_EINT_32K_CK_PDN_HWEN_ADDR                MT6355_TOP_CKHWEN_CON0
#define PMIC_RG_EINT_32K_CK_PDN_HWEN_MASK                0x1
#define PMIC_RG_EINT_32K_CK_PDN_HWEN_SHIFT               13
#define PMIC_TOP_CKHWEN_CON0_RSV_ADDR                    MT6355_TOP_CKHWEN_CON0
#define PMIC_TOP_CKHWEN_CON0_RSV_MASK                    0x3
#define PMIC_TOP_CKHWEN_CON0_RSV_SHIFT                   14
#define PMIC_TOP_CKHWEN_CON0_SET_ADDR                    MT6355_TOP_CKHWEN_CON0_SET
#define PMIC_TOP_CKHWEN_CON0_SET_MASK                    0xFFFF
#define PMIC_TOP_CKHWEN_CON0_SET_SHIFT                   0
#define PMIC_TOP_CKHWEN_CON0_CLR_ADDR                    MT6355_TOP_CKHWEN_CON0_CLR
#define PMIC_TOP_CKHWEN_CON0_CLR_MASK                    0xFFFF
#define PMIC_TOP_CKHWEN_CON0_CLR_SHIFT                   0
#define PMIC_RG_BUCK_9M_CK_PDN_HWEN_ADDR                 MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_BUCK_9M_CK_PDN_HWEN_MASK                 0x1
#define PMIC_RG_BUCK_9M_CK_PDN_HWEN_SHIFT                0
#define PMIC_RG_BUCK_1M_CK_PDN_HWEN_ADDR                 MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_BUCK_1M_CK_PDN_HWEN_MASK                 0x1
#define PMIC_RG_BUCK_1M_CK_PDN_HWEN_SHIFT                1
#define PMIC_RG_BUCK_18M_CK_PDN_HWEN_ADDR                MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_BUCK_18M_CK_PDN_HWEN_MASK                0x1
#define PMIC_RG_BUCK_18M_CK_PDN_HWEN_SHIFT               2
#define PMIC_RG_LDO_1M_CK_PDN_HWEN_ADDR                  MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_LDO_1M_CK_PDN_HWEN_MASK                  0x1
#define PMIC_RG_LDO_1M_CK_PDN_HWEN_SHIFT                 4
#define PMIC_RG_LDO_9M_CK_PDN_HWEN_ADDR                  MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_LDO_9M_CK_PDN_HWEN_MASK                  0x1
#define PMIC_RG_LDO_9M_CK_PDN_HWEN_SHIFT                 5
#define PMIC_RG_BUCK_VMODEM_1M_CK_PDN_HWEN_ADDR          MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_BUCK_VMODEM_1M_CK_PDN_HWEN_MASK          0x1
#define PMIC_RG_BUCK_VMODEM_1M_CK_PDN_HWEN_SHIFT         6
#define PMIC_RG_AUXADC_1M_CK_PDN_HWEN_ADDR               MT6355_TOP_CKHWEN_CON1
#define PMIC_RG_AUXADC_1M_CK_PDN_HWEN_MASK               0x1
#define PMIC_RG_AUXADC_1M_CK_PDN_HWEN_SHIFT              7
#define PMIC_TOP_CKHWEN_RSV_ADDR                         MT6355_TOP_CKHWEN_CON1
#define PMIC_TOP_CKHWEN_RSV_MASK                         0xFF
#define PMIC_TOP_CKHWEN_RSV_SHIFT                        8
#define PMIC_TOP_CKHWEN_CON1_SET_ADDR                    MT6355_TOP_CKHWEN_CON1_SET
#define PMIC_TOP_CKHWEN_CON1_SET_MASK                    0xFFFF
#define PMIC_TOP_CKHWEN_CON1_SET_SHIFT                   0
#define PMIC_TOP_CKHWEN_CON1_CLR_ADDR                    MT6355_TOP_CKHWEN_CON1_CLR
#define PMIC_TOP_CKHWEN_CON1_CLR_MASK                    0xFFFF
#define PMIC_TOP_CKHWEN_CON1_CLR_SHIFT                   0
#define PMIC_RG_VPROC11_FREQ_SEL_ADDR                    MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VPROC11_FREQ_SEL_MASK                    0x3
#define PMIC_RG_VPROC11_FREQ_SEL_SHIFT                   0
#define PMIC_RG_VPROC12_FREQ_SEL_ADDR                    MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VPROC12_FREQ_SEL_MASK                    0x3
#define PMIC_RG_VPROC12_FREQ_SEL_SHIFT                   2
#define PMIC_RG_VCORE_FREQ_SEL_ADDR                      MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VCORE_FREQ_SEL_MASK                      0x3
#define PMIC_RG_VCORE_FREQ_SEL_SHIFT                     4
#define PMIC_RG_VGPU_FREQ_SEL_ADDR                       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VGPU_FREQ_SEL_MASK                       0x3
#define PMIC_RG_VGPU_FREQ_SEL_SHIFT                      6
#define PMIC_RG_VDRAM1_FREQ_SEL_ADDR                     MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VDRAM1_FREQ_SEL_MASK                     0x3
#define PMIC_RG_VDRAM1_FREQ_SEL_SHIFT                    8
#define PMIC_RG_VDRAM2_FREQ_SEL_ADDR                     MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VDRAM2_FREQ_SEL_MASK                     0x3
#define PMIC_RG_VDRAM2_FREQ_SEL_SHIFT                    10
#define PMIC_RG_VMODEM_FREQ_SEL_ADDR                     MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_RG_VMODEM_FREQ_SEL_MASK                     0x3
#define PMIC_RG_VMODEM_FREQ_SEL_SHIFT                    12
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_RSV_ADDR       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_RSV_MASK       0x3
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_RSV_SHIFT      14
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_SET_ADDR       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0_SET
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_SET_MASK       0xFFFF
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_SET_SHIFT      0
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_CLR_ADDR       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON0_CLR
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_CLR_MASK       0xFFFF
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_CLR_SHIFT      0
#define PMIC_RG_VS1_FREQ_SEL_ADDR                        MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1
#define PMIC_RG_VS1_FREQ_SEL_MASK                        0x3
#define PMIC_RG_VS1_FREQ_SEL_SHIFT                       0
#define PMIC_RG_VS2_FREQ_SEL_ADDR                        MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1
#define PMIC_RG_VS2_FREQ_SEL_MASK                        0x3
#define PMIC_RG_VS2_FREQ_SEL_SHIFT                       2
#define PMIC_RG_VPA_PHS_SEL_ADDR                         MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1
#define PMIC_RG_VPA_PHS_SEL_MASK                         0x3
#define PMIC_RG_VPA_PHS_SEL_SHIFT                        4
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_RSV_ADDR       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_RSV_MASK       0x3FF
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_RSV_SHIFT      6
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_SET_ADDR       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1_SET
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_SET_MASK       0xFFFF
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_SET_SHIFT      0
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_CLR_ADDR       MT6355_TOP_BUCK_ANACK_FREQ_SEL_CON1_CLR
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_CLR_MASK       0xFFFF
#define PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_CLR_SHIFT      0
#define PMIC_RG_PMU75K_CK_TST_DIS_ADDR                   MT6355_TOP_CKTST_CON0
#define PMIC_RG_PMU75K_CK_TST_DIS_MASK                   0x1
#define PMIC_RG_PMU75K_CK_TST_DIS_SHIFT                  0
#define PMIC_RG_SMPS_CK_TST_DIS_ADDR                     MT6355_TOP_CKTST_CON0
#define PMIC_RG_SMPS_CK_TST_DIS_MASK                     0x1
#define PMIC_RG_SMPS_CK_TST_DIS_SHIFT                    1
#define PMIC_RG_RTC32K_CK_TST_DIS_ADDR                   MT6355_TOP_CKTST_CON0
#define PMIC_RG_RTC32K_CK_TST_DIS_MASK                   0x1
#define PMIC_RG_RTC32K_CK_TST_DIS_SHIFT                  2
#define PMIC_RG_FG_CK_TST_DIS_ADDR                       MT6355_TOP_CKTST_CON0
#define PMIC_RG_FG_CK_TST_DIS_MASK                       0x1
#define PMIC_RG_FG_CK_TST_DIS_SHIFT                      3
#define PMIC_RG_RTC26M_CK_TST_DIS_ADDR                   MT6355_TOP_CKTST_CON0
#define PMIC_RG_RTC26M_CK_TST_DIS_MASK                   0x1
#define PMIC_RG_RTC26M_CK_TST_DIS_SHIFT                  4
#define PMIC_RG_AUD26M_CK_TST_DIS_ADDR                   MT6355_TOP_CKTST_CON0
#define PMIC_RG_AUD26M_CK_TST_DIS_MASK                   0x1
#define PMIC_RG_AUD26M_CK_TST_DIS_SHIFT                  5
#define PMIC_RG_VOW12M_CK_TST_DIS_ADDR                   MT6355_TOP_CKTST_CON0
#define PMIC_RG_VOW12M_CK_TST_DIS_MASK                   0x1
#define PMIC_RG_VOW12M_CK_TST_DIS_SHIFT                  6
#define PMIC_TOP_CKTST_CON0_RSV_ADDR                     MT6355_TOP_CKTST_CON0
#define PMIC_TOP_CKTST_CON0_RSV_MASK                     0xFF
#define PMIC_TOP_CKTST_CON0_RSV_SHIFT                    7
#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_ADDR               MT6355_TOP_CKTST_CON0
#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_MASK               0x1
#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_SHIFT              15
#define PMIC_RG_AUXADC_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_AUXADC_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_AUXADC_CK_TSTSEL_SHIFT                   0
#define PMIC_RG_FQMTR_CK_TSTSEL_ADDR                     MT6355_TOP_CKTST_CON1
#define PMIC_RG_FQMTR_CK_TSTSEL_MASK                     0x1
#define PMIC_RG_FQMTR_CK_TSTSEL_SHIFT                    1
#define PMIC_RG_RTCDET_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_RTCDET_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_RTCDET_CK_TSTSEL_SHIFT                   2
#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_ADDR                MT6355_TOP_CKTST_CON1
#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_MASK                0x1
#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_SHIFT               3
#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_ADDR            MT6355_TOP_CKTST_CON1
#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_MASK            0x1
#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_SHIFT           4
#define PMIC_RG_RTC26M_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_RTC26M_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_RTC26M_CK_TSTSEL_SHIFT                   5
#define PMIC_RG_RTC32K_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_RTC32K_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_RTC32K_CK_TSTSEL_SHIFT                   6
#define PMIC_RG_FG_CK_TSTSEL_ADDR                        MT6355_TOP_CKTST_CON1
#define PMIC_RG_FG_CK_TSTSEL_MASK                        0x1
#define PMIC_RG_FG_CK_TSTSEL_SHIFT                       7
#define PMIC_RG_FGADC_ANA_CK_TSTSEL_ADDR                 MT6355_TOP_CKTST_CON1
#define PMIC_RG_FGADC_ANA_CK_TSTSEL_MASK                 0x1
#define PMIC_RG_FGADC_ANA_CK_TSTSEL_SHIFT                8
#define PMIC_RG_BGR_TEST_CK_TSTSEL_ADDR                  MT6355_TOP_CKTST_CON1
#define PMIC_RG_BGR_TEST_CK_TSTSEL_MASK                  0x1
#define PMIC_RG_BGR_TEST_CK_TSTSEL_SHIFT                 9
#define PMIC_RG_PMU75K_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_PMU75K_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_PMU75K_CK_TSTSEL_SHIFT                   10
#define PMIC_RG_SMPS_CK_TSTSEL_ADDR                      MT6355_TOP_CKTST_CON1
#define PMIC_RG_SMPS_CK_TSTSEL_MASK                      0x1
#define PMIC_RG_SMPS_CK_TSTSEL_SHIFT                     11
#define PMIC_RG_AUD_CK_TSTSEL_ADDR                       MT6355_TOP_CKTST_CON1
#define PMIC_RG_AUD_CK_TSTSEL_MASK                       0x1
#define PMIC_RG_AUD_CK_TSTSEL_SHIFT                      12
#define PMIC_RG_AUDIF_CK_TSTSEL_ADDR                     MT6355_TOP_CKTST_CON1
#define PMIC_RG_AUDIF_CK_TSTSEL_MASK                     0x1
#define PMIC_RG_AUDIF_CK_TSTSEL_SHIFT                    13
#define PMIC_RG_AUD26M_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_AUD26M_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_AUD26M_CK_TSTSEL_SHIFT                   14
#define PMIC_RG_VOW12M_CK_TSTSEL_ADDR                    MT6355_TOP_CKTST_CON1
#define PMIC_RG_VOW12M_CK_TSTSEL_MASK                    0x1
#define PMIC_RG_VOW12M_CK_TSTSEL_SHIFT                   15
#define PMIC_RG_CLKSQ_EN_AUD_ADDR                        MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUD_MASK                        0x1
#define PMIC_RG_CLKSQ_EN_AUD_SHIFT                       0
#define PMIC_RG_CLKSQ_EN_FQR_ADDR                        MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_FQR_MASK                        0x1
#define PMIC_RG_CLKSQ_EN_FQR_SHIFT                       1
#define PMIC_RG_CLKSQ_EN_AUX_AP_ADDR                     MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUX_AP_MASK                     0x1
#define PMIC_RG_CLKSQ_EN_AUX_AP_SHIFT                    2
#define PMIC_RG_CLKSQ_EN_AUX_MD_ADDR                     MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUX_MD_MASK                     0x1
#define PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT                    3
#define PMIC_RG_CLKSQ_EN_AUX_GPS_ADDR                    MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUX_GPS_MASK                    0x1
#define PMIC_RG_CLKSQ_EN_AUX_GPS_SHIFT                   4
#define PMIC_RG_CLKSQ_EN_AUX_RSV_ADDR                    MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUX_RSV_MASK                    0x1
#define PMIC_RG_CLKSQ_EN_AUX_RSV_SHIFT                   5
#define PMIC_RG_CLKSQ_EN_AUX_AP_MODE_ADDR                MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUX_AP_MODE_MASK                0x1
#define PMIC_RG_CLKSQ_EN_AUX_AP_MODE_SHIFT               8
#define PMIC_RG_CLKSQ_EN_AUX_MD_MODE_ADDR                MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_EN_AUX_MD_MODE_MASK                0x1
#define PMIC_RG_CLKSQ_EN_AUX_MD_MODE_SHIFT               9
#define PMIC_RG_CLKSQ_IN_SEL_VA18_ADDR                   MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_IN_SEL_VA18_MASK                   0x1
#define PMIC_RG_CLKSQ_IN_SEL_VA18_SHIFT                  10
#define PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL_ADDR            MT6355_TOP_CLKSQ
#define PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL_MASK            0x1
#define PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL_SHIFT           11
#define PMIC_TOP_CLKSQ_RSV_ADDR                          MT6355_TOP_CLKSQ
#define PMIC_TOP_CLKSQ_RSV_MASK                          0x7
#define PMIC_TOP_CLKSQ_RSV_SHIFT                         12
#define PMIC_DA_CLKSQ_EN_VA18_ADDR                       MT6355_TOP_CLKSQ
#define PMIC_DA_CLKSQ_EN_VA18_MASK                       0x1
#define PMIC_DA_CLKSQ_EN_VA18_SHIFT                      15
#define PMIC_TOP_CLKSQ_SET_ADDR                          MT6355_TOP_CLKSQ_SET
#define PMIC_TOP_CLKSQ_SET_MASK                          0xFFFF
#define PMIC_TOP_CLKSQ_SET_SHIFT                         0
#define PMIC_TOP_CLKSQ_CLR_ADDR                          MT6355_TOP_CLKSQ_CLR
#define PMIC_TOP_CLKSQ_CLR_MASK                          0xFFFF
#define PMIC_TOP_CLKSQ_CLR_SHIFT                         0
#define PMIC_RG_CLKSQ_RTC_EN_ADDR                        MT6355_TOP_CLKSQ_RTC
#define PMIC_RG_CLKSQ_RTC_EN_MASK                        0x1
#define PMIC_RG_CLKSQ_RTC_EN_SHIFT                       0
#define PMIC_RG_CLKSQ_RTC_EN_HW_MODE_ADDR                MT6355_TOP_CLKSQ_RTC
#define PMIC_RG_CLKSQ_RTC_EN_HW_MODE_MASK                0x1
#define PMIC_RG_CLKSQ_RTC_EN_HW_MODE_SHIFT               1
#define PMIC_TOP_CLKSQ_RTC_RSV0_ADDR                     MT6355_TOP_CLKSQ_RTC
#define PMIC_TOP_CLKSQ_RTC_RSV0_MASK                     0xF
#define PMIC_TOP_CLKSQ_RTC_RSV0_SHIFT                    2
#define PMIC_RG_ENBB_SEL_ADDR                            MT6355_TOP_CLKSQ_RTC
#define PMIC_RG_ENBB_SEL_MASK                            0x1
#define PMIC_RG_ENBB_SEL_SHIFT                           8
#define PMIC_RG_XOSC_EN_SEL_ADDR                         MT6355_TOP_CLKSQ_RTC
#define PMIC_RG_XOSC_EN_SEL_MASK                         0x1
#define PMIC_RG_XOSC_EN_SEL_SHIFT                        9
#define PMIC_TOP_CLKSQ_RTC_RSV1_ADDR                     MT6355_TOP_CLKSQ_RTC
#define PMIC_TOP_CLKSQ_RTC_RSV1_MASK                     0x3
#define PMIC_TOP_CLKSQ_RTC_RSV1_SHIFT                    10
#define PMIC_DA_CLKSQ_EN_VDIG18_ADDR                     MT6355_TOP_CLKSQ_RTC
#define PMIC_DA_CLKSQ_EN_VDIG18_MASK                     0x1
#define PMIC_DA_CLKSQ_EN_VDIG18_SHIFT                    15
#define PMIC_TOP_CLKSQ_RTC_SET_ADDR                      MT6355_TOP_CLKSQ_RTC_SET
#define PMIC_TOP_CLKSQ_RTC_SET_MASK                      0xFFFF
#define PMIC_TOP_CLKSQ_RTC_SET_SHIFT                     0
#define PMIC_TOP_CLKSQ_RTC_CLR_ADDR                      MT6355_TOP_CLKSQ_RTC_CLR
#define PMIC_TOP_CLKSQ_RTC_CLR_MASK                      0xFFFF
#define PMIC_TOP_CLKSQ_RTC_CLR_SHIFT                     0
#define PMIC_RG_OSC_75K_TRIM_ADDR                        MT6355_TOP_CLK_TRIM
#define PMIC_RG_OSC_75K_TRIM_MASK                        0x3F
#define PMIC_RG_OSC_75K_TRIM_SHIFT                       0
#define PMIC_RG_OSC_75K_TRIM_EN_ADDR                     MT6355_TOP_CLK_TRIM
#define PMIC_RG_OSC_75K_TRIM_EN_MASK                     0x1
#define PMIC_RG_OSC_75K_TRIM_EN_SHIFT                    6
#define PMIC_RG_OSC_75K_TRIM_RATE_ADDR                   MT6355_TOP_CLK_TRIM
#define PMIC_RG_OSC_75K_TRIM_RATE_MASK                   0x3
#define PMIC_RG_OSC_75K_TRIM_RATE_SHIFT                  7
#define PMIC_DA_OSC_75K_TRIM_ADDR                        MT6355_TOP_CLK_TRIM
#define PMIC_DA_OSC_75K_TRIM_MASK                        0x3F
#define PMIC_DA_OSC_75K_TRIM_SHIFT                       9
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN0_EN_ADDR           MT6355_TOP_CLK_CON0
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN0_EN_MASK           0x1
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN0_EN_SHIFT          0
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN1_EN_ADDR           MT6355_TOP_CLK_CON0
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN1_EN_MASK           0x1
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN1_EN_SHIFT          1
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN2_EN_ADDR           MT6355_TOP_CLK_CON0
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN2_EN_MASK           0x1
#define PMIC_RG_G_SMPS_CK_PDN_SRCLKEN2_EN_SHIFT          2
#define PMIC_RG_G_SMPS_CK_PDN_BUCK_OSC_SEL_EN_ADDR       MT6355_TOP_CLK_CON0
#define PMIC_RG_G_SMPS_CK_PDN_BUCK_OSC_SEL_EN_MASK       0x1
#define PMIC_RG_G_SMPS_CK_PDN_BUCK_OSC_SEL_EN_SHIFT      3
#define PMIC_RG_G_SMPS_CK_PDN_VOWEN_EN_ADDR              MT6355_TOP_CLK_CON0
#define PMIC_RG_G_SMPS_CK_PDN_VOWEN_EN_MASK              0x1
#define PMIC_RG_G_SMPS_CK_PDN_VOWEN_EN_SHIFT             4
#define PMIC_RG_OSC_SEL_SRCLKEN0_EN_ADDR                 MT6355_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_SRCLKEN0_EN_MASK                 0x1
#define PMIC_RG_OSC_SEL_SRCLKEN0_EN_SHIFT                5
#define PMIC_RG_OSC_SEL_SRCLKEN1_EN_ADDR                 MT6355_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_SRCLKEN1_EN_MASK                 0x1
#define PMIC_RG_OSC_SEL_SRCLKEN1_EN_SHIFT                6
#define PMIC_RG_OSC_SEL_SRCLKEN2_EN_ADDR                 MT6355_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_SRCLKEN2_EN_MASK                 0x1
#define PMIC_RG_OSC_SEL_SRCLKEN2_EN_SHIFT                7
#define PMIC_RG_OSC_SEL_BUCK_LDO_EN_ADDR                 MT6355_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_BUCK_LDO_EN_MASK                 0x1
#define PMIC_RG_OSC_SEL_BUCK_LDO_EN_SHIFT                8
#define PMIC_RG_OSC_SEL_VOWEN_EN_ADDR                    MT6355_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_VOWEN_EN_MASK                    0x1
#define PMIC_RG_OSC_SEL_VOWEN_EN_SHIFT                   9
#define PMIC_RG_CLK_RSV_ADDR                             MT6355_TOP_CLK_CON0
#define PMIC_RG_CLK_RSV_MASK                             0x3F
#define PMIC_RG_CLK_RSV_SHIFT                            10
#define PMIC_TOP_CLK_CON0_SET_ADDR                       MT6355_TOP_CLK_CON0_SET
#define PMIC_TOP_CLK_CON0_SET_MASK                       0xFFFF
#define PMIC_TOP_CLK_CON0_SET_SHIFT                      0
#define PMIC_TOP_CLK_CON0_CLR_ADDR                       MT6355_TOP_CLK_CON0_CLR
#define PMIC_TOP_CLK_CON0_CLR_MASK                       0xFFFF
#define PMIC_TOP_CLK_CON0_CLR_SHIFT                      0
#define PMIC_RG_VPROC2_CKMUX_EN_ADDR                     MT6355_TOP_CLK_CON1
#define PMIC_RG_VPROC2_CKMUX_EN_MASK                     0x1
#define PMIC_RG_VPROC2_CKMUX_EN_SHIFT                    0
#define PMIC_RG_VPA_SW_PDN_EN_ADDR                       MT6355_TOP_CLK_CON1
#define PMIC_RG_VPA_SW_PDN_EN_MASK                       0x1
#define PMIC_RG_VPA_SW_PDN_EN_SHIFT                      1
#define PMIC_RG_LDO_1M_PDN_W_OSC_SEL_ADDR                MT6355_TOP_CLK_CON1
#define PMIC_RG_LDO_1M_PDN_W_OSC_SEL_MASK                0x1
#define PMIC_RG_LDO_1M_PDN_W_OSC_SEL_SHIFT               2
#define PMIC_RG_BUCK_1M_PDN_W_OSC_SEL_ADDR               MT6355_TOP_CLK_CON1
#define PMIC_RG_BUCK_1M_PDN_W_OSC_SEL_MASK               0x1
#define PMIC_RG_BUCK_1M_PDN_W_OSC_SEL_SHIFT              3
#define PMIC_RG_CLKCTL_RSV0_ADDR                         MT6355_TOP_CLK_CON1
#define PMIC_RG_CLKCTL_RSV0_MASK                         0xFFF
#define PMIC_RG_CLKCTL_RSV0_SHIFT                        4
#define PMIC_TOP_CLK_CON1_SET_ADDR                       MT6355_TOP_CLK_CON1_SET
#define PMIC_TOP_CLK_CON1_SET_MASK                       0xFFFF
#define PMIC_TOP_CLK_CON1_SET_SHIFT                      0
#define PMIC_TOP_CLK_CON1_CLR_ADDR                       MT6355_TOP_CLK_CON1_CLR
#define PMIC_TOP_CLK_CON1_CLR_MASK                       0xFFFF
#define PMIC_TOP_CLK_CON1_CLR_SHIFT                      0
#define PMIC_RG_DCXO_PWRKEY_RSTB_SEL_ADDR                MT6355_TOP_CLK_CON2
#define PMIC_RG_DCXO_PWRKEY_RSTB_SEL_MASK                0x1
#define PMIC_RG_DCXO_PWRKEY_RSTB_SEL_SHIFT               0
#define PMIC_RG_EFUSE_MAN_RST_ADDR                       MT6355_TOP_RST_CON0
#define PMIC_RG_EFUSE_MAN_RST_MASK                       0x1
#define PMIC_RG_EFUSE_MAN_RST_SHIFT                      0
#define PMIC_RG_AUXADC_RST_ADDR                          MT6355_TOP_RST_CON0
#define PMIC_RG_AUXADC_RST_MASK                          0x1
#define PMIC_RG_AUXADC_RST_SHIFT                         1
#define PMIC_RG_AUXADC_REG_RST_ADDR                      MT6355_TOP_RST_CON0
#define PMIC_RG_AUXADC_REG_RST_MASK                      0x1
#define PMIC_RG_AUXADC_REG_RST_SHIFT                     2
#define PMIC_RG_AUDIO_RST_ADDR                           MT6355_TOP_RST_CON0
#define PMIC_RG_AUDIO_RST_MASK                           0x1
#define PMIC_RG_AUDIO_RST_SHIFT                          3
#define PMIC_RG_ACCDET_RST_ADDR                          MT6355_TOP_RST_CON0
#define PMIC_RG_ACCDET_RST_MASK                          0x1
#define PMIC_RG_ACCDET_RST_SHIFT                         4
#define PMIC_RG_BIF_RST_ADDR                             MT6355_TOP_RST_CON0
#define PMIC_RG_BIF_RST_MASK                             0x1
#define PMIC_RG_BIF_RST_SHIFT                            5
#define PMIC_RG_DRIVER_RST_ADDR                          MT6355_TOP_RST_CON0
#define PMIC_RG_DRIVER_RST_MASK                          0x1
#define PMIC_RG_DRIVER_RST_SHIFT                         6
#define PMIC_RG_FGADC_RST_ADDR                           MT6355_TOP_RST_CON0
#define PMIC_RG_FGADC_RST_MASK                           0x1
#define PMIC_RG_FGADC_RST_SHIFT                          7
#define PMIC_RG_FQMTR_RST_ADDR                           MT6355_TOP_RST_CON0
#define PMIC_RG_FQMTR_RST_MASK                           0x1
#define PMIC_RG_FQMTR_RST_SHIFT                          8
#define PMIC_RG_RTC_RST_ADDR                             MT6355_TOP_RST_CON0
#define PMIC_RG_RTC_RST_MASK                             0x1
#define PMIC_RG_RTC_RST_SHIFT                            9
#define PMIC_RG_TYPE_C_CC_RST_ADDR                       MT6355_TOP_RST_CON0
#define PMIC_RG_TYPE_C_CC_RST_MASK                       0x1
#define PMIC_RG_TYPE_C_CC_RST_SHIFT                      10
#define PMIC_RG_CHRWDT_RST_ADDR                          MT6355_TOP_RST_CON0
#define PMIC_RG_CHRWDT_RST_MASK                          0x1
#define PMIC_RG_CHRWDT_RST_SHIFT                         11
#define PMIC_RG_ZCD_RST_ADDR                             MT6355_TOP_RST_CON0
#define PMIC_RG_ZCD_RST_MASK                             0x1
#define PMIC_RG_ZCD_RST_SHIFT                            12
#define PMIC_RG_AUDNCP_RST_ADDR                          MT6355_TOP_RST_CON0
#define PMIC_RG_AUDNCP_RST_MASK                          0x1
#define PMIC_RG_AUDNCP_RST_SHIFT                         13
#define PMIC_RG_CLK_TRIM_RST_ADDR                        MT6355_TOP_RST_CON0
#define PMIC_RG_CLK_TRIM_RST_MASK                        0x1
#define PMIC_RG_CLK_TRIM_RST_SHIFT                       14
#define PMIC_RG_BUCK_SRCLKEN_RST_ADDR                    MT6355_TOP_RST_CON0
#define PMIC_RG_BUCK_SRCLKEN_RST_MASK                    0x1
#define PMIC_RG_BUCK_SRCLKEN_RST_SHIFT                   15
#define PMIC_TOP_RST_CON0_SET_ADDR                       MT6355_TOP_RST_CON0_SET
#define PMIC_TOP_RST_CON0_SET_MASK                       0xFFFF
#define PMIC_TOP_RST_CON0_SET_SHIFT                      0
#define PMIC_TOP_RST_CON0_CLR_ADDR                       MT6355_TOP_RST_CON0_CLR
#define PMIC_TOP_RST_CON0_CLR_MASK                       0xFFFF
#define PMIC_TOP_RST_CON0_CLR_SHIFT                      0
#define PMIC_RG_STRUP_LONG_PRESS_RST_ADDR                MT6355_TOP_RST_CON1
#define PMIC_RG_STRUP_LONG_PRESS_RST_MASK                0x1
#define PMIC_RG_STRUP_LONG_PRESS_RST_SHIFT               0
#define PMIC_RG_BUCK_PROT_PMPP_RST_ADDR                  MT6355_TOP_RST_CON1
#define PMIC_RG_BUCK_PROT_PMPP_RST_MASK                  0x1
#define PMIC_RG_BUCK_PROT_PMPP_RST_SHIFT                 1
#define PMIC_RG_SPK_RST_ADDR                             MT6355_TOP_RST_CON1
#define PMIC_RG_SPK_RST_MASK                             0x1
#define PMIC_RG_SPK_RST_SHIFT                            2
#define PMIC_RG_CHRDET_RST_ADDR                          MT6355_TOP_RST_CON1
#define PMIC_RG_CHRDET_RST_MASK                          0x1
#define PMIC_RG_CHRDET_RST_SHIFT                         3
#define PMIC_RG_BUCK_LDO_FT_TESTMODE_RST_ADDR            MT6355_TOP_RST_CON1
#define PMIC_RG_BUCK_LDO_FT_TESTMODE_RST_MASK            0x1
#define PMIC_RG_BUCK_LDO_FT_TESTMODE_RST_SHIFT           4
#define PMIC_RG_BATON_RST_ADDR                           MT6355_TOP_RST_CON1
#define PMIC_RG_BATON_RST_MASK                           0x1
#define PMIC_RG_BATON_RST_SHIFT                          5
#define PMIC_RG_FGADC_RST_SRC_SEL_ADDR                   MT6355_TOP_RST_CON1
#define PMIC_RG_FGADC_RST_SRC_SEL_MASK                   0x1
#define PMIC_RG_FGADC_RST_SRC_SEL_SHIFT                  6
#define PMIC_RG_LDO_CALI_RST_ADDR                        MT6355_TOP_RST_CON1
#define PMIC_RG_LDO_CALI_RST_MASK                        0x1
#define PMIC_RG_LDO_CALI_RST_SHIFT                       7
#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_ADDR                 MT6355_TOP_RST_CON1
#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_MASK                 0x1
#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_SHIFT                8
#define PMIC_TOP_RST_CON1_RSV_ADDR                       MT6355_TOP_RST_CON1
#define PMIC_TOP_RST_CON1_RSV_MASK                       0x1
#define PMIC_TOP_RST_CON1_RSV_SHIFT                      9
#define PMIC_TOP_RST_CON1_SET_ADDR                       MT6355_TOP_RST_CON1_SET
#define PMIC_TOP_RST_CON1_SET_MASK                       0xFFFF
#define PMIC_TOP_RST_CON1_SET_SHIFT                      0
#define PMIC_TOP_RST_CON1_CLR_ADDR                       MT6355_TOP_RST_CON1_CLR
#define PMIC_TOP_RST_CON1_CLR_MASK                       0xFFFF
#define PMIC_TOP_RST_CON1_CLR_SHIFT                      0
#define PMIC_RG_CHR_LDO_DET_MODE_ADDR                    MT6355_TOP_RST_CON2
#define PMIC_RG_CHR_LDO_DET_MODE_MASK                    0x1
#define PMIC_RG_CHR_LDO_DET_MODE_SHIFT                   0
#define PMIC_RG_CHR_LDO_DET_SW_ADDR                      MT6355_TOP_RST_CON2
#define PMIC_RG_CHR_LDO_DET_SW_MASK                      0x1
#define PMIC_RG_CHR_LDO_DET_SW_SHIFT                     1
#define PMIC_RG_CHRWDT_FLAG_MODE_ADDR                    MT6355_TOP_RST_CON2
#define PMIC_RG_CHRWDT_FLAG_MODE_MASK                    0x1
#define PMIC_RG_CHRWDT_FLAG_MODE_SHIFT                   2
#define PMIC_RG_CHRWDT_FLAG_SW_ADDR                      MT6355_TOP_RST_CON2
#define PMIC_RG_CHRWDT_FLAG_SW_MASK                      0x1
#define PMIC_RG_CHRWDT_FLAG_SW_SHIFT                     3
#define PMIC_TOP_RST_CON2_RSV_ADDR                       MT6355_TOP_RST_CON2
#define PMIC_TOP_RST_CON2_RSV_MASK                       0xF
#define PMIC_TOP_RST_CON2_RSV_SHIFT                      4
#define PMIC_RG_WDTRSTB_EN_ADDR                          MT6355_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_EN_MASK                          0x1
#define PMIC_RG_WDTRSTB_EN_SHIFT                         0
#define PMIC_RG_WDTRSTB_MODE_ADDR                        MT6355_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_MODE_MASK                        0x1
#define PMIC_RG_WDTRSTB_MODE_SHIFT                       1
#define PMIC_WDTRSTB_STATUS_ADDR                         MT6355_TOP_RST_MISC
#define PMIC_WDTRSTB_STATUS_MASK                         0x1
#define PMIC_WDTRSTB_STATUS_SHIFT                        2
#define PMIC_WDTRSTB_STATUS_CLR_ADDR                     MT6355_TOP_RST_MISC
#define PMIC_WDTRSTB_STATUS_CLR_MASK                     0x1
#define PMIC_WDTRSTB_STATUS_CLR_SHIFT                    3
#define PMIC_RG_WDTRSTB_FB_EN_ADDR                       MT6355_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_FB_EN_MASK                       0x1
#define PMIC_RG_WDTRSTB_FB_EN_SHIFT                      4
#define PMIC_RG_WDTRSTB_DEB_ADDR                         MT6355_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_DEB_MASK                         0x1
#define PMIC_RG_WDTRSTB_DEB_SHIFT                        5
#define PMIC_RG_HOMEKEY_RST_EN_ADDR                      MT6355_TOP_RST_MISC
#define PMIC_RG_HOMEKEY_RST_EN_MASK                      0x1
#define PMIC_RG_HOMEKEY_RST_EN_SHIFT                     8
#define PMIC_RG_PWRKEY_RST_EN_ADDR                       MT6355_TOP_RST_MISC
#define PMIC_RG_PWRKEY_RST_EN_MASK                       0x1
#define PMIC_RG_PWRKEY_RST_EN_SHIFT                      9
#define PMIC_RG_PWRRST_TMR_DIS_ADDR                      MT6355_TOP_RST_MISC
#define PMIC_RG_PWRRST_TMR_DIS_MASK                      0x1
#define PMIC_RG_PWRRST_TMR_DIS_SHIFT                     10
#define PMIC_RG_PWRKEY_RST_TD_ADDR                       MT6355_TOP_RST_MISC
#define PMIC_RG_PWRKEY_RST_TD_MASK                       0x3
#define PMIC_RG_PWRKEY_RST_TD_SHIFT                      12
#define PMIC_TOP_RST_MISC_RSV_ADDR                       MT6355_TOP_RST_MISC
#define PMIC_TOP_RST_MISC_RSV_MASK                       0x3
#define PMIC_TOP_RST_MISC_RSV_SHIFT                      14
#define PMIC_TOP_RST_MISC_SET_ADDR                       MT6355_TOP_RST_MISC_SET
#define PMIC_TOP_RST_MISC_SET_MASK                       0xFFFF
#define PMIC_TOP_RST_MISC_SET_SHIFT                      0
#define PMIC_TOP_RST_MISC_CLR_ADDR                       MT6355_TOP_RST_MISC_CLR
#define PMIC_TOP_RST_MISC_CLR_MASK                       0xFFFF
#define PMIC_TOP_RST_MISC_CLR_SHIFT                      0
#define PMIC_VPWRIN_RSTB_STATUS_ADDR                     MT6355_TOP_RST_STATUS
#define PMIC_VPWRIN_RSTB_STATUS_MASK                     0x1
#define PMIC_VPWRIN_RSTB_STATUS_SHIFT                    0
#define PMIC_DDLO_RSTB_STATUS_ADDR                       MT6355_TOP_RST_STATUS
#define PMIC_DDLO_RSTB_STATUS_MASK                       0x1
#define PMIC_DDLO_RSTB_STATUS_SHIFT                      1
#define PMIC_UVLO_RSTB_STATUS_ADDR                       MT6355_TOP_RST_STATUS
#define PMIC_UVLO_RSTB_STATUS_MASK                       0x1
#define PMIC_UVLO_RSTB_STATUS_SHIFT                      2
#define PMIC_RTC_DDLO_RSTB_STATUS_ADDR                   MT6355_TOP_RST_STATUS
#define PMIC_RTC_DDLO_RSTB_STATUS_MASK                   0x1
#define PMIC_RTC_DDLO_RSTB_STATUS_SHIFT                  3
#define PMIC_CHRWDT_REG_RSTB_STATUS_ADDR                 MT6355_TOP_RST_STATUS
#define PMIC_CHRWDT_REG_RSTB_STATUS_MASK                 0x1
#define PMIC_CHRWDT_REG_RSTB_STATUS_SHIFT                4
#define PMIC_CHRDET_REG_RSTB_STATUS_ADDR                 MT6355_TOP_RST_STATUS
#define PMIC_CHRDET_REG_RSTB_STATUS_MASK                 0x1
#define PMIC_CHRDET_REG_RSTB_STATUS_SHIFT                5
#define PMIC_BWDT_DDLO_RSTB_STATUS_ADDR                  MT6355_TOP_RST_STATUS
#define PMIC_BWDT_DDLO_RSTB_STATUS_MASK                  0x1
#define PMIC_BWDT_DDLO_RSTB_STATUS_SHIFT                 6
#define PMIC_TOP_RST_STATUS_RSV_ADDR                     MT6355_TOP_RST_STATUS
#define PMIC_TOP_RST_STATUS_RSV_MASK                     0x1
#define PMIC_TOP_RST_STATUS_RSV_SHIFT                    7
#define PMIC_TOP_RST_STATUS_SET_ADDR                     MT6355_TOP_RST_STATUS_SET
#define PMIC_TOP_RST_STATUS_SET_MASK                     0xFFFF
#define PMIC_TOP_RST_STATUS_SET_SHIFT                    0
#define PMIC_TOP_RST_STATUS_CLR_ADDR                     MT6355_TOP_RST_STATUS_CLR
#define PMIC_TOP_RST_STATUS_CLR_MASK                     0xFFFF
#define PMIC_TOP_RST_STATUS_CLR_SHIFT                    0
#define PMIC_TOP_RST_RSV_CON0_ADDR                       MT6355_TOP_RST_RSV_CON0
#define PMIC_TOP_RST_RSV_CON0_MASK                       0xFFFF
#define PMIC_TOP_RST_RSV_CON0_SHIFT                      0
#define PMIC_TOP_RST_RSV_CON1_ADDR                       MT6355_TOP_RST_RSV_CON1
#define PMIC_TOP_RST_RSV_CON1_MASK                       0xFFFF
#define PMIC_TOP_RST_RSV_CON1_SHIFT                      0
#define PMIC_BANK_FQMTR_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_FQMTR_SWRST_MASK                       0x1
#define PMIC_BANK_FQMTR_SWRST_SHIFT                      0
#define PMIC_BANK_SPI_SWRST_ADDR                         MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_SPI_SWRST_MASK                         0x1
#define PMIC_BANK_SPI_SWRST_SHIFT                        1
#define PMIC_BANK_STRUP_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_STRUP_SWRST_MASK                       0x1
#define PMIC_BANK_STRUP_SWRST_SHIFT                      2
#define PMIC_BANK_BUCK_SWRST_ADDR                        MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_BUCK_SWRST_MASK                        0x1
#define PMIC_BANK_BUCK_SWRST_SHIFT                       3
#define PMIC_BANK_BUCK_ANA_SWRST_ADDR                    MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_BUCK_ANA_SWRST_MASK                    0x1
#define PMIC_BANK_BUCK_ANA_SWRST_SHIFT                   4
#define PMIC_BANK_WDTDBG_SWRST_ADDR                      MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_WDTDBG_SWRST_MASK                      0x1
#define PMIC_BANK_WDTDBG_SWRST_SHIFT                     5
#define PMIC_BANK_LDO_0_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_LDO_0_SWRST_MASK                       0x1
#define PMIC_BANK_LDO_0_SWRST_SHIFT                      6
#define PMIC_BANK_LDO_1_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_LDO_1_SWRST_MASK                       0x1
#define PMIC_BANK_LDO_1_SWRST_SHIFT                      7
#define PMIC_BANK_LDO_ANA_SWRST_ADDR                     MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_LDO_ANA_SWRST_MASK                     0x1
#define PMIC_BANK_LDO_ANA_SWRST_SHIFT                    8
#define PMIC_BANK_ACCDET_SWRST_ADDR                      MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_ACCDET_SWRST_MASK                      0x1
#define PMIC_BANK_ACCDET_SWRST_SHIFT                     9
#define PMIC_BANK_EFUSE_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_EFUSE_SWRST_MASK                       0x1
#define PMIC_BANK_EFUSE_SWRST_SHIFT                      10
#define PMIC_BANK_DCXO_SWRST_ADDR                        MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_DCXO_SWRST_MASK                        0x1
#define PMIC_BANK_DCXO_SWRST_SHIFT                       11
#define PMIC_BANK_PCHR_SWRST_ADDR                        MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_PCHR_SWRST_MASK                        0x1
#define PMIC_BANK_PCHR_SWRST_SHIFT                       12
#define PMIC_BANK_GPIO_SWRST_ADDR                        MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_GPIO_SWRST_MASK                        0x1
#define PMIC_BANK_GPIO_SWRST_SHIFT                       13
#define PMIC_BANK_EOSC_CALI_SWRST_ADDR                   MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_EOSC_CALI_SWRST_MASK                   0x1
#define PMIC_BANK_EOSC_CALI_SWRST_SHIFT                  14
#define PMIC_BANK_VRTC_PWM_SWRST_ADDR                    MT6355_TOP_RST_BANK_CON0
#define PMIC_BANK_VRTC_PWM_SWRST_MASK                    0x1
#define PMIC_BANK_VRTC_PWM_SWRST_SHIFT                   15
#define PMIC_TOP_RST_BANK_CON0_SET_ADDR                  MT6355_TOP_RST_BANK_CON0_SET
#define PMIC_TOP_RST_BANK_CON0_SET_MASK                  0xFFFF
#define PMIC_TOP_RST_BANK_CON0_SET_SHIFT                 0
#define PMIC_TOP_RST_BANK_CON0_CLR_ADDR                  MT6355_TOP_RST_BANK_CON0_CLR
#define PMIC_TOP_RST_BANK_CON0_CLR_MASK                  0xFFFF
#define PMIC_TOP_RST_BANK_CON0_CLR_SHIFT                 0
#define PMIC_BANK_RTC_SWRST_ADDR                         MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_RTC_SWRST_MASK                         0x1
#define PMIC_BANK_RTC_SWRST_SHIFT                        0
#define PMIC_BANK_RTC_SEC_SWRST_ADDR                     MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_RTC_SEC_SWRST_MASK                     0x1
#define PMIC_BANK_RTC_SEC_SWRST_SHIFT                    1
#define PMIC_BANK_BIF_SWRST_ADDR                         MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_BIF_SWRST_MASK                         0x1
#define PMIC_BANK_BIF_SWRST_SHIFT                        2
#define PMIC_BANK_FGADC_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_FGADC_SWRST_MASK                       0x1
#define PMIC_BANK_FGADC_SWRST_SHIFT                      3
#define PMIC_BANK_AUXADC_SWRST_ADDR                      MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_AUXADC_SWRST_MASK                      0x1
#define PMIC_BANK_AUXADC_SWRST_SHIFT                     4
#define PMIC_BANK_DRIVER_SWRST_ADDR                      MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_DRIVER_SWRST_MASK                      0x1
#define PMIC_BANK_DRIVER_SWRST_SHIFT                     5
#define PMIC_BANK_AUDIO_SWRST_ADDR                       MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_AUDIO_SWRST_MASK                       0x1
#define PMIC_BANK_AUDIO_SWRST_SHIFT                      6
#define PMIC_BANK_AUDZCD_SWRST_ADDR                      MT6355_TOP_RST_BANK_CON1
#define PMIC_BANK_AUDZCD_SWRST_MASK                      0x1
#define PMIC_BANK_AUDZCD_SWRST_SHIFT                     7
#define PMIC_TOP_RST_BANK_CON1_RSV_ADDR                  MT6355_TOP_RST_BANK_CON1
#define PMIC_TOP_RST_BANK_CON1_RSV_MASK                  0xFF
#define PMIC_TOP_RST_BANK_CON1_RSV_SHIFT                 8
#define PMIC_TOP_RST_BANK_CON1_SET_ADDR                  MT6355_TOP_RST_BANK_CON1_SET
#define PMIC_TOP_RST_BANK_CON1_SET_MASK                  0xFFFF
#define PMIC_TOP_RST_BANK_CON1_SET_SHIFT                 0
#define PMIC_TOP_RST_BANK_CON1_CLR_ADDR                  MT6355_TOP_RST_BANK_CON1_CLR
#define PMIC_TOP_RST_BANK_CON1_CLR_MASK                  0xFFFF
#define PMIC_TOP_RST_BANK_CON1_CLR_SHIFT                 0
#define PMIC_RG_INT_EN_PWRKEY_ADDR                       MT6355_INT_CON0
#define PMIC_RG_INT_EN_PWRKEY_MASK                       0x1
#define PMIC_RG_INT_EN_PWRKEY_SHIFT                      0
#define PMIC_RG_INT_EN_HOMEKEY_ADDR                      MT6355_INT_CON0
#define PMIC_RG_INT_EN_HOMEKEY_MASK                      0x1
#define PMIC_RG_INT_EN_HOMEKEY_SHIFT                     1
#define PMIC_RG_INT_EN_PWRKEY_R_ADDR                     MT6355_INT_CON0
#define PMIC_RG_INT_EN_PWRKEY_R_MASK                     0x1
#define PMIC_RG_INT_EN_PWRKEY_R_SHIFT                    2
#define PMIC_RG_INT_EN_HOMEKEY_R_ADDR                    MT6355_INT_CON0
#define PMIC_RG_INT_EN_HOMEKEY_R_MASK                    0x1
#define PMIC_RG_INT_EN_HOMEKEY_R_SHIFT                   3
#define PMIC_RG_INT_EN_NI_LBAT_INT_ADDR                  MT6355_INT_CON0
#define PMIC_RG_INT_EN_NI_LBAT_INT_MASK                  0x1
#define PMIC_RG_INT_EN_NI_LBAT_INT_SHIFT                 4
#define PMIC_RG_INT_EN_CHRDET_ADDR                       MT6355_INT_CON0
#define PMIC_RG_INT_EN_CHRDET_MASK                       0x1
#define PMIC_RG_INT_EN_CHRDET_SHIFT                      5
#define PMIC_RG_INT_EN_CHRDET_EDGE_ADDR                  MT6355_INT_CON0
#define PMIC_RG_INT_EN_CHRDET_EDGE_MASK                  0x1
#define PMIC_RG_INT_EN_CHRDET_EDGE_SHIFT                 6
#define PMIC_RG_INT_EN_BATON_LV_ADDR                     MT6355_INT_CON0
#define PMIC_RG_INT_EN_BATON_LV_MASK                     0x1
#define PMIC_RG_INT_EN_BATON_LV_SHIFT                    7
#define PMIC_RG_INT_EN_BATON_HV_ADDR                     MT6355_INT_CON0
#define PMIC_RG_INT_EN_BATON_HV_MASK                     0x1
#define PMIC_RG_INT_EN_BATON_HV_SHIFT                    8
#define PMIC_RG_INT_EN_BATON_BAT_IN_ADDR                 MT6355_INT_CON0
#define PMIC_RG_INT_EN_BATON_BAT_IN_MASK                 0x1
#define PMIC_RG_INT_EN_BATON_BAT_IN_SHIFT                9
#define PMIC_RG_INT_EN_BATON_BAT_OUT_ADDR                MT6355_INT_CON0
#define PMIC_RG_INT_EN_BATON_BAT_OUT_MASK                0x1
#define PMIC_RG_INT_EN_BATON_BAT_OUT_SHIFT               10
#define PMIC_RG_INT_EN_RTC_ADDR                          MT6355_INT_CON0
#define PMIC_RG_INT_EN_RTC_MASK                          0x1
#define PMIC_RG_INT_EN_RTC_SHIFT                         11
#define PMIC_RG_INT_EN_RTC_NSEC_ADDR                     MT6355_INT_CON0
#define PMIC_RG_INT_EN_RTC_NSEC_MASK                     0x1
#define PMIC_RG_INT_EN_RTC_NSEC_SHIFT                    12
#define PMIC_RG_INT_EN_BIF_ADDR                          MT6355_INT_CON0
#define PMIC_RG_INT_EN_BIF_MASK                          0x1
#define PMIC_RG_INT_EN_BIF_SHIFT                         13
#define PMIC_RG_INT_EN_VCDT_HV_DET_ADDR                  MT6355_INT_CON0
#define PMIC_RG_INT_EN_VCDT_HV_DET_MASK                  0x1
#define PMIC_RG_INT_EN_VCDT_HV_DET_SHIFT                 14
#define PMIC_INT_CON0_SET_ADDR                           MT6355_INT_CON0_SET
#define PMIC_INT_CON0_SET_MASK                           0xFFFF
#define PMIC_INT_CON0_SET_SHIFT                          0
#define PMIC_INT_CON0_CLR_ADDR                           MT6355_INT_CON0_CLR
#define PMIC_INT_CON0_CLR_MASK                           0xFFFF
#define PMIC_INT_CON0_CLR_SHIFT                          0
#define PMIC_RG_INT_EN_THR_H_ADDR                        MT6355_INT_CON1
#define PMIC_RG_INT_EN_THR_H_MASK                        0x1
#define PMIC_RG_INT_EN_THR_H_SHIFT                       0
#define PMIC_RG_INT_EN_THR_L_ADDR                        MT6355_INT_CON1
#define PMIC_RG_INT_EN_THR_L_MASK                        0x1
#define PMIC_RG_INT_EN_THR_L_SHIFT                       1
#define PMIC_RG_INT_EN_BAT_H_ADDR                        MT6355_INT_CON1
#define PMIC_RG_INT_EN_BAT_H_MASK                        0x1
#define PMIC_RG_INT_EN_BAT_H_SHIFT                       2
#define PMIC_RG_INT_EN_BAT_L_ADDR                        MT6355_INT_CON1
#define PMIC_RG_INT_EN_BAT_L_MASK                        0x1
#define PMIC_RG_INT_EN_BAT_L_SHIFT                       3
#define PMIC_RG_INT_EN_BAT2_H_ADDR                       MT6355_INT_CON1
#define PMIC_RG_INT_EN_BAT2_H_MASK                       0x1
#define PMIC_RG_INT_EN_BAT2_H_SHIFT                      4
#define PMIC_RG_INT_EN_BAT2_L_ADDR                       MT6355_INT_CON1
#define PMIC_RG_INT_EN_BAT2_L_MASK                       0x1
#define PMIC_RG_INT_EN_BAT2_L_SHIFT                      5
#define PMIC_RG_INT_EN_BAT_TEMP_H_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_BAT_TEMP_H_MASK                   0x1
#define PMIC_RG_INT_EN_BAT_TEMP_H_SHIFT                  6
#define PMIC_RG_INT_EN_BAT_TEMP_L_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_BAT_TEMP_L_MASK                   0x1
#define PMIC_RG_INT_EN_BAT_TEMP_L_SHIFT                  7
#define PMIC_RG_INT_EN_AUXADC_IMP_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_AUXADC_IMP_MASK                   0x1
#define PMIC_RG_INT_EN_AUXADC_IMP_SHIFT                  8
#define PMIC_RG_INT_EN_NAG_C_DLTV_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_NAG_C_DLTV_MASK                   0x1
#define PMIC_RG_INT_EN_NAG_C_DLTV_SHIFT                  9
#define PMIC_RG_INT_EN_JEITA_HOT_ADDR                    MT6355_INT_CON1
#define PMIC_RG_INT_EN_JEITA_HOT_MASK                    0x1
#define PMIC_RG_INT_EN_JEITA_HOT_SHIFT                   10
#define PMIC_RG_INT_EN_JEITA_WARM_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_JEITA_WARM_MASK                   0x1
#define PMIC_RG_INT_EN_JEITA_WARM_SHIFT                  11
#define PMIC_RG_INT_EN_JEITA_COOL_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_JEITA_COOL_MASK                   0x1
#define PMIC_RG_INT_EN_JEITA_COOL_SHIFT                  12
#define PMIC_RG_INT_EN_JEITA_COLD_ADDR                   MT6355_INT_CON1
#define PMIC_RG_INT_EN_JEITA_COLD_MASK                   0x1
#define PMIC_RG_INT_EN_JEITA_COLD_SHIFT                  13
#define PMIC_INT_CON1_SET_ADDR                           MT6355_INT_CON1_SET
#define PMIC_INT_CON1_SET_MASK                           0xFFFF
#define PMIC_INT_CON1_SET_SHIFT                          0
#define PMIC_INT_CON1_CLR_ADDR                           MT6355_INT_CON1_CLR
#define PMIC_INT_CON1_CLR_MASK                           0xFFFF
#define PMIC_INT_CON1_CLR_SHIFT                          0
#define PMIC_RG_INT_EN_VPROC11_OC_ADDR                   MT6355_INT_CON2
#define PMIC_RG_INT_EN_VPROC11_OC_MASK                   0x1
#define PMIC_RG_INT_EN_VPROC11_OC_SHIFT                  0
#define PMIC_RG_INT_EN_VPROC12_OC_ADDR                   MT6355_INT_CON2
#define PMIC_RG_INT_EN_VPROC12_OC_MASK                   0x1
#define PMIC_RG_INT_EN_VPROC12_OC_SHIFT                  1
#define PMIC_RG_INT_EN_VCORE_OC_ADDR                     MT6355_INT_CON2
#define PMIC_RG_INT_EN_VCORE_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VCORE_OC_SHIFT                    2
#define PMIC_RG_INT_EN_VGPU_OC_ADDR                      MT6355_INT_CON2
#define PMIC_RG_INT_EN_VGPU_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VGPU_OC_SHIFT                     3
#define PMIC_RG_INT_EN_VDRAM1_OC_ADDR                    MT6355_INT_CON2
#define PMIC_RG_INT_EN_VDRAM1_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VDRAM1_OC_SHIFT                   4
#define PMIC_RG_INT_EN_VDRAM2_OC_ADDR                    MT6355_INT_CON2
#define PMIC_RG_INT_EN_VDRAM2_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VDRAM2_OC_SHIFT                   5
#define PMIC_RG_INT_EN_VMODEM_OC_ADDR                    MT6355_INT_CON2
#define PMIC_RG_INT_EN_VMODEM_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VMODEM_OC_SHIFT                   6
#define PMIC_RG_INT_EN_VS1_OC_ADDR                       MT6355_INT_CON2
#define PMIC_RG_INT_EN_VS1_OC_MASK                       0x1
#define PMIC_RG_INT_EN_VS1_OC_SHIFT                      7
#define PMIC_RG_INT_EN_VS2_OC_ADDR                       MT6355_INT_CON2
#define PMIC_RG_INT_EN_VS2_OC_MASK                       0x1
#define PMIC_RG_INT_EN_VS2_OC_SHIFT                      8
#define PMIC_RG_INT_EN_VPA_OC_ADDR                       MT6355_INT_CON2
#define PMIC_RG_INT_EN_VPA_OC_MASK                       0x1
#define PMIC_RG_INT_EN_VPA_OC_SHIFT                      9
#define PMIC_RG_INT_EN_VCORE_PREOC_ADDR                  MT6355_INT_CON2
#define PMIC_RG_INT_EN_VCORE_PREOC_MASK                  0x1
#define PMIC_RG_INT_EN_VCORE_PREOC_SHIFT                 10
#define PMIC_RG_INT_EN_VA10_OC_ADDR                      MT6355_INT_CON2
#define PMIC_RG_INT_EN_VA10_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VA10_OC_SHIFT                     11
#define PMIC_RG_INT_EN_VA12_OC_ADDR                      MT6355_INT_CON2
#define PMIC_RG_INT_EN_VA12_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VA12_OC_SHIFT                     12
#define PMIC_RG_INT_EN_VA18_OC_ADDR                      MT6355_INT_CON2
#define PMIC_RG_INT_EN_VA18_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VA18_OC_SHIFT                     13
#define PMIC_RG_INT_EN_VBIF28_OC_ADDR                    MT6355_INT_CON2
#define PMIC_RG_INT_EN_VBIF28_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VBIF28_OC_SHIFT                   14
#define PMIC_RG_INT_EN_VCAMA1_OC_ADDR                    MT6355_INT_CON2
#define PMIC_RG_INT_EN_VCAMA1_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VCAMA1_OC_SHIFT                   15
#define PMIC_INT_CON2_SET_ADDR                           MT6355_INT_CON2_SET
#define PMIC_INT_CON2_SET_MASK                           0xFFFF
#define PMIC_INT_CON2_SET_SHIFT                          0
#define PMIC_INT_CON2_CLR_ADDR                           MT6355_INT_CON2_CLR
#define PMIC_INT_CON2_CLR_MASK                           0xFFFF
#define PMIC_INT_CON2_CLR_SHIFT                          0
#define PMIC_RG_INT_EN_VCAMA2_OC_ADDR                    MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCAMA2_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VCAMA2_OC_SHIFT                   0
#define PMIC_RG_INT_EN_VXO18_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VXO18_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VXO18_OC_SHIFT                    1
#define PMIC_RG_INT_EN_VCAMD1_OC_ADDR                    MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCAMD1_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VCAMD1_OC_SHIFT                   2
#define PMIC_RG_INT_EN_VCAMD2_OC_ADDR                    MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCAMD2_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VCAMD2_OC_SHIFT                   3
#define PMIC_RG_INT_EN_VCAMIO_OC_ADDR                    MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCAMIO_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VCAMIO_OC_SHIFT                   4
#define PMIC_RG_INT_EN_VCN18_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCN18_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VCN18_OC_SHIFT                    5
#define PMIC_RG_INT_EN_VCN28_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCN28_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VCN28_OC_SHIFT                    6
#define PMIC_RG_INT_EN_VCN33_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VCN33_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VCN33_OC_SHIFT                    7
#define PMIC_RG_INT_EN_VTCXO24_OC_ADDR                   MT6355_INT_CON3
#define PMIC_RG_INT_EN_VTCXO24_OC_MASK                   0x1
#define PMIC_RG_INT_EN_VTCXO24_OC_SHIFT                  8
#define PMIC_RG_INT_EN_VEMC_OC_ADDR                      MT6355_INT_CON3
#define PMIC_RG_INT_EN_VEMC_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VEMC_OC_SHIFT                     9
#define PMIC_RG_INT_EN_VFE28_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VFE28_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VFE28_OC_SHIFT                    10
#define PMIC_RG_INT_EN_VGP_OC_ADDR                       MT6355_INT_CON3
#define PMIC_RG_INT_EN_VGP_OC_MASK                       0x1
#define PMIC_RG_INT_EN_VGP_OC_SHIFT                      11
#define PMIC_RG_INT_EN_VLDO28_OC_ADDR                    MT6355_INT_CON3
#define PMIC_RG_INT_EN_VLDO28_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VLDO28_OC_SHIFT                   12
#define PMIC_RG_INT_EN_VIO18_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VIO18_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VIO18_OC_SHIFT                    13
#define PMIC_RG_INT_EN_VIO28_OC_ADDR                     MT6355_INT_CON3
#define PMIC_RG_INT_EN_VIO28_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VIO28_OC_SHIFT                    14
#define PMIC_RG_INT_EN_VMC_OC_ADDR                       MT6355_INT_CON3
#define PMIC_RG_INT_EN_VMC_OC_MASK                       0x1
#define PMIC_RG_INT_EN_VMC_OC_SHIFT                      15
#define PMIC_INT_CON3_SET_ADDR                           MT6355_INT_CON3_SET
#define PMIC_INT_CON3_SET_MASK                           0xFFFF
#define PMIC_INT_CON3_SET_SHIFT                          0
#define PMIC_INT_CON3_CLR_ADDR                           MT6355_INT_CON3_CLR
#define PMIC_INT_CON3_CLR_MASK                           0xFFFF
#define PMIC_INT_CON3_CLR_SHIFT                          0
#define PMIC_RG_INT_EN_VMCH_OC_ADDR                      MT6355_INT_CON4
#define PMIC_RG_INT_EN_VMCH_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VMCH_OC_SHIFT                     0
#define PMIC_RG_INT_EN_VMIPI_OC_ADDR                     MT6355_INT_CON4
#define PMIC_RG_INT_EN_VMIPI_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VMIPI_OC_SHIFT                    1
#define PMIC_RG_INT_EN_VRF12_OC_ADDR                     MT6355_INT_CON4
#define PMIC_RG_INT_EN_VRF12_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VRF12_OC_SHIFT                    2
#define PMIC_RG_INT_EN_VRF18_1_OC_ADDR                   MT6355_INT_CON4
#define PMIC_RG_INT_EN_VRF18_1_OC_MASK                   0x1
#define PMIC_RG_INT_EN_VRF18_1_OC_SHIFT                  3
#define PMIC_RG_INT_EN_VRF18_2_OC_ADDR                   MT6355_INT_CON4
#define PMIC_RG_INT_EN_VRF18_2_OC_MASK                   0x1
#define PMIC_RG_INT_EN_VRF18_2_OC_SHIFT                  4
#define PMIC_RG_INT_EN_VSIM1_OC_ADDR                     MT6355_INT_CON4
#define PMIC_RG_INT_EN_VSIM1_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VSIM1_OC_SHIFT                    5
#define PMIC_RG_INT_EN_VSIM2_OC_ADDR                     MT6355_INT_CON4
#define PMIC_RG_INT_EN_VSIM2_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VSIM2_OC_SHIFT                    6
#define PMIC_RG_INT_EN_VGP2_OC_ADDR                      MT6355_INT_CON4
#define PMIC_RG_INT_EN_VGP2_OC_MASK                      0x1
#define PMIC_RG_INT_EN_VGP2_OC_SHIFT                     7
#define PMIC_RG_INT_EN_VSRAM_CORE_OC_ADDR                MT6355_INT_CON4
#define PMIC_RG_INT_EN_VSRAM_CORE_OC_MASK                0x1
#define PMIC_RG_INT_EN_VSRAM_CORE_OC_SHIFT               8
#define PMIC_RG_INT_EN_VSRAM_PROC_OC_ADDR                MT6355_INT_CON4
#define PMIC_RG_INT_EN_VSRAM_PROC_OC_MASK                0x1
#define PMIC_RG_INT_EN_VSRAM_PROC_OC_SHIFT               9
#define PMIC_RG_INT_EN_VSRAM_GPU_OC_ADDR                 MT6355_INT_CON4
#define PMIC_RG_INT_EN_VSRAM_GPU_OC_MASK                 0x1
#define PMIC_RG_INT_EN_VSRAM_GPU_OC_SHIFT                10
#define PMIC_RG_INT_EN_VSRAM_MD_OC_ADDR                  MT6355_INT_CON4
#define PMIC_RG_INT_EN_VSRAM_MD_OC_MASK                  0x1
#define PMIC_RG_INT_EN_VSRAM_MD_OC_SHIFT                 11
#define PMIC_RG_INT_EN_VUFS18_OC_ADDR                    MT6355_INT_CON4
#define PMIC_RG_INT_EN_VUFS18_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VUFS18_OC_SHIFT                   12
#define PMIC_RG_INT_EN_VUSB33_OC_ADDR                    MT6355_INT_CON4
#define PMIC_RG_INT_EN_VUSB33_OC_MASK                    0x1
#define PMIC_RG_INT_EN_VUSB33_OC_SHIFT                   13
#define PMIC_RG_INT_EN_VXO22_OC_ADDR                     MT6355_INT_CON4
#define PMIC_RG_INT_EN_VXO22_OC_MASK                     0x1
#define PMIC_RG_INT_EN_VXO22_OC_SHIFT                    14
#define PMIC_INT_CON4_SET_ADDR                           MT6355_INT_CON4_SET
#define PMIC_INT_CON4_SET_MASK                           0xFFFF
#define PMIC_INT_CON4_SET_SHIFT                          0
#define PMIC_INT_CON4_CLR_ADDR                           MT6355_INT_CON4_CLR
#define PMIC_INT_CON4_CLR_MASK                           0xFFFF
#define PMIC_INT_CON4_CLR_SHIFT                          0
#define PMIC_RG_INT_EN_FG_BAT0_H_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_BAT0_H_MASK                    0x1
#define PMIC_RG_INT_EN_FG_BAT0_H_SHIFT                   0
#define PMIC_RG_INT_EN_FG_BAT0_L_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_BAT0_L_MASK                    0x1
#define PMIC_RG_INT_EN_FG_BAT0_L_SHIFT                   1
#define PMIC_RG_INT_EN_FG_CUR_H_ADDR                     MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_CUR_H_MASK                     0x1
#define PMIC_RG_INT_EN_FG_CUR_H_SHIFT                    2
#define PMIC_RG_INT_EN_FG_CUR_L_ADDR                     MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_CUR_L_MASK                     0x1
#define PMIC_RG_INT_EN_FG_CUR_L_SHIFT                    3
#define PMIC_RG_INT_EN_FG_ZCV_ADDR                       MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_ZCV_MASK                       0x1
#define PMIC_RG_INT_EN_FG_ZCV_SHIFT                      4
#define PMIC_RG_INT_EN_FG_BAT1_H_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_BAT1_H_MASK                    0x1
#define PMIC_RG_INT_EN_FG_BAT1_H_SHIFT                   5
#define PMIC_RG_INT_EN_FG_BAT1_L_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_BAT1_L_MASK                    0x1
#define PMIC_RG_INT_EN_FG_BAT1_L_SHIFT                   6
#define PMIC_RG_INT_EN_FG_N_CHARGE_L_ADDR                MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_N_CHARGE_L_MASK                0x1
#define PMIC_RG_INT_EN_FG_N_CHARGE_L_SHIFT               7
#define PMIC_RG_INT_EN_FG_IAVG_H_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_IAVG_H_MASK                    0x1
#define PMIC_RG_INT_EN_FG_IAVG_H_SHIFT                   8
#define PMIC_RG_INT_EN_FG_IAVG_L_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_IAVG_L_MASK                    0x1
#define PMIC_RG_INT_EN_FG_IAVG_L_SHIFT                   9
#define PMIC_RG_INT_EN_FG_TIME_H_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_TIME_H_MASK                    0x1
#define PMIC_RG_INT_EN_FG_TIME_H_SHIFT                   10
#define PMIC_RG_INT_EN_FG_DISCHARGE_ADDR                 MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_DISCHARGE_MASK                 0x1
#define PMIC_RG_INT_EN_FG_DISCHARGE_SHIFT                11
#define PMIC_RG_INT_EN_FG_CHARGE_ADDR                    MT6355_INT_CON5
#define PMIC_RG_INT_EN_FG_CHARGE_MASK                    0x1
#define PMIC_RG_INT_EN_FG_CHARGE_SHIFT                   12
#define PMIC_RG_INT_EN_CON5_ADDR                         MT6355_INT_CON5
#define PMIC_RG_INT_EN_CON5_MASK                         0x7
#define PMIC_RG_INT_EN_CON5_SHIFT                        13
#define PMIC_INT_CON5_SET_ADDR                           MT6355_INT_CON5_SET
#define PMIC_INT_CON5_SET_MASK                           0xFFFF
#define PMIC_INT_CON5_SET_SHIFT                          0
#define PMIC_INT_CON5_CLR_ADDR                           MT6355_INT_CON5_CLR
#define PMIC_INT_CON5_CLR_MASK                           0xFFFF
#define PMIC_INT_CON5_CLR_SHIFT                          0
#define PMIC_RG_INT_EN_AUDIO_ADDR                        MT6355_INT_CON6
#define PMIC_RG_INT_EN_AUDIO_MASK                        0x1
#define PMIC_RG_INT_EN_AUDIO_SHIFT                       0
#define PMIC_RG_INT_EN_MAD_ADDR                          MT6355_INT_CON6
#define PMIC_RG_INT_EN_MAD_MASK                          0x1
#define PMIC_RG_INT_EN_MAD_SHIFT                         1
#define PMIC_RG_INT_EN_EINT_RTC32K_1V8_1_ADDR            MT6355_INT_CON6
#define PMIC_RG_INT_EN_EINT_RTC32K_1V8_1_MASK            0x1
#define PMIC_RG_INT_EN_EINT_RTC32K_1V8_1_SHIFT           2
#define PMIC_RG_INT_EN_EINT_AUD_CLK_ADDR                 MT6355_INT_CON6
#define PMIC_RG_INT_EN_EINT_AUD_CLK_MASK                 0x1
#define PMIC_RG_INT_EN_EINT_AUD_CLK_SHIFT                3
#define PMIC_RG_INT_EN_EINT_AUD_DAT_MOSI_ADDR            MT6355_INT_CON6
#define PMIC_RG_INT_EN_EINT_AUD_DAT_MOSI_MASK            0x1
#define PMIC_RG_INT_EN_EINT_AUD_DAT_MOSI_SHIFT           4
#define PMIC_RG_INT_EN_EINT_AUD_DAT_MISO_ADDR            MT6355_INT_CON6
#define PMIC_RG_INT_EN_EINT_AUD_DAT_MISO_MASK            0x1
#define PMIC_RG_INT_EN_EINT_AUD_DAT_MISO_SHIFT           5
#define PMIC_RG_INT_EN_EINT_VOW_CLK_MISO_ADDR            MT6355_INT_CON6
#define PMIC_RG_INT_EN_EINT_VOW_CLK_MISO_MASK            0x1
#define PMIC_RG_INT_EN_EINT_VOW_CLK_MISO_SHIFT           6
#define PMIC_RG_INT_EN_ACCDET_ADDR                       MT6355_INT_CON6
#define PMIC_RG_INT_EN_ACCDET_MASK                       0x1
#define PMIC_RG_INT_EN_ACCDET_SHIFT                      7
#define PMIC_RG_INT_EN_ACCDET_EINT_ADDR                  MT6355_INT_CON6
#define PMIC_RG_INT_EN_ACCDET_EINT_MASK                  0x1
#define PMIC_RG_INT_EN_ACCDET_EINT_SHIFT                 8
#define PMIC_RG_INT_EN_SPI_CMD_ALERT_ADDR                MT6355_INT_CON6
#define PMIC_RG_INT_EN_SPI_CMD_ALERT_MASK                0x1
#define PMIC_RG_INT_EN_SPI_CMD_ALERT_SHIFT               9
#define PMIC_INT_CON6_SET_ADDR                           MT6355_INT_CON6_SET
#define PMIC_INT_CON6_SET_MASK                           0xFFFF
#define PMIC_INT_CON6_SET_SHIFT                          0
#define PMIC_INT_CON6_CLR_ADDR                           MT6355_INT_CON6_CLR
#define PMIC_INT_CON6_CLR_MASK                           0xFFFF
#define PMIC_INT_CON6_CLR_SHIFT                          0
#define PMIC_RG_INT_MASK_PWRKEY_ADDR                     MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_PWRKEY_MASK                     0x1
#define PMIC_RG_INT_MASK_PWRKEY_SHIFT                    0
#define PMIC_RG_INT_MASK_HOMEKEY_ADDR                    MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_HOMEKEY_MASK                    0x1
#define PMIC_RG_INT_MASK_HOMEKEY_SHIFT                   1
#define PMIC_RG_INT_MASK_PWRKEY_R_ADDR                   MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_PWRKEY_R_MASK                   0x1
#define PMIC_RG_INT_MASK_PWRKEY_R_SHIFT                  2
#define PMIC_RG_INT_MASK_HOMEKEY_R_ADDR                  MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_HOMEKEY_R_MASK                  0x1
#define PMIC_RG_INT_MASK_HOMEKEY_R_SHIFT                 3
#define PMIC_RG_INT_MASK_NI_LBAT_INT_ADDR                MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_NI_LBAT_INT_MASK                0x1
#define PMIC_RG_INT_MASK_NI_LBAT_INT_SHIFT               4
#define PMIC_RG_INT_MASK_CHRDET_ADDR                     MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_CHRDET_MASK                     0x1
#define PMIC_RG_INT_MASK_CHRDET_SHIFT                    5
#define PMIC_RG_INT_MASK_CHRDET_EDGE_ADDR                MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_CHRDET_EDGE_MASK                0x1
#define PMIC_RG_INT_MASK_CHRDET_EDGE_SHIFT               6
#define PMIC_RG_INT_MASK_BATON_LV_ADDR                   MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BATON_LV_MASK                   0x1
#define PMIC_RG_INT_MASK_BATON_LV_SHIFT                  7
#define PMIC_RG_INT_MASK_BATON_HV_ADDR                   MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BATON_HV_MASK                   0x1
#define PMIC_RG_INT_MASK_BATON_HV_SHIFT                  8
#define PMIC_RG_INT_MASK_BATON_BAT_IN_ADDR               MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BATON_BAT_IN_MASK               0x1
#define PMIC_RG_INT_MASK_BATON_BAT_IN_SHIFT              9
#define PMIC_RG_INT_MASK_BATON_BAT_OUT_ADDR              MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BATON_BAT_OUT_MASK              0x1
#define PMIC_RG_INT_MASK_BATON_BAT_OUT_SHIFT             10
#define PMIC_RG_INT_MASK_RTC_ADDR                        MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_RTC_MASK                        0x1
#define PMIC_RG_INT_MASK_RTC_SHIFT                       11
#define PMIC_RG_INT_MASK_RTC_NSEC_ADDR                   MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_RTC_NSEC_MASK                   0x1
#define PMIC_RG_INT_MASK_RTC_NSEC_SHIFT                  12
#define PMIC_RG_INT_MASK_BIF_ADDR                        MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BIF_MASK                        0x1
#define PMIC_RG_INT_MASK_BIF_SHIFT                       13
#define PMIC_RG_INT_MASK_VCDT_HV_DET_ADDR                MT6355_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCDT_HV_DET_MASK                0x1
#define PMIC_RG_INT_MASK_VCDT_HV_DET_SHIFT               14
#define PMIC_INT_MASK_CON0_SET_ADDR                      MT6355_INT_MASK_CON0_SET
#define PMIC_INT_MASK_CON0_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON0_SET_SHIFT                     0
#define PMIC_INT_MASK_CON0_CLR_ADDR                      MT6355_INT_MASK_CON0_CLR
#define PMIC_INT_MASK_CON0_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON0_CLR_SHIFT                     0
#define PMIC_RG_INT_MASK_THR_H_ADDR                      MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_THR_H_MASK                      0x1
#define PMIC_RG_INT_MASK_THR_H_SHIFT                     0
#define PMIC_RG_INT_MASK_THR_L_ADDR                      MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_THR_L_MASK                      0x1
#define PMIC_RG_INT_MASK_THR_L_SHIFT                     1
#define PMIC_RG_INT_MASK_BAT_H_ADDR                      MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BAT_H_MASK                      0x1
#define PMIC_RG_INT_MASK_BAT_H_SHIFT                     2
#define PMIC_RG_INT_MASK_BAT_L_ADDR                      MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BAT_L_MASK                      0x1
#define PMIC_RG_INT_MASK_BAT_L_SHIFT                     3
#define PMIC_RG_INT_MASK_BAT2_H_ADDR                     MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BAT2_H_MASK                     0x1
#define PMIC_RG_INT_MASK_BAT2_H_SHIFT                    4
#define PMIC_RG_INT_MASK_BAT2_L_ADDR                     MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BAT2_L_MASK                     0x1
#define PMIC_RG_INT_MASK_BAT2_L_SHIFT                    5
#define PMIC_RG_INT_MASK_BAT_TEMP_H_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BAT_TEMP_H_MASK                 0x1
#define PMIC_RG_INT_MASK_BAT_TEMP_H_SHIFT                6
#define PMIC_RG_INT_MASK_BAT_TEMP_L_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BAT_TEMP_L_MASK                 0x1
#define PMIC_RG_INT_MASK_BAT_TEMP_L_SHIFT                7
#define PMIC_RG_INT_MASK_AUXADC_IMP_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_AUXADC_IMP_MASK                 0x1
#define PMIC_RG_INT_MASK_AUXADC_IMP_SHIFT                8
#define PMIC_RG_INT_MASK_NAG_C_DLTV_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_NAG_C_DLTV_MASK                 0x1
#define PMIC_RG_INT_MASK_NAG_C_DLTV_SHIFT                9
#define PMIC_RG_INT_MASK_JEITA_HOT_ADDR                  MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_JEITA_HOT_MASK                  0x1
#define PMIC_RG_INT_MASK_JEITA_HOT_SHIFT                 10
#define PMIC_RG_INT_MASK_JEITA_WARM_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_JEITA_WARM_MASK                 0x1
#define PMIC_RG_INT_MASK_JEITA_WARM_SHIFT                11
#define PMIC_RG_INT_MASK_JEITA_COOL_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_JEITA_COOL_MASK                 0x1
#define PMIC_RG_INT_MASK_JEITA_COOL_SHIFT                12
#define PMIC_RG_INT_MASK_JEITA_COLD_ADDR                 MT6355_INT_MASK_CON1
#define PMIC_RG_INT_MASK_JEITA_COLD_MASK                 0x1
#define PMIC_RG_INT_MASK_JEITA_COLD_SHIFT                13
#define PMIC_INT_MASK_CON1_SET_ADDR                      MT6355_INT_MASK_CON1_SET
#define PMIC_INT_MASK_CON1_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON1_SET_SHIFT                     0
#define PMIC_INT_MASK_CON1_CLR_ADDR                      MT6355_INT_MASK_CON1_CLR
#define PMIC_INT_MASK_CON1_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON1_CLR_SHIFT                     0
#define PMIC_RG_INT_MASK_VPROC11_OC_ADDR                 MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VPROC11_OC_MASK                 0x1
#define PMIC_RG_INT_MASK_VPROC11_OC_SHIFT                0
#define PMIC_RG_INT_MASK_VPROC12_OC_ADDR                 MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VPROC12_OC_MASK                 0x1
#define PMIC_RG_INT_MASK_VPROC12_OC_SHIFT                1
#define PMIC_RG_INT_MASK_VCORE_OC_ADDR                   MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VCORE_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VCORE_OC_SHIFT                  2
#define PMIC_RG_INT_MASK_VGPU_OC_ADDR                    MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VGPU_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VGPU_OC_SHIFT                   3
#define PMIC_RG_INT_MASK_VDRAM1_OC_ADDR                  MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VDRAM1_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VDRAM1_OC_SHIFT                 4
#define PMIC_RG_INT_MASK_VDRAM2_OC_ADDR                  MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VDRAM2_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VDRAM2_OC_SHIFT                 5
#define PMIC_RG_INT_MASK_VMODEM_OC_ADDR                  MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VMODEM_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VMODEM_OC_SHIFT                 6
#define PMIC_RG_INT_MASK_VS1_OC_ADDR                     MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VS1_OC_MASK                     0x1
#define PMIC_RG_INT_MASK_VS1_OC_SHIFT                    7
#define PMIC_RG_INT_MASK_VS2_OC_ADDR                     MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VS2_OC_MASK                     0x1
#define PMIC_RG_INT_MASK_VS2_OC_SHIFT                    8
#define PMIC_RG_INT_MASK_VPA_OC_ADDR                     MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VPA_OC_MASK                     0x1
#define PMIC_RG_INT_MASK_VPA_OC_SHIFT                    9
#define PMIC_RG_INT_MASK_VCORE_PREOC_ADDR                MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VCORE_PREOC_MASK                0x1
#define PMIC_RG_INT_MASK_VCORE_PREOC_SHIFT               10
#define PMIC_RG_INT_MASK_VA10_OC_ADDR                    MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VA10_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VA10_OC_SHIFT                   11
#define PMIC_RG_INT_MASK_VA12_OC_ADDR                    MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VA12_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VA12_OC_SHIFT                   12
#define PMIC_RG_INT_MASK_VA18_OC_ADDR                    MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VA18_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VA18_OC_SHIFT                   13
#define PMIC_RG_INT_MASK_VBIF28_OC_ADDR                  MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VBIF28_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VBIF28_OC_SHIFT                 14
#define PMIC_RG_INT_MASK_VCAMA1_OC_ADDR                  MT6355_INT_MASK_CON2
#define PMIC_RG_INT_MASK_VCAMA1_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VCAMA1_OC_SHIFT                 15
#define PMIC_INT_MASK_CON2_SET_ADDR                      MT6355_INT_MASK_CON2_SET
#define PMIC_INT_MASK_CON2_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON2_SET_SHIFT                     0
#define PMIC_INT_MASK_CON2_CLR_ADDR                      MT6355_INT_MASK_CON2_CLR
#define PMIC_INT_MASK_CON2_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON2_CLR_SHIFT                     0
#define PMIC_RG_INT_MASK_VCAMA2_OC_ADDR                  MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCAMA2_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VCAMA2_OC_SHIFT                 0
#define PMIC_RG_INT_MASK_VXO18_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VXO18_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VXO18_OC_SHIFT                  1
#define PMIC_RG_INT_MASK_VCAMD1_OC_ADDR                  MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCAMD1_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VCAMD1_OC_SHIFT                 2
#define PMIC_RG_INT_MASK_VCAMD2_OC_ADDR                  MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCAMD2_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VCAMD2_OC_SHIFT                 3
#define PMIC_RG_INT_MASK_VCAMIO_OC_ADDR                  MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCAMIO_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VCAMIO_OC_SHIFT                 4
#define PMIC_RG_INT_MASK_VCN18_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCN18_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VCN18_OC_SHIFT                  5
#define PMIC_RG_INT_MASK_VCN28_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCN28_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VCN28_OC_SHIFT                  6
#define PMIC_RG_INT_MASK_VCN33_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VCN33_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VCN33_OC_SHIFT                  7
#define PMIC_RG_INT_MASK_VTCXO24_OC_ADDR                 MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VTCXO24_OC_MASK                 0x1
#define PMIC_RG_INT_MASK_VTCXO24_OC_SHIFT                8
#define PMIC_RG_INT_MASK_VEMC_OC_ADDR                    MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VEMC_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VEMC_OC_SHIFT                   9
#define PMIC_RG_INT_MASK_VFE28_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VFE28_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VFE28_OC_SHIFT                  10
#define PMIC_RG_INT_MASK_VGP_OC_ADDR                     MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VGP_OC_MASK                     0x1
#define PMIC_RG_INT_MASK_VGP_OC_SHIFT                    11
#define PMIC_RG_INT_MASK_VLDO28_OC_ADDR                  MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VLDO28_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VLDO28_OC_SHIFT                 12
#define PMIC_RG_INT_MASK_VIO18_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VIO18_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VIO18_OC_SHIFT                  13
#define PMIC_RG_INT_MASK_VIO28_OC_ADDR                   MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VIO28_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VIO28_OC_SHIFT                  14
#define PMIC_RG_INT_MASK_VMC_OC_ADDR                     MT6355_INT_MASK_CON3
#define PMIC_RG_INT_MASK_VMC_OC_MASK                     0x1
#define PMIC_RG_INT_MASK_VMC_OC_SHIFT                    15
#define PMIC_INT_MASK_CON3_SET_ADDR                      MT6355_INT_MASK_CON3_SET
#define PMIC_INT_MASK_CON3_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON3_SET_SHIFT                     0
#define PMIC_INT_MASK_CON3_CLR_ADDR                      MT6355_INT_MASK_CON3_CLR
#define PMIC_INT_MASK_CON3_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON3_CLR_SHIFT                     0
#define PMIC_RG_INT_MASK_VMCH_OC_ADDR                    MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VMCH_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VMCH_OC_SHIFT                   0
#define PMIC_RG_INT_MASK_VMIPI_OC_ADDR                   MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VMIPI_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VMIPI_OC_SHIFT                  1
#define PMIC_RG_INT_MASK_VRF12_OC_ADDR                   MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VRF12_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VRF12_OC_SHIFT                  2
#define PMIC_RG_INT_MASK_VRF18_1_OC_ADDR                 MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VRF18_1_OC_MASK                 0x1
#define PMIC_RG_INT_MASK_VRF18_1_OC_SHIFT                3
#define PMIC_RG_INT_MASK_VRF18_2_OC_ADDR                 MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VRF18_2_OC_MASK                 0x1
#define PMIC_RG_INT_MASK_VRF18_2_OC_SHIFT                4
#define PMIC_RG_INT_MASK_VSIM1_OC_ADDR                   MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VSIM1_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VSIM1_OC_SHIFT                  5
#define PMIC_RG_INT_MASK_VSIM2_OC_ADDR                   MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VSIM2_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VSIM2_OC_SHIFT                  6
#define PMIC_RG_INT_MASK_VGP2_OC_ADDR                    MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VGP2_OC_MASK                    0x1
#define PMIC_RG_INT_MASK_VGP2_OC_SHIFT                   7
#define PMIC_RG_INT_MASK_VSRAM_CORE_OC_ADDR              MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VSRAM_CORE_OC_MASK              0x1
#define PMIC_RG_INT_MASK_VSRAM_CORE_OC_SHIFT             8
#define PMIC_RG_INT_MASK_VSRAM_PROC_OC_ADDR              MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VSRAM_PROC_OC_MASK              0x1
#define PMIC_RG_INT_MASK_VSRAM_PROC_OC_SHIFT             9
#define PMIC_RG_INT_MASK_VSRAM_GPU_OC_ADDR               MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VSRAM_GPU_OC_MASK               0x1
#define PMIC_RG_INT_MASK_VSRAM_GPU_OC_SHIFT              10
#define PMIC_RG_INT_MASK_VSRAM_MD_OC_ADDR                MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VSRAM_MD_OC_MASK                0x1
#define PMIC_RG_INT_MASK_VSRAM_MD_OC_SHIFT               11
#define PMIC_RG_INT_MASK_VUFS18_OC_ADDR                  MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VUFS18_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VUFS18_OC_SHIFT                 12
#define PMIC_RG_INT_MASK_VUSB33_OC_ADDR                  MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VUSB33_OC_MASK                  0x1
#define PMIC_RG_INT_MASK_VUSB33_OC_SHIFT                 13
#define PMIC_RG_INT_MASK_VXO22_OC_ADDR                   MT6355_INT_MASK_CON4
#define PMIC_RG_INT_MASK_VXO22_OC_MASK                   0x1
#define PMIC_RG_INT_MASK_VXO22_OC_SHIFT                  14
#define PMIC_INT_MASK_CON4_SET_ADDR                      MT6355_INT_MASK_CON4_SET
#define PMIC_INT_MASK_CON4_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON4_SET_SHIFT                     0
#define PMIC_INT_MASK_CON4_CLR_ADDR                      MT6355_INT_MASK_CON4_CLR
#define PMIC_INT_MASK_CON4_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON4_CLR_SHIFT                     0
#define PMIC_RG_INT_MASK_FG_BAT0_H_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_BAT0_H_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_BAT0_H_SHIFT                 0
#define PMIC_RG_INT_MASK_FG_BAT0_L_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_BAT0_L_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_BAT0_L_SHIFT                 1
#define PMIC_RG_INT_MASK_FG_CUR_H_ADDR                   MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_CUR_H_MASK                   0x1
#define PMIC_RG_INT_MASK_FG_CUR_H_SHIFT                  2
#define PMIC_RG_INT_MASK_FG_CUR_L_ADDR                   MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_CUR_L_MASK                   0x1
#define PMIC_RG_INT_MASK_FG_CUR_L_SHIFT                  3
#define PMIC_RG_INT_MASK_FG_ZCV_ADDR                     MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_ZCV_MASK                     0x1
#define PMIC_RG_INT_MASK_FG_ZCV_SHIFT                    4
#define PMIC_RG_INT_MASK_FG_BAT1_H_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_BAT1_H_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_BAT1_H_SHIFT                 5
#define PMIC_RG_INT_MASK_FG_BAT1_L_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_BAT1_L_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_BAT1_L_SHIFT                 6
#define PMIC_RG_INT_MASK_FG_N_CHARGE_L_ADDR              MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_N_CHARGE_L_MASK              0x1
#define PMIC_RG_INT_MASK_FG_N_CHARGE_L_SHIFT             7
#define PMIC_RG_INT_MASK_FG_IAVG_H_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_IAVG_H_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_IAVG_H_SHIFT                 8
#define PMIC_RG_INT_MASK_FG_IAVG_L_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_IAVG_L_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_IAVG_L_SHIFT                 9
#define PMIC_RG_INT_MASK_FG_TIME_H_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_TIME_H_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_TIME_H_SHIFT                 10
#define PMIC_RG_INT_MASK_FG_DISCHARGE_ADDR               MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_DISCHARGE_MASK               0x1
#define PMIC_RG_INT_MASK_FG_DISCHARGE_SHIFT              11
#define PMIC_RG_INT_MASK_FG_CHARGE_ADDR                  MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_FG_CHARGE_MASK                  0x1
#define PMIC_RG_INT_MASK_FG_CHARGE_SHIFT                 12
#define PMIC_RG_INT_MASK_CON5_ADDR                       MT6355_INT_MASK_CON5
#define PMIC_RG_INT_MASK_CON5_MASK                       0x7
#define PMIC_RG_INT_MASK_CON5_SHIFT                      13
#define PMIC_INT_MASK_CON5_SET_ADDR                      MT6355_INT_MASK_CON5_SET
#define PMIC_INT_MASK_CON5_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON5_SET_SHIFT                     0
#define PMIC_INT_MASK_CON5_CLR_ADDR                      MT6355_INT_MASK_CON5_CLR
#define PMIC_INT_MASK_CON5_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON5_CLR_SHIFT                     0
#define PMIC_RG_INT_MASK_AUDIO_ADDR                      MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_AUDIO_MASK                      0x1
#define PMIC_RG_INT_MASK_AUDIO_SHIFT                     0
#define PMIC_RG_INT_MASK_MAD_ADDR                        MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_MAD_MASK                        0x1
#define PMIC_RG_INT_MASK_MAD_SHIFT                       1
#define PMIC_RG_INT_MASK_EINT_RTC32K_1V8_1_ADDR          MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_EINT_RTC32K_1V8_1_MASK          0x1
#define PMIC_RG_INT_MASK_EINT_RTC32K_1V8_1_SHIFT         2
#define PMIC_RG_INT_MASK_EINT_AUD_CLK_ADDR               MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_EINT_AUD_CLK_MASK               0x1
#define PMIC_RG_INT_MASK_EINT_AUD_CLK_SHIFT              3
#define PMIC_RG_INT_MASK_EINT_AUD_DAT_MOSI_ADDR          MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_EINT_AUD_DAT_MOSI_MASK          0x1
#define PMIC_RG_INT_MASK_EINT_AUD_DAT_MOSI_SHIFT         4
#define PMIC_RG_INT_MASK_EINT_AUD_DAT_MISO_ADDR          MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_EINT_AUD_DAT_MISO_MASK          0x1
#define PMIC_RG_INT_MASK_EINT_AUD_DAT_MISO_SHIFT         5
#define PMIC_RG_INT_MASK_EINT_VOW_CLK_MISO_ADDR          MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_EINT_VOW_CLK_MISO_MASK          0x1
#define PMIC_RG_INT_MASK_EINT_VOW_CLK_MISO_SHIFT         6
#define PMIC_RG_INT_MASK_ACCDET_ADDR                     MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_ACCDET_MASK                     0x1
#define PMIC_RG_INT_MASK_ACCDET_SHIFT                    7
#define PMIC_RG_INT_MASK_ACCDET_EINT_ADDR                MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_ACCDET_EINT_MASK                0x1
#define PMIC_RG_INT_MASK_ACCDET_EINT_SHIFT               8
#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_ADDR              MT6355_INT_MASK_CON6
#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_MASK              0x1
#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_SHIFT             9
#define PMIC_INT_MASK_CON6_SET_ADDR                      MT6355_INT_MASK_CON6_SET
#define PMIC_INT_MASK_CON6_SET_MASK                      0xFFFF
#define PMIC_INT_MASK_CON6_SET_SHIFT                     0
#define PMIC_INT_MASK_CON6_CLR_ADDR                      MT6355_INT_MASK_CON6_CLR
#define PMIC_INT_MASK_CON6_CLR_MASK                      0xFFFF
#define PMIC_INT_MASK_CON6_CLR_SHIFT                     0
#define PMIC_RG_INT_STATUS_PWRKEY_ADDR                   MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_PWRKEY_MASK                   0x1
#define PMIC_RG_INT_STATUS_PWRKEY_SHIFT                  0
#define PMIC_RG_INT_STATUS_HOMEKEY_ADDR                  MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_HOMEKEY_MASK                  0x1
#define PMIC_RG_INT_STATUS_HOMEKEY_SHIFT                 1
#define PMIC_RG_INT_STATUS_PWRKEY_R_ADDR                 MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_PWRKEY_R_MASK                 0x1
#define PMIC_RG_INT_STATUS_PWRKEY_R_SHIFT                2
#define PMIC_RG_INT_STATUS_HOMEKEY_R_ADDR                MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_HOMEKEY_R_MASK                0x1
#define PMIC_RG_INT_STATUS_HOMEKEY_R_SHIFT               3
#define PMIC_RG_INT_STATUS_NI_LBAT_INT_ADDR              MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_NI_LBAT_INT_MASK              0x1
#define PMIC_RG_INT_STATUS_NI_LBAT_INT_SHIFT             4
#define PMIC_RG_INT_STATUS_CHRDET_ADDR                   MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_CHRDET_MASK                   0x1
#define PMIC_RG_INT_STATUS_CHRDET_SHIFT                  5
#define PMIC_RG_INT_STATUS_CHRDET_EDGE_ADDR              MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_CHRDET_EDGE_MASK              0x1
#define PMIC_RG_INT_STATUS_CHRDET_EDGE_SHIFT             6
#define PMIC_RG_INT_STATUS_BATON_LV_ADDR                 MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_BATON_LV_MASK                 0x1
#define PMIC_RG_INT_STATUS_BATON_LV_SHIFT                7
#define PMIC_RG_INT_STATUS_BATON_HV_ADDR                 MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_BATON_HV_MASK                 0x1
#define PMIC_RG_INT_STATUS_BATON_HV_SHIFT                8
#define PMIC_RG_INT_STATUS_BATON_BAT_IN_ADDR             MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_BATON_BAT_IN_MASK             0x1
#define PMIC_RG_INT_STATUS_BATON_BAT_IN_SHIFT            9
#define PMIC_RG_INT_STATUS_BATON_BAT_OUT_ADDR            MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_BATON_BAT_OUT_MASK            0x1
#define PMIC_RG_INT_STATUS_BATON_BAT_OUT_SHIFT           10
#define PMIC_RG_INT_STATUS_RTC_ADDR                      MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_RTC_MASK                      0x1
#define PMIC_RG_INT_STATUS_RTC_SHIFT                     11
#define PMIC_RG_INT_STATUS_RTC_NSEC_ADDR                 MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_RTC_NSEC_MASK                 0x1
#define PMIC_RG_INT_STATUS_RTC_NSEC_SHIFT                12
#define PMIC_RG_INT_STATUS_BIF_ADDR                      MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_BIF_MASK                      0x1
#define PMIC_RG_INT_STATUS_BIF_SHIFT                     13
#define PMIC_RG_INT_STATUS_VCDT_HV_DET_ADDR              MT6355_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCDT_HV_DET_MASK              0x1
#define PMIC_RG_INT_STATUS_VCDT_HV_DET_SHIFT             14
#define PMIC_RG_INT_STATUS_THR_H_ADDR                    MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_THR_H_MASK                    0x1
#define PMIC_RG_INT_STATUS_THR_H_SHIFT                   0
#define PMIC_RG_INT_STATUS_THR_L_ADDR                    MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_THR_L_MASK                    0x1
#define PMIC_RG_INT_STATUS_THR_L_SHIFT                   1
#define PMIC_RG_INT_STATUS_BAT_H_ADDR                    MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_BAT_H_MASK                    0x1
#define PMIC_RG_INT_STATUS_BAT_H_SHIFT                   2
#define PMIC_RG_INT_STATUS_BAT_L_ADDR                    MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_BAT_L_MASK                    0x1
#define PMIC_RG_INT_STATUS_BAT_L_SHIFT                   3
#define PMIC_RG_INT_STATUS_BAT2_H_ADDR                   MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_BAT2_H_MASK                   0x1
#define PMIC_RG_INT_STATUS_BAT2_H_SHIFT                  4
#define PMIC_RG_INT_STATUS_BAT2_L_ADDR                   MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_BAT2_L_MASK                   0x1
#define PMIC_RG_INT_STATUS_BAT2_L_SHIFT                  5
#define PMIC_RG_INT_STATUS_BAT_TEMP_H_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_BAT_TEMP_H_MASK               0x1
#define PMIC_RG_INT_STATUS_BAT_TEMP_H_SHIFT              6
#define PMIC_RG_INT_STATUS_BAT_TEMP_L_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_BAT_TEMP_L_MASK               0x1
#define PMIC_RG_INT_STATUS_BAT_TEMP_L_SHIFT              7
#define PMIC_RG_INT_STATUS_AUXADC_IMP_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_AUXADC_IMP_MASK               0x1
#define PMIC_RG_INT_STATUS_AUXADC_IMP_SHIFT              8
#define PMIC_RG_INT_STATUS_NAG_C_DLTV_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_NAG_C_DLTV_MASK               0x1
#define PMIC_RG_INT_STATUS_NAG_C_DLTV_SHIFT              9
#define PMIC_RG_INT_STATUS_JEITA_HOT_ADDR                MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_JEITA_HOT_MASK                0x1
#define PMIC_RG_INT_STATUS_JEITA_HOT_SHIFT               10
#define PMIC_RG_INT_STATUS_JEITA_WARM_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_JEITA_WARM_MASK               0x1
#define PMIC_RG_INT_STATUS_JEITA_WARM_SHIFT              11
#define PMIC_RG_INT_STATUS_JEITA_COOL_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_JEITA_COOL_MASK               0x1
#define PMIC_RG_INT_STATUS_JEITA_COOL_SHIFT              12
#define PMIC_RG_INT_STATUS_JEITA_COLD_ADDR               MT6355_INT_STATUS1
#define PMIC_RG_INT_STATUS_JEITA_COLD_MASK               0x1
#define PMIC_RG_INT_STATUS_JEITA_COLD_SHIFT              13
#define PMIC_RG_INT_STATUS_VPROC11_OC_ADDR               MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VPROC11_OC_MASK               0x1
#define PMIC_RG_INT_STATUS_VPROC11_OC_SHIFT              0
#define PMIC_RG_INT_STATUS_VPROC12_OC_ADDR               MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VPROC12_OC_MASK               0x1
#define PMIC_RG_INT_STATUS_VPROC12_OC_SHIFT              1
#define PMIC_RG_INT_STATUS_VCORE_OC_ADDR                 MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VCORE_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VCORE_OC_SHIFT                2
#define PMIC_RG_INT_STATUS_VGPU_OC_ADDR                  MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VGPU_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VGPU_OC_SHIFT                 3
#define PMIC_RG_INT_STATUS_VDRAM1_OC_ADDR                MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VDRAM1_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VDRAM1_OC_SHIFT               4
#define PMIC_RG_INT_STATUS_VDRAM2_OC_ADDR                MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VDRAM2_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VDRAM2_OC_SHIFT               5
#define PMIC_RG_INT_STATUS_VMODEM_OC_ADDR                MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VMODEM_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VMODEM_OC_SHIFT               6
#define PMIC_RG_INT_STATUS_VS1_OC_ADDR                   MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VS1_OC_MASK                   0x1
#define PMIC_RG_INT_STATUS_VS1_OC_SHIFT                  7
#define PMIC_RG_INT_STATUS_VS2_OC_ADDR                   MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VS2_OC_MASK                   0x1
#define PMIC_RG_INT_STATUS_VS2_OC_SHIFT                  8
#define PMIC_RG_INT_STATUS_VPA_OC_ADDR                   MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VPA_OC_MASK                   0x1
#define PMIC_RG_INT_STATUS_VPA_OC_SHIFT                  9
#define PMIC_RG_INT_STATUS_VCORE_PREOC_ADDR              MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VCORE_PREOC_MASK              0x1
#define PMIC_RG_INT_STATUS_VCORE_PREOC_SHIFT             10
#define PMIC_RG_INT_STATUS_VA10_OC_ADDR                  MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VA10_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VA10_OC_SHIFT                 11
#define PMIC_RG_INT_STATUS_VA12_OC_ADDR                  MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VA12_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VA12_OC_SHIFT                 12
#define PMIC_RG_INT_STATUS_VA18_OC_ADDR                  MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VA18_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VA18_OC_SHIFT                 13
#define PMIC_RG_INT_STATUS_VBIF28_OC_ADDR                MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VBIF28_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VBIF28_OC_SHIFT               14
#define PMIC_RG_INT_STATUS_VCAMA1_OC_ADDR                MT6355_INT_STATUS2
#define PMIC_RG_INT_STATUS_VCAMA1_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VCAMA1_OC_SHIFT               15
#define PMIC_RG_INT_STATUS_VCAMA2_OC_ADDR                MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCAMA2_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VCAMA2_OC_SHIFT               0
#define PMIC_RG_INT_STATUS_VXO18_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VXO18_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VXO18_OC_SHIFT                1
#define PMIC_RG_INT_STATUS_VCAMD1_OC_ADDR                MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCAMD1_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VCAMD1_OC_SHIFT               2
#define PMIC_RG_INT_STATUS_VCAMD2_OC_ADDR                MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCAMD2_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VCAMD2_OC_SHIFT               3
#define PMIC_RG_INT_STATUS_VCAMIO_OC_ADDR                MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCAMIO_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VCAMIO_OC_SHIFT               4
#define PMIC_RG_INT_STATUS_VCN18_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCN18_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VCN18_OC_SHIFT                5
#define PMIC_RG_INT_STATUS_VCN28_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCN28_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VCN28_OC_SHIFT                6
#define PMIC_RG_INT_STATUS_VCN33_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VCN33_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VCN33_OC_SHIFT                7
#define PMIC_RG_INT_STATUS_VTCXO24_OC_ADDR               MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VTCXO24_OC_MASK               0x1
#define PMIC_RG_INT_STATUS_VTCXO24_OC_SHIFT              8
#define PMIC_RG_INT_STATUS_VEMC_OC_ADDR                  MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VEMC_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VEMC_OC_SHIFT                 9
#define PMIC_RG_INT_STATUS_VFE28_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VFE28_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VFE28_OC_SHIFT                10
#define PMIC_RG_INT_STATUS_VGP_OC_ADDR                   MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VGP_OC_MASK                   0x1
#define PMIC_RG_INT_STATUS_VGP_OC_SHIFT                  11
#define PMIC_RG_INT_STATUS_VLDO28_OC_ADDR                MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VLDO28_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VLDO28_OC_SHIFT               12
#define PMIC_RG_INT_STATUS_VIO18_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VIO18_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VIO18_OC_SHIFT                13
#define PMIC_RG_INT_STATUS_VIO28_OC_ADDR                 MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VIO28_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VIO28_OC_SHIFT                14
#define PMIC_RG_INT_STATUS_VMC_OC_ADDR                   MT6355_INT_STATUS3
#define PMIC_RG_INT_STATUS_VMC_OC_MASK                   0x1
#define PMIC_RG_INT_STATUS_VMC_OC_SHIFT                  15
#define PMIC_RG_INT_STATUS_VMCH_OC_ADDR                  MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VMCH_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VMCH_OC_SHIFT                 0
#define PMIC_RG_INT_STATUS_VMIPI_OC_ADDR                 MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VMIPI_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VMIPI_OC_SHIFT                1
#define PMIC_RG_INT_STATUS_VRF12_OC_ADDR                 MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VRF12_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VRF12_OC_SHIFT                2
#define PMIC_RG_INT_STATUS_VRF18_1_OC_ADDR               MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VRF18_1_OC_MASK               0x1
#define PMIC_RG_INT_STATUS_VRF18_1_OC_SHIFT              3
#define PMIC_RG_INT_STATUS_VRF18_2_OC_ADDR               MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VRF18_2_OC_MASK               0x1
#define PMIC_RG_INT_STATUS_VRF18_2_OC_SHIFT              4
#define PMIC_RG_INT_STATUS_VSIM1_OC_ADDR                 MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VSIM1_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VSIM1_OC_SHIFT                5
#define PMIC_RG_INT_STATUS_VSIM2_OC_ADDR                 MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VSIM2_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VSIM2_OC_SHIFT                6
#define PMIC_RG_INT_STATUS_VGP2_OC_ADDR                  MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VGP2_OC_MASK                  0x1
#define PMIC_RG_INT_STATUS_VGP2_OC_SHIFT                 7
#define PMIC_RG_INT_STATUS_VSRAM_CORE_OC_ADDR            MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VSRAM_CORE_OC_MASK            0x1
#define PMIC_RG_INT_STATUS_VSRAM_CORE_OC_SHIFT           8
#define PMIC_RG_INT_STATUS_VSRAM_PROC_OC_ADDR            MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VSRAM_PROC_OC_MASK            0x1
#define PMIC_RG_INT_STATUS_VSRAM_PROC_OC_SHIFT           9
#define PMIC_RG_INT_STATUS_VSRAM_GPU_OC_ADDR             MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VSRAM_GPU_OC_MASK             0x1
#define PMIC_RG_INT_STATUS_VSRAM_GPU_OC_SHIFT            10
#define PMIC_RG_INT_STATUS_VSRAM_MD_OC_ADDR              MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VSRAM_MD_OC_MASK              0x1
#define PMIC_RG_INT_STATUS_VSRAM_MD_OC_SHIFT             11
#define PMIC_RG_INT_STATUS_VUFS18_OC_ADDR                MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VUFS18_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VUFS18_OC_SHIFT               12
#define PMIC_RG_INT_STATUS_VUSB33_OC_ADDR                MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VUSB33_OC_MASK                0x1
#define PMIC_RG_INT_STATUS_VUSB33_OC_SHIFT               13
#define PMIC_RG_INT_STATUS_VXO22_OC_ADDR                 MT6355_INT_STATUS4
#define PMIC_RG_INT_STATUS_VXO22_OC_MASK                 0x1
#define PMIC_RG_INT_STATUS_VXO22_OC_SHIFT                14
#define PMIC_RG_INT_STATUS_FG_BAT0_H_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_BAT0_H_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_BAT0_H_SHIFT               0
#define PMIC_RG_INT_STATUS_FG_BAT0_L_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_BAT0_L_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_BAT0_L_SHIFT               1
#define PMIC_RG_INT_STATUS_FG_CUR_H_ADDR                 MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_CUR_H_MASK                 0x1
#define PMIC_RG_INT_STATUS_FG_CUR_H_SHIFT                2
#define PMIC_RG_INT_STATUS_FG_CUR_L_ADDR                 MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_CUR_L_MASK                 0x1
#define PMIC_RG_INT_STATUS_FG_CUR_L_SHIFT                3
#define PMIC_RG_INT_STATUS_FG_ZCV_ADDR                   MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_ZCV_MASK                   0x1
#define PMIC_RG_INT_STATUS_FG_ZCV_SHIFT                  4
#define PMIC_RG_INT_STATUS_FG_BAT1_H_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_BAT1_H_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_BAT1_H_SHIFT               5
#define PMIC_RG_INT_STATUS_FG_BAT1_L_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_BAT1_L_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_BAT1_L_SHIFT               6
#define PMIC_RG_INT_STATUS_FG_N_CHARGE_L_ADDR            MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_N_CHARGE_L_MASK            0x1
#define PMIC_RG_INT_STATUS_FG_N_CHARGE_L_SHIFT           7
#define PMIC_RG_INT_STATUS_FG_IAVG_H_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_IAVG_H_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_IAVG_H_SHIFT               8
#define PMIC_RG_INT_STATUS_FG_IAVG_L_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_IAVG_L_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_IAVG_L_SHIFT               9
#define PMIC_RG_INT_STATUS_FG_TIME_H_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_TIME_H_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_TIME_H_SHIFT               10
#define PMIC_RG_INT_STATUS_FG_DISCHARGE_ADDR             MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_DISCHARGE_MASK             0x1
#define PMIC_RG_INT_STATUS_FG_DISCHARGE_SHIFT            11
#define PMIC_RG_INT_STATUS_FG_CHARGE_ADDR                MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_FG_CHARGE_MASK                0x1
#define PMIC_RG_INT_STATUS_FG_CHARGE_SHIFT               12
#define PMIC_RG_INT_STATUS_CON5_ADDR                     MT6355_INT_STATUS5
#define PMIC_RG_INT_STATUS_CON5_MASK                     0x7
#define PMIC_RG_INT_STATUS_CON5_SHIFT                    13
#define PMIC_RG_INT_STATUS_AUDIO_ADDR                    MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_AUDIO_MASK                    0x1
#define PMIC_RG_INT_STATUS_AUDIO_SHIFT                   0
#define PMIC_RG_INT_STATUS_MAD_ADDR                      MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_MAD_MASK                      0x1
#define PMIC_RG_INT_STATUS_MAD_SHIFT                     1
#define PMIC_RG_INT_STATUS_EINT_RTC32K_1V8_1_ADDR        MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_EINT_RTC32K_1V8_1_MASK        0x1
#define PMIC_RG_INT_STATUS_EINT_RTC32K_1V8_1_SHIFT       2
#define PMIC_RG_INT_STATUS_EINT_AUD_CLK_ADDR             MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_EINT_AUD_CLK_MASK             0x1
#define PMIC_RG_INT_STATUS_EINT_AUD_CLK_SHIFT            3
#define PMIC_RG_INT_STATUS_EINT_AUD_DAT_MOSI_ADDR        MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_EINT_AUD_DAT_MOSI_MASK        0x1
#define PMIC_RG_INT_STATUS_EINT_AUD_DAT_MOSI_SHIFT       4
#define PMIC_RG_INT_STATUS_EINT_AUD_DAT_MISO_ADDR        MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_EINT_AUD_DAT_MISO_MASK        0x1
#define PMIC_RG_INT_STATUS_EINT_AUD_DAT_MISO_SHIFT       5
#define PMIC_RG_INT_STATUS_EINT_VOW_CLK_MISO_ADDR        MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_EINT_VOW_CLK_MISO_MASK        0x1
#define PMIC_RG_INT_STATUS_EINT_VOW_CLK_MISO_SHIFT       6
#define PMIC_RG_INT_STATUS_ACCDET_ADDR                   MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_ACCDET_MASK                   0x1
#define PMIC_RG_INT_STATUS_ACCDET_SHIFT                  7
#define PMIC_RG_INT_STATUS_ACCDET_EINT_ADDR              MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_ACCDET_EINT_MASK              0x1
#define PMIC_RG_INT_STATUS_ACCDET_EINT_SHIFT             8
#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_ADDR            MT6355_INT_STATUS6
#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_MASK            0x1
#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_SHIFT           9
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_ADDR               MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_SHIFT              0
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_ADDR              MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_SHIFT             1
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_R_ADDR             MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_R_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_R_SHIFT            2
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_R_ADDR            MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_R_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_R_SHIFT           3
#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_ADDR          MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_MASK          0x1
#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_SHIFT         4
#define PMIC_RG_INT_RAW_STATUS_CHRDET_ADDR               MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_CHRDET_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_CHRDET_SHIFT              5
#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_ADDR          MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_MASK          0x1
#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_SHIFT         6
#define PMIC_RG_INT_RAW_STATUS_BATON_LV_ADDR             MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BATON_LV_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_LV_SHIFT            7
#define PMIC_RG_INT_RAW_STATUS_BATON_HV_ADDR             MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BATON_HV_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_HV_SHIFT            8
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN_ADDR         MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN_MASK         0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN_SHIFT        9
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT_ADDR        MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT_MASK        0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT_SHIFT       10
#define PMIC_RG_INT_RAW_STATUS_RTC_ADDR                  MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_RTC_MASK                  0x1
#define PMIC_RG_INT_RAW_STATUS_RTC_SHIFT                 11
#define PMIC_RG_INT_RAW_STATUS_RTC_NSEC_ADDR             MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_RTC_NSEC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_RTC_NSEC_SHIFT            12
#define PMIC_RG_INT_RAW_STATUS_BIF_ADDR                  MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BIF_MASK                  0x1
#define PMIC_RG_INT_RAW_STATUS_BIF_SHIFT                 13
#define PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET_ADDR          MT6355_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET_MASK          0x1
#define PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET_SHIFT         14
#define PMIC_RG_INT_RAW_STATUS_THR_H_ADDR                MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_THR_H_MASK                0x1
#define PMIC_RG_INT_RAW_STATUS_THR_H_SHIFT               0
#define PMIC_RG_INT_RAW_STATUS_THR_L_ADDR                MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_THR_L_MASK                0x1
#define PMIC_RG_INT_RAW_STATUS_THR_L_SHIFT               1
#define PMIC_RG_INT_RAW_STATUS_BAT_H_ADDR                MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BAT_H_MASK                0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_H_SHIFT               2
#define PMIC_RG_INT_RAW_STATUS_BAT_L_ADDR                MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BAT_L_MASK                0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_L_SHIFT               3
#define PMIC_RG_INT_RAW_STATUS_BAT2_H_ADDR               MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BAT2_H_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_BAT2_H_SHIFT              4
#define PMIC_RG_INT_RAW_STATUS_BAT2_L_ADDR               MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BAT2_L_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_BAT2_L_SHIFT              5
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_SHIFT          6
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_SHIFT          7
#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_SHIFT          8
#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_SHIFT          9
#define PMIC_RG_INT_RAW_STATUS_JEITA_HOT_ADDR            MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_JEITA_HOT_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_JEITA_HOT_SHIFT           10
#define PMIC_RG_INT_RAW_STATUS_JEITA_WARM_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_JEITA_WARM_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_JEITA_WARM_SHIFT          11
#define PMIC_RG_INT_RAW_STATUS_JEITA_COOL_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_JEITA_COOL_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_JEITA_COOL_SHIFT          12
#define PMIC_RG_INT_RAW_STATUS_JEITA_COLD_ADDR           MT6355_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_JEITA_COLD_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_JEITA_COLD_SHIFT          13
#define PMIC_RG_INT_RAW_STATUS_VPROC11_OC_ADDR           MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VPROC11_OC_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_VPROC11_OC_SHIFT          0
#define PMIC_RG_INT_RAW_STATUS_VPROC12_OC_ADDR           MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VPROC12_OC_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_VPROC12_OC_SHIFT          1
#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_ADDR             MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_SHIFT            2
#define PMIC_RG_INT_RAW_STATUS_VGPU_OC_ADDR              MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VGPU_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VGPU_OC_SHIFT             3
#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_ADDR            MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_SHIFT           4
#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_ADDR            MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_SHIFT           5
#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_ADDR            MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_SHIFT           6
#define PMIC_RG_INT_RAW_STATUS_VS1_OC_ADDR               MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VS1_OC_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_VS1_OC_SHIFT              7
#define PMIC_RG_INT_RAW_STATUS_VS2_OC_ADDR               MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VS2_OC_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_VS2_OC_SHIFT              8
#define PMIC_RG_INT_RAW_STATUS_VPA_OC_ADDR               MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VPA_OC_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_VPA_OC_SHIFT              9
#define PMIC_RG_INT_RAW_STATUS_VCORE_PREOC_ADDR          MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VCORE_PREOC_MASK          0x1
#define PMIC_RG_INT_RAW_STATUS_VCORE_PREOC_SHIFT         10
#define PMIC_RG_INT_RAW_STATUS_VA10_OC_ADDR              MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VA10_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VA10_OC_SHIFT             11
#define PMIC_RG_INT_RAW_STATUS_VA12_OC_ADDR              MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VA12_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VA12_OC_SHIFT             12
#define PMIC_RG_INT_RAW_STATUS_VA18_OC_ADDR              MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VA18_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VA18_OC_SHIFT             13
#define PMIC_RG_INT_RAW_STATUS_VBIF28_OC_ADDR            MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VBIF28_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VBIF28_OC_SHIFT           14
#define PMIC_RG_INT_RAW_STATUS_VCAMA1_OC_ADDR            MT6355_INT_RAW_STATUS2
#define PMIC_RG_INT_RAW_STATUS_VCAMA1_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMA1_OC_SHIFT           15
#define PMIC_RG_INT_RAW_STATUS_VCAMA2_OC_ADDR            MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCAMA2_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMA2_OC_SHIFT           0
#define PMIC_RG_INT_RAW_STATUS_VXO18_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VXO18_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VXO18_OC_SHIFT            1
#define PMIC_RG_INT_RAW_STATUS_VCAMD1_OC_ADDR            MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCAMD1_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMD1_OC_SHIFT           2
#define PMIC_RG_INT_RAW_STATUS_VCAMD2_OC_ADDR            MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCAMD2_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMD2_OC_SHIFT           3
#define PMIC_RG_INT_RAW_STATUS_VCAMIO_OC_ADDR            MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCAMIO_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMIO_OC_SHIFT           4
#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_SHIFT            5
#define PMIC_RG_INT_RAW_STATUS_VCN28_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCN28_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VCN28_OC_SHIFT            6
#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_SHIFT            7
#define PMIC_RG_INT_RAW_STATUS_VTCXO24_OC_ADDR           MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VTCXO24_OC_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_VTCXO24_OC_SHIFT          8
#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_ADDR              MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_SHIFT             9
#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_SHIFT            10
#define PMIC_RG_INT_RAW_STATUS_VGP_OC_ADDR               MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VGP_OC_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_VGP_OC_SHIFT              11
#define PMIC_RG_INT_RAW_STATUS_VLDO28_OC_ADDR            MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VLDO28_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VLDO28_OC_SHIFT           12
#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_SHIFT            13
#define PMIC_RG_INT_RAW_STATUS_VIO28_OC_ADDR             MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VIO28_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VIO28_OC_SHIFT            14
#define PMIC_RG_INT_RAW_STATUS_VMC_OC_ADDR               MT6355_INT_RAW_STATUS3
#define PMIC_RG_INT_RAW_STATUS_VMC_OC_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_VMC_OC_SHIFT              15
#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_ADDR              MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_SHIFT             0
#define PMIC_RG_INT_RAW_STATUS_VMIPI_OC_ADDR             MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VMIPI_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VMIPI_OC_SHIFT            1
#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_ADDR             MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_SHIFT            2
#define PMIC_RG_INT_RAW_STATUS_VRF18_1_OC_ADDR           MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VRF18_1_OC_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_VRF18_1_OC_SHIFT          3
#define PMIC_RG_INT_RAW_STATUS_VRF18_2_OC_ADDR           MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VRF18_2_OC_MASK           0x1
#define PMIC_RG_INT_RAW_STATUS_VRF18_2_OC_SHIFT          4
#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_ADDR             MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_SHIFT            5
#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_ADDR             MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_SHIFT            6
#define PMIC_RG_INT_RAW_STATUS_VGP2_OC_ADDR              MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VGP2_OC_MASK              0x1
#define PMIC_RG_INT_RAW_STATUS_VGP2_OC_SHIFT             7
#define PMIC_RG_INT_RAW_STATUS_VSRAM_CORE_OC_ADDR        MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VSRAM_CORE_OC_MASK        0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_CORE_OC_SHIFT       8
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC_ADDR        MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC_MASK        0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC_SHIFT       9
#define PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC_ADDR         MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC_MASK         0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC_SHIFT        10
#define PMIC_RG_INT_RAW_STATUS_VSRAM_MD_OC_ADDR          MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VSRAM_MD_OC_MASK          0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_MD_OC_SHIFT         11
#define PMIC_RG_INT_RAW_STATUS_VUFS18_OC_ADDR            MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VUFS18_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VUFS18_OC_SHIFT           12
#define PMIC_RG_INT_RAW_STATUS_VUSB33_OC_ADDR            MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VUSB33_OC_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_VUSB33_OC_SHIFT           13
#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_ADDR             MT6355_INT_RAW_STATUS4
#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_SHIFT            14
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_H_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_H_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_H_SHIFT           0
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_L_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_L_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_L_SHIFT           1
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_H_ADDR             MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_H_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_H_SHIFT            2
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_L_ADDR             MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_L_MASK             0x1
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_L_SHIFT            3
#define PMIC_RG_INT_RAW_STATUS_FG_ZCV_ADDR               MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_ZCV_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_FG_ZCV_SHIFT              4
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_H_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_H_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_H_SHIFT           5
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_L_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_L_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_L_SHIFT           6
#define PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L_ADDR        MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L_MASK        0x1
#define PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L_SHIFT       7
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_H_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_H_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_H_SHIFT           8
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_L_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_L_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_L_SHIFT           9
#define PMIC_RG_INT_RAW_STATUS_FG_TIME_H_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_TIME_H_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_TIME_H_SHIFT           10
#define PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE_ADDR         MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE_MASK         0x1
#define PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE_SHIFT        11
#define PMIC_RG_INT_RAW_STATUS_FG_CHARGE_ADDR            MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_FG_CHARGE_MASK            0x1
#define PMIC_RG_INT_RAW_STATUS_FG_CHARGE_SHIFT           12
#define PMIC_RG_INT_RAW_STATUS_CON5_ADDR                 MT6355_INT_RAW_STATUS5
#define PMIC_RG_INT_RAW_STATUS_CON5_MASK                 0x7
#define PMIC_RG_INT_RAW_STATUS_CON5_SHIFT                13
#define PMIC_RG_INT_RAW_STATUS_AUDIO_ADDR                MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_AUDIO_MASK                0x1
#define PMIC_RG_INT_RAW_STATUS_AUDIO_SHIFT               0
#define PMIC_RG_INT_RAW_STATUS_MAD_ADDR                  MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_MAD_MASK                  0x1
#define PMIC_RG_INT_RAW_STATUS_MAD_SHIFT                 1
#define PMIC_RG_INT_RAW_STATUS_EINT_RTC32K_1V8_1_ADDR    MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_EINT_RTC32K_1V8_1_MASK    0x1
#define PMIC_RG_INT_RAW_STATUS_EINT_RTC32K_1V8_1_SHIFT   2
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_CLK_ADDR         MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_CLK_MASK         0x1
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_CLK_SHIFT        3
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MOSI_ADDR    MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MOSI_MASK    0x1
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MOSI_SHIFT   4
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MISO_ADDR    MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MISO_MASK    0x1
#define PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MISO_SHIFT   5
#define PMIC_RG_INT_RAW_STATUS_EINT_VOW_CLK_MISO_ADDR    MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_EINT_VOW_CLK_MISO_MASK    0x1
#define PMIC_RG_INT_RAW_STATUS_EINT_VOW_CLK_MISO_SHIFT   6
#define PMIC_RG_INT_RAW_STATUS_ACCDET_ADDR               MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_ACCDET_MASK               0x1
#define PMIC_RG_INT_RAW_STATUS_ACCDET_SHIFT              7
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT_ADDR          MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT_MASK          0x1
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT_SHIFT         8
#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_ADDR        MT6355_INT_RAW_STATUS6
#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_MASK        0x1
#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_SHIFT       9
#define PMIC_POLARITY_ADDR                               MT6355_INT_MISC_CON
#define PMIC_POLARITY_MASK                               0x1
#define PMIC_POLARITY_SHIFT                              0
#define PMIC_RG_HOMEKEY_INT_SEL_ADDR                     MT6355_INT_MISC_CON
#define PMIC_RG_HOMEKEY_INT_SEL_MASK                     0x1
#define PMIC_RG_HOMEKEY_INT_SEL_SHIFT                    1
#define PMIC_RG_PWRKEY_INT_SEL_ADDR                      MT6355_INT_MISC_CON
#define PMIC_RG_PWRKEY_INT_SEL_MASK                      0x1
#define PMIC_RG_PWRKEY_INT_SEL_SHIFT                     2
#define PMIC_RG_CHRDET_INT_SEL_ADDR                      MT6355_INT_MISC_CON
#define PMIC_RG_CHRDET_INT_SEL_MASK                      0x1
#define PMIC_RG_CHRDET_INT_SEL_SHIFT                     3
#define PMIC_RG_PCHR_CM_VINC_POLARITY_RSV_ADDR           MT6355_INT_MISC_CON
#define PMIC_RG_PCHR_CM_VINC_POLARITY_RSV_MASK           0x1
#define PMIC_RG_PCHR_CM_VINC_POLARITY_RSV_SHIFT          4
#define PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV_ADDR           MT6355_INT_MISC_CON
#define PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV_MASK           0x1
#define PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV_SHIFT          5
#define PMIC_INT_MISC_CON_SET_ADDR                       MT6355_INT_MISC_CON_SET
#define PMIC_INT_MISC_CON_SET_MASK                       0xFFFF
#define PMIC_INT_MISC_CON_SET_SHIFT                      0
#define PMIC_INT_MISC_CON_CLR_ADDR                       MT6355_INT_MISC_CON_CLR
#define PMIC_INT_MISC_CON_CLR_MASK                       0xFFFF
#define PMIC_INT_MISC_CON_CLR_SHIFT                      0
#define PMIC_RG_INT_SEN_EINT_RTC32K_1V8_1_ADDR           MT6355_INT_EINT_CON0
#define PMIC_RG_INT_SEN_EINT_RTC32K_1V8_1_MASK           0x1
#define PMIC_RG_INT_SEN_EINT_RTC32K_1V8_1_SHIFT          0
#define PMIC_RG_INT_SEN_EINT_AUD_CLK_ADDR                MT6355_INT_EINT_CON0
#define PMIC_RG_INT_SEN_EINT_AUD_CLK_MASK                0x1
#define PMIC_RG_INT_SEN_EINT_AUD_CLK_SHIFT               1
#define PMIC_RG_INT_SEN_EINT_AUD_DAT_MOSI_ADDR           MT6355_INT_EINT_CON0
#define PMIC_RG_INT_SEN_EINT_AUD_DAT_MOSI_MASK           0x1
#define PMIC_RG_INT_SEN_EINT_AUD_DAT_MOSI_SHIFT          2
#define PMIC_RG_INT_SEN_EINT_AUD_DAT_MISO_ADDR           MT6355_INT_EINT_CON0
#define PMIC_RG_INT_SEN_EINT_AUD_DAT_MISO_MASK           0x1
#define PMIC_RG_INT_SEN_EINT_AUD_DAT_MISO_SHIFT          3
#define PMIC_RG_INT_SEN_EINT_VOW_CLK_MISO_ADDR           MT6355_INT_EINT_CON0
#define PMIC_RG_INT_SEN_EINT_VOW_CLK_MISO_MASK           0x1
#define PMIC_RG_INT_SEN_EINT_VOW_CLK_MISO_SHIFT          4
#define PMIC_INT_EINT_CON0_SET_ADDR                      MT6355_INT_EINT_CON0_SET
#define PMIC_INT_EINT_CON0_SET_MASK                      0xFFFF
#define PMIC_INT_EINT_CON0_SET_SHIFT                     0
#define PMIC_INT_EINT_CON0_CLR_ADDR                      MT6355_INT_EINT_CON0_CLR
#define PMIC_INT_EINT_CON0_CLR_MASK                      0xFFFF
#define PMIC_INT_EINT_CON0_CLR_SHIFT                     0
#define PMIC_RG_INT_POL_EINT_RTC32K_1V8_1_ADDR           MT6355_INT_EINT_CON1
#define PMIC_RG_INT_POL_EINT_RTC32K_1V8_1_MASK           0x1
#define PMIC_RG_INT_POL_EINT_RTC32K_1V8_1_SHIFT          0
#define PMIC_RG_INT_POL_EINT_AUD_CLK_ADDR                MT6355_INT_EINT_CON1
#define PMIC_RG_INT_POL_EINT_AUD_CLK_MASK                0x1
#define PMIC_RG_INT_POL_EINT_AUD_CLK_SHIFT               1
#define PMIC_RG_INT_POL_EINT_AUD_DAT_MOSI_ADDR           MT6355_INT_EINT_CON1
#define PMIC_RG_INT_POL_EINT_AUD_DAT_MOSI_MASK           0x1
#define PMIC_RG_INT_POL_EINT_AUD_DAT_MOSI_SHIFT          2
#define PMIC_RG_INT_POL_EINT_AUD_DAT_MISO_ADDR           MT6355_INT_EINT_CON1
#define PMIC_RG_INT_POL_EINT_AUD_DAT_MISO_MASK           0x1
#define PMIC_RG_INT_POL_EINT_AUD_DAT_MISO_SHIFT          3
#define PMIC_RG_INT_POL_EINT_VOW_CLK_MISO_ADDR           MT6355_INT_EINT_CON1
#define PMIC_RG_INT_POL_EINT_VOW_CLK_MISO_MASK           0x1
#define PMIC_RG_INT_POL_EINT_VOW_CLK_MISO_SHIFT          4
#define PMIC_INT_EINT_CON1_SET_ADDR                      MT6355_INT_EINT_CON1_SET
#define PMIC_INT_EINT_CON1_SET_MASK                      0xFFFF
#define PMIC_INT_EINT_CON1_SET_SHIFT                     0
#define PMIC_INT_EINT_CON1_CLR_ADDR                      MT6355_INT_EINT_CON1_CLR
#define PMIC_INT_EINT_CON1_CLR_MASK                      0xFFFF
#define PMIC_INT_EINT_CON1_CLR_SHIFT                     0
#define PMIC_RG_SW_SEL_EINT_RTC32K_1V8_1_ADDR            MT6355_INT_EINT_CON2
#define PMIC_RG_SW_SEL_EINT_RTC32K_1V8_1_MASK            0x1
#define PMIC_RG_SW_SEL_EINT_RTC32K_1V8_1_SHIFT           0
#define PMIC_RG_SW_SEL_EINT_AUD_CLK_ADDR                 MT6355_INT_EINT_CON2
#define PMIC_RG_SW_SEL_EINT_AUD_CLK_MASK                 0x1
#define PMIC_RG_SW_SEL_EINT_AUD_CLK_SHIFT                1
#define PMIC_RG_SW_SEL_EINT_AUD_DAT_MOSI_ADDR            MT6355_INT_EINT_CON2
#define PMIC_RG_SW_SEL_EINT_AUD_DAT_MOSI_MASK            0x1
#define PMIC_RG_SW_SEL_EINT_AUD_DAT_MOSI_SHIFT           2
#define PMIC_RG_SW_SEL_EINT_AUD_DAT_MISO_ADDR            MT6355_INT_EINT_CON2
#define PMIC_RG_SW_SEL_EINT_AUD_DAT_MISO_MASK            0x1
#define PMIC_RG_SW_SEL_EINT_AUD_DAT_MISO_SHIFT           3
#define PMIC_RG_SW_SEL_EINT_VOW_CLK_MISO_ADDR            MT6355_INT_EINT_CON2
#define PMIC_RG_SW_SEL_EINT_VOW_CLK_MISO_MASK            0x1
#define PMIC_RG_SW_SEL_EINT_VOW_CLK_MISO_SHIFT           4
#define PMIC_INT_EINT_CON2_SET_ADDR                      MT6355_INT_EINT_CON2_SET
#define PMIC_INT_EINT_CON2_SET_MASK                      0xFFFF
#define PMIC_INT_EINT_CON2_SET_SHIFT                     0
#define PMIC_INT_EINT_CON2_CLR_ADDR                      MT6355_INT_EINT_CON2_CLR
#define PMIC_INT_EINT_CON2_CLR_MASK                      0xFFFF
#define PMIC_INT_EINT_CON2_CLR_SHIFT                     0
#define PMIC_RG_SW_EINT_RTC32K_1V8_1_ADDR                MT6355_INT_EINT_CON3
#define PMIC_RG_SW_EINT_RTC32K_1V8_1_MASK                0x1
#define PMIC_RG_SW_EINT_RTC32K_1V8_1_SHIFT               0
#define PMIC_RG_SW_EINT_AUD_CLK_ADDR                     MT6355_INT_EINT_CON3
#define PMIC_RG_SW_EINT_AUD_CLK_MASK                     0x1
#define PMIC_RG_SW_EINT_AUD_CLK_SHIFT                    1
#define PMIC_RG_SW_EINT_AUD_DAT_MOSI_ADDR                MT6355_INT_EINT_CON3
#define PMIC_RG_SW_EINT_AUD_DAT_MOSI_MASK                0x1
#define PMIC_RG_SW_EINT_AUD_DAT_MOSI_SHIFT               2
#define PMIC_RG_SW_EINT_AUD_DAT_MISO_ADDR                MT6355_INT_EINT_CON3
#define PMIC_RG_SW_EINT_AUD_DAT_MISO_MASK                0x1
#define PMIC_RG_SW_EINT_AUD_DAT_MISO_SHIFT               3
#define PMIC_RG_SW_EINT_VOW_CLK_MISO_ADDR                MT6355_INT_EINT_CON3
#define PMIC_RG_SW_EINT_VOW_CLK_MISO_MASK                0x1
#define PMIC_RG_SW_EINT_VOW_CLK_MISO_SHIFT               4
#define PMIC_INT_EINT_CON3_SET_ADDR                      MT6355_INT_EINT_CON3_SET
#define PMIC_INT_EINT_CON3_SET_MASK                      0xFFFF
#define PMIC_INT_EINT_CON3_SET_SHIFT                     0
#define PMIC_INT_EINT_CON3_CLR_ADDR                      MT6355_INT_EINT_CON3_CLR
#define PMIC_INT_EINT_CON3_CLR_MASK                      0xFFFF
#define PMIC_INT_EINT_CON3_CLR_SHIFT                     0
#define PMIC_RG_DEB_EINT_RTC32K_1V8_1_ADDR               MT6355_INT_EINT_CON4
#define PMIC_RG_DEB_EINT_RTC32K_1V8_1_MASK               0x3
#define PMIC_RG_DEB_EINT_RTC32K_1V8_1_SHIFT              0
#define PMIC_RG_DEB_EINT_AUD_CLK_ADDR                    MT6355_INT_EINT_CON4
#define PMIC_RG_DEB_EINT_AUD_CLK_MASK                    0x3
#define PMIC_RG_DEB_EINT_AUD_CLK_SHIFT                   2
#define PMIC_RG_DEB_EINT_AUD_DAT_MOSI_ADDR               MT6355_INT_EINT_CON4
#define PMIC_RG_DEB_EINT_AUD_DAT_MOSI_MASK               0x3
#define PMIC_RG_DEB_EINT_AUD_DAT_MOSI_SHIFT              4
#define PMIC_RG_DEB_EINT_AUD_DAT_MISO_ADDR               MT6355_INT_EINT_CON4
#define PMIC_RG_DEB_EINT_AUD_DAT_MISO_MASK               0x3
#define PMIC_RG_DEB_EINT_AUD_DAT_MISO_SHIFT              6
#define PMIC_RG_DEB_EINT_VOW_CLK_MISO_ADDR               MT6355_INT_EINT_CON4
#define PMIC_RG_DEB_EINT_VOW_CLK_MISO_MASK               0x3
#define PMIC_RG_DEB_EINT_VOW_CLK_MISO_SHIFT              8
#define PMIC_INT_EINT_CON4_SET_ADDR                      MT6355_INT_EINT_CON4_SET
#define PMIC_INT_EINT_CON4_SET_MASK                      0xFFFF
#define PMIC_INT_EINT_CON4_SET_SHIFT                     0
#define PMIC_INT_EINT_CON4_CLR_ADDR                      MT6355_INT_EINT_CON4_CLR
#define PMIC_INT_EINT_CON4_CLR_MASK                      0xFFFF
#define PMIC_INT_EINT_CON4_CLR_SHIFT                     0
#define PMIC_FQMTR_TCKSEL_ADDR                           MT6355_FQMTR_CON0
#define PMIC_FQMTR_TCKSEL_MASK                           0x7
#define PMIC_FQMTR_TCKSEL_SHIFT                          0
#define PMIC_FQMTR_BUSY_ADDR                             MT6355_FQMTR_CON0
#define PMIC_FQMTR_BUSY_MASK                             0x1
#define PMIC_FQMTR_BUSY_SHIFT                            3
#define PMIC_FQMTR_DCXO26M_EN_ADDR                       MT6355_FQMTR_CON0
#define PMIC_FQMTR_DCXO26M_EN_MASK                       0x1
#define PMIC_FQMTR_DCXO26M_EN_SHIFT                      4
#define PMIC_FQMTR_EN_ADDR                               MT6355_FQMTR_CON0
#define PMIC_FQMTR_EN_MASK                               0x1
#define PMIC_FQMTR_EN_SHIFT                              15
#define PMIC_FQMTR_WINSET_ADDR                           MT6355_FQMTR_CON1
#define PMIC_FQMTR_WINSET_MASK                           0xFFFF
#define PMIC_FQMTR_WINSET_SHIFT                          0
#define PMIC_FQMTR_DATA_ADDR                             MT6355_FQMTR_CON2
#define PMIC_FQMTR_DATA_MASK                             0xFFFF
#define PMIC_FQMTR_DATA_SHIFT                            0
#define PMIC_RG_SLP_RW_EN_ADDR                           MT6355_RG_SPI_CON0
#define PMIC_RG_SLP_RW_EN_MASK                           0x1
#define PMIC_RG_SLP_RW_EN_SHIFT                          0
#define PMIC_RG_SPI_RSV_ADDR                             MT6355_RG_SPI_CON0
#define PMIC_RG_SPI_RSV_MASK                             0x7FFF
#define PMIC_RG_SPI_RSV_SHIFT                            1
#define PMIC_DEW_DIO_EN_ADDR                             MT6355_DEW_DIO_EN
#define PMIC_DEW_DIO_EN_MASK                             0x1
#define PMIC_DEW_DIO_EN_SHIFT                            0
#define PMIC_DEW_READ_TEST_ADDR                          MT6355_DEW_READ_TEST
#define PMIC_DEW_READ_TEST_MASK                          0xFFFF
#define PMIC_DEW_READ_TEST_SHIFT                         0
#define PMIC_DEW_WRITE_TEST_ADDR                         MT6355_DEW_WRITE_TEST
#define PMIC_DEW_WRITE_TEST_MASK                         0xFFFF
#define PMIC_DEW_WRITE_TEST_SHIFT                        0
#define PMIC_DEW_CRC_SWRST_ADDR                          MT6355_DEW_CRC_SWRST
#define PMIC_DEW_CRC_SWRST_MASK                          0x1
#define PMIC_DEW_CRC_SWRST_SHIFT                         0
#define PMIC_DEW_CRC_EN_ADDR                             MT6355_DEW_CRC_EN
#define PMIC_DEW_CRC_EN_MASK                             0x1
#define PMIC_DEW_CRC_EN_SHIFT                            0
#define PMIC_DEW_CRC_VAL_ADDR                            MT6355_DEW_CRC_VAL
#define PMIC_DEW_CRC_VAL_MASK                            0xFF
#define PMIC_DEW_CRC_VAL_SHIFT                           0
#define PMIC_DEW_DBG_MON_SEL_ADDR                        MT6355_DEW_DBG_MON_SEL
#define PMIC_DEW_DBG_MON_SEL_MASK                        0xF
#define PMIC_DEW_DBG_MON_SEL_SHIFT                       0
#define PMIC_DEW_CIPHER_KEY_SEL_ADDR                     MT6355_DEW_CIPHER_KEY_SEL
#define PMIC_DEW_CIPHER_KEY_SEL_MASK                     0x3
#define PMIC_DEW_CIPHER_KEY_SEL_SHIFT                    0
#define PMIC_DEW_CIPHER_IV_SEL_ADDR                      MT6355_DEW_CIPHER_IV_SEL
#define PMIC_DEW_CIPHER_IV_SEL_MASK                      0x3
#define PMIC_DEW_CIPHER_IV_SEL_SHIFT                     0
#define PMIC_DEW_CIPHER_EN_ADDR                          MT6355_DEW_CIPHER_EN
#define PMIC_DEW_CIPHER_EN_MASK                          0x1
#define PMIC_DEW_CIPHER_EN_SHIFT                         0
#define PMIC_DEW_CIPHER_RDY_ADDR                         MT6355_DEW_CIPHER_RDY
#define PMIC_DEW_CIPHER_RDY_MASK                         0x1
#define PMIC_DEW_CIPHER_RDY_SHIFT                        0
#define PMIC_DEW_CIPHER_MODE_ADDR                        MT6355_DEW_CIPHER_MODE
#define PMIC_DEW_CIPHER_MODE_MASK                        0x1
#define PMIC_DEW_CIPHER_MODE_SHIFT                       0
#define PMIC_DEW_CIPHER_SWRST_ADDR                       MT6355_DEW_CIPHER_SWRST
#define PMIC_DEW_CIPHER_SWRST_MASK                       0x1
#define PMIC_DEW_CIPHER_SWRST_SHIFT                      0
#define PMIC_DEW_RDDMY_NO_ADDR                           MT6355_DEW_RDDMY_NO
#define PMIC_DEW_RDDMY_NO_MASK                           0xF
#define PMIC_DEW_RDDMY_NO_SHIFT                          0
#define PMIC_INT_TYPE_CON0_ADDR                          MT6355_INT_TYPE_CON0
#define PMIC_INT_TYPE_CON0_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON0_SHIFT                         0
#define PMIC_INT_TYPE_CON0_SET_ADDR                      MT6355_INT_TYPE_CON0_SET
#define PMIC_INT_TYPE_CON0_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON0_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON0_CLR_ADDR                      MT6355_INT_TYPE_CON0_CLR
#define PMIC_INT_TYPE_CON0_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON0_CLR_SHIFT                     0
#define PMIC_INT_TYPE_CON1_ADDR                          MT6355_INT_TYPE_CON1
#define PMIC_INT_TYPE_CON1_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON1_SHIFT                         0
#define PMIC_INT_TYPE_CON1_SET_ADDR                      MT6355_INT_TYPE_CON1_SET
#define PMIC_INT_TYPE_CON1_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON1_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON1_CLR_ADDR                      MT6355_INT_TYPE_CON1_CLR
#define PMIC_INT_TYPE_CON1_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON1_CLR_SHIFT                     0
#define PMIC_INT_TYPE_CON2_ADDR                          MT6355_INT_TYPE_CON2
#define PMIC_INT_TYPE_CON2_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON2_SHIFT                         0
#define PMIC_INT_TYPE_CON2_SET_ADDR                      MT6355_INT_TYPE_CON2_SET
#define PMIC_INT_TYPE_CON2_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON2_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON2_CLR_ADDR                      MT6355_INT_TYPE_CON2_CLR
#define PMIC_INT_TYPE_CON2_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON2_CLR_SHIFT                     0
#define PMIC_INT_TYPE_CON3_ADDR                          MT6355_INT_TYPE_CON3
#define PMIC_INT_TYPE_CON3_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON3_SHIFT                         0
#define PMIC_INT_TYPE_CON3_SET_ADDR                      MT6355_INT_TYPE_CON3_SET
#define PMIC_INT_TYPE_CON3_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON3_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON3_CLR_ADDR                      MT6355_INT_TYPE_CON3_CLR
#define PMIC_INT_TYPE_CON3_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON3_CLR_SHIFT                     0
#define PMIC_INT_TYPE_CON4_ADDR                          MT6355_INT_TYPE_CON4
#define PMIC_INT_TYPE_CON4_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON4_SHIFT                         0
#define PMIC_INT_TYPE_CON4_SET_ADDR                      MT6355_INT_TYPE_CON4_SET
#define PMIC_INT_TYPE_CON4_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON4_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON4_CLR_ADDR                      MT6355_INT_TYPE_CON4_CLR
#define PMIC_INT_TYPE_CON4_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON4_CLR_SHIFT                     0
#define PMIC_INT_TYPE_CON5_ADDR                          MT6355_INT_TYPE_CON5
#define PMIC_INT_TYPE_CON5_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON5_SHIFT                         0
#define PMIC_INT_TYPE_CON5_SET_ADDR                      MT6355_INT_TYPE_CON5_SET
#define PMIC_INT_TYPE_CON5_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON5_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON5_CLR_ADDR                      MT6355_INT_TYPE_CON5_CLR
#define PMIC_INT_TYPE_CON5_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON5_CLR_SHIFT                     0
#define PMIC_INT_TYPE_CON6_ADDR                          MT6355_INT_TYPE_CON6
#define PMIC_INT_TYPE_CON6_MASK                          0xFFFF
#define PMIC_INT_TYPE_CON6_SHIFT                         0
#define PMIC_INT_TYPE_CON6_SET_ADDR                      MT6355_INT_TYPE_CON6_SET
#define PMIC_INT_TYPE_CON6_SET_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON6_SET_SHIFT                     0
#define PMIC_INT_TYPE_CON6_CLR_ADDR                      MT6355_INT_TYPE_CON6_CLR
#define PMIC_INT_TYPE_CON6_CLR_MASK                      0xFFFF
#define PMIC_INT_TYPE_CON6_CLR_SHIFT                     0
#define PMIC_CPU_INT_STA_ADDR                            MT6355_INT_STA
#define PMIC_CPU_INT_STA_MASK                            0x1
#define PMIC_CPU_INT_STA_SHIFT                           0
#define PMIC_MD32_INT_STA_ADDR                           MT6355_INT_STA
#define PMIC_MD32_INT_STA_MASK                           0x1
#define PMIC_MD32_INT_STA_SHIFT                          1
#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_ADDR           MT6355_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_MASK           0x1
#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_SHIFT          0
#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_ADDR            MT6355_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_MASK            0x1
#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_SHIFT           1
#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_ADDR           MT6355_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_MASK           0x1
#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_SHIFT          2
#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_ADDR            MT6355_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_MASK            0x1
#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_SHIFT           3
#define PMIC_RG_SPI_DLY_SEL_ADDR                         MT6355_RG_SPI_CON2
#define PMIC_RG_SPI_DLY_SEL_MASK                         0xF
#define PMIC_RG_SPI_DLY_SEL_SHIFT                        0
#define PMIC_RECORD_CMD0_ADDR                            MT6355_RG_SPI_CON3
#define PMIC_RECORD_CMD0_MASK                            0xFFFF
#define PMIC_RECORD_CMD0_SHIFT                           0
#define PMIC_RECORD_CMD1_ADDR                            MT6355_RG_SPI_CON4
#define PMIC_RECORD_CMD1_MASK                            0xFFFF
#define PMIC_RECORD_CMD1_SHIFT                           0
#define PMIC_RECORD_CMD2_ADDR                            MT6355_RG_SPI_CON5
#define PMIC_RECORD_CMD2_MASK                            0xFFFF
#define PMIC_RECORD_CMD2_SHIFT                           0
#define PMIC_RECORD_WDATA0_ADDR                          MT6355_RG_SPI_CON6
#define PMIC_RECORD_WDATA0_MASK                          0xFFFF
#define PMIC_RECORD_WDATA0_SHIFT                         0
#define PMIC_RECORD_WDATA1_ADDR                          MT6355_RG_SPI_CON7
#define PMIC_RECORD_WDATA1_MASK                          0xFFFF
#define PMIC_RECORD_WDATA1_SHIFT                         0
#define PMIC_RECORD_WDATA2_ADDR                          MT6355_RG_SPI_CON8
#define PMIC_RECORD_WDATA2_MASK                          0xFFFF
#define PMIC_RECORD_WDATA2_SHIFT                         0
#define PMIC_RG_ADDR_TARGET_ADDR                         MT6355_RG_SPI_CON9
#define PMIC_RG_ADDR_TARGET_MASK                         0xFFFF
#define PMIC_RG_ADDR_TARGET_SHIFT                        0
#define PMIC_RG_ADDR_MASK_ADDR                           MT6355_RG_SPI_CON10
#define PMIC_RG_ADDR_MASK_MASK                           0xFFFF
#define PMIC_RG_ADDR_MASK_SHIFT                          0
#define PMIC_RG_WDATA_TARGET_ADDR                        MT6355_RG_SPI_CON11
#define PMIC_RG_WDATA_TARGET_MASK                        0xFFFF
#define PMIC_RG_WDATA_TARGET_SHIFT                       0
#define PMIC_RG_WDATA_MASK_ADDR                          MT6355_RG_SPI_CON12
#define PMIC_RG_WDATA_MASK_MASK                          0xFFFF
#define PMIC_RG_WDATA_MASK_SHIFT                         0
#define PMIC_RG_SPI_RECORD_CLR_ADDR                      MT6355_RG_SPI_CON13
#define PMIC_RG_SPI_RECORD_CLR_MASK                      0x1
#define PMIC_RG_SPI_RECORD_CLR_SHIFT                     0
#define PMIC_RG_CMD_ALERT_CLR_ADDR                       MT6355_RG_SPI_CON13
#define PMIC_RG_CMD_ALERT_CLR_MASK                       0x1
#define PMIC_RG_CMD_ALERT_CLR_SHIFT                      15
#define PMIC_RG_THR_DET_DIS_ADDR                         MT6355_STRUP_CON0
#define PMIC_RG_THR_DET_DIS_MASK                         0x1
#define PMIC_RG_THR_DET_DIS_SHIFT                        12
#define PMIC_RG_THR_TEST_ADDR                            MT6355_STRUP_CON0
#define PMIC_RG_THR_TEST_MASK                            0x3
#define PMIC_RG_THR_TEST_SHIFT                           13
#define PMIC_RG_STRUP_THER_DEB_RMAX_ADDR                 MT6355_STRUP_CON1
#define PMIC_RG_STRUP_THER_DEB_RMAX_MASK                 0xFFFF
#define PMIC_RG_STRUP_THER_DEB_RMAX_SHIFT                0
#define PMIC_RG_STRUP_THER_DEB_FMAX_ADDR                 MT6355_STRUP_CON2
#define PMIC_RG_STRUP_THER_DEB_FMAX_MASK                 0xFFFF
#define PMIC_RG_STRUP_THER_DEB_FMAX_SHIFT                0
#define PMIC_DDUVLO_DEB_EN_ADDR                          MT6355_STRUP_CON3
#define PMIC_DDUVLO_DEB_EN_MASK                          0x1
#define PMIC_DDUVLO_DEB_EN_SHIFT                         0
#define PMIC_RG_STRUP_OSC_EN_ADDR                        MT6355_STRUP_CON3
#define PMIC_RG_STRUP_OSC_EN_MASK                        0x1
#define PMIC_RG_STRUP_OSC_EN_SHIFT                       2
#define PMIC_RG_STRUP_OSC_EN_SEL_ADDR                    MT6355_STRUP_CON3
#define PMIC_RG_STRUP_OSC_EN_SEL_MASK                    0x1
#define PMIC_RG_STRUP_OSC_EN_SEL_SHIFT                   3
#define PMIC_RG_STRUP_FT_CTRL_ADDR                       MT6355_STRUP_CON3
#define PMIC_RG_STRUP_FT_CTRL_MASK                       0x3
#define PMIC_RG_STRUP_FT_CTRL_SHIFT                      4
#define PMIC_RG_STRUP_PWRON_FORCE_ADDR                   MT6355_STRUP_CON3
#define PMIC_RG_STRUP_PWRON_FORCE_MASK                   0x1
#define PMIC_RG_STRUP_PWRON_FORCE_SHIFT                  6
#define PMIC_RG_BIASGEN_FORCE_ADDR                       MT6355_STRUP_CON3
#define PMIC_RG_BIASGEN_FORCE_MASK                       0x1
#define PMIC_RG_BIASGEN_FORCE_SHIFT                      7
#define PMIC_RG_STRUP_PWRON_ADDR                         MT6355_STRUP_CON3
#define PMIC_RG_STRUP_PWRON_MASK                         0x1
#define PMIC_RG_STRUP_PWRON_SHIFT                        8
#define PMIC_RG_STRUP_PWRON_SEL_ADDR                     MT6355_STRUP_CON3
#define PMIC_RG_STRUP_PWRON_SEL_MASK                     0x1
#define PMIC_RG_STRUP_PWRON_SEL_SHIFT                    9
#define PMIC_RG_BIASGEN_ADDR                             MT6355_STRUP_CON3
#define PMIC_RG_BIASGEN_MASK                             0x1
#define PMIC_RG_BIASGEN_SHIFT                            10
#define PMIC_RG_BIASGEN_SEL_ADDR                         MT6355_STRUP_CON3
#define PMIC_RG_BIASGEN_SEL_MASK                         0x1
#define PMIC_RG_BIASGEN_SEL_SHIFT                        11
#define PMIC_RG_RTC_XOSC32_ENB_ADDR                      MT6355_STRUP_CON3
#define PMIC_RG_RTC_XOSC32_ENB_MASK                      0x1
#define PMIC_RG_RTC_XOSC32_ENB_SHIFT                     12
#define PMIC_RG_RTC_XOSC32_ENB_SEL_ADDR                  MT6355_STRUP_CON3
#define PMIC_RG_RTC_XOSC32_ENB_SEL_MASK                  0x1
#define PMIC_RG_RTC_XOSC32_ENB_SEL_SHIFT                 13
#define PMIC_STRUP_DIG_IO_PG_FORCE_ADDR                  MT6355_STRUP_CON3
#define PMIC_STRUP_DIG_IO_PG_FORCE_MASK                  0x1
#define PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT                 15
#define PMIC_RG_CLR_JUST_SMART_RST_ADDR                  MT6355_STRUP_CON4
#define PMIC_RG_CLR_JUST_SMART_RST_MASK                  0x1
#define PMIC_RG_CLR_JUST_SMART_RST_SHIFT                 3
#define PMIC_CLR_JUST_RST_ADDR                           MT6355_STRUP_CON4
#define PMIC_CLR_JUST_RST_MASK                           0x1
#define PMIC_CLR_JUST_RST_SHIFT                          4
#define PMIC_UVLO_L2H_DEB_EN_ADDR                        MT6355_STRUP_CON4
#define PMIC_UVLO_L2H_DEB_EN_MASK                        0x1
#define PMIC_UVLO_L2H_DEB_EN_SHIFT                       5
#define PMIC_JUST_SMART_RST_ADDR                         MT6355_STRUP_CON4
#define PMIC_JUST_SMART_RST_MASK                         0x1
#define PMIC_JUST_SMART_RST_SHIFT                        13
#define PMIC_JUST_PWRKEY_RST_ADDR                        MT6355_STRUP_CON4
#define PMIC_JUST_PWRKEY_RST_MASK                        0x1
#define PMIC_JUST_PWRKEY_RST_SHIFT                       14
#define PMIC_DA_QI_OSC_EN_ADDR                           MT6355_STRUP_CON4
#define PMIC_DA_QI_OSC_EN_MASK                           0x1
#define PMIC_DA_QI_OSC_EN_SHIFT                          15
#define PMIC_RG_STRUP_EXT_PMIC_EN_ADDR                   MT6355_STRUP_CON5
#define PMIC_RG_STRUP_EXT_PMIC_EN_MASK                   0x1
#define PMIC_RG_STRUP_EXT_PMIC_EN_SHIFT                  0
#define PMIC_RG_STRUP_EXT_PMIC_SEL_ADDR                  MT6355_STRUP_CON5
#define PMIC_RG_STRUP_EXT_PMIC_SEL_MASK                  0x1
#define PMIC_RG_STRUP_EXT_PMIC_SEL_SHIFT                 1
#define PMIC_STRUP_CON8_RSV0_ADDR                        MT6355_STRUP_CON5
#define PMIC_STRUP_CON8_RSV0_MASK                        0x7F
#define PMIC_STRUP_CON8_RSV0_SHIFT                       8
#define PMIC_DA_QI_EXT_PMIC_EN_ADDR                      MT6355_STRUP_CON5
#define PMIC_DA_QI_EXT_PMIC_EN_MASK                      0x1
#define PMIC_DA_QI_EXT_PMIC_EN_SHIFT                     15
#define PMIC_RG_STRUP_AUXADC_START_SW_ADDR               MT6355_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_START_SW_MASK               0x1
#define PMIC_RG_STRUP_AUXADC_START_SW_SHIFT              0
#define PMIC_RG_STRUP_AUXADC_RSTB_SW_ADDR                MT6355_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_RSTB_SW_MASK                0x1
#define PMIC_RG_STRUP_AUXADC_RSTB_SW_SHIFT               1
#define PMIC_RG_STRUP_AUXADC_START_SEL_ADDR              MT6355_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_START_SEL_MASK              0x1
#define PMIC_RG_STRUP_AUXADC_START_SEL_SHIFT             2
#define PMIC_RG_STRUP_AUXADC_RSTB_SEL_ADDR               MT6355_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_RSTB_SEL_MASK               0x1
#define PMIC_RG_STRUP_AUXADC_RSTB_SEL_SHIFT              3
#define PMIC_RG_STRUP_AUXADC_RPCNT_MAX_ADDR              MT6355_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_RPCNT_MAX_MASK              0x7F
#define PMIC_RG_STRUP_AUXADC_RPCNT_MAX_SHIFT             4
#define PMIC_STRUP_PWROFF_SEQ_EN_ADDR                    MT6355_STRUP_CON7
#define PMIC_STRUP_PWROFF_SEQ_EN_MASK                    0x1
#define PMIC_STRUP_PWROFF_SEQ_EN_SHIFT                   0
#define PMIC_STRUP_PWROFF_PREOFF_EN_ADDR                 MT6355_STRUP_CON7
#define PMIC_STRUP_PWROFF_PREOFF_EN_MASK                 0x1
#define PMIC_STRUP_PWROFF_PREOFF_EN_SHIFT                1
#define PMIC_STRUP_DIG0_RSV0_ADDR                        MT6355_STRUP_CON8
#define PMIC_STRUP_DIG0_RSV0_MASK                        0xF
#define PMIC_STRUP_DIG0_RSV0_SHIFT                       2
#define PMIC_STRUP_DIG1_RSV0_ADDR                        MT6355_STRUP_CON8
#define PMIC_STRUP_DIG1_RSV0_MASK                        0x1F
#define PMIC_STRUP_DIG1_RSV0_SHIFT                       6
#define PMIC_RG_RSV_SWREG_ADDR                           MT6355_STRUP_CON9
#define PMIC_RG_RSV_SWREG_MASK                           0xFFFF
#define PMIC_RG_RSV_SWREG_SHIFT                          0
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_ADDR                 MT6355_STRUP_CON10
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_MASK                 0x1
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SHIFT                0
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_ADDR          MT6355_STRUP_CON10
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK          0x1
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT         1
#define PMIC_RG_STRUP_THR_CLR_ADDR                       MT6355_STRUP_CON11
#define PMIC_RG_STRUP_THR_CLR_MASK                       0x1
#define PMIC_RG_STRUP_THR_CLR_SHIFT                      0
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_ADDR            MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_MASK            0x3
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_SHIFT           0
#define PMIC_RG_STRUP_LONG_PRESS_EXT_TD_ADDR             MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_TD_MASK             0x3
#define PMIC_RG_STRUP_LONG_PRESS_EXT_TD_SHIFT            2
#define PMIC_RG_STRUP_LONG_PRESS_EXT_EN_ADDR             MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_EN_MASK             0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_EN_SHIFT            4
#define PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_ADDR       MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_MASK       0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_SHIFT      5
#define PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_ADDR    MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_MASK    0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_SHIFT   6
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL_ADDR      MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL_MASK      0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL_SHIFT     7
#define PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL_ADDR      MT6355_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL_MASK      0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL_SHIFT     8
#define PMIC_RG_SMART_RST_MODE_ADDR                      MT6355_STRUP_CON12
#define PMIC_RG_SMART_RST_MODE_MASK                      0x1
#define PMIC_RG_SMART_RST_MODE_SHIFT                     13
#define PMIC_RG_STRUP_ENVTEM_ADDR                        MT6355_STRUP_CON12
#define PMIC_RG_STRUP_ENVTEM_MASK                        0x1
#define PMIC_RG_STRUP_ENVTEM_SHIFT                       14
#define PMIC_RG_STRUP_ENVTEM_CTRL_ADDR                   MT6355_STRUP_CON12
#define PMIC_RG_STRUP_ENVTEM_CTRL_MASK                   0x1
#define PMIC_RG_STRUP_ENVTEM_CTRL_SHIFT                  15
#define PMIC_RG_STRUP_PWRKEY_COUNT_RESET_ADDR            MT6355_STRUP_CON13
#define PMIC_RG_STRUP_PWRKEY_COUNT_RESET_MASK            0x1
#define PMIC_RG_STRUP_PWRKEY_COUNT_RESET_SHIFT           0
#define PMIC_RG_STRUP_VA12_PG_H2L_EN_ADDR                MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VA12_PG_H2L_EN_MASK                0x1
#define PMIC_RG_STRUP_VA12_PG_H2L_EN_SHIFT               0
#define PMIC_RG_STRUP_VA10_PG_H2L_EN_ADDR                MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VA10_PG_H2L_EN_MASK                0x1
#define PMIC_RG_STRUP_VA10_PG_H2L_EN_SHIFT               1
#define PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN_ADDR           MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN_MASK           0x1
#define PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN_SHIFT          2
#define PMIC_RG_STRUP_VSRAM_MD_PG_H2L_EN_ADDR            MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_MD_PG_H2L_EN_MASK            0x1
#define PMIC_RG_STRUP_VSRAM_MD_PG_H2L_EN_SHIFT           3
#define PMIC_RG_STRUP_VSRAM_CORE_PG_H2L_EN_ADDR          MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_CORE_PG_H2L_EN_MASK          0x1
#define PMIC_RG_STRUP_VSRAM_CORE_PG_H2L_EN_SHIFT         4
#define PMIC_RG_STRUP_VA18_PG_H2L_EN_ADDR                MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VA18_PG_H2L_EN_MASK                0x1
#define PMIC_RG_STRUP_VA18_PG_H2L_EN_SHIFT               5
#define PMIC_RG_STRUP_BUCK_RSV_PG_H2L_EN_ADDR            MT6355_STRUP_CON14
#define PMIC_RG_STRUP_BUCK_RSV_PG_H2L_EN_MASK            0x1
#define PMIC_RG_STRUP_BUCK_RSV_PG_H2L_EN_SHIFT           6
#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_ADDR              MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_MASK              0x1
#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_SHIFT             7
#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_ADDR              MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_MASK              0x1
#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_SHIFT             8
#define PMIC_RG_STRUP_VPROC12_PG_H2L_EN_ADDR             MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VPROC12_PG_H2L_EN_MASK             0x1
#define PMIC_RG_STRUP_VPROC12_PG_H2L_EN_SHIFT            9
#define PMIC_RG_STRUP_VPROC11_PG_H2L_EN_ADDR             MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VPROC11_PG_H2L_EN_MASK             0x1
#define PMIC_RG_STRUP_VPROC11_PG_H2L_EN_SHIFT            10
#define PMIC_RG_STRUP_VS1_PG_H2L_EN_ADDR                 MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VS1_PG_H2L_EN_MASK                 0x1
#define PMIC_RG_STRUP_VS1_PG_H2L_EN_SHIFT                11
#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_ADDR              MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_MASK              0x1
#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_SHIFT             12
#define PMIC_RG_STRUP_VGPU_PG_H2L_EN_ADDR                MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VGPU_PG_H2L_EN_MASK                0x1
#define PMIC_RG_STRUP_VGPU_PG_H2L_EN_SHIFT               13
#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_ADDR               MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_MASK               0x1
#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_SHIFT              14
#define PMIC_RG_STRUP_VS2_PG_H2L_EN_ADDR                 MT6355_STRUP_CON14
#define PMIC_RG_STRUP_VS2_PG_H2L_EN_MASK                 0x1
#define PMIC_RG_STRUP_VS2_PG_H2L_EN_SHIFT                15
#define PMIC_RG_STRUP_EXT_PMIC_PG_H2L_EN_ADDR            MT6355_STRUP_CON15
#define PMIC_RG_STRUP_EXT_PMIC_PG_H2L_EN_MASK            0x1
#define PMIC_RG_STRUP_EXT_PMIC_PG_H2L_EN_SHIFT           11
#define PMIC_RG_STRUP_VUSB33_PG_H2L_EN_ADDR              MT6355_STRUP_CON15
#define PMIC_RG_STRUP_VUSB33_PG_H2L_EN_MASK              0x1
#define PMIC_RG_STRUP_VUSB33_PG_H2L_EN_SHIFT             12
#define PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_ADDR          MT6355_STRUP_CON15
#define PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_MASK          0x1
#define PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_SHIFT         13
#define PMIC_RG_STRUP_VUFS18_PG_H2L_EN_ADDR              MT6355_STRUP_CON15
#define PMIC_RG_STRUP_VUFS18_PG_H2L_EN_MASK              0x1
#define PMIC_RG_STRUP_VUFS18_PG_H2L_EN_SHIFT             14
#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_ADDR                MT6355_STRUP_CON15
#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_MASK                0x1
#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_SHIFT               15
#define PMIC_RG_STRUP_VA12_PG_ENB_ADDR                   MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VA12_PG_ENB_MASK                   0x1
#define PMIC_RG_STRUP_VA12_PG_ENB_SHIFT                  0
#define PMIC_RG_STRUP_VA10_PG_ENB_ADDR                   MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VA10_PG_ENB_MASK                   0x1
#define PMIC_RG_STRUP_VA10_PG_ENB_SHIFT                  1
#define PMIC_RG_STRUP_VSRAM_GPU_PG_ENB_ADDR              MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_GPU_PG_ENB_MASK              0x1
#define PMIC_RG_STRUP_VSRAM_GPU_PG_ENB_SHIFT             2
#define PMIC_RG_STRUP_VSRAM_MD_PG_ENB_ADDR               MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_MD_PG_ENB_MASK               0x1
#define PMIC_RG_STRUP_VSRAM_MD_PG_ENB_SHIFT              3
#define PMIC_RG_STRUP_VSRAM_CORE_PG_ENB_ADDR             MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_CORE_PG_ENB_MASK             0x1
#define PMIC_RG_STRUP_VSRAM_CORE_PG_ENB_SHIFT            4
#define PMIC_RG_STRUP_VA18_PG_ENB_ADDR                   MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VA18_PG_ENB_MASK                   0x1
#define PMIC_RG_STRUP_VA18_PG_ENB_SHIFT                  5
#define PMIC_RG_STRUP_BUCK_RSV_PG_ENB_ADDR               MT6355_STRUP_CON16
#define PMIC_RG_STRUP_BUCK_RSV_PG_ENB_MASK               0x1
#define PMIC_RG_STRUP_BUCK_RSV_PG_ENB_SHIFT              6
#define PMIC_RG_STRUP_VDRAM2_PG_ENB_ADDR                 MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VDRAM2_PG_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VDRAM2_PG_ENB_SHIFT                7
#define PMIC_RG_STRUP_VDRAM1_PG_ENB_ADDR                 MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VDRAM1_PG_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VDRAM1_PG_ENB_SHIFT                8
#define PMIC_RG_STRUP_VPROC12_PG_ENB_ADDR                MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VPROC12_PG_ENB_MASK                0x1
#define PMIC_RG_STRUP_VPROC12_PG_ENB_SHIFT               9
#define PMIC_RG_STRUP_VPROC11_PG_ENB_ADDR                MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VPROC11_PG_ENB_MASK                0x1
#define PMIC_RG_STRUP_VPROC11_PG_ENB_SHIFT               10
#define PMIC_RG_STRUP_VS1_PG_ENB_ADDR                    MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VS1_PG_ENB_MASK                    0x1
#define PMIC_RG_STRUP_VS1_PG_ENB_SHIFT                   11
#define PMIC_RG_STRUP_VMODEM_PG_ENB_ADDR                 MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VMODEM_PG_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VMODEM_PG_ENB_SHIFT                12
#define PMIC_RG_STRUP_VGPU_PG_ENB_ADDR                   MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VGPU_PG_ENB_MASK                   0x1
#define PMIC_RG_STRUP_VGPU_PG_ENB_SHIFT                  13
#define PMIC_RG_STRUP_VCORE_PG_ENB_ADDR                  MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VCORE_PG_ENB_MASK                  0x1
#define PMIC_RG_STRUP_VCORE_PG_ENB_SHIFT                 14
#define PMIC_RG_STRUP_VS2_PG_ENB_ADDR                    MT6355_STRUP_CON16
#define PMIC_RG_STRUP_VS2_PG_ENB_MASK                    0x1
#define PMIC_RG_STRUP_VS2_PG_ENB_SHIFT                   15
#define PMIC_RG_STRUP_EXT_PMIC_PG_ENB_ADDR               MT6355_STRUP_CON17
#define PMIC_RG_STRUP_EXT_PMIC_PG_ENB_MASK               0x1
#define PMIC_RG_STRUP_EXT_PMIC_PG_ENB_SHIFT              7
#define PMIC_RG_STRUP_VXO18_PG_ENB_ADDR                  MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VXO18_PG_ENB_MASK                  0x1
#define PMIC_RG_STRUP_VXO18_PG_ENB_SHIFT                 8
#define PMIC_RG_STRUP_VXO22_PG_ENB_ADDR                  MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VXO22_PG_ENB_MASK                  0x1
#define PMIC_RG_STRUP_VXO22_PG_ENB_SHIFT                 9
#define PMIC_RG_STRUP_VUSB33_PG_ENB_ADDR                 MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VUSB33_PG_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VUSB33_PG_ENB_SHIFT                10
#define PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_ADDR             MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_MASK             0x1
#define PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_SHIFT            11
#define PMIC_RG_STRUP_VIO28_PG_ENB_ADDR                  MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VIO28_PG_ENB_MASK                  0x1
#define PMIC_RG_STRUP_VIO28_PG_ENB_SHIFT                 12
#define PMIC_RG_STRUP_VUFS18_PG_ENB_ADDR                 MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VUFS18_PG_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VUFS18_PG_ENB_SHIFT                13
#define PMIC_RG_STRUP_VEMC_PG_ENB_ADDR                   MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VEMC_PG_ENB_MASK                   0x1
#define PMIC_RG_STRUP_VEMC_PG_ENB_SHIFT                  14
#define PMIC_RG_STRUP_VIO18_PG_ENB_ADDR                  MT6355_STRUP_CON17
#define PMIC_RG_STRUP_VIO18_PG_ENB_MASK                  0x1
#define PMIC_RG_STRUP_VIO18_PG_ENB_SHIFT                 15
#define PMIC_RG_STRUP_BUCK_RSV_OC_ENB_ADDR               MT6355_STRUP_CON18
#define PMIC_RG_STRUP_BUCK_RSV_OC_ENB_MASK               0x1
#define PMIC_RG_STRUP_BUCK_RSV_OC_ENB_SHIFT              6
#define PMIC_RG_STRUP_VDRAM2_OC_ENB_ADDR                 MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VDRAM2_OC_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VDRAM2_OC_ENB_SHIFT                7
#define PMIC_RG_STRUP_VDRAM1_OC_ENB_ADDR                 MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VDRAM1_OC_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VDRAM1_OC_ENB_SHIFT                8
#define PMIC_RG_STRUP_VPROC12_OC_ENB_ADDR                MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VPROC12_OC_ENB_MASK                0x1
#define PMIC_RG_STRUP_VPROC12_OC_ENB_SHIFT               9
#define PMIC_RG_STRUP_VPROC11_OC_ENB_ADDR                MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VPROC11_OC_ENB_MASK                0x1
#define PMIC_RG_STRUP_VPROC11_OC_ENB_SHIFT               10
#define PMIC_RG_STRUP_VS1_OC_ENB_ADDR                    MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VS1_OC_ENB_MASK                    0x1
#define PMIC_RG_STRUP_VS1_OC_ENB_SHIFT                   11
#define PMIC_RG_STRUP_VMODEM_OC_ENB_ADDR                 MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VMODEM_OC_ENB_MASK                 0x1
#define PMIC_RG_STRUP_VMODEM_OC_ENB_SHIFT                12
#define PMIC_RG_STRUP_VGPU_OC_ENB_ADDR                   MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VGPU_OC_ENB_MASK                   0x1
#define PMIC_RG_STRUP_VGPU_OC_ENB_SHIFT                  13
#define PMIC_RG_STRUP_VCORE_OC_ENB_ADDR                  MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VCORE_OC_ENB_MASK                  0x1
#define PMIC_RG_STRUP_VCORE_OC_ENB_SHIFT                 14
#define PMIC_RG_STRUP_VS2_OC_ENB_ADDR                    MT6355_STRUP_CON18
#define PMIC_RG_STRUP_VS2_OC_ENB_MASK                    0x1
#define PMIC_RG_STRUP_VS2_OC_ENB_SHIFT                   15
#define PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_ADDR       MT6355_STRUP_CON19
#define PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_MASK       0x1
#define PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_SHIFT      0
#define PMIC_RG_EXT_PMIC_PG_DEBTD_ADDR                   MT6355_STRUP_CON20
#define PMIC_RG_EXT_PMIC_PG_DEBTD_MASK                   0x1
#define PMIC_RG_EXT_PMIC_PG_DEBTD_SHIFT                  0
#define PMIC_RG_RTC_SPAR_DEB_EN_ADDR                     MT6355_STRUP_CON20
#define PMIC_RG_RTC_SPAR_DEB_EN_MASK                     0x1
#define PMIC_RG_RTC_SPAR_DEB_EN_SHIFT                    8
#define PMIC_RG_RTC_ALARM_DEB_EN_ADDR                    MT6355_STRUP_CON20
#define PMIC_RG_RTC_ALARM_DEB_EN_MASK                    0x1
#define PMIC_RG_RTC_ALARM_DEB_EN_SHIFT                   9
#define PMIC_RG_TM_OUT_ADDR                              MT6355_STRUP_ANA_CON0
#define PMIC_RG_TM_OUT_MASK                              0xF
#define PMIC_RG_TM_OUT_SHIFT                             0
#define PMIC_RG_THR_LOC_SEL_ADDR                         MT6355_STRUP_ANA_CON0
#define PMIC_RG_THR_LOC_SEL_MASK                         0xF
#define PMIC_RG_THR_LOC_SEL_SHIFT                        4
#define PMIC_RG_THRDET_SEL_ADDR                          MT6355_STRUP_ANA_CON0
#define PMIC_RG_THRDET_SEL_MASK                          0x1
#define PMIC_RG_THRDET_SEL_SHIFT                         8
#define PMIC_RG_STRUP_THR_SEL_ADDR                       MT6355_STRUP_ANA_CON0
#define PMIC_RG_STRUP_THR_SEL_MASK                       0x3
#define PMIC_RG_STRUP_THR_SEL_SHIFT                      9
#define PMIC_RG_THR_TMODE_ADDR                           MT6355_STRUP_ANA_CON0
#define PMIC_RG_THR_TMODE_MASK                           0x1
#define PMIC_RG_THR_TMODE_SHIFT                          11
#define PMIC_RG_VREF_BG_ADDR                             MT6355_STRUP_ANA_CON0
#define PMIC_RG_VREF_BG_MASK                             0x7
#define PMIC_RG_VREF_BG_SHIFT                            12
#define PMIC_RG_STRUP_IREF_TRIM_ADDR                     MT6355_STRUP_ANA_CON1
#define PMIC_RG_STRUP_IREF_TRIM_MASK                     0x3F
#define PMIC_RG_STRUP_IREF_TRIM_SHIFT                    0
#define PMIC_RG_RST_DRVSEL_ADDR                          MT6355_STRUP_ANA_CON1
#define PMIC_RG_RST_DRVSEL_MASK                          0x1
#define PMIC_RG_RST_DRVSEL_SHIFT                         6
#define PMIC_RG_EN_DRVSEL_ADDR                           MT6355_STRUP_ANA_CON1
#define PMIC_RG_EN_DRVSEL_MASK                           0x1
#define PMIC_RG_EN_DRVSEL_SHIFT                          7
#define PMIC_RG_PMU_RSV_ADDR                             MT6355_STRUP_ANA_CON1
#define PMIC_RG_PMU_RSV_MASK                             0xF
#define PMIC_RG_PMU_RSV_SHIFT                            8
#define PMIC_RGS_ANA_CHIP_ID_ADDR                        MT6355_STRUP_ANA_CON1
#define PMIC_RGS_ANA_CHIP_ID_MASK                        0x7
#define PMIC_RGS_ANA_CHIP_ID_SHIFT                       12
#define PMIC_RG_PWRHOLD_ADDR                             MT6355_PPCCTL0
#define PMIC_RG_PWRHOLD_MASK                             0x1
#define PMIC_RG_PWRHOLD_SHIFT                            0
#define PMIC_RG_USBDL_MODE_ADDR                          MT6355_PPCCTL0
#define PMIC_RG_USBDL_MODE_MASK                          0x1
#define PMIC_RG_USBDL_MODE_SHIFT                         4
#define PMIC_RG_CRST_ADDR                                MT6355_PPCCTL0
#define PMIC_RG_CRST_MASK                                0x1
#define PMIC_RG_CRST_SHIFT                               8
#define PMIC_RG_WRST_ADDR                                MT6355_PPCCTL0
#define PMIC_RG_WRST_MASK                                0x1
#define PMIC_RG_WRST_SHIFT                               9
#define PMIC_RG_RSTB_ONINTV_ADDR                         MT6355_PPCCTL1
#define PMIC_RG_RSTB_ONINTV_MASK                         0x3
#define PMIC_RG_RSTB_ONINTV_SHIFT                        0
#define PMIC_RG_CRST_INTV_ADDR                           MT6355_PPCCTL1
#define PMIC_RG_CRST_INTV_MASK                           0x3
#define PMIC_RG_CRST_INTV_SHIFT                          8
#define PMIC_RG_WRST_INTV_ADDR                           MT6355_PPCCTL1
#define PMIC_RG_WRST_INTV_MASK                           0x3
#define PMIC_RG_WRST_INTV_SHIFT                          10
#define PMIC_RG_PSEQ_IVGEN_SEL_ADDR                      MT6355_PPCCTL2
#define PMIC_RG_PSEQ_IVGEN_SEL_MASK                      0x1
#define PMIC_RG_PSEQ_IVGEN_SEL_SHIFT                     0
#define PMIC_RG_PSEQ_FSM_RST_SEL_ADDR                    MT6355_PPCCTL2
#define PMIC_RG_PSEQ_FSM_RST_SEL_MASK                    0x1
#define PMIC_RG_PSEQ_FSM_RST_SEL_SHIFT                   4
#define PMIC_RG_PSEQ_PG_CK_SEL_ADDR                      MT6355_PPCCTL2
#define PMIC_RG_PSEQ_PG_CK_SEL_MASK                      0x1
#define PMIC_RG_PSEQ_PG_CK_SEL_SHIFT                     8
#define PMIC_RG_PSEQ_1MS_TK_EXT_ADDR                     MT6355_PPCCTL2
#define PMIC_RG_PSEQ_1MS_TK_EXT_MASK                     0x1
#define PMIC_RG_PSEQ_1MS_TK_EXT_SHIFT                    12
#define PMIC_RG_PSEQ_SPAR_XCPT_MASK_ADDR                 MT6355_PPCCTL2
#define PMIC_RG_PSEQ_SPAR_XCPT_MASK_MASK                 0x1
#define PMIC_RG_PSEQ_SPAR_XCPT_MASK_SHIFT                13
#define PMIC_RG_PSEQ_RTCA_XCPT_MASK_ADDR                 MT6355_PPCCTL2
#define PMIC_RG_PSEQ_RTCA_XCPT_MASK_MASK                 0x1
#define PMIC_RG_PSEQ_RTCA_XCPT_MASK_SHIFT                14
#define PMIC_RG_WDTRST_EN_ADDR                           MT6355_PPCCFG0
#define PMIC_RG_WDTRST_EN_MASK                           0x1
#define PMIC_RG_WDTRST_EN_SHIFT                          0
#define PMIC_RG_WDTRST_ACT_ADDR                          MT6355_PPCCFG0
#define PMIC_RG_WDTRST_ACT_MASK                          0x3
#define PMIC_RG_WDTRST_ACT_SHIFT                         4
#define PMIC_RG_PSPG_SHDN_EN_ADDR                        MT6355_PPCCFG0
#define PMIC_RG_PSPG_SHDN_EN_MASK                        0x3
#define PMIC_RG_PSPG_SHDN_EN_SHIFT                       8
#define PMIC_RG_THM_SHDN_EN_ADDR                         MT6355_PPCCFG0
#define PMIC_RG_THM_SHDN_EN_MASK                         0x1
#define PMIC_RG_THM_SHDN_EN_SHIFT                        12
#define PMIC_RG_KEYPWR_VCORE_OPT_ADDR                    MT6355_PPCCFG0
#define PMIC_RG_KEYPWR_VCORE_OPT_MASK                    0x1
#define PMIC_RG_KEYPWR_VCORE_OPT_SHIFT                   13
#define PMIC_RG_PSEQ_FORCE_ON_ADDR                       MT6355_PPCTST0
#define PMIC_RG_PSEQ_FORCE_ON_MASK                       0x1
#define PMIC_RG_PSEQ_FORCE_ON_SHIFT                      0
#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_ADDR                 MT6355_PPCTST0
#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_MASK                 0x1
#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_SHIFT                8
#define PMIC_RG_PSEQ_F75K_FORCE_ADDR                     MT6355_PPCTST0
#define PMIC_RG_PSEQ_F75K_FORCE_MASK                     0x1
#define PMIC_RG_PSEQ_F75K_FORCE_SHIFT                    12
#define PMIC_RG_PSEQ_RSV0_ADDR                           MT6355_PPCRSV0
#define PMIC_RG_PSEQ_RSV0_MASK                           0xFF
#define PMIC_RG_PSEQ_RSV0_SHIFT                          0
#define PMIC_RG_PSEQ_RSV1_ADDR                           MT6355_PPCRSV0
#define PMIC_RG_PSEQ_RSV1_MASK                           0xF
#define PMIC_RG_PSEQ_RSV1_SHIFT                          8
#define PMIC_RG_PSEQ_RSV2_ADDR                           MT6355_PPCRSV0
#define PMIC_RG_PSEQ_RSV2_MASK                           0xF
#define PMIC_RG_PSEQ_RSV2_SHIFT                          12
#define PMIC_RG_BWDT_EN_ADDR                             MT6355_BWDTCTL0
#define PMIC_RG_BWDT_EN_MASK                             0x1
#define PMIC_RG_BWDT_EN_SHIFT                            0
#define PMIC_RG_BWDT_TSEL_ADDR                           MT6355_BWDTCTL0
#define PMIC_RG_BWDT_TSEL_MASK                           0x1
#define PMIC_RG_BWDT_TSEL_SHIFT                          1
#define PMIC_RG_BWDT_CSEL_ADDR                           MT6355_BWDTCTL0
#define PMIC_RG_BWDT_CSEL_MASK                           0x1
#define PMIC_RG_BWDT_CSEL_SHIFT                          2
#define PMIC_RG_BWDT_TD_ADDR                             MT6355_BWDTCTL0
#define PMIC_RG_BWDT_TD_MASK                             0x3
#define PMIC_RG_BWDT_TD_SHIFT                            7
#define PMIC_RG_BWDT_CHRTD_ADDR                          MT6355_BWDTCTL0
#define PMIC_RG_BWDT_CHRTD_MASK                          0x1
#define PMIC_RG_BWDT_CHRTD_SHIFT                         12
#define PMIC_RG_BWDT_DDLO_TD_ADDR                        MT6355_BWDTCTL0
#define PMIC_RG_BWDT_DDLO_TD_MASK                        0x3
#define PMIC_RG_BWDT_DDLO_TD_SHIFT                       13
#define PMIC_RG_BWDT_SRCSEL_ADDR                         MT6355_BWDTCTL0
#define PMIC_RG_BWDT_SRCSEL_MASK                         0x1
#define PMIC_RG_BWDT_SRCSEL_SHIFT                        15
#define PMIC_RG_CPS_W_KEY_ADDR                           MT6355_CPSWKEY
#define PMIC_RG_CPS_W_KEY_MASK                           0xFFFF
#define PMIC_RG_CPS_W_KEY_SHIFT                          0
#define PMIC_RG_SLOT_INTV_UP_ADDR                        MT6355_CPSCFG0
#define PMIC_RG_SLOT_INTV_UP_MASK                        0x3
#define PMIC_RG_SLOT_INTV_UP_SHIFT                       0
#define PMIC_RG_SEQ_LEN_ADDR                             MT6355_CPSCFG0
#define PMIC_RG_SEQ_LEN_MASK                             0x1F
#define PMIC_RG_SEQ_LEN_SHIFT                            8
#define PMIC_RG_SLOT_INTV_DOWN_ADDR                      MT6355_CPSCFG1
#define PMIC_RG_SLOT_INTV_DOWN_MASK                      0x3
#define PMIC_RG_SLOT_INTV_DOWN_SHIFT                     0
#define PMIC_RG_DSEQ_LEN_ADDR                            MT6355_CPSCFG1
#define PMIC_RG_DSEQ_LEN_MASK                            0x1F
#define PMIC_RG_DSEQ_LEN_SHIFT                           8
#define PMIC_RG_VS2_USA_ADDR                             MT6355_CPSPSA0
#define PMIC_RG_VS2_USA_MASK                             0x1F
#define PMIC_RG_VS2_USA_SHIFT                            0
#define PMIC_RG_VSRAM_CORE_USA_ADDR                      MT6355_CPSPSA0
#define PMIC_RG_VSRAM_CORE_USA_MASK                      0x1F
#define PMIC_RG_VSRAM_CORE_USA_SHIFT                     8
#define PMIC_RG_VSRAM_MD_USA_ADDR                        MT6355_CPSPSA1
#define PMIC_RG_VSRAM_MD_USA_MASK                        0x1F
#define PMIC_RG_VSRAM_MD_USA_SHIFT                       0
#define PMIC_RG_VSRAM_GPU_USA_ADDR                       MT6355_CPSPSA1
#define PMIC_RG_VSRAM_GPU_USA_MASK                       0x1F
#define PMIC_RG_VSRAM_GPU_USA_SHIFT                      8
#define PMIC_RG_VCORE_USA_ADDR                           MT6355_CPSPSA2
#define PMIC_RG_VCORE_USA_MASK                           0x1F
#define PMIC_RG_VCORE_USA_SHIFT                          0
#define PMIC_RG_VGPU_USA_ADDR                            MT6355_CPSPSA2
#define PMIC_RG_VGPU_USA_MASK                            0x1F
#define PMIC_RG_VGPU_USA_SHIFT                           8
#define PMIC_RG_VMODEM_USA_ADDR                          MT6355_CPSPSA3
#define PMIC_RG_VMODEM_USA_MASK                          0x1F
#define PMIC_RG_VMODEM_USA_SHIFT                         0
#define PMIC_RG_VS1_USA_ADDR                             MT6355_CPSPSA3
#define PMIC_RG_VS1_USA_MASK                             0x1F
#define PMIC_RG_VS1_USA_SHIFT                            8
#define PMIC_RG_VA10_USA_ADDR                            MT6355_CPSPSA4
#define PMIC_RG_VA10_USA_MASK                            0x1F
#define PMIC_RG_VA10_USA_SHIFT                           0
#define PMIC_RG_VA12_USA_ADDR                            MT6355_CPSPSA4
#define PMIC_RG_VA12_USA_MASK                            0x1F
#define PMIC_RG_VA12_USA_SHIFT                           8
#define PMIC_RG_VIO18_USA_ADDR                           MT6355_CPSPSA5
#define PMIC_RG_VIO18_USA_MASK                           0x1F
#define PMIC_RG_VIO18_USA_SHIFT                          0
#define PMIC_RG_VEMC_USA_ADDR                            MT6355_CPSPSA5
#define PMIC_RG_VEMC_USA_MASK                            0x1F
#define PMIC_RG_VEMC_USA_SHIFT                           8
#define PMIC_RG_VUFS18_USA_ADDR                          MT6355_CPSPSA6
#define PMIC_RG_VUFS18_USA_MASK                          0x1F
#define PMIC_RG_VUFS18_USA_SHIFT                         0
#define PMIC_RG_VIO28_USA_ADDR                           MT6355_CPSPSA6
#define PMIC_RG_VIO28_USA_MASK                           0x1F
#define PMIC_RG_VIO28_USA_SHIFT                          8
#define PMIC_RG_VSRAM_PROC_USA_ADDR                      MT6355_CPSPSA7
#define PMIC_RG_VSRAM_PROC_USA_MASK                      0x1F
#define PMIC_RG_VSRAM_PROC_USA_SHIFT                     0
#define PMIC_RG_VPROC11_USA_ADDR                         MT6355_CPSPSA7
#define PMIC_RG_VPROC11_USA_MASK                         0x1F
#define PMIC_RG_VPROC11_USA_SHIFT                        8
#define PMIC_RG_VPROC12_USA_ADDR                         MT6355_CPSPSA8
#define PMIC_RG_VPROC12_USA_MASK                         0x1F
#define PMIC_RG_VPROC12_USA_SHIFT                        0
#define PMIC_RG_EXT_PMIC_USA_ADDR                        MT6355_CPSPSA8
#define PMIC_RG_EXT_PMIC_USA_MASK                        0x1F
#define PMIC_RG_EXT_PMIC_USA_SHIFT                       8
#define PMIC_RG_VDRAM1_USA_ADDR                          MT6355_CPSPSA9
#define PMIC_RG_VDRAM1_USA_MASK                          0x1F
#define PMIC_RG_VDRAM1_USA_SHIFT                         0
#define PMIC_RG_VDRAM2_USA_ADDR                          MT6355_CPSPSA9
#define PMIC_RG_VDRAM2_USA_MASK                          0x1F
#define PMIC_RG_VDRAM2_USA_SHIFT                         8
#define PMIC_RG_VUSB33_USA_ADDR                          MT6355_CPSPSA10
#define PMIC_RG_VUSB33_USA_MASK                          0x1F
#define PMIC_RG_VUSB33_USA_SHIFT                         0
#define PMIC_RG_VXO22_USA_ADDR                           MT6355_CPSPSA10
#define PMIC_RG_VXO22_USA_MASK                           0x1F
#define PMIC_RG_VXO22_USA_SHIFT                          8
#define PMIC_RG_VXO18_USA_ADDR                           MT6355_CPSPSA11
#define PMIC_RG_VXO18_USA_MASK                           0x1F
#define PMIC_RG_VXO18_USA_SHIFT                          0
#define PMIC_RG_BUCK_RSV_USA_ADDR                        MT6355_CPSPSA11
#define PMIC_RG_BUCK_RSV_USA_MASK                        0x1F
#define PMIC_RG_BUCK_RSV_USA_SHIFT                       8
#define PMIC_RG_VS2_DSA_ADDR                             MT6355_CPSDSA0
#define PMIC_RG_VS2_DSA_MASK                             0x1F
#define PMIC_RG_VS2_DSA_SHIFT                            0
#define PMIC_RG_VSRAM_CORE_DSA_ADDR                      MT6355_CPSDSA0
#define PMIC_RG_VSRAM_CORE_DSA_MASK                      0x1F
#define PMIC_RG_VSRAM_CORE_DSA_SHIFT                     8
#define PMIC_RG_VSRAM_MD_DSA_ADDR                        MT6355_CPSDSA1
#define PMIC_RG_VSRAM_MD_DSA_MASK                        0x1F
#define PMIC_RG_VSRAM_MD_DSA_SHIFT                       0
#define PMIC_RG_VSRAM_GPU_DSA_ADDR                       MT6355_CPSDSA1
#define PMIC_RG_VSRAM_GPU_DSA_MASK                       0x1F
#define PMIC_RG_VSRAM_GPU_DSA_SHIFT                      8
#define PMIC_RG_VCORE_DSA_ADDR                           MT6355_CPSDSA2
#define PMIC_RG_VCORE_DSA_MASK                           0x1F
#define PMIC_RG_VCORE_DSA_SHIFT                          0
#define PMIC_RG_VGPU_DSA_ADDR                            MT6355_CPSDSA2
#define PMIC_RG_VGPU_DSA_MASK                            0x1F
#define PMIC_RG_VGPU_DSA_SHIFT                           8
#define PMIC_RG_VMODEM_DSA_ADDR                          MT6355_CPSDSA3
#define PMIC_RG_VMODEM_DSA_MASK                          0x1F
#define PMIC_RG_VMODEM_DSA_SHIFT                         0
#define PMIC_RG_VS1_DSA_ADDR                             MT6355_CPSDSA3
#define PMIC_RG_VS1_DSA_MASK                             0x1F
#define PMIC_RG_VS1_DSA_SHIFT                            8
#define PMIC_RG_VA10_DSA_ADDR                            MT6355_CPSDSA4
#define PMIC_RG_VA10_DSA_MASK                            0x1F
#define PMIC_RG_VA10_DSA_SHIFT                           0
#define PMIC_RG_VA12_DSA_ADDR                            MT6355_CPSDSA4
#define PMIC_RG_VA12_DSA_MASK                            0x1F
#define PMIC_RG_VA12_DSA_SHIFT                           8
#define PMIC_RG_VIO18_DSA_ADDR                           MT6355_CPSDSA5
#define PMIC_RG_VIO18_DSA_MASK                           0x1F
#define PMIC_RG_VIO18_DSA_SHIFT                          0
#define PMIC_RG_VEMC_DSA_ADDR                            MT6355_CPSDSA5
#define PMIC_RG_VEMC_DSA_MASK                            0x1F
#define PMIC_RG_VEMC_DSA_SHIFT                           8
#define PMIC_RG_VUFS18_DSA_ADDR                          MT6355_CPSDSA6
#define PMIC_RG_VUFS18_DSA_MASK                          0x1F
#define PMIC_RG_VUFS18_DSA_SHIFT                         0
#define PMIC_RG_VIO28_DSA_ADDR                           MT6355_CPSDSA6
#define PMIC_RG_VIO28_DSA_MASK                           0x1F
#define PMIC_RG_VIO28_DSA_SHIFT                          8
#define PMIC_RG_VSRAM_PROC_DSA_ADDR                      MT6355_CPSDSA7
#define PMIC_RG_VSRAM_PROC_DSA_MASK                      0x1F
#define PMIC_RG_VSRAM_PROC_DSA_SHIFT                     0
#define PMIC_RG_VPROC11_DSA_ADDR                         MT6355_CPSDSA7
#define PMIC_RG_VPROC11_DSA_MASK                         0x1F
#define PMIC_RG_VPROC11_DSA_SHIFT                        8
#define PMIC_RG_VPROC12_DSA_ADDR                         MT6355_CPSDSA8
#define PMIC_RG_VPROC12_DSA_MASK                         0x1F
#define PMIC_RG_VPROC12_DSA_SHIFT                        0
#define PMIC_RG_EXT_PMIC_DSA_ADDR                        MT6355_CPSDSA8
#define PMIC_RG_EXT_PMIC_DSA_MASK                        0x1F
#define PMIC_RG_EXT_PMIC_DSA_SHIFT                       8
#define PMIC_RG_VDRAM1_DSA_ADDR                          MT6355_CPSDSA9
#define PMIC_RG_VDRAM1_DSA_MASK                          0x1F
#define PMIC_RG_VDRAM1_DSA_SHIFT                         0
#define PMIC_RG_VDRAM2_DSA_ADDR                          MT6355_CPSDSA9
#define PMIC_RG_VDRAM2_DSA_MASK                          0x1F
#define PMIC_RG_VDRAM2_DSA_SHIFT                         8
#define PMIC_RG_VUSB33_DSA_ADDR                          MT6355_CPSDSA10
#define PMIC_RG_VUSB33_DSA_MASK                          0x1F
#define PMIC_RG_VUSB33_DSA_SHIFT                         0
#define PMIC_RG_VXO22_DSA_ADDR                           MT6355_CPSDSA10
#define PMIC_RG_VXO22_DSA_MASK                           0x1F
#define PMIC_RG_VXO22_DSA_SHIFT                          8
#define PMIC_RG_VXO18_DSA_ADDR                           MT6355_CPSDSA11
#define PMIC_RG_VXO18_DSA_MASK                           0x1F
#define PMIC_RG_VXO18_DSA_SHIFT                          0
#define PMIC_RG_BUCK_RSV_DSA_ADDR                        MT6355_CPSDSA11
#define PMIC_RG_BUCK_RSV_DSA_MASK                        0x1F
#define PMIC_RG_BUCK_RSV_DSA_SHIFT                       8
#define PMIC_RG_POR_FLAG_ADDR                            MT6355_PORFLAG
#define PMIC_RG_POR_FLAG_MASK                            0x1
#define PMIC_RG_POR_FLAG_SHIFT                           0
#define PMIC_STS_PWRKEY_ADDR                             MT6355_PONSTS
#define PMIC_STS_PWRKEY_MASK                             0x1
#define PMIC_STS_PWRKEY_SHIFT                            0
#define PMIC_STS_RTCA_ADDR                               MT6355_PONSTS
#define PMIC_STS_RTCA_MASK                               0x1
#define PMIC_STS_RTCA_SHIFT                              1
#define PMIC_STS_CHRIN_ADDR                              MT6355_PONSTS
#define PMIC_STS_CHRIN_MASK                              0x1
#define PMIC_STS_CHRIN_SHIFT                             2
#define PMIC_STS_SPAR_ADDR                               MT6355_PONSTS
#define PMIC_STS_SPAR_MASK                               0x1
#define PMIC_STS_SPAR_SHIFT                              3
#define PMIC_STS_RBOOT_ADDR                              MT6355_PONSTS
#define PMIC_STS_RBOOT_MASK                              0x1
#define PMIC_STS_RBOOT_SHIFT                             4
#define PMIC_STS_UVLO_ADDR                               MT6355_POFFSTS
#define PMIC_STS_UVLO_MASK                               0x1
#define PMIC_STS_UVLO_SHIFT                              0
#define PMIC_STS_PGFAIL_ADDR                             MT6355_POFFSTS
#define PMIC_STS_PGFAIL_MASK                             0x1
#define PMIC_STS_PGFAIL_SHIFT                            1
#define PMIC_STS_PSOC_ADDR                               MT6355_POFFSTS
#define PMIC_STS_PSOC_MASK                               0x1
#define PMIC_STS_PSOC_SHIFT                              2
#define PMIC_STS_THRDN_ADDR                              MT6355_POFFSTS
#define PMIC_STS_THRDN_MASK                              0x1
#define PMIC_STS_THRDN_SHIFT                             3
#define PMIC_STS_WRST_ADDR                               MT6355_POFFSTS
#define PMIC_STS_WRST_MASK                               0x1
#define PMIC_STS_WRST_SHIFT                              4
#define PMIC_STS_CRST_ADDR                               MT6355_POFFSTS
#define PMIC_STS_CRST_MASK                               0x1
#define PMIC_STS_CRST_SHIFT                              5
#define PMIC_STS_PKEYLP_ADDR                             MT6355_POFFSTS
#define PMIC_STS_PKEYLP_MASK                             0x1
#define PMIC_STS_PKEYLP_SHIFT                            6
#define PMIC_STS_NORMOFF_ADDR                            MT6355_POFFSTS
#define PMIC_STS_NORMOFF_MASK                            0x1
#define PMIC_STS_NORMOFF_SHIFT                           7
#define PMIC_STS_BWDT_ADDR                               MT6355_POFFSTS
#define PMIC_STS_BWDT_MASK                               0x1
#define PMIC_STS_BWDT_SHIFT                              8
#define PMIC_STS_DDLO_ADDR                               MT6355_POFFSTS
#define PMIC_STS_DDLO_MASK                               0x1
#define PMIC_STS_DDLO_SHIFT                              9
#define PMIC_STS_WDT_ADDR                                MT6355_POFFSTS
#define PMIC_STS_WDT_MASK                                0x1
#define PMIC_STS_WDT_SHIFT                               10
#define PMIC_STS_PUPSRC_ADDR                             MT6355_POFFSTS
#define PMIC_STS_PUPSRC_MASK                             0x1
#define PMIC_STS_PUPSRC_SHIFT                            11
#define PMIC_STS_KEYPWR_ADDR                             MT6355_POFFSTS
#define PMIC_STS_KEYPWR_MASK                             0x1
#define PMIC_STS_KEYPWR_SHIFT                            12
#define PMIC_RG_POFFSTS_CLR_ADDR                         MT6355_PSTSCTL
#define PMIC_RG_POFFSTS_CLR_MASK                         0x1
#define PMIC_RG_POFFSTS_CLR_SHIFT                        0
#define PMIC_RG_PONSTS_CLR_ADDR                          MT6355_PSTSCTL
#define PMIC_RG_PONSTS_CLR_MASK                          0x1
#define PMIC_RG_PONSTS_CLR_SHIFT                         8
#define PMIC_RG_BUCK_LDO_FT_EN_ADDR                      MT6355_BUCK_ALL_CON0
#define PMIC_RG_BUCK_LDO_FT_EN_MASK                      0x1
#define PMIC_RG_BUCK_LDO_FT_EN_SHIFT                     0
#define PMIC_RG_BUCK_DCM_MODE_ADDR                       MT6355_BUCK_ALL_CON0
#define PMIC_RG_BUCK_DCM_MODE_MASK                       0x1
#define PMIC_RG_BUCK_DCM_MODE_SHIFT                      1
#define PMIC_RG_BUCK_ALL_CON0_RSV_ADDR                   MT6355_BUCK_ALL_CON0
#define PMIC_RG_BUCK_ALL_CON0_RSV_MASK                   0x3FFF
#define PMIC_RG_BUCK_ALL_CON0_RSV_SHIFT                  2
#define PMIC_RG_BUCK_STB_MAX_ADDR                        MT6355_BUCK_STB_CON
#define PMIC_RG_BUCK_STB_MAX_MASK                        0x1FF
#define PMIC_RG_BUCK_STB_MAX_SHIFT                       0
#define PMIC_RG_BUCK_LP_PROT_DISABLE_ADDR                MT6355_BUCK_STB_CON
#define PMIC_RG_BUCK_LP_PROT_DISABLE_MASK                0x1
#define PMIC_RG_BUCK_LP_PROT_DISABLE_SHIFT               9
#define PMIC_RG_BUCK_VSLEEP_SRC0_ADDR                    MT6355_BUCK_SLP_CON0
#define PMIC_RG_BUCK_VSLEEP_SRC0_MASK                    0x1FF
#define PMIC_RG_BUCK_VSLEEP_SRC0_SHIFT                   0
#define PMIC_RG_BUCK_VSLEEP_SRC1_ADDR                    MT6355_BUCK_SLP_CON0
#define PMIC_RG_BUCK_VSLEEP_SRC1_MASK                    0xF
#define PMIC_RG_BUCK_VSLEEP_SRC1_SHIFT                   12
#define PMIC_RG_BUCK_R2R_SRC0_ADDR                       MT6355_BUCK_SLP_CON1
#define PMIC_RG_BUCK_R2R_SRC0_MASK                       0x1FF
#define PMIC_RG_BUCK_R2R_SRC0_SHIFT                      0
#define PMIC_RG_BUCK_R2R_SRC1_ADDR                       MT6355_BUCK_SLP_CON1
#define PMIC_RG_BUCK_R2R_SRC1_MASK                       0xF
#define PMIC_RG_BUCK_R2R_SRC1_SHIFT                      12
#define PMIC_RG_BUCK_LP_SEQ_COUNT_ADDR                   MT6355_BUCK_SLP_CON2
#define PMIC_RG_BUCK_LP_SEQ_COUNT_MASK                   0x1FF
#define PMIC_RG_BUCK_LP_SEQ_COUNT_SHIFT                  0
#define PMIC_RG_BUCK_ON_SEQ_COUNT_ADDR                   MT6355_BUCK_SLP_CON2
#define PMIC_RG_BUCK_ON_SEQ_COUNT_MASK                   0xF
#define PMIC_RG_BUCK_ON_SEQ_COUNT_SHIFT                  12
#define PMIC_RG_BUCK_MINFREQ_LATENCY_MAX_ADDR            MT6355_BUCK_MINFREQ_CON
#define PMIC_RG_BUCK_MINFREQ_LATENCY_MAX_MASK            0x3F
#define PMIC_RG_BUCK_MINFREQ_LATENCY_MAX_SHIFT           0
#define PMIC_RG_BUCK_MINFREQ_DURATION_MAX_ADDR           MT6355_BUCK_MINFREQ_CON
#define PMIC_RG_BUCK_MINFREQ_DURATION_MAX_MASK           0x7
#define PMIC_RG_BUCK_MINFREQ_DURATION_MAX_SHIFT          8
#define PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS_ADDR          MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS_MASK          0x1
#define PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS_SHIFT         0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS_ADDR          MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS_MASK          0x1
#define PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS_SHIFT         1
#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_ADDR            MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_MASK            0x1
#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_SHIFT           2
#define PMIC_RG_BUCK_VGPU_OC_SDN_STATUS_ADDR             MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VGPU_OC_SDN_STATUS_MASK             0x1
#define PMIC_RG_BUCK_VGPU_OC_SDN_STATUS_SHIFT            3
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_ADDR           MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_MASK           0x1
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_SHIFT          4
#define PMIC_RG_BUCK_VDRAM2_OC_SDN_STATUS_ADDR           MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VDRAM2_OC_SDN_STATUS_MASK           0x1
#define PMIC_RG_BUCK_VDRAM2_OC_SDN_STATUS_SHIFT          5
#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_ADDR           MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_MASK           0x1
#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_SHIFT          6
#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_ADDR              MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_MASK              0x1
#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_SHIFT             7
#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_ADDR              MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_MASK              0x1
#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_SHIFT             8
#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_ADDR              MT6355_BUCK_OC_CON0
#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK              0x1
#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT             9
#define PMIC_RG_BUCK_VPROC11_OC_SDN_EN_ADDR              MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VPROC11_OC_SDN_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_OC_SDN_EN_SHIFT             0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_EN_ADDR              MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VPROC12_OC_SDN_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_OC_SDN_EN_SHIFT             1
#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_ADDR                MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_SHIFT               2
#define PMIC_RG_BUCK_VGPU_OC_SDN_EN_ADDR                 MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VGPU_OC_SDN_EN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_OC_SDN_EN_SHIFT                3
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_ADDR               MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_SHIFT              4
#define PMIC_RG_BUCK_VDRAM2_OC_SDN_EN_ADDR               MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VDRAM2_OC_SDN_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_OC_SDN_EN_SHIFT              5
#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_ADDR               MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_SHIFT              6
#define PMIC_RG_BUCK_VS1_OC_SDN_EN_ADDR                  MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VS1_OC_SDN_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_OC_SDN_EN_SHIFT                 7
#define PMIC_RG_BUCK_VS2_OC_SDN_EN_ADDR                  MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VS2_OC_SDN_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_OC_SDN_EN_SHIFT                 8
#define PMIC_RG_BUCK_VPA_OC_SDN_EN_ADDR                  MT6355_BUCK_OC_CON1
#define PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK                  0x1
#define PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT                 9
#define PMIC_RG_BUCK_K_RST_DONE_ADDR                     MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_RST_DONE_MASK                     0x1
#define PMIC_RG_BUCK_K_RST_DONE_SHIFT                    0
#define PMIC_RG_BUCK_K_MAP_SEL_ADDR                      MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_MAP_SEL_MASK                      0x1
#define PMIC_RG_BUCK_K_MAP_SEL_SHIFT                     1
#define PMIC_RG_BUCK_K_ONCE_EN_ADDR                      MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_ONCE_EN_MASK                      0x1
#define PMIC_RG_BUCK_K_ONCE_EN_SHIFT                     2
#define PMIC_RG_BUCK_K_ONCE_ADDR                         MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_ONCE_MASK                         0x1
#define PMIC_RG_BUCK_K_ONCE_SHIFT                        3
#define PMIC_RG_BUCK_K_START_MANUAL_ADDR                 MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_START_MANUAL_MASK                 0x1
#define PMIC_RG_BUCK_K_START_MANUAL_SHIFT                4
#define PMIC_RG_BUCK_K_SRC_SEL_ADDR                      MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_SRC_SEL_MASK                      0x1
#define PMIC_RG_BUCK_K_SRC_SEL_SHIFT                     5
#define PMIC_RG_BUCK_K_AUTO_EN_ADDR                      MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_AUTO_EN_MASK                      0x1
#define PMIC_RG_BUCK_K_AUTO_EN_SHIFT                     6
#define PMIC_RG_BUCK_K_INV_ADDR                          MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_INV_MASK                          0x1
#define PMIC_RG_BUCK_K_INV_SHIFT                         7
#define PMIC_RG_BUCK_K_CK_EN_ADDR                        MT6355_BUCK_K_CON0
#define PMIC_RG_BUCK_K_CK_EN_MASK                        0x1
#define PMIC_RG_BUCK_K_CK_EN_SHIFT                       8
#define PMIC_RG_BUCK_K_CONTROL_SMPS_ADDR                 MT6355_BUCK_K_CON1
#define PMIC_RG_BUCK_K_CONTROL_SMPS_MASK                 0x3F
#define PMIC_RG_BUCK_K_CONTROL_SMPS_SHIFT                8
#define PMIC_BUCK_K_RESULT_ADDR                          MT6355_BUCK_K_CON2
#define PMIC_BUCK_K_RESULT_MASK                          0x1
#define PMIC_BUCK_K_RESULT_SHIFT                         0
#define PMIC_BUCK_K_DONE_ADDR                            MT6355_BUCK_K_CON2
#define PMIC_BUCK_K_DONE_MASK                            0x1
#define PMIC_BUCK_K_DONE_SHIFT                           1
#define PMIC_BUCK_K_CONTROL_ADDR                         MT6355_BUCK_K_CON2
#define PMIC_BUCK_K_CONTROL_MASK                         0x3F
#define PMIC_BUCK_K_CONTROL_SHIFT                        2
#define PMIC_DA_QI_SMPS_OSC_CAL_ADDR                     MT6355_BUCK_K_CON2
#define PMIC_DA_QI_SMPS_OSC_CAL_MASK                     0x3F
#define PMIC_DA_QI_SMPS_OSC_CAL_SHIFT                    8
#define PMIC_RG_BUCK_K_BUCK_CK_CNT_ADDR                  MT6355_BUCK_K_CON3
#define PMIC_RG_BUCK_K_BUCK_CK_CNT_MASK                  0x3FF
#define PMIC_RG_BUCK_K_BUCK_CK_CNT_SHIFT                 0
#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_ADDR             MT6355_BUCK_VOW_CON
#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_MASK             0x1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_SHIFT            0
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_ADDR         MT6355_BUCK_VOW_CON
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_MASK         0x1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_SHIFT        1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_ADDR          MT6355_BUCK_VOW_CON
#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_MASK          0x1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_SHIFT         8
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_ADDR      MT6355_BUCK_VOW_CON
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_MASK      0x1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_SHIFT     9
#define PMIC_VOW_BUCK_VCORE_DVS_DONE_ADDR                MT6355_BUCK_VOW_CON
#define PMIC_VOW_BUCK_VCORE_DVS_DONE_MASK                0x1
#define PMIC_VOW_BUCK_VCORE_DVS_DONE_SHIFT               13
#define PMIC_VOW_LDO_VSRAM_CORE_DVS_DONE_ADDR            MT6355_BUCK_VOW_CON
#define PMIC_VOW_LDO_VSRAM_CORE_DVS_DONE_MASK            0x1
#define PMIC_VOW_LDO_VSRAM_CORE_DVS_DONE_SHIFT           14
#define PMIC_VOW_DVS_DONE_ADDR                           MT6355_BUCK_VOW_CON
#define PMIC_VOW_DVS_DONE_MASK                           0x1
#define PMIC_VOW_DVS_DONE_SHIFT                          15
#define PMIC_RG_BUCK_VPROC11_EN_ADDR                     MT6355_BUCK_VPROC11_CON0
#define PMIC_RG_BUCK_VPROC11_EN_MASK                     0x1
#define PMIC_RG_BUCK_VPROC11_EN_SHIFT                    0
#define PMIC_RG_BUCK_VPROC11_LP_ADDR                     MT6355_BUCK_VPROC11_CON0
#define PMIC_RG_BUCK_VPROC11_LP_MASK                     0x1
#define PMIC_RG_BUCK_VPROC11_LP_SHIFT                    1
#define PMIC_RG_BUCK_VPROC11_VOSEL_ADDR                  MT6355_BUCK_VPROC11_CON1
#define PMIC_RG_BUCK_VPROC11_VOSEL_MASK                  0x7F
#define PMIC_RG_BUCK_VPROC11_VOSEL_SHIFT                 0
#define PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP_ADDR            MT6355_BUCK_VPROC11_CON2
#define PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP_MASK            0x7F
#define PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP_SHIFT           0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FRATE_ADDR            MT6355_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FRATE_MASK            0x7F
#define PMIC_RG_BUCK_VPROC11_SFCHG_FRATE_SHIFT           0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FEN_ADDR              MT6355_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FEN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_SFCHG_FEN_SHIFT             7
#define PMIC_RG_BUCK_VPROC11_SFCHG_RRATE_ADDR            MT6355_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_RRATE_MASK            0x7F
#define PMIC_RG_BUCK_VPROC11_SFCHG_RRATE_SHIFT           8
#define PMIC_RG_BUCK_VPROC11_SFCHG_REN_ADDR              MT6355_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_REN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_SFCHG_REN_SHIFT             15
#define PMIC_RG_BUCK_VPROC11_DVS_EN_TD_ADDR              MT6355_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_TD_MASK              0x3
#define PMIC_RG_BUCK_VPROC11_DVS_EN_TD_SHIFT             0
#define PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL_ADDR            MT6355_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL_MASK            0x3
#define PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL_SHIFT           4
#define PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE_ADDR            MT6355_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE_MASK            0x1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE_SHIFT           6
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD_ADDR            MT6355_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD_MASK            0x3
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD_SHIFT           8
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL_ADDR          MT6355_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL_MASK          0x3
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL_SHIFT         12
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE_ADDR          MT6355_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE_MASK          0x1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE_SHIFT         14
#define PMIC_RG_BUCK_VPROC11_SW_OP_EN_ADDR               MT6355_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_SW_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VPROC11_SW_OP_EN_SHIFT              0
#define PMIC_RG_BUCK_VPROC11_HW0_OP_EN_ADDR              MT6355_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_HW0_OP_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_HW0_OP_EN_SHIFT             1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_EN_ADDR              MT6355_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_HW1_OP_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_EN_SHIFT             2
#define PMIC_RG_BUCK_VPROC11_HW2_OP_EN_ADDR              MT6355_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_HW2_OP_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_HW2_OP_EN_SHIFT             3
#define PMIC_RG_BUCK_VPROC11_OP_EN_SET_ADDR              MT6355_BUCK_VPROC11_OP_EN_SET
#define PMIC_RG_BUCK_VPROC11_OP_EN_SET_MASK              0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_EN_SET_SHIFT             0
#define PMIC_RG_BUCK_VPROC11_OP_EN_CLR_ADDR              MT6355_BUCK_VPROC11_OP_EN_CLR
#define PMIC_RG_BUCK_VPROC11_OP_EN_CLR_MASK              0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_EN_CLR_SHIFT             0
#define PMIC_RG_BUCK_VPROC11_HW0_OP_CFG_ADDR             MT6355_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_HW0_OP_CFG_MASK             0x1
#define PMIC_RG_BUCK_VPROC11_HW0_OP_CFG_SHIFT            1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_CFG_ADDR             MT6355_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_HW1_OP_CFG_MASK             0x1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_CFG_SHIFT            2
#define PMIC_RG_BUCK_VPROC11_HW2_OP_CFG_ADDR             MT6355_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_HW2_OP_CFG_MASK             0x1
#define PMIC_RG_BUCK_VPROC11_HW2_OP_CFG_SHIFT            3
#define PMIC_RG_BUCK_VPROC11_ON_OP_ADDR                  MT6355_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_ON_OP_MASK                  0x1
#define PMIC_RG_BUCK_VPROC11_ON_OP_SHIFT                 8
#define PMIC_RG_BUCK_VPROC11_LP_OP_ADDR                  MT6355_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_LP_OP_MASK                  0x1
#define PMIC_RG_BUCK_VPROC11_LP_OP_SHIFT                 9
#define PMIC_RG_BUCK_VPROC11_OP_CFG_SET_ADDR             MT6355_BUCK_VPROC11_OP_CFG_SET
#define PMIC_RG_BUCK_VPROC11_OP_CFG_SET_MASK             0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_CFG_SET_SHIFT            0
#define PMIC_RG_BUCK_VPROC11_OP_CFG_CLR_ADDR             MT6355_BUCK_VPROC11_OP_CFG_CLR
#define PMIC_RG_BUCK_VPROC11_OP_CFG_CLR_MASK             0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_CFG_CLR_SHIFT            0
#define PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_ADDR            MT6355_BUCK_VPROC11_SP_CON
#define PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_MASK            0x7F
#define PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_SHIFT           0
#define PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_EN_ADDR         MT6355_BUCK_VPROC11_SP_CFG
#define PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_EN_MASK         0x1
#define PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_EN_SHIFT        0
#define PMIC_RG_BUCK_VPROC11_SP_ON_VOSEL_MUX_SEL_ADDR    MT6355_BUCK_VPROC11_SP_CFG
#define PMIC_RG_BUCK_VPROC11_SP_ON_VOSEL_MUX_SEL_MASK    0x1
#define PMIC_RG_BUCK_VPROC11_SP_ON_VOSEL_MUX_SEL_SHIFT   1
#define PMIC_RG_BUCK_VPROC11_OC_DEG_EN_ADDR              MT6355_BUCK_VPROC11_OC_CFG
#define PMIC_RG_BUCK_VPROC11_OC_DEG_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC11_OC_DEG_EN_SHIFT             1
#define PMIC_RG_BUCK_VPROC11_OC_WND_ADDR                 MT6355_BUCK_VPROC11_OC_CFG
#define PMIC_RG_BUCK_VPROC11_OC_WND_MASK                 0x3
#define PMIC_RG_BUCK_VPROC11_OC_WND_SHIFT                2
#define PMIC_RG_BUCK_VPROC11_OC_THD_ADDR                 MT6355_BUCK_VPROC11_OC_CFG
#define PMIC_RG_BUCK_VPROC11_OC_THD_MASK                 0x3
#define PMIC_RG_BUCK_VPROC11_OC_THD_SHIFT                6
#define PMIC_DA_VPROC11_VOSEL_ADDR                       MT6355_BUCK_VPROC11_DBG0
#define PMIC_DA_VPROC11_VOSEL_MASK                       0x7F
#define PMIC_DA_VPROC11_VOSEL_SHIFT                      0
#define PMIC_DA_VPROC11_VOSEL_GRAY_ADDR                  MT6355_BUCK_VPROC11_DBG0
#define PMIC_DA_VPROC11_VOSEL_GRAY_MASK                  0x7F
#define PMIC_DA_VPROC11_VOSEL_GRAY_SHIFT                 8
#define PMIC_DA_VPROC11_EN_ADDR                          MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_EN_MASK                          0x1
#define PMIC_DA_VPROC11_EN_SHIFT                         0
#define PMIC_DA_VPROC11_STB_ADDR                         MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_STB_MASK                         0x1
#define PMIC_DA_VPROC11_STB_SHIFT                        1
#define PMIC_DA_VPROC11_VSLEEP_SEL_ADDR                  MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_VSLEEP_SEL_MASK                  0x1
#define PMIC_DA_VPROC11_VSLEEP_SEL_SHIFT                 2
#define PMIC_DA_VPROC11_R2R_PDN_ADDR                     MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_R2R_PDN_MASK                     0x1
#define PMIC_DA_VPROC11_R2R_PDN_SHIFT                    3
#define PMIC_DA_VPROC11_DVS_EN_ADDR                      MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_DVS_EN_MASK                      0x1
#define PMIC_DA_VPROC11_DVS_EN_SHIFT                     4
#define PMIC_DA_VPROC11_DVS_DOWN_ADDR                    MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_DVS_DOWN_MASK                    0x1
#define PMIC_DA_VPROC11_DVS_DOWN_SHIFT                   5
#define PMIC_DA_VPROC11_SSH_ADDR                         MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_SSH_MASK                         0x1
#define PMIC_DA_VPROC11_SSH_SHIFT                        6
#define PMIC_DA_VPROC11_MINFREQ_DISCHARGE_ADDR           MT6355_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_MINFREQ_DISCHARGE_MASK           0x1
#define PMIC_DA_VPROC11_MINFREQ_DISCHARGE_SHIFT          8
#define PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL_ADDR        MT6355_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL_MASK        0x1
#define PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL_SHIFT       4
#define PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS_ADDR            MT6355_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS_MASK            0x1
#define PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS_SHIFT           5
#define PMIC_RG_BUCK_VPROC11_CK_SW_MODE_ADDR             MT6355_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_CK_SW_MODE_MASK             0x1
#define PMIC_RG_BUCK_VPROC11_CK_SW_MODE_SHIFT            6
#define PMIC_RG_BUCK_VPROC11_CK_SW_EN_ADDR               MT6355_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_CK_SW_EN_MASK               0x1
#define PMIC_RG_BUCK_VPROC11_CK_SW_EN_SHIFT              7
#define PMIC_RG_BUCK_VPROC12_EN_ADDR                     MT6355_BUCK_VPROC12_CON0
#define PMIC_RG_BUCK_VPROC12_EN_MASK                     0x1
#define PMIC_RG_BUCK_VPROC12_EN_SHIFT                    0
#define PMIC_RG_BUCK_VPROC12_LP_ADDR                     MT6355_BUCK_VPROC12_CON0
#define PMIC_RG_BUCK_VPROC12_LP_MASK                     0x1
#define PMIC_RG_BUCK_VPROC12_LP_SHIFT                    1
#define PMIC_RG_BUCK_VPROC12_VOSEL_ADDR                  MT6355_BUCK_VPROC12_CON1
#define PMIC_RG_BUCK_VPROC12_VOSEL_MASK                  0x7F
#define PMIC_RG_BUCK_VPROC12_VOSEL_SHIFT                 0
#define PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP_ADDR            MT6355_BUCK_VPROC12_CON2
#define PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP_MASK            0x7F
#define PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP_SHIFT           0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FRATE_ADDR            MT6355_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FRATE_MASK            0x7F
#define PMIC_RG_BUCK_VPROC12_SFCHG_FRATE_SHIFT           0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FEN_ADDR              MT6355_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FEN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_SFCHG_FEN_SHIFT             7
#define PMIC_RG_BUCK_VPROC12_SFCHG_RRATE_ADDR            MT6355_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_RRATE_MASK            0x7F
#define PMIC_RG_BUCK_VPROC12_SFCHG_RRATE_SHIFT           8
#define PMIC_RG_BUCK_VPROC12_SFCHG_REN_ADDR              MT6355_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_REN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_SFCHG_REN_SHIFT             15
#define PMIC_RG_BUCK_VPROC12_DVS_EN_TD_ADDR              MT6355_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_TD_MASK              0x3
#define PMIC_RG_BUCK_VPROC12_DVS_EN_TD_SHIFT             0
#define PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL_ADDR            MT6355_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL_MASK            0x3
#define PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL_SHIFT           4
#define PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE_ADDR            MT6355_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE_MASK            0x1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE_SHIFT           6
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD_ADDR            MT6355_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD_MASK            0x3
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD_SHIFT           8
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL_ADDR          MT6355_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL_MASK          0x3
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL_SHIFT         12
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE_ADDR          MT6355_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE_MASK          0x1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE_SHIFT         14
#define PMIC_RG_BUCK_VPROC12_SW_OP_EN_ADDR               MT6355_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_SW_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VPROC12_SW_OP_EN_SHIFT              0
#define PMIC_RG_BUCK_VPROC12_HW0_OP_EN_ADDR              MT6355_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_HW0_OP_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_HW0_OP_EN_SHIFT             1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_EN_ADDR              MT6355_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_HW1_OP_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_EN_SHIFT             2
#define PMIC_RG_BUCK_VPROC12_HW2_OP_EN_ADDR              MT6355_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_HW2_OP_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_HW2_OP_EN_SHIFT             3
#define PMIC_RG_BUCK_VPROC12_OP_EN_SET_ADDR              MT6355_BUCK_VPROC12_OP_EN_SET
#define PMIC_RG_BUCK_VPROC12_OP_EN_SET_MASK              0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_EN_SET_SHIFT             0
#define PMIC_RG_BUCK_VPROC12_OP_EN_CLR_ADDR              MT6355_BUCK_VPROC12_OP_EN_CLR
#define PMIC_RG_BUCK_VPROC12_OP_EN_CLR_MASK              0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_EN_CLR_SHIFT             0
#define PMIC_RG_BUCK_VPROC12_HW0_OP_CFG_ADDR             MT6355_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_HW0_OP_CFG_MASK             0x1
#define PMIC_RG_BUCK_VPROC12_HW0_OP_CFG_SHIFT            1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_CFG_ADDR             MT6355_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_HW1_OP_CFG_MASK             0x1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_CFG_SHIFT            2
#define PMIC_RG_BUCK_VPROC12_HW2_OP_CFG_ADDR             MT6355_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_HW2_OP_CFG_MASK             0x1
#define PMIC_RG_BUCK_VPROC12_HW2_OP_CFG_SHIFT            3
#define PMIC_RG_BUCK_VPROC12_ON_OP_ADDR                  MT6355_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_ON_OP_MASK                  0x1
#define PMIC_RG_BUCK_VPROC12_ON_OP_SHIFT                 8
#define PMIC_RG_BUCK_VPROC12_LP_OP_ADDR                  MT6355_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_LP_OP_MASK                  0x1
#define PMIC_RG_BUCK_VPROC12_LP_OP_SHIFT                 9
#define PMIC_RG_BUCK_VPROC12_OP_CFG_SET_ADDR             MT6355_BUCK_VPROC12_OP_CFG_SET
#define PMIC_RG_BUCK_VPROC12_OP_CFG_SET_MASK             0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_CFG_SET_SHIFT            0
#define PMIC_RG_BUCK_VPROC12_OP_CFG_CLR_ADDR             MT6355_BUCK_VPROC12_OP_CFG_CLR
#define PMIC_RG_BUCK_VPROC12_OP_CFG_CLR_MASK             0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_CFG_CLR_SHIFT            0
#define PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_ADDR            MT6355_BUCK_VPROC12_SP_CON
#define PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_MASK            0x7F
#define PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_SHIFT           0
#define PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_EN_ADDR         MT6355_BUCK_VPROC12_SP_CFG
#define PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_EN_MASK         0x1
#define PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_EN_SHIFT        0
#define PMIC_RG_BUCK_VPROC12_SP_ON_VOSEL_MUX_SEL_ADDR    MT6355_BUCK_VPROC12_SP_CFG
#define PMIC_RG_BUCK_VPROC12_SP_ON_VOSEL_MUX_SEL_MASK    0x1
#define PMIC_RG_BUCK_VPROC12_SP_ON_VOSEL_MUX_SEL_SHIFT   1
#define PMIC_RG_BUCK_VPROC12_OC_DEG_EN_ADDR              MT6355_BUCK_VPROC12_OC_CFG
#define PMIC_RG_BUCK_VPROC12_OC_DEG_EN_MASK              0x1
#define PMIC_RG_BUCK_VPROC12_OC_DEG_EN_SHIFT             1
#define PMIC_RG_BUCK_VPROC12_OC_WND_ADDR                 MT6355_BUCK_VPROC12_OC_CFG
#define PMIC_RG_BUCK_VPROC12_OC_WND_MASK                 0x3
#define PMIC_RG_BUCK_VPROC12_OC_WND_SHIFT                2
#define PMIC_RG_BUCK_VPROC12_OC_THD_ADDR                 MT6355_BUCK_VPROC12_OC_CFG
#define PMIC_RG_BUCK_VPROC12_OC_THD_MASK                 0x3
#define PMIC_RG_BUCK_VPROC12_OC_THD_SHIFT                6
#define PMIC_DA_VPROC12_VOSEL_ADDR                       MT6355_BUCK_VPROC12_DBG0
#define PMIC_DA_VPROC12_VOSEL_MASK                       0x7F
#define PMIC_DA_VPROC12_VOSEL_SHIFT                      0
#define PMIC_DA_VPROC12_VOSEL_GRAY_ADDR                  MT6355_BUCK_VPROC12_DBG0
#define PMIC_DA_VPROC12_VOSEL_GRAY_MASK                  0x7F
#define PMIC_DA_VPROC12_VOSEL_GRAY_SHIFT                 8
#define PMIC_DA_VPROC12_EN_ADDR                          MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_EN_MASK                          0x1
#define PMIC_DA_VPROC12_EN_SHIFT                         0
#define PMIC_DA_VPROC12_STB_ADDR                         MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_STB_MASK                         0x1
#define PMIC_DA_VPROC12_STB_SHIFT                        1
#define PMIC_DA_VPROC12_VSLEEP_SEL_ADDR                  MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_VSLEEP_SEL_MASK                  0x1
#define PMIC_DA_VPROC12_VSLEEP_SEL_SHIFT                 2
#define PMIC_DA_VPROC12_R2R_PDN_ADDR                     MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_R2R_PDN_MASK                     0x1
#define PMIC_DA_VPROC12_R2R_PDN_SHIFT                    3
#define PMIC_DA_VPROC12_DVS_EN_ADDR                      MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_DVS_EN_MASK                      0x1
#define PMIC_DA_VPROC12_DVS_EN_SHIFT                     4
#define PMIC_DA_VPROC12_DVS_DOWN_ADDR                    MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_DVS_DOWN_MASK                    0x1
#define PMIC_DA_VPROC12_DVS_DOWN_SHIFT                   5
#define PMIC_DA_VPROC12_SSH_ADDR                         MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_SSH_MASK                         0x1
#define PMIC_DA_VPROC12_SSH_SHIFT                        6
#define PMIC_DA_VPROC12_MINFREQ_DISCHARGE_ADDR           MT6355_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_MINFREQ_DISCHARGE_MASK           0x1
#define PMIC_DA_VPROC12_MINFREQ_DISCHARGE_SHIFT          8
#define PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL_ADDR        MT6355_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL_MASK        0x1
#define PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL_SHIFT       4
#define PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS_ADDR            MT6355_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS_MASK            0x1
#define PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS_SHIFT           5
#define PMIC_RG_BUCK_VPROC12_CK_SW_MODE_ADDR             MT6355_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_CK_SW_MODE_MASK             0x1
#define PMIC_RG_BUCK_VPROC12_CK_SW_MODE_SHIFT            6
#define PMIC_RG_BUCK_VPROC12_CK_SW_EN_ADDR               MT6355_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_CK_SW_EN_MASK               0x1
#define PMIC_RG_BUCK_VPROC12_CK_SW_EN_SHIFT              7
#define PMIC_RG_BUCK_VCORE_EN_ADDR                       MT6355_BUCK_VCORE_CON0
#define PMIC_RG_BUCK_VCORE_EN_MASK                       0x1
#define PMIC_RG_BUCK_VCORE_EN_SHIFT                      0
#define PMIC_RG_BUCK_VCORE_LP_ADDR                       MT6355_BUCK_VCORE_CON0
#define PMIC_RG_BUCK_VCORE_LP_MASK                       0x1
#define PMIC_RG_BUCK_VCORE_LP_SHIFT                      1
#define PMIC_RG_BUCK_VCORE_VOSEL_ADDR                    MT6355_BUCK_VCORE_CON1
#define PMIC_RG_BUCK_VCORE_VOSEL_MASK                    0x7F
#define PMIC_RG_BUCK_VCORE_VOSEL_SHIFT                   0
#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR              MT6355_BUCK_VCORE_CON2
#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK              0x7F
#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT             0
#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_ADDR              MT6355_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_MASK              0x7F
#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_SHIFT             0
#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_ADDR                MT6355_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_SHIFT               7
#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_ADDR              MT6355_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_MASK              0x7F
#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_SHIFT             8
#define PMIC_RG_BUCK_VCORE_SFCHG_REN_ADDR                MT6355_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_REN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_SFCHG_REN_SHIFT               15
#define PMIC_RG_BUCK_VCORE_DVS_EN_TD_ADDR                MT6355_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_EN_TD_MASK                0x3
#define PMIC_RG_BUCK_VCORE_DVS_EN_TD_SHIFT               0
#define PMIC_RG_BUCK_VCORE_DVS_EN_CTRL_ADDR              MT6355_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_EN_CTRL_MASK              0x3
#define PMIC_RG_BUCK_VCORE_DVS_EN_CTRL_SHIFT             4
#define PMIC_RG_BUCK_VCORE_DVS_EN_ONCE_ADDR              MT6355_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_EN_ONCE_MASK              0x1
#define PMIC_RG_BUCK_VCORE_DVS_EN_ONCE_SHIFT             6
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_TD_ADDR              MT6355_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_TD_MASK              0x3
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_TD_SHIFT             8
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL_ADDR            MT6355_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL_MASK            0x3
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL_SHIFT           12
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE_ADDR            MT6355_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE_MASK            0x1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE_SHIFT           14
#define PMIC_RG_BUCK_VCORE_SW_OP_EN_ADDR                 MT6355_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_SW_OP_EN_MASK                 0x1
#define PMIC_RG_BUCK_VCORE_SW_OP_EN_SHIFT                0
#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_ADDR                MT6355_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_SHIFT               1
#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_ADDR                MT6355_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_SHIFT               2
#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_ADDR                MT6355_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_SHIFT               3
#define PMIC_RG_BUCK_VCORE_OP_EN_SET_ADDR                MT6355_BUCK_VCORE_OP_EN_SET
#define PMIC_RG_BUCK_VCORE_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_EN_SET_SHIFT               0
#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_ADDR                MT6355_BUCK_VCORE_OP_EN_CLR
#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_SHIFT               0
#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_ADDR               MT6355_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_ADDR               MT6355_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_ADDR               MT6355_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_BUCK_VCORE_ON_OP_ADDR                    MT6355_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_ON_OP_MASK                    0x1
#define PMIC_RG_BUCK_VCORE_ON_OP_SHIFT                   8
#define PMIC_RG_BUCK_VCORE_LP_OP_ADDR                    MT6355_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_LP_OP_MASK                    0x1
#define PMIC_RG_BUCK_VCORE_LP_OP_SHIFT                   9
#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_ADDR               MT6355_BUCK_VCORE_OP_CFG_SET
#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_SHIFT              0
#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_ADDR               MT6355_BUCK_VCORE_OP_CFG_CLR
#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_SHIFT              0
#define PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_ADDR              MT6355_BUCK_VCORE_SP_CON
#define PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_MASK              0x7F
#define PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_SHIFT             0
#define PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_EN_ADDR           MT6355_BUCK_VCORE_SP_CFG
#define PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_EN_MASK           0x1
#define PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_EN_SHIFT          0
#define PMIC_RG_BUCK_VCORE_SP_ON_VOSEL_MUX_SEL_ADDR      MT6355_BUCK_VCORE_SP_CFG
#define PMIC_RG_BUCK_VCORE_SP_ON_VOSEL_MUX_SEL_MASK      0x1
#define PMIC_RG_BUCK_VCORE_SP_ON_VOSEL_MUX_SEL_SHIFT     1
#define PMIC_RG_BUCK_VCORE_OC_DEG_EN_ADDR                MT6355_BUCK_VCORE_OC_CFG
#define PMIC_RG_BUCK_VCORE_OC_DEG_EN_MASK                0x1
#define PMIC_RG_BUCK_VCORE_OC_DEG_EN_SHIFT               1
#define PMIC_RG_BUCK_VCORE_OC_WND_ADDR                   MT6355_BUCK_VCORE_OC_CFG
#define PMIC_RG_BUCK_VCORE_OC_WND_MASK                   0x3
#define PMIC_RG_BUCK_VCORE_OC_WND_SHIFT                  2
#define PMIC_RG_BUCK_VCORE_OC_THD_ADDR                   MT6355_BUCK_VCORE_OC_CFG
#define PMIC_RG_BUCK_VCORE_OC_THD_MASK                   0x3
#define PMIC_RG_BUCK_VCORE_OC_THD_SHIFT                  6
#define PMIC_DA_VCORE_VOSEL_ADDR                         MT6355_BUCK_VCORE_DBG0
#define PMIC_DA_VCORE_VOSEL_MASK                         0x7F
#define PMIC_DA_VCORE_VOSEL_SHIFT                        0
#define PMIC_DA_VCORE_VOSEL_GRAY_ADDR                    MT6355_BUCK_VCORE_DBG0
#define PMIC_DA_VCORE_VOSEL_GRAY_MASK                    0x7F
#define PMIC_DA_VCORE_VOSEL_GRAY_SHIFT                   8
#define PMIC_DA_VCORE_EN_ADDR                            MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_EN_MASK                            0x1
#define PMIC_DA_VCORE_EN_SHIFT                           0
#define PMIC_DA_VCORE_STB_ADDR                           MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_STB_MASK                           0x1
#define PMIC_DA_VCORE_STB_SHIFT                          1
#define PMIC_DA_VCORE_VSLEEP_SEL_ADDR                    MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_VSLEEP_SEL_MASK                    0x1
#define PMIC_DA_VCORE_VSLEEP_SEL_SHIFT                   2
#define PMIC_DA_VCORE_R2R_PDN_ADDR                       MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_R2R_PDN_MASK                       0x1
#define PMIC_DA_VCORE_R2R_PDN_SHIFT                      3
#define PMIC_DA_VCORE_DVS_EN_ADDR                        MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_DVS_EN_MASK                        0x1
#define PMIC_DA_VCORE_DVS_EN_SHIFT                       4
#define PMIC_DA_VCORE_DVS_DOWN_ADDR                      MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_DVS_DOWN_MASK                      0x1
#define PMIC_DA_VCORE_DVS_DOWN_SHIFT                     5
#define PMIC_DA_VCORE_SSH_ADDR                           MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_SSH_MASK                           0x1
#define PMIC_DA_VCORE_SSH_SHIFT                          6
#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_ADDR             MT6355_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_MASK             0x1
#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_SHIFT            8
#define PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL_ADDR          MT6355_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL_MASK          0x1
#define PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL_SHIFT         4
#define PMIC_RG_BUCK_VCORE_OSC_SEL_DIS_ADDR              MT6355_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_BUCK_VCORE_OSC_SEL_DIS_SHIFT             5
#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_ADDR               MT6355_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_MASK               0x1
#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_SHIFT              6
#define PMIC_RG_BUCK_VCORE_CK_SW_EN_ADDR                 MT6355_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_CK_SW_EN_MASK                 0x1
#define PMIC_RG_BUCK_VCORE_CK_SW_EN_SHIFT                7
#define PMIC_RG_BUCK_VCORE_SSHUB_MODE_ADDR               MT6355_BUCK_VCORE_SSHUB_CON
#define PMIC_RG_BUCK_VCORE_SSHUB_MODE_MASK               0x1
#define PMIC_RG_BUCK_VCORE_SSHUB_MODE_SHIFT              0
#define PMIC_RG_BUCK_VCORE_SSHUB_ON_ADDR                 MT6355_BUCK_VCORE_SSHUB_CON
#define PMIC_RG_BUCK_VCORE_SSHUB_ON_MASK                 0x1
#define PMIC_RG_BUCK_VCORE_SSHUB_ON_SHIFT                1
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR              MT6355_BUCK_VCORE_SSHUB_CON
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_MASK              0x7F
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT             8
#define PMIC_RG_BUCK_VGPU_EN_ADDR                        MT6355_BUCK_VGPU_CON0
#define PMIC_RG_BUCK_VGPU_EN_MASK                        0x1
#define PMIC_RG_BUCK_VGPU_EN_SHIFT                       0
#define PMIC_RG_BUCK_VGPU_LP_ADDR                        MT6355_BUCK_VGPU_CON0
#define PMIC_RG_BUCK_VGPU_LP_MASK                        0x1
#define PMIC_RG_BUCK_VGPU_LP_SHIFT                       1
#define PMIC_RG_BUCK_VGPU_VOSEL_ADDR                     MT6355_BUCK_VGPU_CON1
#define PMIC_RG_BUCK_VGPU_VOSEL_MASK                     0x7F
#define PMIC_RG_BUCK_VGPU_VOSEL_SHIFT                    0
#define PMIC_RG_BUCK_VGPU_VOSEL_SLEEP_ADDR               MT6355_BUCK_VGPU_CON2
#define PMIC_RG_BUCK_VGPU_VOSEL_SLEEP_MASK               0x7F
#define PMIC_RG_BUCK_VGPU_VOSEL_SLEEP_SHIFT              0
#define PMIC_RG_BUCK_VGPU_SFCHG_FRATE_ADDR               MT6355_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_FRATE_MASK               0x7F
#define PMIC_RG_BUCK_VGPU_SFCHG_FRATE_SHIFT              0
#define PMIC_RG_BUCK_VGPU_SFCHG_FEN_ADDR                 MT6355_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_FEN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_SFCHG_FEN_SHIFT                7
#define PMIC_RG_BUCK_VGPU_SFCHG_RRATE_ADDR               MT6355_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_RRATE_MASK               0x7F
#define PMIC_RG_BUCK_VGPU_SFCHG_RRATE_SHIFT              8
#define PMIC_RG_BUCK_VGPU_SFCHG_REN_ADDR                 MT6355_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_REN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_SFCHG_REN_SHIFT                15
#define PMIC_RG_BUCK_VGPU_DVS_EN_TD_ADDR                 MT6355_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_EN_TD_MASK                 0x3
#define PMIC_RG_BUCK_VGPU_DVS_EN_TD_SHIFT                0
#define PMIC_RG_BUCK_VGPU_DVS_EN_CTRL_ADDR               MT6355_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_EN_CTRL_MASK               0x3
#define PMIC_RG_BUCK_VGPU_DVS_EN_CTRL_SHIFT              4
#define PMIC_RG_BUCK_VGPU_DVS_EN_ONCE_ADDR               MT6355_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_EN_ONCE_MASK               0x1
#define PMIC_RG_BUCK_VGPU_DVS_EN_ONCE_SHIFT              6
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_TD_ADDR               MT6355_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_TD_MASK               0x3
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_TD_SHIFT              8
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL_ADDR             MT6355_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL_MASK             0x3
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL_SHIFT            12
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE_ADDR             MT6355_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE_MASK             0x1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE_SHIFT            14
#define PMIC_RG_BUCK_VGPU_SW_OP_EN_ADDR                  MT6355_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_SW_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VGPU_SW_OP_EN_SHIFT                 0
#define PMIC_RG_BUCK_VGPU_HW0_OP_EN_ADDR                 MT6355_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_HW0_OP_EN_SHIFT                1
#define PMIC_RG_BUCK_VGPU_HW1_OP_EN_ADDR                 MT6355_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_HW1_OP_EN_SHIFT                2
#define PMIC_RG_BUCK_VGPU_HW2_OP_EN_ADDR                 MT6355_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_HW2_OP_EN_SHIFT                3
#define PMIC_RG_BUCK_VGPU_OP_EN_SET_ADDR                 MT6355_BUCK_VGPU_OP_EN_SET
#define PMIC_RG_BUCK_VGPU_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_EN_SET_SHIFT                0
#define PMIC_RG_BUCK_VGPU_OP_EN_CLR_ADDR                 MT6355_BUCK_VGPU_OP_EN_CLR
#define PMIC_RG_BUCK_VGPU_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_EN_CLR_SHIFT                0
#define PMIC_RG_BUCK_VGPU_HW0_OP_CFG_ADDR                MT6355_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_BUCK_VGPU_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_BUCK_VGPU_HW1_OP_CFG_ADDR                MT6355_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_BUCK_VGPU_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_BUCK_VGPU_HW2_OP_CFG_ADDR                MT6355_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_BUCK_VGPU_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_BUCK_VGPU_ON_OP_ADDR                     MT6355_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_ON_OP_MASK                     0x1
#define PMIC_RG_BUCK_VGPU_ON_OP_SHIFT                    8
#define PMIC_RG_BUCK_VGPU_LP_OP_ADDR                     MT6355_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_LP_OP_MASK                     0x1
#define PMIC_RG_BUCK_VGPU_LP_OP_SHIFT                    9
#define PMIC_RG_BUCK_VGPU_OP_CFG_SET_ADDR                MT6355_BUCK_VGPU_OP_CFG_SET
#define PMIC_RG_BUCK_VGPU_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_CFG_SET_SHIFT               0
#define PMIC_RG_BUCK_VGPU_OP_CFG_CLR_ADDR                MT6355_BUCK_VGPU_OP_CFG_CLR
#define PMIC_RG_BUCK_VGPU_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_CFG_CLR_SHIFT               0
#define PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_ADDR               MT6355_BUCK_VGPU_SP_CON
#define PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_MASK               0x7F
#define PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_SHIFT              0
#define PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_EN_ADDR            MT6355_BUCK_VGPU_SP_CFG
#define PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_EN_MASK            0x1
#define PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_EN_SHIFT           0
#define PMIC_RG_BUCK_VGPU_SP_ON_VOSEL_MUX_SEL_ADDR       MT6355_BUCK_VGPU_SP_CFG
#define PMIC_RG_BUCK_VGPU_SP_ON_VOSEL_MUX_SEL_MASK       0x1
#define PMIC_RG_BUCK_VGPU_SP_ON_VOSEL_MUX_SEL_SHIFT      1
#define PMIC_RG_BUCK_VGPU_OC_DEG_EN_ADDR                 MT6355_BUCK_VGPU_OC_CFG
#define PMIC_RG_BUCK_VGPU_OC_DEG_EN_MASK                 0x1
#define PMIC_RG_BUCK_VGPU_OC_DEG_EN_SHIFT                1
#define PMIC_RG_BUCK_VGPU_OC_WND_ADDR                    MT6355_BUCK_VGPU_OC_CFG
#define PMIC_RG_BUCK_VGPU_OC_WND_MASK                    0x3
#define PMIC_RG_BUCK_VGPU_OC_WND_SHIFT                   2
#define PMIC_RG_BUCK_VGPU_OC_THD_ADDR                    MT6355_BUCK_VGPU_OC_CFG
#define PMIC_RG_BUCK_VGPU_OC_THD_MASK                    0x3
#define PMIC_RG_BUCK_VGPU_OC_THD_SHIFT                   6
#define PMIC_DA_VGPU_VOSEL_ADDR                          MT6355_BUCK_VGPU_DBG0
#define PMIC_DA_VGPU_VOSEL_MASK                          0x7F
#define PMIC_DA_VGPU_VOSEL_SHIFT                         0
#define PMIC_DA_VGPU_VOSEL_GRAY_ADDR                     MT6355_BUCK_VGPU_DBG0
#define PMIC_DA_VGPU_VOSEL_GRAY_MASK                     0x7F
#define PMIC_DA_VGPU_VOSEL_GRAY_SHIFT                    8
#define PMIC_DA_VGPU_EN_ADDR                             MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_EN_MASK                             0x1
#define PMIC_DA_VGPU_EN_SHIFT                            0
#define PMIC_DA_VGPU_STB_ADDR                            MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_STB_MASK                            0x1
#define PMIC_DA_VGPU_STB_SHIFT                           1
#define PMIC_DA_VGPU_VSLEEP_SEL_ADDR                     MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_VSLEEP_SEL_MASK                     0x1
#define PMIC_DA_VGPU_VSLEEP_SEL_SHIFT                    2
#define PMIC_DA_VGPU_R2R_PDN_ADDR                        MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_R2R_PDN_MASK                        0x1
#define PMIC_DA_VGPU_R2R_PDN_SHIFT                       3
#define PMIC_DA_VGPU_DVS_EN_ADDR                         MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_DVS_EN_MASK                         0x1
#define PMIC_DA_VGPU_DVS_EN_SHIFT                        4
#define PMIC_DA_VGPU_DVS_DOWN_ADDR                       MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_DVS_DOWN_MASK                       0x1
#define PMIC_DA_VGPU_DVS_DOWN_SHIFT                      5
#define PMIC_DA_VGPU_SSH_ADDR                            MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_SSH_MASK                            0x1
#define PMIC_DA_VGPU_SSH_SHIFT                           6
#define PMIC_DA_VGPU_MINFREQ_DISCHARGE_ADDR              MT6355_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_MINFREQ_DISCHARGE_MASK              0x1
#define PMIC_DA_VGPU_MINFREQ_DISCHARGE_SHIFT             8
#define PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL_ADDR           MT6355_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL_MASK           0x1
#define PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL_SHIFT          4
#define PMIC_RG_BUCK_VGPU_OSC_SEL_DIS_ADDR               MT6355_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_BUCK_VGPU_OSC_SEL_DIS_SHIFT              5
#define PMIC_RG_BUCK_VGPU_CK_SW_MODE_ADDR                MT6355_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_CK_SW_MODE_MASK                0x1
#define PMIC_RG_BUCK_VGPU_CK_SW_MODE_SHIFT               6
#define PMIC_RG_BUCK_VGPU_CK_SW_EN_ADDR                  MT6355_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_CK_SW_EN_MASK                  0x1
#define PMIC_RG_BUCK_VGPU_CK_SW_EN_SHIFT                 7
#define PMIC_RG_BUCK_VDRAM1_EN_ADDR                      MT6355_BUCK_VDRAM1_CON0
#define PMIC_RG_BUCK_VDRAM1_EN_MASK                      0x1
#define PMIC_RG_BUCK_VDRAM1_EN_SHIFT                     0
#define PMIC_RG_BUCK_VDRAM1_LP_ADDR                      MT6355_BUCK_VDRAM1_CON0
#define PMIC_RG_BUCK_VDRAM1_LP_MASK                      0x1
#define PMIC_RG_BUCK_VDRAM1_LP_SHIFT                     1
#define PMIC_RG_BUCK_VDRAM1_VOSEL_ADDR                   MT6355_BUCK_VDRAM1_CON1
#define PMIC_RG_BUCK_VDRAM1_VOSEL_MASK                   0x7F
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SHIFT                  0
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_ADDR             MT6355_BUCK_VDRAM1_CON2
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_SHIFT            0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_ADDR             MT6355_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_SHIFT            0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_ADDR               MT6355_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_SHIFT              7
#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_ADDR             MT6355_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_SHIFT            8
#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_ADDR               MT6355_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_SHIFT              15
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_TD_ADDR               MT6355_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_TD_MASK               0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_TD_SHIFT              0
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL_ADDR             MT6355_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL_MASK             0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL_SHIFT            4
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE_ADDR             MT6355_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE_MASK             0x1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE_SHIFT            6
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD_ADDR             MT6355_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD_MASK             0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD_SHIFT            8
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL_ADDR           MT6355_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL_MASK           0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL_SHIFT          12
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE_ADDR           MT6355_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE_MASK           0x1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE_SHIFT          14
#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_ADDR                MT6355_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_MASK                0x1
#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_SHIFT               0
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_ADDR               MT6355_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_SHIFT              1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_ADDR               MT6355_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_SHIFT              2
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_ADDR               MT6355_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_SHIFT              3
#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_ADDR               MT6355_BUCK_VDRAM1_OP_EN_SET
#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_MASK               0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_SHIFT              0
#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_ADDR               MT6355_BUCK_VDRAM1_OP_EN_CLR
#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_MASK               0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_SHIFT              0
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_ADDR              MT6355_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_SHIFT             1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_ADDR              MT6355_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_SHIFT             2
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_ADDR              MT6355_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_SHIFT             3
#define PMIC_RG_BUCK_VDRAM1_ON_OP_ADDR                   MT6355_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_ON_OP_MASK                   0x1
#define PMIC_RG_BUCK_VDRAM1_ON_OP_SHIFT                  8
#define PMIC_RG_BUCK_VDRAM1_LP_OP_ADDR                   MT6355_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_LP_OP_MASK                   0x1
#define PMIC_RG_BUCK_VDRAM1_LP_OP_SHIFT                  9
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_ADDR              MT6355_BUCK_VDRAM1_OP_CFG_SET
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_MASK              0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_SHIFT             0
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_ADDR              MT6355_BUCK_VDRAM1_OP_CFG_CLR
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_MASK              0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_SHIFT             0
#define PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_ADDR             MT6355_BUCK_VDRAM1_SP_CON
#define PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_SHIFT            0
#define PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_EN_ADDR          MT6355_BUCK_VDRAM1_SP_CFG
#define PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_EN_MASK          0x1
#define PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_EN_SHIFT         0
#define PMIC_RG_BUCK_VDRAM1_SP_ON_VOSEL_MUX_SEL_ADDR     MT6355_BUCK_VDRAM1_SP_CFG
#define PMIC_RG_BUCK_VDRAM1_SP_ON_VOSEL_MUX_SEL_MASK     0x1
#define PMIC_RG_BUCK_VDRAM1_SP_ON_VOSEL_MUX_SEL_SHIFT    1
#define PMIC_RG_BUCK_VDRAM1_OC_DEG_EN_ADDR               MT6355_BUCK_VDRAM1_OC_CFG
#define PMIC_RG_BUCK_VDRAM1_OC_DEG_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM1_OC_DEG_EN_SHIFT              1
#define PMIC_RG_BUCK_VDRAM1_OC_WND_ADDR                  MT6355_BUCK_VDRAM1_OC_CFG
#define PMIC_RG_BUCK_VDRAM1_OC_WND_MASK                  0x3
#define PMIC_RG_BUCK_VDRAM1_OC_WND_SHIFT                 2
#define PMIC_RG_BUCK_VDRAM1_OC_THD_ADDR                  MT6355_BUCK_VDRAM1_OC_CFG
#define PMIC_RG_BUCK_VDRAM1_OC_THD_MASK                  0x3
#define PMIC_RG_BUCK_VDRAM1_OC_THD_SHIFT                 6
#define PMIC_DA_VDRAM1_VOSEL_ADDR                        MT6355_BUCK_VDRAM1_DBG0
#define PMIC_DA_VDRAM1_VOSEL_MASK                        0x7F
#define PMIC_DA_VDRAM1_VOSEL_SHIFT                       0
#define PMIC_DA_VDRAM1_VOSEL_GRAY_ADDR                   MT6355_BUCK_VDRAM1_DBG0
#define PMIC_DA_VDRAM1_VOSEL_GRAY_MASK                   0x7F
#define PMIC_DA_VDRAM1_VOSEL_GRAY_SHIFT                  8
#define PMIC_DA_VDRAM1_EN_ADDR                           MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_EN_MASK                           0x1
#define PMIC_DA_VDRAM1_EN_SHIFT                          0
#define PMIC_DA_VDRAM1_STB_ADDR                          MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_STB_MASK                          0x1
#define PMIC_DA_VDRAM1_STB_SHIFT                         1
#define PMIC_DA_VDRAM1_VSLEEP_SEL_ADDR                   MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_VSLEEP_SEL_MASK                   0x1
#define PMIC_DA_VDRAM1_VSLEEP_SEL_SHIFT                  2
#define PMIC_DA_VDRAM1_R2R_PDN_ADDR                      MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_R2R_PDN_MASK                      0x1
#define PMIC_DA_VDRAM1_R2R_PDN_SHIFT                     3
#define PMIC_DA_VDRAM1_DVS_EN_ADDR                       MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_DVS_EN_MASK                       0x1
#define PMIC_DA_VDRAM1_DVS_EN_SHIFT                      4
#define PMIC_DA_VDRAM1_DVS_DOWN_ADDR                     MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_DVS_DOWN_MASK                     0x1
#define PMIC_DA_VDRAM1_DVS_DOWN_SHIFT                    5
#define PMIC_DA_VDRAM1_SSH_ADDR                          MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_SSH_MASK                          0x1
#define PMIC_DA_VDRAM1_SSH_SHIFT                         6
#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_ADDR            MT6355_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_MASK            0x1
#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_SHIFT           8
#define PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL_ADDR         MT6355_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL_MASK         0x1
#define PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL_SHIFT        4
#define PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS_ADDR             MT6355_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS_MASK             0x1
#define PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS_SHIFT            5
#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_ADDR              MT6355_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_MASK              0x1
#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_SHIFT             6
#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_ADDR                MT6355_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_MASK                0x1
#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_SHIFT               7
#define PMIC_RG_BUCK_VDRAM2_EN_ADDR                      MT6355_BUCK_VDRAM2_CON0
#define PMIC_RG_BUCK_VDRAM2_EN_MASK                      0x1
#define PMIC_RG_BUCK_VDRAM2_EN_SHIFT                     0
#define PMIC_RG_BUCK_VDRAM2_LP_ADDR                      MT6355_BUCK_VDRAM2_CON0
#define PMIC_RG_BUCK_VDRAM2_LP_MASK                      0x1
#define PMIC_RG_BUCK_VDRAM2_LP_SHIFT                     1
#define PMIC_RG_BUCK_VDRAM2_VOSEL_ADDR                   MT6355_BUCK_VDRAM2_CON1
#define PMIC_RG_BUCK_VDRAM2_VOSEL_MASK                   0x7F
#define PMIC_RG_BUCK_VDRAM2_VOSEL_SHIFT                  0
#define PMIC_RG_BUCK_VDRAM2_VOSEL_SLEEP_ADDR             MT6355_BUCK_VDRAM2_CON2
#define PMIC_RG_BUCK_VDRAM2_VOSEL_SLEEP_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM2_VOSEL_SLEEP_SHIFT            0
#define PMIC_RG_BUCK_VDRAM2_SFCHG_FRATE_ADDR             MT6355_BUCK_VDRAM2_CFG0
#define PMIC_RG_BUCK_VDRAM2_SFCHG_FRATE_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM2_SFCHG_FRATE_SHIFT            0
#define PMIC_RG_BUCK_VDRAM2_SFCHG_FEN_ADDR               MT6355_BUCK_VDRAM2_CFG0
#define PMIC_RG_BUCK_VDRAM2_SFCHG_FEN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_SFCHG_FEN_SHIFT              7
#define PMIC_RG_BUCK_VDRAM2_SFCHG_RRATE_ADDR             MT6355_BUCK_VDRAM2_CFG0
#define PMIC_RG_BUCK_VDRAM2_SFCHG_RRATE_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM2_SFCHG_RRATE_SHIFT            8
#define PMIC_RG_BUCK_VDRAM2_SFCHG_REN_ADDR               MT6355_BUCK_VDRAM2_CFG0
#define PMIC_RG_BUCK_VDRAM2_SFCHG_REN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_SFCHG_REN_SHIFT              15
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_TD_ADDR               MT6355_BUCK_VDRAM2_CFG1
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_TD_MASK               0x3
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_TD_SHIFT              0
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_CTRL_ADDR             MT6355_BUCK_VDRAM2_CFG1
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_CTRL_MASK             0x3
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_CTRL_SHIFT            4
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_ONCE_ADDR             MT6355_BUCK_VDRAM2_CFG1
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_ONCE_MASK             0x1
#define PMIC_RG_BUCK_VDRAM2_DVS_EN_ONCE_SHIFT            6
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_TD_ADDR             MT6355_BUCK_VDRAM2_CFG1
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_TD_MASK             0x3
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_TD_SHIFT            8
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_CTRL_ADDR           MT6355_BUCK_VDRAM2_CFG1
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_CTRL_MASK           0x3
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_CTRL_SHIFT          12
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_ONCE_ADDR           MT6355_BUCK_VDRAM2_CFG1
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_ONCE_MASK           0x1
#define PMIC_RG_BUCK_VDRAM2_DVS_DOWN_ONCE_SHIFT          14
#define PMIC_RG_BUCK_VDRAM2_SW_OP_EN_ADDR                MT6355_BUCK_VDRAM2_OP_EN
#define PMIC_RG_BUCK_VDRAM2_SW_OP_EN_MASK                0x1
#define PMIC_RG_BUCK_VDRAM2_SW_OP_EN_SHIFT               0
#define PMIC_RG_BUCK_VDRAM2_HW0_OP_EN_ADDR               MT6355_BUCK_VDRAM2_OP_EN
#define PMIC_RG_BUCK_VDRAM2_HW0_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_HW0_OP_EN_SHIFT              1
#define PMIC_RG_BUCK_VDRAM2_HW1_OP_EN_ADDR               MT6355_BUCK_VDRAM2_OP_EN
#define PMIC_RG_BUCK_VDRAM2_HW1_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_HW1_OP_EN_SHIFT              2
#define PMIC_RG_BUCK_VDRAM2_HW2_OP_EN_ADDR               MT6355_BUCK_VDRAM2_OP_EN
#define PMIC_RG_BUCK_VDRAM2_HW2_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_HW2_OP_EN_SHIFT              3
#define PMIC_RG_BUCK_VDRAM2_OP_EN_SET_ADDR               MT6355_BUCK_VDRAM2_OP_EN_SET
#define PMIC_RG_BUCK_VDRAM2_OP_EN_SET_MASK               0xFFFF
#define PMIC_RG_BUCK_VDRAM2_OP_EN_SET_SHIFT              0
#define PMIC_RG_BUCK_VDRAM2_OP_EN_CLR_ADDR               MT6355_BUCK_VDRAM2_OP_EN_CLR
#define PMIC_RG_BUCK_VDRAM2_OP_EN_CLR_MASK               0xFFFF
#define PMIC_RG_BUCK_VDRAM2_OP_EN_CLR_SHIFT              0
#define PMIC_RG_BUCK_VDRAM2_HW0_OP_CFG_ADDR              MT6355_BUCK_VDRAM2_OP_CFG
#define PMIC_RG_BUCK_VDRAM2_HW0_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VDRAM2_HW0_OP_CFG_SHIFT             1
#define PMIC_RG_BUCK_VDRAM2_HW1_OP_CFG_ADDR              MT6355_BUCK_VDRAM2_OP_CFG
#define PMIC_RG_BUCK_VDRAM2_HW1_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VDRAM2_HW1_OP_CFG_SHIFT             2
#define PMIC_RG_BUCK_VDRAM2_HW2_OP_CFG_ADDR              MT6355_BUCK_VDRAM2_OP_CFG
#define PMIC_RG_BUCK_VDRAM2_HW2_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VDRAM2_HW2_OP_CFG_SHIFT             3
#define PMIC_RG_BUCK_VDRAM2_ON_OP_ADDR                   MT6355_BUCK_VDRAM2_OP_CFG
#define PMIC_RG_BUCK_VDRAM2_ON_OP_MASK                   0x1
#define PMIC_RG_BUCK_VDRAM2_ON_OP_SHIFT                  8
#define PMIC_RG_BUCK_VDRAM2_LP_OP_ADDR                   MT6355_BUCK_VDRAM2_OP_CFG
#define PMIC_RG_BUCK_VDRAM2_LP_OP_MASK                   0x1
#define PMIC_RG_BUCK_VDRAM2_LP_OP_SHIFT                  9
#define PMIC_RG_BUCK_VDRAM2_OP_CFG_SET_ADDR              MT6355_BUCK_VDRAM2_OP_CFG_SET
#define PMIC_RG_BUCK_VDRAM2_OP_CFG_SET_MASK              0xFFFF
#define PMIC_RG_BUCK_VDRAM2_OP_CFG_SET_SHIFT             0
#define PMIC_RG_BUCK_VDRAM2_OP_CFG_CLR_ADDR              MT6355_BUCK_VDRAM2_OP_CFG_CLR
#define PMIC_RG_BUCK_VDRAM2_OP_CFG_CLR_MASK              0xFFFF
#define PMIC_RG_BUCK_VDRAM2_OP_CFG_CLR_SHIFT             0
#define PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_ADDR             MT6355_BUCK_VDRAM2_SP_CON
#define PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_MASK             0x7F
#define PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_SHIFT            0
#define PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_EN_ADDR          MT6355_BUCK_VDRAM2_SP_CFG
#define PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_EN_MASK          0x1
#define PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_EN_SHIFT         0
#define PMIC_RG_BUCK_VDRAM2_SP_ON_VOSEL_MUX_SEL_ADDR     MT6355_BUCK_VDRAM2_SP_CFG
#define PMIC_RG_BUCK_VDRAM2_SP_ON_VOSEL_MUX_SEL_MASK     0x1
#define PMIC_RG_BUCK_VDRAM2_SP_ON_VOSEL_MUX_SEL_SHIFT    1
#define PMIC_RG_BUCK_VDRAM2_OC_DEG_EN_ADDR               MT6355_BUCK_VDRAM2_OC_CFG
#define PMIC_RG_BUCK_VDRAM2_OC_DEG_EN_MASK               0x1
#define PMIC_RG_BUCK_VDRAM2_OC_DEG_EN_SHIFT              1
#define PMIC_RG_BUCK_VDRAM2_OC_WND_ADDR                  MT6355_BUCK_VDRAM2_OC_CFG
#define PMIC_RG_BUCK_VDRAM2_OC_WND_MASK                  0x3
#define PMIC_RG_BUCK_VDRAM2_OC_WND_SHIFT                 2
#define PMIC_RG_BUCK_VDRAM2_OC_THD_ADDR                  MT6355_BUCK_VDRAM2_OC_CFG
#define PMIC_RG_BUCK_VDRAM2_OC_THD_MASK                  0x3
#define PMIC_RG_BUCK_VDRAM2_OC_THD_SHIFT                 6
#define PMIC_DA_VDRAM2_VOSEL_ADDR                        MT6355_BUCK_VDRAM2_DBG0
#define PMIC_DA_VDRAM2_VOSEL_MASK                        0x7F
#define PMIC_DA_VDRAM2_VOSEL_SHIFT                       0
#define PMIC_DA_VDRAM2_VOSEL_GRAY_ADDR                   MT6355_BUCK_VDRAM2_DBG0
#define PMIC_DA_VDRAM2_VOSEL_GRAY_MASK                   0x7F
#define PMIC_DA_VDRAM2_VOSEL_GRAY_SHIFT                  8
#define PMIC_DA_VDRAM2_EN_ADDR                           MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_EN_MASK                           0x1
#define PMIC_DA_VDRAM2_EN_SHIFT                          0
#define PMIC_DA_VDRAM2_STB_ADDR                          MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_STB_MASK                          0x1
#define PMIC_DA_VDRAM2_STB_SHIFT                         1
#define PMIC_DA_VDRAM2_VSLEEP_SEL_ADDR                   MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_VSLEEP_SEL_MASK                   0x1
#define PMIC_DA_VDRAM2_VSLEEP_SEL_SHIFT                  2
#define PMIC_DA_VDRAM2_R2R_PDN_ADDR                      MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_R2R_PDN_MASK                      0x1
#define PMIC_DA_VDRAM2_R2R_PDN_SHIFT                     3
#define PMIC_DA_VDRAM2_DVS_EN_ADDR                       MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_DVS_EN_MASK                       0x1
#define PMIC_DA_VDRAM2_DVS_EN_SHIFT                      4
#define PMIC_DA_VDRAM2_DVS_DOWN_ADDR                     MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_DVS_DOWN_MASK                     0x1
#define PMIC_DA_VDRAM2_DVS_DOWN_SHIFT                    5
#define PMIC_DA_VDRAM2_SSH_ADDR                          MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_SSH_MASK                          0x1
#define PMIC_DA_VDRAM2_SSH_SHIFT                         6
#define PMIC_DA_VDRAM2_MINFREQ_DISCHARGE_ADDR            MT6355_BUCK_VDRAM2_DBG1
#define PMIC_DA_VDRAM2_MINFREQ_DISCHARGE_MASK            0x1
#define PMIC_DA_VDRAM2_MINFREQ_DISCHARGE_SHIFT           8
#define PMIC_RG_BUCK_VDRAM2_OC_FLAG_CLR_SEL_ADDR         MT6355_BUCK_VDRAM2_DBG2
#define PMIC_RG_BUCK_VDRAM2_OC_FLAG_CLR_SEL_MASK         0x1
#define PMIC_RG_BUCK_VDRAM2_OC_FLAG_CLR_SEL_SHIFT        4
#define PMIC_RG_BUCK_VDRAM2_OSC_SEL_DIS_ADDR             MT6355_BUCK_VDRAM2_DBG2
#define PMIC_RG_BUCK_VDRAM2_OSC_SEL_DIS_MASK             0x1
#define PMIC_RG_BUCK_VDRAM2_OSC_SEL_DIS_SHIFT            5
#define PMIC_RG_BUCK_VDRAM2_CK_SW_MODE_ADDR              MT6355_BUCK_VDRAM2_DBG2
#define PMIC_RG_BUCK_VDRAM2_CK_SW_MODE_MASK              0x1
#define PMIC_RG_BUCK_VDRAM2_CK_SW_MODE_SHIFT             6
#define PMIC_RG_BUCK_VDRAM2_CK_SW_EN_ADDR                MT6355_BUCK_VDRAM2_DBG2
#define PMIC_RG_BUCK_VDRAM2_CK_SW_EN_MASK                0x1
#define PMIC_RG_BUCK_VDRAM2_CK_SW_EN_SHIFT               7
#define PMIC_RG_BUCK_VMODEM_EN_ADDR                      MT6355_BUCK_VMODEM_CON0
#define PMIC_RG_BUCK_VMODEM_EN_MASK                      0x1
#define PMIC_RG_BUCK_VMODEM_EN_SHIFT                     0
#define PMIC_RG_BUCK_VMODEM_LP_ADDR                      MT6355_BUCK_VMODEM_CON0
#define PMIC_RG_BUCK_VMODEM_LP_MASK                      0x1
#define PMIC_RG_BUCK_VMODEM_LP_SHIFT                     1
#define PMIC_RG_BUCK_VMODEM_VOSEL_ADDR                   MT6355_BUCK_VMODEM_CON1
#define PMIC_RG_BUCK_VMODEM_VOSEL_MASK                   0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT                  0
#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR             MT6355_BUCK_VMODEM_CON2
#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK             0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT            0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_ADDR             MT6355_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_MASK             0x7F
#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_SHIFT            0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_ADDR               MT6355_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_SHIFT              7
#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_ADDR             MT6355_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_MASK             0x7F
#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_SHIFT            8
#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_ADDR               MT6355_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_SHIFT              15
#define PMIC_RG_BUCK_VMODEM_DVS_EN_TD_ADDR               MT6355_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_TD_MASK               0x3
#define PMIC_RG_BUCK_VMODEM_DVS_EN_TD_SHIFT              0
#define PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL_ADDR             MT6355_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL_MASK             0x3
#define PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL_SHIFT            4
#define PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE_ADDR             MT6355_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE_MASK             0x1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE_SHIFT            6
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD_ADDR             MT6355_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD_MASK             0x3
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD_SHIFT            8
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL_ADDR           MT6355_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL_MASK           0x3
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL_SHIFT          12
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE_ADDR           MT6355_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE_MASK           0x1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE_SHIFT          14
#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_ADDR                MT6355_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK                0x1
#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT               0
#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_ADDR               MT6355_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT              1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_ADDR               MT6355_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT              2
#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_ADDR               MT6355_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT              3
#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR               MT6355_BUCK_VMODEM_OP_EN_SET
#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK               0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT              0
#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR               MT6355_BUCK_VMODEM_OP_EN_CLR
#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK               0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT              0
#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR              MT6355_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT             1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR              MT6355_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT             2
#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR              MT6355_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK              0x1
#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT             3
#define PMIC_RG_BUCK_VMODEM_ON_OP_ADDR                   MT6355_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_ON_OP_MASK                   0x1
#define PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT                  8
#define PMIC_RG_BUCK_VMODEM_LP_OP_ADDR                   MT6355_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_LP_OP_MASK                   0x1
#define PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT                  9
#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR              MT6355_BUCK_VMODEM_OP_CFG_SET
#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK              0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT             0
#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR              MT6355_BUCK_VMODEM_OP_CFG_CLR
#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK              0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT             0
#define PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_ADDR             MT6355_BUCK_VMODEM_SP_CON
#define PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_MASK             0x7F
#define PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_SHIFT            0
#define PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_EN_ADDR          MT6355_BUCK_VMODEM_SP_CFG
#define PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_EN_MASK          0x1
#define PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_EN_SHIFT         0
#define PMIC_RG_BUCK_VMODEM_SP_ON_VOSEL_MUX_SEL_ADDR     MT6355_BUCK_VMODEM_SP_CFG
#define PMIC_RG_BUCK_VMODEM_SP_ON_VOSEL_MUX_SEL_MASK     0x1
#define PMIC_RG_BUCK_VMODEM_SP_ON_VOSEL_MUX_SEL_SHIFT    1
#define PMIC_RG_BUCK_VMODEM_OC_DEG_EN_ADDR               MT6355_BUCK_VMODEM_OC_CFG
#define PMIC_RG_BUCK_VMODEM_OC_DEG_EN_MASK               0x1
#define PMIC_RG_BUCK_VMODEM_OC_DEG_EN_SHIFT              1
#define PMIC_RG_BUCK_VMODEM_OC_WND_ADDR                  MT6355_BUCK_VMODEM_OC_CFG
#define PMIC_RG_BUCK_VMODEM_OC_WND_MASK                  0x3
#define PMIC_RG_BUCK_VMODEM_OC_WND_SHIFT                 2
#define PMIC_RG_BUCK_VMODEM_OC_THD_ADDR                  MT6355_BUCK_VMODEM_OC_CFG
#define PMIC_RG_BUCK_VMODEM_OC_THD_MASK                  0x3
#define PMIC_RG_BUCK_VMODEM_OC_THD_SHIFT                 6
#define PMIC_DA_VMODEM_VOSEL_ADDR                        MT6355_BUCK_VMODEM_DBG0
#define PMIC_DA_VMODEM_VOSEL_MASK                        0x7F
#define PMIC_DA_VMODEM_VOSEL_SHIFT                       0
#define PMIC_DA_VMODEM_VOSEL_GRAY_ADDR                   MT6355_BUCK_VMODEM_DBG0
#define PMIC_DA_VMODEM_VOSEL_GRAY_MASK                   0x7F
#define PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT                  8
#define PMIC_DA_VMODEM_EN_ADDR                           MT6355_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_EN_MASK                           0x1
#define PMIC_DA_VMODEM_EN_SHIFT                          0
#define PMIC_DA_VMODEM_STB_ADDR                          MT6355_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_STB_MASK                          0x1
#define PMIC_DA_VMODEM_STB_SHIFT                         1
#define PMIC_DA_VMODEM_VSLEEP_SEL_ADDR                   MT6355_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_VSLEEP_SEL_MASK                   0x1
#define PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT                  2
#define PMIC_DA_VMODEM_R2R_PDN_ADDR                      MT6355_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_R2R_PDN_MASK                      0x1
#define PMIC_DA_VMODEM_R2R_PDN_SHIFT                     3
#define PMIC_DA_VMODEM_DVS_EN_ADDR                       MT6355_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_DVS_EN_MASK                       0x1
#define PMIC_DA_VMODEM_DVS_EN_SHIFT                      4
#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_ADDR            MT6355_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_MASK            0x1
#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_SHIFT           8
#define PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL_ADDR         MT6355_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL_MASK         0x1
#define PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL_SHIFT        4
#define PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS_ADDR             MT6355_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS_MASK             0x1
#define PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS_SHIFT            5
#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_ADDR              MT6355_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_MASK              0x1
#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_SHIFT             6
#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_ADDR                MT6355_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_MASK                0x1
#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_SHIFT               7
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC0_ADDR              MT6355_BUCK_VMODEM_DLC_CON0
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC0_MASK              0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC0_SHIFT             0
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC1_ADDR              MT6355_BUCK_VMODEM_DLC_CON0
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC1_MASK              0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC1_SHIFT             8
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC2_ADDR              MT6355_BUCK_VMODEM_DLC_CON1
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC2_MASK              0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_DLC2_SHIFT             0
#define PMIC_RG_BUCK_VMODEM_DLC0_ADDR                    MT6355_BUCK_VMODEM_DLC_CON2
#define PMIC_RG_BUCK_VMODEM_DLC0_MASK                    0x7
#define PMIC_RG_BUCK_VMODEM_DLC0_SHIFT                   0
#define PMIC_RG_BUCK_VMODEM_DLC1_ADDR                    MT6355_BUCK_VMODEM_DLC_CON2
#define PMIC_RG_BUCK_VMODEM_DLC1_MASK                    0x7
#define PMIC_RG_BUCK_VMODEM_DLC1_SHIFT                   4
#define PMIC_RG_BUCK_VMODEM_DLC2_ADDR                    MT6355_BUCK_VMODEM_DLC_CON2
#define PMIC_RG_BUCK_VMODEM_DLC2_MASK                    0x7
#define PMIC_RG_BUCK_VMODEM_DLC2_SHIFT                   8
#define PMIC_RG_BUCK_VMODEM_DLC3_ADDR                    MT6355_BUCK_VMODEM_DLC_CON2
#define PMIC_RG_BUCK_VMODEM_DLC3_MASK                    0x7
#define PMIC_RG_BUCK_VMODEM_DLC3_SHIFT                   12
#define PMIC_RG_BUCK_VMODEM_DLC_MAP_EN_ADDR              MT6355_BUCK_VMODEM_DLC_CON3
#define PMIC_RG_BUCK_VMODEM_DLC_MAP_EN_MASK              0x1
#define PMIC_RG_BUCK_VMODEM_DLC_MAP_EN_SHIFT             0
#define PMIC_RG_BUCK_VMODEM_DLC_ADDR                     MT6355_BUCK_VMODEM_DLC_CON3
#define PMIC_RG_BUCK_VMODEM_DLC_MASK                     0x7
#define PMIC_RG_BUCK_VMODEM_DLC_SHIFT                    8
#define PMIC_DA_VMODEM_DLC_ADDR                          MT6355_BUCK_VMODEM_DLC_CON3
#define PMIC_DA_VMODEM_DLC_MASK                          0x7
#define PMIC_DA_VMODEM_DLC_SHIFT                         12
#define PMIC_RG_BUCK_VS1_EN_ADDR                         MT6355_BUCK_VS1_CON0
#define PMIC_RG_BUCK_VS1_EN_MASK                         0x1
#define PMIC_RG_BUCK_VS1_EN_SHIFT                        0
#define PMIC_RG_BUCK_VS1_LP_ADDR                         MT6355_BUCK_VS1_CON0
#define PMIC_RG_BUCK_VS1_LP_MASK                         0x1
#define PMIC_RG_BUCK_VS1_LP_SHIFT                        1
#define PMIC_RG_BUCK_VS1_VOSEL_ADDR                      MT6355_BUCK_VS1_CON1
#define PMIC_RG_BUCK_VS1_VOSEL_MASK                      0x7F
#define PMIC_RG_BUCK_VS1_VOSEL_SHIFT                     0
#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_ADDR                MT6355_BUCK_VS1_CON2
#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_MASK                0x7F
#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_SHIFT               0
#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_ADDR                MT6355_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_MASK                0x7F
#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_SHIFT               0
#define PMIC_RG_BUCK_VS1_SFCHG_FEN_ADDR                  MT6355_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_FEN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_SFCHG_FEN_SHIFT                 7
#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_ADDR                MT6355_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_MASK                0x7F
#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_SHIFT               8
#define PMIC_RG_BUCK_VS1_SFCHG_REN_ADDR                  MT6355_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_REN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_SFCHG_REN_SHIFT                 15
#define PMIC_RG_BUCK_VS1_DVS_EN_TD_ADDR                  MT6355_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_EN_TD_MASK                  0x3
#define PMIC_RG_BUCK_VS1_DVS_EN_TD_SHIFT                 0
#define PMIC_RG_BUCK_VS1_DVS_EN_CTRL_ADDR                MT6355_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_EN_CTRL_MASK                0x3
#define PMIC_RG_BUCK_VS1_DVS_EN_CTRL_SHIFT               4
#define PMIC_RG_BUCK_VS1_DVS_EN_ONCE_ADDR                MT6355_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_EN_ONCE_MASK                0x1
#define PMIC_RG_BUCK_VS1_DVS_EN_ONCE_SHIFT               6
#define PMIC_RG_BUCK_VS1_DVS_DOWN_TD_ADDR                MT6355_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_TD_MASK                0x3
#define PMIC_RG_BUCK_VS1_DVS_DOWN_TD_SHIFT               8
#define PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL_ADDR              MT6355_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL_MASK              0x3
#define PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL_SHIFT             12
#define PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE_ADDR              MT6355_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE_MASK              0x1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE_SHIFT             14
#define PMIC_RG_BUCK_VS1_SW_OP_EN_ADDR                   MT6355_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_SW_OP_EN_MASK                   0x1
#define PMIC_RG_BUCK_VS1_SW_OP_EN_SHIFT                  0
#define PMIC_RG_BUCK_VS1_HW0_OP_EN_ADDR                  MT6355_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_BUCK_VS1_HW1_OP_EN_ADDR                  MT6355_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_BUCK_VS1_HW2_OP_EN_ADDR                  MT6355_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_BUCK_VS1_OP_EN_SET_ADDR                  MT6355_BUCK_VS1_OP_EN_SET
#define PMIC_RG_BUCK_VS1_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_BUCK_VS1_OP_EN_SET_SHIFT                 0
#define PMIC_RG_BUCK_VS1_OP_EN_CLR_ADDR                  MT6355_BUCK_VS1_OP_EN_CLR
#define PMIC_RG_BUCK_VS1_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_BUCK_VS1_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_ADDR                 MT6355_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_ADDR                 MT6355_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_ADDR                 MT6355_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_BUCK_VS1_ON_OP_ADDR                      MT6355_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_ON_OP_MASK                      0x1
#define PMIC_RG_BUCK_VS1_ON_OP_SHIFT                     8
#define PMIC_RG_BUCK_VS1_LP_OP_ADDR                      MT6355_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_LP_OP_MASK                      0x1
#define PMIC_RG_BUCK_VS1_LP_OP_SHIFT                     9
#define PMIC_RG_BUCK_VS1_OP_CFG_SET_ADDR                 MT6355_BUCK_VS1_OP_CFG_SET
#define PMIC_RG_BUCK_VS1_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_BUCK_VS1_OP_CFG_SET_SHIFT                0
#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_ADDR                 MT6355_BUCK_VS1_OP_CFG_CLR
#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_SHIFT                0
#define PMIC_RG_BUCK_VS1_SP_SW_VOSEL_ADDR                MT6355_BUCK_VS1_SP_CON
#define PMIC_RG_BUCK_VS1_SP_SW_VOSEL_MASK                0x7F
#define PMIC_RG_BUCK_VS1_SP_SW_VOSEL_SHIFT               0
#define PMIC_RG_BUCK_VS1_SP_SW_VOSEL_EN_ADDR             MT6355_BUCK_VS1_SP_CFG
#define PMIC_RG_BUCK_VS1_SP_SW_VOSEL_EN_MASK             0x1
#define PMIC_RG_BUCK_VS1_SP_SW_VOSEL_EN_SHIFT            0
#define PMIC_RG_BUCK_VS1_SP_ON_VOSEL_MUX_SEL_ADDR        MT6355_BUCK_VS1_SP_CFG
#define PMIC_RG_BUCK_VS1_SP_ON_VOSEL_MUX_SEL_MASK        0x1
#define PMIC_RG_BUCK_VS1_SP_ON_VOSEL_MUX_SEL_SHIFT       1
#define PMIC_RG_BUCK_VS1_OC_DEG_EN_ADDR                  MT6355_BUCK_VS1_OC_CFG
#define PMIC_RG_BUCK_VS1_OC_DEG_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS1_OC_DEG_EN_SHIFT                 1
#define PMIC_RG_BUCK_VS1_OC_WND_ADDR                     MT6355_BUCK_VS1_OC_CFG
#define PMIC_RG_BUCK_VS1_OC_WND_MASK                     0x3
#define PMIC_RG_BUCK_VS1_OC_WND_SHIFT                    2
#define PMIC_RG_BUCK_VS1_OC_THD_ADDR                     MT6355_BUCK_VS1_OC_CFG
#define PMIC_RG_BUCK_VS1_OC_THD_MASK                     0x3
#define PMIC_RG_BUCK_VS1_OC_THD_SHIFT                    6
#define PMIC_DA_VS1_VOSEL_ADDR                           MT6355_BUCK_VS1_DBG0
#define PMIC_DA_VS1_VOSEL_MASK                           0x7F
#define PMIC_DA_VS1_VOSEL_SHIFT                          0
#define PMIC_DA_VS1_VOSEL_GRAY_ADDR                      MT6355_BUCK_VS1_DBG0
#define PMIC_DA_VS1_VOSEL_GRAY_MASK                      0x7F
#define PMIC_DA_VS1_VOSEL_GRAY_SHIFT                     8
#define PMIC_DA_VS1_EN_ADDR                              MT6355_BUCK_VS1_DBG1
#define PMIC_DA_VS1_EN_MASK                              0x1
#define PMIC_DA_VS1_EN_SHIFT                             0
#define PMIC_DA_VS1_STB_ADDR                             MT6355_BUCK_VS1_DBG1
#define PMIC_DA_VS1_STB_MASK                             0x1
#define PMIC_DA_VS1_STB_SHIFT                            1
#define PMIC_DA_VS1_VSLEEP_SEL_ADDR                      MT6355_BUCK_VS1_DBG1
#define PMIC_DA_VS1_VSLEEP_SEL_MASK                      0x1
#define PMIC_DA_VS1_VSLEEP_SEL_SHIFT                     2
#define PMIC_DA_VS1_R2R_PDN_ADDR                         MT6355_BUCK_VS1_DBG1
#define PMIC_DA_VS1_R2R_PDN_MASK                         0x1
#define PMIC_DA_VS1_R2R_PDN_SHIFT                        3
#define PMIC_DA_VS1_DVS_EN_ADDR                          MT6355_BUCK_VS1_DBG1
#define PMIC_DA_VS1_DVS_EN_MASK                          0x1
#define PMIC_DA_VS1_DVS_EN_SHIFT                         4
#define PMIC_DA_VS1_MINFREQ_DISCHARGE_ADDR               MT6355_BUCK_VS1_DBG1
#define PMIC_DA_VS1_MINFREQ_DISCHARGE_MASK               0x1
#define PMIC_DA_VS1_MINFREQ_DISCHARGE_SHIFT              8
#define PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL_ADDR            MT6355_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL_MASK            0x1
#define PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL_SHIFT           4
#define PMIC_RG_BUCK_VS1_OSC_SEL_DIS_ADDR                MT6355_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_BUCK_VS1_OSC_SEL_DIS_SHIFT               5
#define PMIC_RG_BUCK_VS1_CK_SW_MODE_ADDR                 MT6355_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_BUCK_VS1_CK_SW_MODE_SHIFT                6
#define PMIC_RG_BUCK_VS1_CK_SW_EN_ADDR                   MT6355_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_CK_SW_EN_MASK                   0x1
#define PMIC_RG_BUCK_VS1_CK_SW_EN_SHIFT                  7
#define PMIC_RG_BUCK_VS1_VOTER_EN_ADDR                   MT6355_BUCK_VS1_VOTER
#define PMIC_RG_BUCK_VS1_VOTER_EN_MASK                   0xFF
#define PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT                  0
#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_ADDR               MT6355_BUCK_VS1_VOTER_SET
#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK               0xFF
#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT              0
#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_ADDR               MT6355_BUCK_VS1_VOTER_CLR
#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK               0xFF
#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT              0
#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_ADDR                MT6355_BUCK_VS1_VOTER_CFG
#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK                0x7F
#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT               0
#define PMIC_RG_BUCK_VS2_EN_ADDR                         MT6355_BUCK_VS2_CON0
#define PMIC_RG_BUCK_VS2_EN_MASK                         0x1
#define PMIC_RG_BUCK_VS2_EN_SHIFT                        0
#define PMIC_RG_BUCK_VS2_LP_ADDR                         MT6355_BUCK_VS2_CON0
#define PMIC_RG_BUCK_VS2_LP_MASK                         0x1
#define PMIC_RG_BUCK_VS2_LP_SHIFT                        1
#define PMIC_RG_BUCK_VS2_VOSEL_ADDR                      MT6355_BUCK_VS2_CON1
#define PMIC_RG_BUCK_VS2_VOSEL_MASK                      0x7F
#define PMIC_RG_BUCK_VS2_VOSEL_SHIFT                     0
#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_ADDR                MT6355_BUCK_VS2_CON2
#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK                0x7F
#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT               0
#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_ADDR                MT6355_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_MASK                0x7F
#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_SHIFT               0
#define PMIC_RG_BUCK_VS2_SFCHG_FEN_ADDR                  MT6355_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_FEN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_SFCHG_FEN_SHIFT                 7
#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_ADDR                MT6355_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_MASK                0x7F
#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_SHIFT               8
#define PMIC_RG_BUCK_VS2_SFCHG_REN_ADDR                  MT6355_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_REN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_SFCHG_REN_SHIFT                 15
#define PMIC_RG_BUCK_VS2_DVS_EN_TD_ADDR                  MT6355_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_EN_TD_MASK                  0x3
#define PMIC_RG_BUCK_VS2_DVS_EN_TD_SHIFT                 0
#define PMIC_RG_BUCK_VS2_DVS_EN_CTRL_ADDR                MT6355_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_EN_CTRL_MASK                0x3
#define PMIC_RG_BUCK_VS2_DVS_EN_CTRL_SHIFT               4
#define PMIC_RG_BUCK_VS2_DVS_EN_ONCE_ADDR                MT6355_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_EN_ONCE_MASK                0x1
#define PMIC_RG_BUCK_VS2_DVS_EN_ONCE_SHIFT               6
#define PMIC_RG_BUCK_VS2_DVS_DOWN_TD_ADDR                MT6355_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_TD_MASK                0x3
#define PMIC_RG_BUCK_VS2_DVS_DOWN_TD_SHIFT               8
#define PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL_ADDR              MT6355_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL_MASK              0x3
#define PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL_SHIFT             12
#define PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE_ADDR              MT6355_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE_MASK              0x1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE_SHIFT             14
#define PMIC_RG_BUCK_VS2_SW_OP_EN_ADDR                   MT6355_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_SW_OP_EN_MASK                   0x1
#define PMIC_RG_BUCK_VS2_SW_OP_EN_SHIFT                  0
#define PMIC_RG_BUCK_VS2_HW0_OP_EN_ADDR                  MT6355_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_BUCK_VS2_HW1_OP_EN_ADDR                  MT6355_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_BUCK_VS2_HW2_OP_EN_ADDR                  MT6355_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_BUCK_VS2_OP_EN_SET_ADDR                  MT6355_BUCK_VS2_OP_EN_SET
#define PMIC_RG_BUCK_VS2_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_BUCK_VS2_OP_EN_SET_SHIFT                 0
#define PMIC_RG_BUCK_VS2_OP_EN_CLR_ADDR                  MT6355_BUCK_VS2_OP_EN_CLR
#define PMIC_RG_BUCK_VS2_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_BUCK_VS2_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_ADDR                 MT6355_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_ADDR                 MT6355_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_ADDR                 MT6355_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_BUCK_VS2_ON_OP_ADDR                      MT6355_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_ON_OP_MASK                      0x1
#define PMIC_RG_BUCK_VS2_ON_OP_SHIFT                     8
#define PMIC_RG_BUCK_VS2_LP_OP_ADDR                      MT6355_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_LP_OP_MASK                      0x1
#define PMIC_RG_BUCK_VS2_LP_OP_SHIFT                     9
#define PMIC_RG_BUCK_VS2_OP_CFG_SET_ADDR                 MT6355_BUCK_VS2_OP_CFG_SET
#define PMIC_RG_BUCK_VS2_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_BUCK_VS2_OP_CFG_SET_SHIFT                0
#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_ADDR                 MT6355_BUCK_VS2_OP_CFG_CLR
#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_SHIFT                0
#define PMIC_RG_BUCK_VS2_SP_SW_VOSEL_ADDR                MT6355_BUCK_VS2_SP_CON
#define PMIC_RG_BUCK_VS2_SP_SW_VOSEL_MASK                0x7F
#define PMIC_RG_BUCK_VS2_SP_SW_VOSEL_SHIFT               0
#define PMIC_RG_BUCK_VS2_SP_SW_VOSEL_EN_ADDR             MT6355_BUCK_VS2_SP_CFG
#define PMIC_RG_BUCK_VS2_SP_SW_VOSEL_EN_MASK             0x1
#define PMIC_RG_BUCK_VS2_SP_SW_VOSEL_EN_SHIFT            0
#define PMIC_RG_BUCK_VS2_SP_ON_VOSEL_MUX_SEL_ADDR        MT6355_BUCK_VS2_SP_CFG
#define PMIC_RG_BUCK_VS2_SP_ON_VOSEL_MUX_SEL_MASK        0x1
#define PMIC_RG_BUCK_VS2_SP_ON_VOSEL_MUX_SEL_SHIFT       1
#define PMIC_RG_BUCK_VS2_OC_DEG_EN_ADDR                  MT6355_BUCK_VS2_OC_CFG
#define PMIC_RG_BUCK_VS2_OC_DEG_EN_MASK                  0x1
#define PMIC_RG_BUCK_VS2_OC_DEG_EN_SHIFT                 1
#define PMIC_RG_BUCK_VS2_OC_WND_ADDR                     MT6355_BUCK_VS2_OC_CFG
#define PMIC_RG_BUCK_VS2_OC_WND_MASK                     0x3
#define PMIC_RG_BUCK_VS2_OC_WND_SHIFT                    2
#define PMIC_RG_BUCK_VS2_OC_THD_ADDR                     MT6355_BUCK_VS2_OC_CFG
#define PMIC_RG_BUCK_VS2_OC_THD_MASK                     0x3
#define PMIC_RG_BUCK_VS2_OC_THD_SHIFT                    6
#define PMIC_DA_VS2_VOSEL_ADDR                           MT6355_BUCK_VS2_DBG0
#define PMIC_DA_VS2_VOSEL_MASK                           0x7F
#define PMIC_DA_VS2_VOSEL_SHIFT                          0
#define PMIC_DA_VS2_VOSEL_GRAY_ADDR                      MT6355_BUCK_VS2_DBG0
#define PMIC_DA_VS2_VOSEL_GRAY_MASK                      0x7F
#define PMIC_DA_VS2_VOSEL_GRAY_SHIFT                     8
#define PMIC_DA_VS2_EN_ADDR                              MT6355_BUCK_VS2_DBG1
#define PMIC_DA_VS2_EN_MASK                              0x1
#define PMIC_DA_VS2_EN_SHIFT                             0
#define PMIC_DA_VS2_STB_ADDR                             MT6355_BUCK_VS2_DBG1
#define PMIC_DA_VS2_STB_MASK                             0x1
#define PMIC_DA_VS2_STB_SHIFT                            1
#define PMIC_DA_VS2_VSLEEP_SEL_ADDR                      MT6355_BUCK_VS2_DBG1
#define PMIC_DA_VS2_VSLEEP_SEL_MASK                      0x1
#define PMIC_DA_VS2_VSLEEP_SEL_SHIFT                     2
#define PMIC_DA_VS2_R2R_PDN_ADDR                         MT6355_BUCK_VS2_DBG1
#define PMIC_DA_VS2_R2R_PDN_MASK                         0x1
#define PMIC_DA_VS2_R2R_PDN_SHIFT                        3
#define PMIC_DA_VS2_DVS_EN_ADDR                          MT6355_BUCK_VS2_DBG1
#define PMIC_DA_VS2_DVS_EN_MASK                          0x1
#define PMIC_DA_VS2_DVS_EN_SHIFT                         4
#define PMIC_DA_VS2_MINFREQ_DISCHARGE_ADDR               MT6355_BUCK_VS2_DBG1
#define PMIC_DA_VS2_MINFREQ_DISCHARGE_MASK               0x1
#define PMIC_DA_VS2_MINFREQ_DISCHARGE_SHIFT              8
#define PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL_ADDR            MT6355_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL_MASK            0x1
#define PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL_SHIFT           4
#define PMIC_RG_BUCK_VS2_OSC_SEL_DIS_ADDR                MT6355_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_BUCK_VS2_OSC_SEL_DIS_SHIFT               5
#define PMIC_RG_BUCK_VS2_CK_SW_MODE_ADDR                 MT6355_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_BUCK_VS2_CK_SW_MODE_SHIFT                6
#define PMIC_RG_BUCK_VS2_CK_SW_EN_ADDR                   MT6355_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_CK_SW_EN_MASK                   0x1
#define PMIC_RG_BUCK_VS2_CK_SW_EN_SHIFT                  7
#define PMIC_RG_BUCK_VS2_VOTER_EN_ADDR                   MT6355_BUCK_VS2_VOTER
#define PMIC_RG_BUCK_VS2_VOTER_EN_MASK                   0xFF
#define PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT                  0
#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_ADDR               MT6355_BUCK_VS2_VOTER_SET
#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK               0xFF
#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT              0
#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_ADDR               MT6355_BUCK_VS2_VOTER_CLR
#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK               0xFF
#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT              0
#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_ADDR                MT6355_BUCK_VS2_VOTER_CFG
#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK                0x7F
#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT               0
#define PMIC_RG_BUCK_VPA_EN_ADDR                         MT6355_BUCK_VPA_CON0
#define PMIC_RG_BUCK_VPA_EN_MASK                         0x1
#define PMIC_RG_BUCK_VPA_EN_SHIFT                        0
#define PMIC_RG_BUCK_VPA_VOSEL_ADDR                      MT6355_BUCK_VPA_CON1
#define PMIC_RG_BUCK_VPA_VOSEL_MASK                      0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_SHIFT                     0
#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_ADDR                MT6355_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_MASK                0x7F
#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_SHIFT               0
#define PMIC_RG_BUCK_VPA_SFCHG_FEN_ADDR                  MT6355_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_FEN_MASK                  0x1
#define PMIC_RG_BUCK_VPA_SFCHG_FEN_SHIFT                 7
#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_ADDR                MT6355_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_MASK                0x7F
#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_SHIFT               8
#define PMIC_RG_BUCK_VPA_SFCHG_REN_ADDR                  MT6355_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_REN_MASK                  0x1
#define PMIC_RG_BUCK_VPA_SFCHG_REN_SHIFT                 15
#define PMIC_RG_BUCK_VPA_DVS_TRANST_TD_ADDR              MT6355_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_TD_MASK              0x3
#define PMIC_RG_BUCK_VPA_DVS_TRANST_TD_SHIFT             0
#define PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL_ADDR            MT6355_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL_MASK            0x3
#define PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL_SHIFT           4
#define PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE_ADDR            MT6355_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE_MASK            0x1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE_SHIFT           6
#define PMIC_RG_BUCK_VPA_DVS_BW_TD_ADDR                  MT6355_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_BW_TD_MASK                  0x3
#define PMIC_RG_BUCK_VPA_DVS_BW_TD_SHIFT                 8
#define PMIC_RG_BUCK_VPA_DVS_BW_CTRL_ADDR                MT6355_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_BW_CTRL_MASK                0x3
#define PMIC_RG_BUCK_VPA_DVS_BW_CTRL_SHIFT               12
#define PMIC_RG_BUCK_VPA_DVS_BW_ONCE_ADDR                MT6355_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_BW_ONCE_MASK                0x1
#define PMIC_RG_BUCK_VPA_DVS_BW_ONCE_SHIFT               14
#define PMIC_RG_BUCK_VPA_OC_DEG_EN_ADDR                  MT6355_BUCK_VPA_OC_CFG
#define PMIC_RG_BUCK_VPA_OC_DEG_EN_MASK                  0x1
#define PMIC_RG_BUCK_VPA_OC_DEG_EN_SHIFT                 1
#define PMIC_RG_BUCK_VPA_OC_WND_ADDR                     MT6355_BUCK_VPA_OC_CFG
#define PMIC_RG_BUCK_VPA_OC_WND_MASK                     0x3
#define PMIC_RG_BUCK_VPA_OC_WND_SHIFT                    2
#define PMIC_RG_BUCK_VPA_OC_THD_ADDR                     MT6355_BUCK_VPA_OC_CFG
#define PMIC_RG_BUCK_VPA_OC_THD_MASK                     0x3
#define PMIC_RG_BUCK_VPA_OC_THD_SHIFT                    6
#define PMIC_DA_VPA_VOSEL_ADDR                           MT6355_BUCK_VPA_DBG0
#define PMIC_DA_VPA_VOSEL_MASK                           0x3F
#define PMIC_DA_VPA_VOSEL_SHIFT                          0
#define PMIC_DA_VPA_VOSEL_GRAY_ADDR                      MT6355_BUCK_VPA_DBG0
#define PMIC_DA_VPA_VOSEL_GRAY_MASK                      0x3F
#define PMIC_DA_VPA_VOSEL_GRAY_SHIFT                     8
#define PMIC_DA_VPA_EN_ADDR                              MT6355_BUCK_VPA_DBG1
#define PMIC_DA_VPA_EN_MASK                              0x1
#define PMIC_DA_VPA_EN_SHIFT                             0
#define PMIC_DA_VPA_STB_ADDR                             MT6355_BUCK_VPA_DBG1
#define PMIC_DA_VPA_STB_MASK                             0x1
#define PMIC_DA_VPA_STB_SHIFT                            1
#define PMIC_DA_VPA_DVS_TRANST_ADDR                      MT6355_BUCK_VPA_DBG1
#define PMIC_DA_VPA_DVS_TRANST_MASK                      0x1
#define PMIC_DA_VPA_DVS_TRANST_SHIFT                     5
#define PMIC_DA_VPA_DVS_BW_ADDR                          MT6355_BUCK_VPA_DBG1
#define PMIC_DA_VPA_DVS_BW_MASK                          0x1
#define PMIC_DA_VPA_DVS_BW_SHIFT                         6
#define PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL_ADDR            MT6355_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL_MASK            0x1
#define PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL_SHIFT           4
#define PMIC_RG_BUCK_VPA_OSC_SEL_DIS_ADDR                MT6355_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_BUCK_VPA_OSC_SEL_DIS_SHIFT               5
#define PMIC_RG_BUCK_VPA_CK_SW_MODE_ADDR                 MT6355_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_BUCK_VPA_CK_SW_MODE_SHIFT                6
#define PMIC_RG_BUCK_VPA_CK_SW_EN_ADDR                   MT6355_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_CK_SW_EN_MASK                   0x1
#define PMIC_RG_BUCK_VPA_CK_SW_EN_SHIFT                  7
#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_ADDR               MT6355_BUCK_VPA_DLC_CON0
#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_MASK               0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_SHIFT              0
#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_ADDR               MT6355_BUCK_VPA_DLC_CON0
#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_MASK               0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_SHIFT              8
#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_ADDR               MT6355_BUCK_VPA_DLC_CON1
#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_MASK               0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_SHIFT              8
#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_ADDR                 MT6355_BUCK_VPA_DLC_CON2
#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_MASK                 0x1
#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_SHIFT                0
#define PMIC_RG_BUCK_VPA_DLC_ADDR                        MT6355_BUCK_VPA_DLC_CON2
#define PMIC_RG_BUCK_VPA_DLC_MASK                        0x7
#define PMIC_RG_BUCK_VPA_DLC_SHIFT                       8
#define PMIC_DA_VPA_DLC_ADDR                             MT6355_BUCK_VPA_DLC_CON2
#define PMIC_DA_VPA_DLC_MASK                             0x7
#define PMIC_DA_VPA_DLC_SHIFT                            12
#define PMIC_RG_BUCK_VPA_MSFG_EN_ADDR                    MT6355_BUCK_VPA_MSFG_CON0
#define PMIC_RG_BUCK_VPA_MSFG_EN_MASK                    0x1
#define PMIC_RG_BUCK_VPA_MSFG_EN_SHIFT                   0
#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_ADDR             MT6355_BUCK_VPA_MSFG_CON1
#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_MASK             0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_SHIFT            0
#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_ADDR             MT6355_BUCK_VPA_MSFG_CON1
#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_MASK             0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_SHIFT            8
#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_ADDR                MT6355_BUCK_VPA_MSFG_RRATE0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_SHIFT               0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_ADDR                MT6355_BUCK_VPA_MSFG_RRATE0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_SHIFT               8
#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_ADDR                MT6355_BUCK_VPA_MSFG_RRATE1
#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_SHIFT               0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_ADDR                MT6355_BUCK_VPA_MSFG_RRATE1
#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_SHIFT               8
#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_ADDR                MT6355_BUCK_VPA_MSFG_RRATE2
#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_SHIFT               0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_ADDR                MT6355_BUCK_VPA_MSFG_RRATE2
#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_SHIFT               8
#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_ADDR                 MT6355_BUCK_VPA_MSFG_RTHD0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_SHIFT                0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_ADDR                 MT6355_BUCK_VPA_MSFG_RTHD0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_SHIFT                8
#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_ADDR                 MT6355_BUCK_VPA_MSFG_RTHD1
#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_SHIFT                0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_ADDR                 MT6355_BUCK_VPA_MSFG_RTHD1
#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_SHIFT                8
#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_ADDR                 MT6355_BUCK_VPA_MSFG_RTHD2
#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_SHIFT                0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_ADDR                MT6355_BUCK_VPA_MSFG_FRATE0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_SHIFT               0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_ADDR                MT6355_BUCK_VPA_MSFG_FRATE0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_SHIFT               8
#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_ADDR                MT6355_BUCK_VPA_MSFG_FRATE1
#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_SHIFT               0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_ADDR                MT6355_BUCK_VPA_MSFG_FRATE1
#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_SHIFT               8
#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_ADDR                MT6355_BUCK_VPA_MSFG_FRATE2
#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_SHIFT               0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_ADDR                MT6355_BUCK_VPA_MSFG_FRATE2
#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_MASK                0x1F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_SHIFT               8
#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_ADDR                 MT6355_BUCK_VPA_MSFG_FTHD0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_SHIFT                0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_ADDR                 MT6355_BUCK_VPA_MSFG_FTHD0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_SHIFT                8
#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_ADDR                 MT6355_BUCK_VPA_MSFG_FTHD1
#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_SHIFT                0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_ADDR                 MT6355_BUCK_VPA_MSFG_FTHD1
#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_SHIFT                8
#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_ADDR                 MT6355_BUCK_VPA_MSFG_FTHD2
#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_MASK                 0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_SHIFT                0
#define PMIC_RG_SMPS_TESTMODE_B_ADDR                     MT6355_SMPS_ANA_CON0
#define PMIC_RG_SMPS_TESTMODE_B_MASK                     0xFFF
#define PMIC_RG_SMPS_TESTMODE_B_SHIFT                    0
#define PMIC_RG_VPA_BURSTH_ADDR                          MT6355_SMPS_ANA_CON0
#define PMIC_RG_VPA_BURSTH_MASK                          0x3
#define PMIC_RG_VPA_BURSTH_SHIFT                         12
#define PMIC_RG_VPA_BURSTL_ADDR                          MT6355_SMPS_ANA_CON0
#define PMIC_RG_VPA_BURSTL_MASK                          0x3
#define PMIC_RG_VPA_BURSTL_SHIFT                         14
#define PMIC_RG_VPA_TRIMH_ADDR                           MT6355_SMPS_ANA_CON1
#define PMIC_RG_VPA_TRIMH_MASK                           0x1F
#define PMIC_RG_VPA_TRIMH_SHIFT                          0
#define PMIC_RG_VPA_TRIML_ADDR                           MT6355_SMPS_ANA_CON1
#define PMIC_RG_VPA_TRIML_MASK                           0x1F
#define PMIC_RG_VPA_TRIML_SHIFT                          5
#define PMIC_RG_VPA_TRIM_REF_ADDR                        MT6355_SMPS_ANA_CON1
#define PMIC_RG_VPA_TRIM_REF_MASK                        0x1F
#define PMIC_RG_VPA_TRIM_REF_SHIFT                       10
#define PMIC_RG_VCORE_TRIMH_ADDR                         MT6355_SMPS_ANA_CON2
#define PMIC_RG_VCORE_TRIMH_MASK                         0x1F
#define PMIC_RG_VCORE_TRIMH_SHIFT                        0
#define PMIC_RG_VCORE_TRIML_ADDR                         MT6355_SMPS_ANA_CON2
#define PMIC_RG_VCORE_TRIML_MASK                         0x1F
#define PMIC_RG_VCORE_TRIML_SHIFT                        5
#define PMIC_RG_VCORE_VSLEEP_TRIM_ADDR                   MT6355_SMPS_ANA_CON2
#define PMIC_RG_VCORE_VSLEEP_TRIM_MASK                   0x7
#define PMIC_RG_VCORE_VSLEEP_TRIM_SHIFT                  10
#define PMIC_RG_VCORE_SLEEP_VOLTAGE_ADDR                 MT6355_SMPS_ANA_CON2
#define PMIC_RG_VCORE_SLEEP_VOLTAGE_MASK                 0x3
#define PMIC_RG_VCORE_SLEEP_VOLTAGE_SHIFT                13
#define PMIC_RG_VDRAM1_TRIMH_ADDR                        MT6355_SMPS_ANA_CON3
#define PMIC_RG_VDRAM1_TRIMH_MASK                        0x1F
#define PMIC_RG_VDRAM1_TRIMH_SHIFT                       0
#define PMIC_RG_VDRAM1_TRIML_ADDR                        MT6355_SMPS_ANA_CON3
#define PMIC_RG_VDRAM1_TRIML_MASK                        0x1F
#define PMIC_RG_VDRAM1_TRIML_SHIFT                       5
#define PMIC_RG_VDRAM1_VSLEEP_TRIM_ADDR                  MT6355_SMPS_ANA_CON3
#define PMIC_RG_VDRAM1_VSLEEP_TRIM_MASK                  0x7
#define PMIC_RG_VDRAM1_VSLEEP_TRIM_SHIFT                 10
#define PMIC_RG_VDRAM1_SLEEP_VOLTAGE_ADDR                MT6355_SMPS_ANA_CON3
#define PMIC_RG_VDRAM1_SLEEP_VOLTAGE_MASK                0x1
#define PMIC_RG_VDRAM1_SLEEP_VOLTAGE_SHIFT               13
#define PMIC_RG_VMODEM_TRIMH_ADDR                        MT6355_SMPS_ANA_CON4
#define PMIC_RG_VMODEM_TRIMH_MASK                        0x1F
#define PMIC_RG_VMODEM_TRIMH_SHIFT                       0
#define PMIC_RG_VMODEM_TRIML_ADDR                        MT6355_SMPS_ANA_CON4
#define PMIC_RG_VMODEM_TRIML_MASK                        0x1F
#define PMIC_RG_VMODEM_TRIML_SHIFT                       5
#define PMIC_RG_VMODEM_VSLEEP_TRIM_ADDR                  MT6355_SMPS_ANA_CON4
#define PMIC_RG_VMODEM_VSLEEP_TRIM_MASK                  0x7
#define PMIC_RG_VMODEM_VSLEEP_TRIM_SHIFT                 10
#define PMIC_RG_VMODEM_SLEEP_VOLTAGE_ADDR                MT6355_SMPS_ANA_CON4
#define PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK                0x7
#define PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT               13
#define PMIC_RG_VGPU_TRIMH_ADDR                          MT6355_SMPS_ANA_CON5
#define PMIC_RG_VGPU_TRIMH_MASK                          0x1F
#define PMIC_RG_VGPU_TRIMH_SHIFT                         0
#define PMIC_RG_VGPU_TRIML_ADDR                          MT6355_SMPS_ANA_CON5
#define PMIC_RG_VGPU_TRIML_MASK                          0x1F
#define PMIC_RG_VGPU_TRIML_SHIFT                         5
#define PMIC_RG_VGPU_VSLEEP_TRIM_ADDR                    MT6355_SMPS_ANA_CON5
#define PMIC_RG_VGPU_VSLEEP_TRIM_MASK                    0x7
#define PMIC_RG_VGPU_VSLEEP_TRIM_SHIFT                   10
#define PMIC_RG_VGPU_SLEEP_VOLTAGE_ADDR                  MT6355_SMPS_ANA_CON5
#define PMIC_RG_VGPU_SLEEP_VOLTAGE_MASK                  0x3
#define PMIC_RG_VGPU_SLEEP_VOLTAGE_SHIFT                 13
#define PMIC_RG_VS1_TRIMH_ADDR                           MT6355_SMPS_ANA_CON6
#define PMIC_RG_VS1_TRIMH_MASK                           0x1F
#define PMIC_RG_VS1_TRIMH_SHIFT                          0
#define PMIC_RG_VS1_TRIML_ADDR                           MT6355_SMPS_ANA_CON6
#define PMIC_RG_VS1_TRIML_MASK                           0x1F
#define PMIC_RG_VS1_TRIML_SHIFT                          5
#define PMIC_RG_VS1_VSLEEP_TRIM_ADDR                     MT6355_SMPS_ANA_CON6
#define PMIC_RG_VS1_VSLEEP_TRIM_MASK                     0x7
#define PMIC_RG_VS1_VSLEEP_TRIM_SHIFT                    10
#define PMIC_RG_VS1_SLEEP_VOLTAGE_ADDR                   MT6355_SMPS_ANA_CON6
#define PMIC_RG_VS1_SLEEP_VOLTAGE_MASK                   0x1
#define PMIC_RG_VS1_SLEEP_VOLTAGE_SHIFT                  13
#define PMIC_RG_VS2_TRIMH_ADDR                           MT6355_SMPS_ANA_CON7
#define PMIC_RG_VS2_TRIMH_MASK                           0x1F
#define PMIC_RG_VS2_TRIMH_SHIFT                          0
#define PMIC_RG_VS2_TRIML_ADDR                           MT6355_SMPS_ANA_CON7
#define PMIC_RG_VS2_TRIML_MASK                           0x1F
#define PMIC_RG_VS2_TRIML_SHIFT                          5
#define PMIC_RG_VS2_VSLEEP_TRIM_ADDR                     MT6355_SMPS_ANA_CON7
#define PMIC_RG_VS2_VSLEEP_TRIM_MASK                     0x7
#define PMIC_RG_VS2_VSLEEP_TRIM_SHIFT                    10
#define PMIC_RG_VS2_SLEEP_VOLTAGE_ADDR                   MT6355_SMPS_ANA_CON7
#define PMIC_RG_VS2_SLEEP_VOLTAGE_MASK                   0x1
#define PMIC_RG_VS2_SLEEP_VOLTAGE_SHIFT                  13
#define PMIC_RG_VDRAM2_TRIMH_ADDR                        MT6355_SMPS_ANA_CON8
#define PMIC_RG_VDRAM2_TRIMH_MASK                        0x1F
#define PMIC_RG_VDRAM2_TRIMH_SHIFT                       0
#define PMIC_RG_VDRAM2_TRIML_ADDR                        MT6355_SMPS_ANA_CON8
#define PMIC_RG_VDRAM2_TRIML_MASK                        0x1F
#define PMIC_RG_VDRAM2_TRIML_SHIFT                       5
#define PMIC_RG_VDRAM2_VSLEEP_TRIM_ADDR                  MT6355_SMPS_ANA_CON8
#define PMIC_RG_VDRAM2_VSLEEP_TRIM_MASK                  0x7
#define PMIC_RG_VDRAM2_VSLEEP_TRIM_SHIFT                 10
#define PMIC_RG_VDRAM2_SLEEP_VOLTAGE_ADDR                MT6355_SMPS_ANA_CON8
#define PMIC_RG_VDRAM2_SLEEP_VOLTAGE_MASK                0x1
#define PMIC_RG_VDRAM2_SLEEP_VOLTAGE_SHIFT               13
#define PMIC_RG_VPROC11_TRIMH_ADDR                       MT6355_SMPS_ANA_CON9
#define PMIC_RG_VPROC11_TRIMH_MASK                       0x1F
#define PMIC_RG_VPROC11_TRIMH_SHIFT                      0
#define PMIC_RG_VPROC11_TRIML_ADDR                       MT6355_SMPS_ANA_CON9
#define PMIC_RG_VPROC11_TRIML_MASK                       0x1F
#define PMIC_RG_VPROC11_TRIML_SHIFT                      5
#define PMIC_RG_VPROC11_VSLEEP_TRIM_ADDR                 MT6355_SMPS_ANA_CON9
#define PMIC_RG_VPROC11_VSLEEP_TRIM_MASK                 0x7
#define PMIC_RG_VPROC11_VSLEEP_TRIM_SHIFT                10
#define PMIC_RG_VPROC11_SLEEP_VOLTAGE_ADDR               MT6355_SMPS_ANA_CON9
#define PMIC_RG_VPROC11_SLEEP_VOLTAGE_MASK               0x3
#define PMIC_RG_VPROC11_SLEEP_VOLTAGE_SHIFT              13
#define PMIC_RG_VPROC12_TRIMH_ADDR                       MT6355_SMPS_ANA_CON10
#define PMIC_RG_VPROC12_TRIMH_MASK                       0x1F
#define PMIC_RG_VPROC12_TRIMH_SHIFT                      0
#define PMIC_RG_VPROC12_TRIML_ADDR                       MT6355_SMPS_ANA_CON10
#define PMIC_RG_VPROC12_TRIML_MASK                       0x1F
#define PMIC_RG_VPROC12_TRIML_SHIFT                      5
#define PMIC_RG_VPROC12_VSLEEP_TRIM_ADDR                 MT6355_SMPS_ANA_CON10
#define PMIC_RG_VPROC12_VSLEEP_TRIM_MASK                 0x7
#define PMIC_RG_VPROC12_VSLEEP_TRIM_SHIFT                10
#define PMIC_RG_VPROC12_SLEEP_VOLTAGE_ADDR               MT6355_SMPS_ANA_CON10
#define PMIC_RG_VPROC12_SLEEP_VOLTAGE_MASK               0x3
#define PMIC_RG_VPROC12_SLEEP_VOLTAGE_SHIFT              13
#define PMIC_RG_VSRAM_PROC_TRIMH_ADDR                    MT6355_SMPS_ANA_CON11
#define PMIC_RG_VSRAM_PROC_TRIMH_MASK                    0x1F
#define PMIC_RG_VSRAM_PROC_TRIMH_SHIFT                   0
#define PMIC_RG_VSRAM_PROC_TRIML_ADDR                    MT6355_SMPS_ANA_CON11
#define PMIC_RG_VSRAM_PROC_TRIML_MASK                    0x1F
#define PMIC_RG_VSRAM_PROC_TRIML_SHIFT                   5
#define PMIC_RG_VSRAM_PROC_VSLEEP_TRIM_ADDR              MT6355_SMPS_ANA_CON11
#define PMIC_RG_VSRAM_PROC_VSLEEP_TRIM_MASK              0x7
#define PMIC_RG_VSRAM_PROC_VSLEEP_TRIM_SHIFT             10
#define PMIC_RG_VSRAM_PROC_SLEEP_VOLTAGE_ADDR            MT6355_SMPS_ANA_CON11
#define PMIC_RG_VSRAM_PROC_SLEEP_VOLTAGE_MASK            0x3
#define PMIC_RG_VSRAM_PROC_SLEEP_VOLTAGE_SHIFT           13
#define PMIC_RG_VSRAM_CORE_TRIMH_ADDR                    MT6355_SMPS_ANA_CON12
#define PMIC_RG_VSRAM_CORE_TRIMH_MASK                    0x1F
#define PMIC_RG_VSRAM_CORE_TRIMH_SHIFT                   0
#define PMIC_RG_VSRAM_CORE_TRIML_ADDR                    MT6355_SMPS_ANA_CON12
#define PMIC_RG_VSRAM_CORE_TRIML_MASK                    0x1F
#define PMIC_RG_VSRAM_CORE_TRIML_SHIFT                   5
#define PMIC_RG_VSRAM_CORE_VSLEEP_TRIM_ADDR              MT6355_SMPS_ANA_CON12
#define PMIC_RG_VSRAM_CORE_VSLEEP_TRIM_MASK              0x7
#define PMIC_RG_VSRAM_CORE_VSLEEP_TRIM_SHIFT             10
#define PMIC_RG_VSRAM_CORE_SLEEP_VOLTAGE_ADDR            MT6355_SMPS_ANA_CON12
#define PMIC_RG_VSRAM_CORE_SLEEP_VOLTAGE_MASK            0x7
#define PMIC_RG_VSRAM_CORE_SLEEP_VOLTAGE_SHIFT           13
#define PMIC_RG_VSRAM_GPU_TRIMH_ADDR                     MT6355_SMPS_ANA_CON13
#define PMIC_RG_VSRAM_GPU_TRIMH_MASK                     0x1F
#define PMIC_RG_VSRAM_GPU_TRIMH_SHIFT                    0
#define PMIC_RG_VSRAM_GPU_TRIML_ADDR                     MT6355_SMPS_ANA_CON13
#define PMIC_RG_VSRAM_GPU_TRIML_MASK                     0x1F
#define PMIC_RG_VSRAM_GPU_TRIML_SHIFT                    5
#define PMIC_RG_VSRAM_GPU_VSLEEP_TRIM_ADDR               MT6355_SMPS_ANA_CON13
#define PMIC_RG_VSRAM_GPU_VSLEEP_TRIM_MASK               0x7
#define PMIC_RG_VSRAM_GPU_VSLEEP_TRIM_SHIFT              10
#define PMIC_RG_VSRAM_GPU_SLEEP_VOLTAGE_ADDR             MT6355_SMPS_ANA_CON13
#define PMIC_RG_VSRAM_GPU_SLEEP_VOLTAGE_MASK             0x3
#define PMIC_RG_VSRAM_GPU_SLEEP_VOLTAGE_SHIFT            13
#define PMIC_RG_VSRAM_MD_TRIMH_ADDR                      MT6355_SMPS_ANA_CON14
#define PMIC_RG_VSRAM_MD_TRIMH_MASK                      0x1F
#define PMIC_RG_VSRAM_MD_TRIMH_SHIFT                     0
#define PMIC_RG_VSRAM_MD_TRIML_ADDR                      MT6355_SMPS_ANA_CON14
#define PMIC_RG_VSRAM_MD_TRIML_MASK                      0x1F
#define PMIC_RG_VSRAM_MD_TRIML_SHIFT                     5
#define PMIC_RG_VSRAM_MD_VSLEEP_TRIM_ADDR                MT6355_SMPS_ANA_CON14
#define PMIC_RG_VSRAM_MD_VSLEEP_TRIM_MASK                0x7
#define PMIC_RG_VSRAM_MD_VSLEEP_TRIM_SHIFT               10
#define PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_ADDR              MT6355_SMPS_ANA_CON14
#define PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_MASK              0x7
#define PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE_SHIFT             13
#define PMIC_RG_SMPS_IVGD_DET_ADDR                       MT6355_SMPS_ANA_CON15
#define PMIC_RG_SMPS_IVGD_DET_MASK                       0x1
#define PMIC_RG_SMPS_IVGD_DET_SHIFT                      0
#define PMIC_RG_VOUTDET_EN_ADDR                          MT6355_SMPS_ANA_CON15
#define PMIC_RG_VOUTDET_EN_MASK                          0x1
#define PMIC_RG_VOUTDET_EN_SHIFT                         1
#define PMIC_RG_AUTOK_RST_ADDR                           MT6355_SMPS_ANA_CON15
#define PMIC_RG_AUTOK_RST_MASK                           0x1
#define PMIC_RG_AUTOK_RST_SHIFT                          2
#define PMIC_RG_VPROC11_FPWM_ADDR                        MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_FPWM_MASK                        0x1
#define PMIC_RG_VPROC11_FPWM_SHIFT                       1
#define PMIC_RG_VPROC12_FPWM_ADDR                        MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_FPWM_MASK                        0x1
#define PMIC_RG_VPROC12_FPWM_SHIFT                       2
#define PMIC_RG_VPROC11_NDIS_EN_ADDR                     MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_NDIS_EN_MASK                     0x1
#define PMIC_RG_VPROC11_NDIS_EN_SHIFT                    3
#define PMIC_RG_VPROC12_NDIS_EN_ADDR                     MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_NDIS_EN_MASK                     0x1
#define PMIC_RG_VPROC12_NDIS_EN_SHIFT                    4
#define PMIC_RG_VPROC11_FCOT_ADDR                        MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_FCOT_MASK                        0x1
#define PMIC_RG_VPROC11_FCOT_SHIFT                       5
#define PMIC_RG_VPROC12_FCOT_ADDR                        MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_FCOT_MASK                        0x1
#define PMIC_RG_VPROC12_FCOT_SHIFT                       6
#define PMIC_RG_VPROC_TMDL_ADDR                          MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC_TMDL_MASK                          0x1
#define PMIC_RG_VPROC_TMDL_SHIFT                         7
#define PMIC_RG_VPROC_DISCONFIG20_ADDR                   MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC_DISCONFIG20_MASK                   0x1
#define PMIC_RG_VPROC_DISCONFIG20_SHIFT                  8
#define PMIC_RG_VPROC11_TBDIS_ADDR                       MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_TBDIS_MASK                       0x1
#define PMIC_RG_VPROC11_TBDIS_SHIFT                      9
#define PMIC_RG_VPROC12_TBDIS_ADDR                       MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_TBDIS_MASK                       0x1
#define PMIC_RG_VPROC12_TBDIS_SHIFT                      10
#define PMIC_RG_VPROC11_VDIFFOFF_ADDR                    MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_VDIFFOFF_MASK                    0x1
#define PMIC_RG_VPROC11_VDIFFOFF_SHIFT                   11
#define PMIC_RG_VPROC12_VDIFFOFF_ADDR                    MT6355_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_VDIFFOFF_MASK                    0x1
#define PMIC_RG_VPROC12_VDIFFOFF_SHIFT                   12
#define PMIC_RG_VPROC11_RCOMP0_ADDR                      MT6355_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_RCOMP0_MASK                      0xF
#define PMIC_RG_VPROC11_RCOMP0_SHIFT                     0
#define PMIC_RG_VPROC11_RCOMP1_ADDR                      MT6355_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_RCOMP1_MASK                      0x7
#define PMIC_RG_VPROC11_RCOMP1_SHIFT                     4
#define PMIC_RG_VPROC11_CCOMP0_ADDR                      MT6355_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_CCOMP0_MASK                      0x3
#define PMIC_RG_VPROC11_CCOMP0_SHIFT                     7
#define PMIC_RG_VPROC11_CCOMP1_ADDR                      MT6355_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_CCOMP1_MASK                      0x3
#define PMIC_RG_VPROC11_CCOMP1_SHIFT                     9
#define PMIC_RG_VPROC11_RAMP_SLP_ADDR                    MT6355_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_RAMP_SLP_MASK                    0x7
#define PMIC_RG_VPROC11_RAMP_SLP_SHIFT                   11
#define PMIC_RG_VPROC12_RCOMP0_ADDR                      MT6355_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_RCOMP0_MASK                      0xF
#define PMIC_RG_VPROC12_RCOMP0_SHIFT                     0
#define PMIC_RG_VPROC12_RCOMP1_ADDR                      MT6355_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_RCOMP1_MASK                      0x7
#define PMIC_RG_VPROC12_RCOMP1_SHIFT                     4
#define PMIC_RG_VPROC12_CCOMP0_ADDR                      MT6355_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_CCOMP0_MASK                      0x3
#define PMIC_RG_VPROC12_CCOMP0_SHIFT                     7
#define PMIC_RG_VPROC12_CCOMP1_ADDR                      MT6355_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_CCOMP1_MASK                      0x3
#define PMIC_RG_VPROC12_CCOMP1_SHIFT                     9
#define PMIC_RG_VPROC12_RAMP_SLP_ADDR                    MT6355_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_RAMP_SLP_MASK                    0x7
#define PMIC_RG_VPROC12_RAMP_SLP_SHIFT                   11
#define PMIC_RG_VPROC11_RCS_ADDR                         MT6355_VPROC_ANA_CON3
#define PMIC_RG_VPROC11_RCS_MASK                         0x7
#define PMIC_RG_VPROC11_RCS_SHIFT                        0
#define PMIC_RG_VPROC12_RCS_ADDR                         MT6355_VPROC_ANA_CON3
#define PMIC_RG_VPROC12_RCS_MASK                         0x7
#define PMIC_RG_VPROC12_RCS_SHIFT                        3
#define PMIC_RG_VPROC11_RCB_ADDR                         MT6355_VPROC_ANA_CON3
#define PMIC_RG_VPROC11_RCB_MASK                         0xF
#define PMIC_RG_VPROC11_RCB_SHIFT                        6
#define PMIC_RG_VPROC12_RCB_ADDR                         MT6355_VPROC_ANA_CON3
#define PMIC_RG_VPROC12_RCB_MASK                         0xF
#define PMIC_RG_VPROC12_RCB_SHIFT                        10
#define PMIC_RG_VPROC11_CSP_TRIM_ADDR                    MT6355_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_CSP_TRIM_MASK                    0x7
#define PMIC_RG_VPROC11_CSP_TRIM_SHIFT                   0
#define PMIC_RG_VPROC12_CSP_TRIM_ADDR                    MT6355_VPROC_ANA_CON4
#define PMIC_RG_VPROC12_CSP_TRIM_MASK                    0x7
#define PMIC_RG_VPROC12_CSP_TRIM_SHIFT                   3
#define PMIC_RG_VPROC11_CSN_TRIM_ADDR                    MT6355_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_CSN_TRIM_MASK                    0x7
#define PMIC_RG_VPROC11_CSN_TRIM_SHIFT                   6
#define PMIC_RG_VPROC12_CSN_TRIM_ADDR                    MT6355_VPROC_ANA_CON4
#define PMIC_RG_VPROC12_CSN_TRIM_MASK                    0x7
#define PMIC_RG_VPROC12_CSN_TRIM_SHIFT                   9
#define PMIC_RG_VPROC11_ZC_TRIM_ADDR                     MT6355_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_ZC_TRIM_MASK                     0x3
#define PMIC_RG_VPROC11_ZC_TRIM_SHIFT                    12
#define PMIC_RG_VPROC12_ZC_TRIM_ADDR                     MT6355_VPROC_ANA_CON4
#define PMIC_RG_VPROC12_ZC_TRIM_MASK                     0x3
#define PMIC_RG_VPROC12_ZC_TRIM_SHIFT                    14
#define PMIC_RG_VPROC11_NLIM_TRIM_ADDR                   MT6355_VPROC_ANA_CON5
#define PMIC_RG_VPROC11_NLIM_TRIM_MASK                   0xF
#define PMIC_RG_VPROC11_NLIM_TRIM_SHIFT                  0
#define PMIC_RG_VPROC12_NLIM_TRIM_ADDR                   MT6355_VPROC_ANA_CON5
#define PMIC_RG_VPROC12_NLIM_TRIM_MASK                   0xF
#define PMIC_RG_VPROC12_NLIM_TRIM_SHIFT                  4
#define PMIC_RG_VPROC11_RPSI1_TRIM_ADDR                  MT6355_VPROC_ANA_CON5
#define PMIC_RG_VPROC11_RPSI1_TRIM_MASK                  0x7
#define PMIC_RG_VPROC11_RPSI1_TRIM_SHIFT                 8
#define PMIC_RG_VPROC12_RPSI1_TRIM_ADDR                  MT6355_VPROC_ANA_CON5
#define PMIC_RG_VPROC12_RPSI1_TRIM_MASK                  0x7
#define PMIC_RG_VPROC12_RPSI1_TRIM_SHIFT                 11
#define PMIC_RG_VPROC11_TB_WIDTH_ADDR                    MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC11_TB_WIDTH_MASK                    0x3
#define PMIC_RG_VPROC11_TB_WIDTH_SHIFT                   0
#define PMIC_RG_VPROC12_TB_WIDTH_ADDR                    MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC12_TB_WIDTH_MASK                    0x3
#define PMIC_RG_VPROC12_TB_WIDTH_SHIFT                   2
#define PMIC_RG_VPROC11_UG_SR_ADDR                       MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC11_UG_SR_MASK                       0x3
#define PMIC_RG_VPROC11_UG_SR_SHIFT                      4
#define PMIC_RG_VPROC11_LG_SR_ADDR                       MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC11_LG_SR_MASK                       0x3
#define PMIC_RG_VPROC11_LG_SR_SHIFT                      6
#define PMIC_RG_VPROC12_UG_SR_ADDR                       MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC12_UG_SR_MASK                       0x3
#define PMIC_RG_VPROC12_UG_SR_SHIFT                      8
#define PMIC_RG_VPROC12_LG_SR_ADDR                       MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC12_LG_SR_MASK                       0x3
#define PMIC_RG_VPROC12_LG_SR_SHIFT                      10
#define PMIC_RG_VPROC11_PFM_TON_ADDR                     MT6355_VPROC_ANA_CON6
#define PMIC_RG_VPROC11_PFM_TON_MASK                     0x7
#define PMIC_RG_VPROC11_PFM_TON_SHIFT                    12
#define PMIC_RG_VPROC12_PFM_TON_ADDR                     MT6355_VPROC_ANA_CON7
#define PMIC_RG_VPROC12_PFM_TON_MASK                     0x7
#define PMIC_RG_VPROC12_PFM_TON_SHIFT                    0
#define PMIC_RG_VPROC11_TON_TRIM_ADDR                    MT6355_VPROC_ANA_CON7
#define PMIC_RG_VPROC11_TON_TRIM_MASK                    0x3F
#define PMIC_RG_VPROC11_TON_TRIM_SHIFT                   3
#define PMIC_RG_VPROC12_TON_TRIM_ADDR                    MT6355_VPROC_ANA_CON7
#define PMIC_RG_VPROC12_TON_TRIM_MASK                    0x3F
#define PMIC_RG_VPROC12_TON_TRIM_SHIFT                   9
#define PMIC_RGS_VPROC11_OC_STATUS_ADDR                  MT6355_VPROC_ANA_CON7
#define PMIC_RGS_VPROC11_OC_STATUS_MASK                  0x1
#define PMIC_RGS_VPROC11_OC_STATUS_SHIFT                 15
#define PMIC_RGS_VPROC12_OC_STATUS_ADDR                  MT6355_VPROC_ANA_CON8
#define PMIC_RGS_VPROC12_OC_STATUS_MASK                  0x1
#define PMIC_RGS_VPROC12_OC_STATUS_SHIFT                 0
#define PMIC_RGS_VPROC_TRIMOK_STATUS_ADDR                MT6355_VPROC_ANA_CON8
#define PMIC_RGS_VPROC_TRIMOK_STATUS_MASK                0x1
#define PMIC_RGS_VPROC_TRIMOK_STATUS_SHIFT               1
#define PMIC_RGS_VPROC_CONFIG20_STATUS_ADDR              MT6355_VPROC_ANA_CON8
#define PMIC_RGS_VPROC_CONFIG20_STATUS_MASK              0x1
#define PMIC_RGS_VPROC_CONFIG20_STATUS_SHIFT             2
#define PMIC_RGS_VPROC11_PREOC_STATUS_ADDR               MT6355_VPROC_ANA_CON8
#define PMIC_RGS_VPROC11_PREOC_STATUS_MASK               0x1
#define PMIC_RGS_VPROC11_PREOC_STATUS_SHIFT              3
#define PMIC_RGS_VPROC11_DIG_MON_ADDR                    MT6355_VPROC_ANA_CON9
#define PMIC_RGS_VPROC11_DIG_MON_MASK                    0xFF
#define PMIC_RGS_VPROC11_DIG_MON_SHIFT                   0
#define PMIC_RGS_VPROC12_DIG_MON_ADDR                    MT6355_VPROC_ANA_CON9
#define PMIC_RGS_VPROC12_DIG_MON_MASK                    0xFF
#define PMIC_RGS_VPROC12_DIG_MON_SHIFT                   8
#define PMIC_RG_VPROC11_TRAN_BST_ADDR                    MT6355_VPROC_ANA_CON10
#define PMIC_RG_VPROC11_TRAN_BST_MASK                    0x3F
#define PMIC_RG_VPROC11_TRAN_BST_SHIFT                   0
#define PMIC_RG_VPROC12_TRAN_BST_ADDR                    MT6355_VPROC_ANA_CON10
#define PMIC_RG_VPROC12_TRAN_BST_MASK                    0x3F
#define PMIC_RG_VPROC12_TRAN_BST_SHIFT                   6
#define PMIC_RG_VPROC11_COTRAMP_SLP_ADDR                 MT6355_VPROC_ANA_CON11
#define PMIC_RG_VPROC11_COTRAMP_SLP_MASK                 0x7
#define PMIC_RG_VPROC11_COTRAMP_SLP_SHIFT                0
#define PMIC_RG_VPROC12_COTRAMP_SLP_ADDR                 MT6355_VPROC_ANA_CON11
#define PMIC_RG_VPROC12_COTRAMP_SLP_MASK                 0x7
#define PMIC_RG_VPROC12_COTRAMP_SLP_SHIFT                3
#define PMIC_RG_VPROC11_SLEEP_TIME_ADDR                  MT6355_VPROC_ANA_CON11
#define PMIC_RG_VPROC11_SLEEP_TIME_MASK                  0x3
#define PMIC_RG_VPROC11_SLEEP_TIME_SHIFT                 6
#define PMIC_RG_VPROC12_SLEEP_TIME_ADDR                  MT6355_VPROC_ANA_CON11
#define PMIC_RG_VPROC12_SLEEP_TIME_MASK                  0x3
#define PMIC_RG_VPROC12_SLEEP_TIME_SHIFT                 8
#define PMIC_RG_VPROC11_VREFTB_ADDR                      MT6355_VPROC_ANA_CON11
#define PMIC_RG_VPROC11_VREFTB_MASK                      0x3
#define PMIC_RG_VPROC11_VREFTB_SHIFT                     10
#define PMIC_RG_VPROC12_VREFTB_ADDR                      MT6355_VPROC_ANA_CON11
#define PMIC_RG_VPROC12_VREFTB_MASK                      0x3
#define PMIC_RG_VPROC12_VREFTB_SHIFT                     12
#define PMIC_RG_VPROC11_CSNSLP_TRIM_ADDR                 MT6355_VPROC_ANA_CON12
#define PMIC_RG_VPROC11_CSNSLP_TRIM_MASK                 0xF
#define PMIC_RG_VPROC11_CSNSLP_TRIM_SHIFT                0
#define PMIC_RG_VPROC12_CSNSLP_TRIM_ADDR                 MT6355_VPROC_ANA_CON12
#define PMIC_RG_VPROC12_CSNSLP_TRIM_MASK                 0xF
#define PMIC_RG_VPROC12_CSNSLP_TRIM_SHIFT                4
#define PMIC_RG_VPROC11_CSPSLP_TRIM_ADDR                 MT6355_VPROC_ANA_CON12
#define PMIC_RG_VPROC11_CSPSLP_TRIM_MASK                 0xF
#define PMIC_RG_VPROC11_CSPSLP_TRIM_SHIFT                8
#define PMIC_RG_VPROC12_CSPSLP_TRIM_ADDR                 MT6355_VPROC_ANA_CON12
#define PMIC_RG_VPROC12_CSPSLP_TRIM_MASK                 0xF
#define PMIC_RG_VPROC12_CSPSLP_TRIM_SHIFT                12
#define PMIC_RG_VPROC11_FUGON_ADDR                       MT6355_VPROC_ANA_CON13
#define PMIC_RG_VPROC11_FUGON_MASK                       0x1
#define PMIC_RG_VPROC11_FUGON_SHIFT                      0
#define PMIC_RG_VPROC12_FUGON_ADDR                       MT6355_VPROC_ANA_CON13
#define PMIC_RG_VPROC12_FUGON_MASK                       0x1
#define PMIC_RG_VPROC12_FUGON_SHIFT                      1
#define PMIC_RG_VPROC11_FLGON_ADDR                       MT6355_VPROC_ANA_CON13
#define PMIC_RG_VPROC11_FLGON_MASK                       0x1
#define PMIC_RG_VPROC11_FLGON_SHIFT                      2
#define PMIC_RG_VPROC12_FLGON_ADDR                       MT6355_VPROC_ANA_CON13
#define PMIC_RG_VPROC12_FLGON_MASK                       0x1
#define PMIC_RG_VPROC12_FLGON_SHIFT                      3
#define PMIC_RG_VPROC11_PREOC_TRIM_ADDR                  MT6355_VPROC_ANA_CON13
#define PMIC_RG_VPROC11_PREOC_TRIM_MASK                  0x7
#define PMIC_RG_VPROC11_PREOC_TRIM_SHIFT                 4
#define PMIC_RG_VPROC11_RSV_ADDR                         MT6355_VPROC_ANA_CON14
#define PMIC_RG_VPROC11_RSV_MASK                         0xFFFF
#define PMIC_RG_VPROC11_RSV_SHIFT                        0
#define PMIC_RG_VPROC12_RSV_ADDR                         MT6355_VPROC_ANA_CON15
#define PMIC_RG_VPROC12_RSV_MASK                         0xFFFF
#define PMIC_RG_VPROC12_RSV_SHIFT                        0
#define PMIC_RG_VPROC11_NONAUDIBLE_EN_ADDR               MT6355_VPROC_ANA_CON16
#define PMIC_RG_VPROC11_NONAUDIBLE_EN_MASK               0x1
#define PMIC_RG_VPROC11_NONAUDIBLE_EN_SHIFT              0
#define PMIC_RG_VPROC12_NONAUDIBLE_EN_ADDR               MT6355_VPROC_ANA_CON16
#define PMIC_RG_VPROC12_NONAUDIBLE_EN_MASK               0x1
#define PMIC_RG_VPROC12_NONAUDIBLE_EN_SHIFT              1
#define PMIC_RG_VPROC_DISAUTOK_ADDR                      MT6355_VPROC_ANA_CON16
#define PMIC_RG_VPROC_DISAUTOK_MASK                      0x1
#define PMIC_RG_VPROC_DISAUTOK_SHIFT                     2
#define PMIC_RG_VCORE_FPWM_ADDR                          MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_FPWM_MASK                          0x1
#define PMIC_RG_VCORE_FPWM_SHIFT                         1
#define PMIC_RG_VGPU_FPWM_ADDR                           MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_FPWM_MASK                           0x1
#define PMIC_RG_VGPU_FPWM_SHIFT                          2
#define PMIC_RG_VCORE_NDIS_EN_ADDR                       MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_NDIS_EN_MASK                       0x1
#define PMIC_RG_VCORE_NDIS_EN_SHIFT                      3
#define PMIC_RG_VGPU_NDIS_EN_ADDR                        MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_NDIS_EN_MASK                        0x1
#define PMIC_RG_VGPU_NDIS_EN_SHIFT                       4
#define PMIC_RG_VCORE_FCOT_ADDR                          MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_FCOT_MASK                          0x1
#define PMIC_RG_VCORE_FCOT_SHIFT                         5
#define PMIC_RG_VGPU_FCOT_ADDR                           MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_FCOT_MASK                           0x1
#define PMIC_RG_VGPU_FCOT_SHIFT                          6
#define PMIC_RG_VCOREVGPU_TMDL_ADDR                      MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCOREVGPU_TMDL_MASK                      0x1
#define PMIC_RG_VCOREVGPU_TMDL_SHIFT                     7
#define PMIC_RG_VCOREVGPU_DISCONFIG20_ADDR               MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCOREVGPU_DISCONFIG20_MASK               0x1
#define PMIC_RG_VCOREVGPU_DISCONFIG20_SHIFT              8
#define PMIC_RG_VCORE_TBDIS_ADDR                         MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_TBDIS_MASK                         0x1
#define PMIC_RG_VCORE_TBDIS_SHIFT                        9
#define PMIC_RG_VGPU_TBDIS_ADDR                          MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_TBDIS_MASK                          0x1
#define PMIC_RG_VGPU_TBDIS_SHIFT                         10
#define PMIC_RG_VCORE_VDIFFOFF_ADDR                      MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_VDIFFOFF_MASK                      0x1
#define PMIC_RG_VCORE_VDIFFOFF_SHIFT                     11
#define PMIC_RG_VGPU_VDIFFOFF_ADDR                       MT6355_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_VDIFFOFF_MASK                       0x1
#define PMIC_RG_VGPU_VDIFFOFF_SHIFT                      12
#define PMIC_RG_VCORE_RCOMP0_ADDR                        MT6355_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_RCOMP0_MASK                        0xF
#define PMIC_RG_VCORE_RCOMP0_SHIFT                       0
#define PMIC_RG_VCORE_RCOMP1_ADDR                        MT6355_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_RCOMP1_MASK                        0x7
#define PMIC_RG_VCORE_RCOMP1_SHIFT                       4
#define PMIC_RG_VCORE_CCOMP0_ADDR                        MT6355_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_CCOMP0_MASK                        0x3
#define PMIC_RG_VCORE_CCOMP0_SHIFT                       7
#define PMIC_RG_VCORE_CCOMP1_ADDR                        MT6355_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_CCOMP1_MASK                        0x3
#define PMIC_RG_VCORE_CCOMP1_SHIFT                       9
#define PMIC_RG_VCORE_RAMP_SLP_ADDR                      MT6355_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_RAMP_SLP_MASK                      0x7
#define PMIC_RG_VCORE_RAMP_SLP_SHIFT                     11
#define PMIC_RG_VGPU_RCOMP0_ADDR                         MT6355_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_RCOMP0_MASK                         0xF
#define PMIC_RG_VGPU_RCOMP0_SHIFT                        0
#define PMIC_RG_VGPU_RCOMP1_ADDR                         MT6355_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_RCOMP1_MASK                         0x7
#define PMIC_RG_VGPU_RCOMP1_SHIFT                        4
#define PMIC_RG_VGPU_CCOMP0_ADDR                         MT6355_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_CCOMP0_MASK                         0x3
#define PMIC_RG_VGPU_CCOMP0_SHIFT                        7
#define PMIC_RG_VGPU_CCOMP1_ADDR                         MT6355_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_CCOMP1_MASK                         0x3
#define PMIC_RG_VGPU_CCOMP1_SHIFT                        9
#define PMIC_RG_VGPU_RAMP_SLP_ADDR                       MT6355_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_RAMP_SLP_MASK                       0x7
#define PMIC_RG_VGPU_RAMP_SLP_SHIFT                      11
#define PMIC_RG_VCORE_RCS_ADDR                           MT6355_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VCORE_RCS_MASK                           0x7
#define PMIC_RG_VCORE_RCS_SHIFT                          0
#define PMIC_RG_VGPU_RCS_ADDR                            MT6355_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VGPU_RCS_MASK                            0x7
#define PMIC_RG_VGPU_RCS_SHIFT                           3
#define PMIC_RG_VCORE_RCB_ADDR                           MT6355_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VCORE_RCB_MASK                           0xF
#define PMIC_RG_VCORE_RCB_SHIFT                          6
#define PMIC_RG_VGPU_RCB_ADDR                            MT6355_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VGPU_RCB_MASK                            0xF
#define PMIC_RG_VGPU_RCB_SHIFT                           10
#define PMIC_RG_VCORE_CSP_TRIM_ADDR                      MT6355_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_CSP_TRIM_MASK                      0x7
#define PMIC_RG_VCORE_CSP_TRIM_SHIFT                     0
#define PMIC_RG_VGPU_CSP_TRIM_ADDR                       MT6355_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VGPU_CSP_TRIM_MASK                       0x7
#define PMIC_RG_VGPU_CSP_TRIM_SHIFT                      3
#define PMIC_RG_VCORE_CSN_TRIM_ADDR                      MT6355_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_CSN_TRIM_MASK                      0x7
#define PMIC_RG_VCORE_CSN_TRIM_SHIFT                     6
#define PMIC_RG_VGPU_CSN_TRIM_ADDR                       MT6355_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VGPU_CSN_TRIM_MASK                       0x7
#define PMIC_RG_VGPU_CSN_TRIM_SHIFT                      9
#define PMIC_RG_VCORE_ZC_TRIM_ADDR                       MT6355_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_ZC_TRIM_MASK                       0x3
#define PMIC_RG_VCORE_ZC_TRIM_SHIFT                      12
#define PMIC_RG_VGPU_ZC_TRIM_ADDR                        MT6355_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VGPU_ZC_TRIM_MASK                        0x3
#define PMIC_RG_VGPU_ZC_TRIM_SHIFT                       14
#define PMIC_RG_VCORE_NLIM_TRIM_ADDR                     MT6355_VCORE_VGPU_ANA_CON5
#define PMIC_RG_VCORE_NLIM_TRIM_MASK                     0xF
#define PMIC_RG_VCORE_NLIM_TRIM_SHIFT                    0
#define PMIC_RG_VGPU_NLIM_TRIM_ADDR                      MT6355_VCORE_VGPU_ANA_CON5
#define PMIC_RG_VGPU_NLIM_TRIM_MASK                      0xF
#define PMIC_RG_VGPU_NLIM_TRIM_SHIFT                     4
#define PMIC_RG_VCORE_RPSI1_TRIM_ADDR                    MT6355_VCORE_VGPU_ANA_CON5
#define PMIC_RG_VCORE_RPSI1_TRIM_MASK                    0x7
#define PMIC_RG_VCORE_RPSI1_TRIM_SHIFT                   8
#define PMIC_RG_VGPU_RPSI1_TRIM_ADDR                     MT6355_VCORE_VGPU_ANA_CON5
#define PMIC_RG_VGPU_RPSI1_TRIM_MASK                     0x7
#define PMIC_RG_VGPU_RPSI1_TRIM_SHIFT                    11
#define PMIC_RG_VCORE_TB_WIDTH_ADDR                      MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VCORE_TB_WIDTH_MASK                      0x3
#define PMIC_RG_VCORE_TB_WIDTH_SHIFT                     0
#define PMIC_RG_VGPU_TB_WIDTH_ADDR                       MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VGPU_TB_WIDTH_MASK                       0x3
#define PMIC_RG_VGPU_TB_WIDTH_SHIFT                      2
#define PMIC_RG_VCORE_UG_SR_ADDR                         MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VCORE_UG_SR_MASK                         0x3
#define PMIC_RG_VCORE_UG_SR_SHIFT                        4
#define PMIC_RG_VCORE_LG_SR_ADDR                         MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VCORE_LG_SR_MASK                         0x3
#define PMIC_RG_VCORE_LG_SR_SHIFT                        6
#define PMIC_RG_VGPU_UG_SR_ADDR                          MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VGPU_UG_SR_MASK                          0x3
#define PMIC_RG_VGPU_UG_SR_SHIFT                         8
#define PMIC_RG_VGPU_LG_SR_ADDR                          MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VGPU_LG_SR_MASK                          0x3
#define PMIC_RG_VGPU_LG_SR_SHIFT                         10
#define PMIC_RG_VCORE_PFM_TON_ADDR                       MT6355_VCORE_VGPU_ANA_CON6
#define PMIC_RG_VCORE_PFM_TON_MASK                       0x7
#define PMIC_RG_VCORE_PFM_TON_SHIFT                      12
#define PMIC_RG_VGPU_PFM_TON_ADDR                        MT6355_VCORE_VGPU_ANA_CON7
#define PMIC_RG_VGPU_PFM_TON_MASK                        0x7
#define PMIC_RG_VGPU_PFM_TON_SHIFT                       0
#define PMIC_RG_VCORE_TON_TRIM_ADDR                      MT6355_VCORE_VGPU_ANA_CON7
#define PMIC_RG_VCORE_TON_TRIM_MASK                      0x3F
#define PMIC_RG_VCORE_TON_TRIM_SHIFT                     3
#define PMIC_RG_VGPU_TON_TRIM_ADDR                       MT6355_VCORE_VGPU_ANA_CON7
#define PMIC_RG_VGPU_TON_TRIM_MASK                       0x3F
#define PMIC_RG_VGPU_TON_TRIM_SHIFT                      9
#define PMIC_RGS_VCORE_OC_STATUS_ADDR                    MT6355_VCORE_VGPU_ANA_CON7
#define PMIC_RGS_VCORE_OC_STATUS_MASK                    0x1
#define PMIC_RGS_VCORE_OC_STATUS_SHIFT                   15
#define PMIC_RGS_VGPU_OC_STATUS_ADDR                     MT6355_VCORE_VGPU_ANA_CON8
#define PMIC_RGS_VGPU_OC_STATUS_MASK                     0x1
#define PMIC_RGS_VGPU_OC_STATUS_SHIFT                    0
#define PMIC_RGS_VCOREVGPU_TRIMOK_STATUS_ADDR            MT6355_VCORE_VGPU_ANA_CON8
#define PMIC_RGS_VCOREVGPU_TRIMOK_STATUS_MASK            0x1
#define PMIC_RGS_VCOREVGPU_TRIMOK_STATUS_SHIFT           1
#define PMIC_RGS_VCOREVGPU_CONFIG20_STATUS_ADDR          MT6355_VCORE_VGPU_ANA_CON8
#define PMIC_RGS_VCOREVGPU_CONFIG20_STATUS_MASK          0x1
#define PMIC_RGS_VCOREVGPU_CONFIG20_STATUS_SHIFT         2
#define PMIC_RGS_VCORE_PREOC_STATUS_ADDR                 MT6355_VCORE_VGPU_ANA_CON8
#define PMIC_RGS_VCORE_PREOC_STATUS_MASK                 0x1
#define PMIC_RGS_VCORE_PREOC_STATUS_SHIFT                3
#define PMIC_RGS_VCORE_DIG_MON_ADDR                      MT6355_VCORE_VGPU_ANA_CON9
#define PMIC_RGS_VCORE_DIG_MON_MASK                      0xFF
#define PMIC_RGS_VCORE_DIG_MON_SHIFT                     0
#define PMIC_RGS_VGPU_DIG_MON_ADDR                       MT6355_VCORE_VGPU_ANA_CON9
#define PMIC_RGS_VGPU_DIG_MON_MASK                       0xFF
#define PMIC_RGS_VGPU_DIG_MON_SHIFT                      8
#define PMIC_RG_VCORE_TRAN_BST_ADDR                      MT6355_VCORE_VGPU_ANA_CON10
#define PMIC_RG_VCORE_TRAN_BST_MASK                      0x3F
#define PMIC_RG_VCORE_TRAN_BST_SHIFT                     0
#define PMIC_RG_VGPU_TRAN_BST_ADDR                       MT6355_VCORE_VGPU_ANA_CON10
#define PMIC_RG_VGPU_TRAN_BST_MASK                       0x3F
#define PMIC_RG_VGPU_TRAN_BST_SHIFT                      6
#define PMIC_RG_VCORE_COTRAMP_SLP_ADDR                   MT6355_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VCORE_COTRAMP_SLP_MASK                   0x7
#define PMIC_RG_VCORE_COTRAMP_SLP_SHIFT                  0
#define PMIC_RG_VGPU_COTRAMP_SLP_ADDR                    MT6355_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VGPU_COTRAMP_SLP_MASK                    0x7
#define PMIC_RG_VGPU_COTRAMP_SLP_SHIFT                   3
#define PMIC_RG_VCORE_SLEEP_TIME_ADDR                    MT6355_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VCORE_SLEEP_TIME_MASK                    0x3
#define PMIC_RG_VCORE_SLEEP_TIME_SHIFT                   6
#define PMIC_RG_VGPU_SLEEP_TIME_ADDR                     MT6355_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VGPU_SLEEP_TIME_MASK                     0x3
#define PMIC_RG_VGPU_SLEEP_TIME_SHIFT                    8
#define PMIC_RG_VCORE_VREFTB_ADDR                        MT6355_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VCORE_VREFTB_MASK                        0x3
#define PMIC_RG_VCORE_VREFTB_SHIFT                       10
#define PMIC_RG_VGPU_VREFTB_ADDR                         MT6355_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VGPU_VREFTB_MASK                         0x3
#define PMIC_RG_VGPU_VREFTB_SHIFT                        12
#define PMIC_RG_VCORE_CSNSLP_TRIM_ADDR                   MT6355_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VCORE_CSNSLP_TRIM_MASK                   0xF
#define PMIC_RG_VCORE_CSNSLP_TRIM_SHIFT                  0
#define PMIC_RG_VGPU_CSNSLP_TRIM_ADDR                    MT6355_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VGPU_CSNSLP_TRIM_MASK                    0xF
#define PMIC_RG_VGPU_CSNSLP_TRIM_SHIFT                   4
#define PMIC_RG_VCORE_CSPSLP_TRIM_ADDR                   MT6355_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VCORE_CSPSLP_TRIM_MASK                   0xF
#define PMIC_RG_VCORE_CSPSLP_TRIM_SHIFT                  8
#define PMIC_RG_VGPU_CSPSLP_TRIM_ADDR                    MT6355_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VGPU_CSPSLP_TRIM_MASK                    0xF
#define PMIC_RG_VGPU_CSPSLP_TRIM_SHIFT                   12
#define PMIC_RG_VCORE_FUGON_ADDR                         MT6355_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VCORE_FUGON_MASK                         0x1
#define PMIC_RG_VCORE_FUGON_SHIFT                        0
#define PMIC_RG_VGPU_FUGON_ADDR                          MT6355_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VGPU_FUGON_MASK                          0x1
#define PMIC_RG_VGPU_FUGON_SHIFT                         1
#define PMIC_RG_VCORE_FLGON_ADDR                         MT6355_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VCORE_FLGON_MASK                         0x1
#define PMIC_RG_VCORE_FLGON_SHIFT                        2
#define PMIC_RG_VGPU_FLGON_ADDR                          MT6355_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VGPU_FLGON_MASK                          0x1
#define PMIC_RG_VGPU_FLGON_SHIFT                         3
#define PMIC_RG_VCORE_PREOC_TRIM_ADDR                    MT6355_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VCORE_PREOC_TRIM_MASK                    0x7
#define PMIC_RG_VCORE_PREOC_TRIM_SHIFT                   4
#define PMIC_RG_VCORE_RSV_ADDR                           MT6355_VCORE_VGPU_ANA_CON14
#define PMIC_RG_VCORE_RSV_MASK                           0xFFFF
#define PMIC_RG_VCORE_RSV_SHIFT                          0
#define PMIC_RG_VGPU_RSV_ADDR                            MT6355_VCORE_VGPU_ANA_CON15
#define PMIC_RG_VGPU_RSV_MASK                            0xFFFF
#define PMIC_RG_VGPU_RSV_SHIFT                           0
#define PMIC_RG_VCORE_NONAUDIBLE_EN_ADDR                 MT6355_VCORE_VGPU_ANA_CON16
#define PMIC_RG_VCORE_NONAUDIBLE_EN_MASK                 0x1
#define PMIC_RG_VCORE_NONAUDIBLE_EN_SHIFT                1
#define PMIC_RG_VGPU_NONAUDIBLE_EN_ADDR                  MT6355_VCORE_VGPU_ANA_CON16
#define PMIC_RG_VGPU_NONAUDIBLE_EN_MASK                  0x1
#define PMIC_RG_VGPU_NONAUDIBLE_EN_SHIFT                 2
#define PMIC_RG_VCOREVGPU_DISAUTOK_ADDR                  MT6355_VCORE_VGPU_ANA_CON16
#define PMIC_RG_VCOREVGPU_DISAUTOK_MASK                  0x1
#define PMIC_RG_VCOREVGPU_DISAUTOK_SHIFT                 3
#define PMIC_RG_VDRAM1_FCOT_ADDR                         MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_FCOT_MASK                         0x1
#define PMIC_RG_VDRAM1_FCOT_SHIFT                        1
#define PMIC_RG_VDRAM1_RCOMP_ADDR                        MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_RCOMP_MASK                        0xF
#define PMIC_RG_VDRAM1_RCOMP_SHIFT                       2
#define PMIC_RG_VDRAM1_TB_DIS_ADDR                       MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_TB_DIS_MASK                       0x1
#define PMIC_RG_VDRAM1_TB_DIS_SHIFT                      6
#define PMIC_RG_VDRAM1_DISPG_ADDR                        MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_DISPG_MASK                        0x1
#define PMIC_RG_VDRAM1_DISPG_SHIFT                       7
#define PMIC_RG_VDRAM1_FPWM_ADDR                         MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_FPWM_MASK                         0x1
#define PMIC_RG_VDRAM1_FPWM_SHIFT                        8
#define PMIC_RG_VDRAM1_ZC_TRIM_ADDR                      MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_ZC_TRIM_MASK                      0x3
#define PMIC_RG_VDRAM1_ZC_TRIM_SHIFT                     9
#define PMIC_RG_VDRAM1_NLIM_TRIM_ADDR                    MT6355_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_NLIM_TRIM_MASK                    0xF
#define PMIC_RG_VDRAM1_NLIM_TRIM_SHIFT                   11
#define PMIC_RG_VDRAM1_PFM_TON_ADDR                      MT6355_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_PFM_TON_MASK                      0x7
#define PMIC_RG_VDRAM1_PFM_TON_SHIFT                     0
#define PMIC_RG_VDRAM1_PWMRAMP_SLP_ADDR                  MT6355_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_PWMRAMP_SLP_MASK                  0x7
#define PMIC_RG_VDRAM1_PWMRAMP_SLP_SHIFT                 3
#define PMIC_RG_VDRAM1_COTRAMP_SLP_ADDR                  MT6355_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_COTRAMP_SLP_MASK                  0x7
#define PMIC_RG_VDRAM1_COTRAMP_SLP_SHIFT                 6
#define PMIC_RG_VDRAM1_RCS_ADDR                          MT6355_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_RCS_MASK                          0x7
#define PMIC_RG_VDRAM1_RCS_SHIFT                         9
#define PMIC_RG_VDRAM1_CSN_TRIM_ADDR                     MT6355_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_CSN_TRIM_MASK                     0x7
#define PMIC_RG_VDRAM1_CSN_TRIM_SHIFT                    0
#define PMIC_RG_VDRAM1_CSP_TRIM_ADDR                     MT6355_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_CSP_TRIM_MASK                     0x7
#define PMIC_RG_VDRAM1_CSP_TRIM_SHIFT                    3
#define PMIC_RG_VDRAM1_RPSI_TRIM_ADDR                    MT6355_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_RPSI_TRIM_MASK                    0x7
#define PMIC_RG_VDRAM1_RPSI_TRIM_SHIFT                   6
#define PMIC_RG_VDRAM1_SLEEP_TIME_ADDR                   MT6355_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_SLEEP_TIME_MASK                   0x3
#define PMIC_RG_VDRAM1_SLEEP_TIME_SHIFT                  9
#define PMIC_RG_VDRAM1_NLIM_GATING_ADDR                  MT6355_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_NLIM_GATING_MASK                  0x1
#define PMIC_RG_VDRAM1_NLIM_GATING_SHIFT                 11
#define PMIC_RG_VDRAM1_TON_TRIM_ADDR                     MT6355_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_TON_TRIM_MASK                     0x3F
#define PMIC_RG_VDRAM1_TON_TRIM_SHIFT                    0
#define PMIC_RG_VDRAM1_VDIFF_OFF_ADDR                    MT6355_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_VDIFF_OFF_MASK                    0x1
#define PMIC_RG_VDRAM1_VDIFF_OFF_SHIFT                   6
#define PMIC_RG_VDRAM1_VREFUP_ADDR                       MT6355_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_VREFUP_MASK                       0x3
#define PMIC_RG_VDRAM1_VREFUP_SHIFT                      7
#define PMIC_RG_VDRAM1_TB_WIDTH_ADDR                     MT6355_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_TB_WIDTH_MASK                     0x3
#define PMIC_RG_VDRAM1_TB_WIDTH_SHIFT                    9
#define PMIC_RG_VDRAM1_UG_SR_ADDR                        MT6355_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_UG_SR_MASK                        0x3
#define PMIC_RG_VDRAM1_UG_SR_SHIFT                       11
#define PMIC_RG_VDRAM1_LG_SR_ADDR                        MT6355_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_LG_SR_MASK                        0x3
#define PMIC_RG_VDRAM1_LG_SR_SHIFT                       13
#define PMIC_RG_VDRAM1_CCOMP_ADDR                        MT6355_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_CCOMP_MASK                        0x3
#define PMIC_RG_VDRAM1_CCOMP_SHIFT                       0
#define PMIC_RG_VDRAM1_NDIS_EN_ADDR                      MT6355_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_NDIS_EN_MASK                      0x1
#define PMIC_RG_VDRAM1_NDIS_EN_SHIFT                     2
#define PMIC_RG_VDRAM1_TMDL_ADDR                         MT6355_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_TMDL_MASK                         0x1
#define PMIC_RG_VDRAM1_TMDL_SHIFT                        3
#define PMIC_RG_VDRAM1_RSV_ADDR                          MT6355_VDRAM1_ANA_CON5
#define PMIC_RG_VDRAM1_RSV_MASK                          0xFFFF
#define PMIC_RG_VDRAM1_RSV_SHIFT                         0
#define PMIC_RG_VDRAM1_CSNSLP_TRIM_ADDR                  MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_CSNSLP_TRIM_MASK                  0xF
#define PMIC_RG_VDRAM1_CSNSLP_TRIM_SHIFT                 0
#define PMIC_RG_VDRAM1_CSPSLP_TRIM_ADDR                  MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_CSPSLP_TRIM_MASK                  0xF
#define PMIC_RG_VDRAM1_CSPSLP_TRIM_SHIFT                 4
#define PMIC_RG_VDRAM1_FUGON_ADDR                        MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_FUGON_MASK                        0x1
#define PMIC_RG_VDRAM1_FUGON_SHIFT                       8
#define PMIC_RG_VDRAM1_FLGON_ADDR                        MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_FLGON_MASK                        0x1
#define PMIC_RG_VDRAM1_FLGON_SHIFT                       9
#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_ADDR                MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_MASK                0x1
#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_SHIFT               10
#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_ADDR                 MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_MASK                 0x1
#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_SHIFT                11
#define PMIC_RGS_VDRAM1_OC_STATUS_ADDR                   MT6355_VDRAM1_ANA_CON6
#define PMIC_RGS_VDRAM1_OC_STATUS_MASK                   0x1
#define PMIC_RGS_VDRAM1_OC_STATUS_SHIFT                  12
#define PMIC_RGS_VDRAM1_ENPWM_STATUS_ADDR                MT6355_VDRAM1_ANA_CON6
#define PMIC_RGS_VDRAM1_ENPWM_STATUS_MASK                0x1
#define PMIC_RGS_VDRAM1_ENPWM_STATUS_SHIFT               13
#define PMIC_RG_VDRAM1_DISAUTOK_ADDR                     MT6355_VDRAM1_ANA_CON6
#define PMIC_RG_VDRAM1_DISAUTOK_MASK                     0x1
#define PMIC_RG_VDRAM1_DISAUTOK_SHIFT                    14
#define PMIC_RGS_VDRAM1_TRIMOK_STATUS_ADDR               MT6355_VDRAM1_ANA_CON6
#define PMIC_RGS_VDRAM1_TRIMOK_STATUS_MASK               0x1
#define PMIC_RGS_VDRAM1_TRIMOK_STATUS_SHIFT              15
#define PMIC_RGS_VDRAM1_DIG_MON_ADDR                     MT6355_VDRAM1_ANA_CON7
#define PMIC_RGS_VDRAM1_DIG_MON_MASK                     0xFF
#define PMIC_RGS_VDRAM1_DIG_MON_SHIFT                    0
#define PMIC_RG_VDRAM2_FCOT_ADDR                         MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_FCOT_MASK                         0x1
#define PMIC_RG_VDRAM2_FCOT_SHIFT                        1
#define PMIC_RG_VDRAM2_RCOMP_ADDR                        MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_RCOMP_MASK                        0xF
#define PMIC_RG_VDRAM2_RCOMP_SHIFT                       2
#define PMIC_RG_VDRAM2_TB_DIS_ADDR                       MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_TB_DIS_MASK                       0x1
#define PMIC_RG_VDRAM2_TB_DIS_SHIFT                      6
#define PMIC_RG_VDRAM2_DISPG_ADDR                        MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_DISPG_MASK                        0x1
#define PMIC_RG_VDRAM2_DISPG_SHIFT                       7
#define PMIC_RG_VDRAM2_FPWM_ADDR                         MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_FPWM_MASK                         0x1
#define PMIC_RG_VDRAM2_FPWM_SHIFT                        8
#define PMIC_RG_VDRAM2_ZC_TRIM_ADDR                      MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_ZC_TRIM_MASK                      0x3
#define PMIC_RG_VDRAM2_ZC_TRIM_SHIFT                     9
#define PMIC_RG_VDRAM2_NLIM_TRIM_ADDR                    MT6355_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_NLIM_TRIM_MASK                    0xF
#define PMIC_RG_VDRAM2_NLIM_TRIM_SHIFT                   11
#define PMIC_RG_VDRAM2_PFM_TON_ADDR                      MT6355_VDRAM2_ANA_CON1
#define PMIC_RG_VDRAM2_PFM_TON_MASK                      0x7
#define PMIC_RG_VDRAM2_PFM_TON_SHIFT                     0
#define PMIC_RG_VDRAM2_PWMRAMP_SLP_ADDR                  MT6355_VDRAM2_ANA_CON1
#define PMIC_RG_VDRAM2_PWMRAMP_SLP_MASK                  0x7
#define PMIC_RG_VDRAM2_PWMRAMP_SLP_SHIFT                 3
#define PMIC_RG_VDRAM2_COTRAMP_SLP_ADDR                  MT6355_VDRAM2_ANA_CON1
#define PMIC_RG_VDRAM2_COTRAMP_SLP_MASK                  0x7
#define PMIC_RG_VDRAM2_COTRAMP_SLP_SHIFT                 6
#define PMIC_RG_VDRAM2_RCS_ADDR                          MT6355_VDRAM2_ANA_CON1
#define PMIC_RG_VDRAM2_RCS_MASK                          0x7
#define PMIC_RG_VDRAM2_RCS_SHIFT                         9
#define PMIC_RG_VDRAM2_CSN_TRIM_ADDR                     MT6355_VDRAM2_ANA_CON2
#define PMIC_RG_VDRAM2_CSN_TRIM_MASK                     0x7
#define PMIC_RG_VDRAM2_CSN_TRIM_SHIFT                    0
#define PMIC_RG_VDRAM2_CSP_TRIM_ADDR                     MT6355_VDRAM2_ANA_CON2
#define PMIC_RG_VDRAM2_CSP_TRIM_MASK                     0x7
#define PMIC_RG_VDRAM2_CSP_TRIM_SHIFT                    3
#define PMIC_RG_VDRAM2_RPSI_TRIM_ADDR                    MT6355_VDRAM2_ANA_CON2
#define PMIC_RG_VDRAM2_RPSI_TRIM_MASK                    0x7
#define PMIC_RG_VDRAM2_RPSI_TRIM_SHIFT                   6
#define PMIC_RG_VDRAM2_SLEEP_TIME_ADDR                   MT6355_VDRAM2_ANA_CON2
#define PMIC_RG_VDRAM2_SLEEP_TIME_MASK                   0x3
#define PMIC_RG_VDRAM2_SLEEP_TIME_SHIFT                  9
#define PMIC_RG_VDRAM2_NLIM_GATING_ADDR                  MT6355_VDRAM2_ANA_CON2
#define PMIC_RG_VDRAM2_NLIM_GATING_MASK                  0x1
#define PMIC_RG_VDRAM2_NLIM_GATING_SHIFT                 11
#define PMIC_RG_VDRAM2_TON_TRIM_ADDR                     MT6355_VDRAM2_ANA_CON3
#define PMIC_RG_VDRAM2_TON_TRIM_MASK                     0x3F
#define PMIC_RG_VDRAM2_TON_TRIM_SHIFT                    0
#define PMIC_RG_VDRAM2_VDIFF_OFF_ADDR                    MT6355_VDRAM2_ANA_CON3
#define PMIC_RG_VDRAM2_VDIFF_OFF_MASK                    0x1
#define PMIC_RG_VDRAM2_VDIFF_OFF_SHIFT                   6
#define PMIC_RG_VDRAM2_VREFUP_ADDR                       MT6355_VDRAM2_ANA_CON3
#define PMIC_RG_VDRAM2_VREFUP_MASK                       0x3
#define PMIC_RG_VDRAM2_VREFUP_SHIFT                      7
#define PMIC_RG_VDRAM2_TB_WIDTH_ADDR                     MT6355_VDRAM2_ANA_CON3
#define PMIC_RG_VDRAM2_TB_WIDTH_MASK                     0x3
#define PMIC_RG_VDRAM2_TB_WIDTH_SHIFT                    9
#define PMIC_RG_VDRAM2_UG_SR_ADDR                        MT6355_VDRAM2_ANA_CON3
#define PMIC_RG_VDRAM2_UG_SR_MASK                        0x3
#define PMIC_RG_VDRAM2_UG_SR_SHIFT                       11
#define PMIC_RG_VDRAM2_LG_SR_ADDR                        MT6355_VDRAM2_ANA_CON3
#define PMIC_RG_VDRAM2_LG_SR_MASK                        0x3
#define PMIC_RG_VDRAM2_LG_SR_SHIFT                       13
#define PMIC_RG_VDRAM2_CCOMP_ADDR                        MT6355_VDRAM2_ANA_CON4
#define PMIC_RG_VDRAM2_CCOMP_MASK                        0x3
#define PMIC_RG_VDRAM2_CCOMP_SHIFT                       0
#define PMIC_RG_VDRAM2_NDIS_EN_ADDR                      MT6355_VDRAM2_ANA_CON4
#define PMIC_RG_VDRAM2_NDIS_EN_MASK                      0x1
#define PMIC_RG_VDRAM2_NDIS_EN_SHIFT                     2
#define PMIC_RG_VDRAM2_TMDL_ADDR                         MT6355_VDRAM2_ANA_CON4
#define PMIC_RG_VDRAM2_TMDL_MASK                         0x1
#define PMIC_RG_VDRAM2_TMDL_SHIFT                        3
#define PMIC_RG_VDRAM2_RSV_ADDR                          MT6355_VDRAM2_ANA_CON5
#define PMIC_RG_VDRAM2_RSV_MASK                          0xFFFF
#define PMIC_RG_VDRAM2_RSV_SHIFT                         0
#define PMIC_RG_VDRAM2_CSNSLP_TRIM_ADDR                  MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_CSNSLP_TRIM_MASK                  0xF
#define PMIC_RG_VDRAM2_CSNSLP_TRIM_SHIFT                 0
#define PMIC_RG_VDRAM2_CSPSLP_TRIM_ADDR                  MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_CSPSLP_TRIM_MASK                  0xF
#define PMIC_RG_VDRAM2_CSPSLP_TRIM_SHIFT                 4
#define PMIC_RG_VDRAM2_FUGON_ADDR                        MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_FUGON_MASK                        0x1
#define PMIC_RG_VDRAM2_FUGON_SHIFT                       8
#define PMIC_RG_VDRAM2_FLGON_ADDR                        MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_FLGON_MASK                        0x1
#define PMIC_RG_VDRAM2_FLGON_SHIFT                       9
#define PMIC_RG_VDRAM2_NONAUDIBLE_EN_ADDR                MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_NONAUDIBLE_EN_MASK                0x1
#define PMIC_RG_VDRAM2_NONAUDIBLE_EN_SHIFT               10
#define PMIC_RG_VDRAM2_VDIFFPFM_OFF_ADDR                 MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_VDIFFPFM_OFF_MASK                 0x1
#define PMIC_RG_VDRAM2_VDIFFPFM_OFF_SHIFT                11
#define PMIC_RGS_VDRAM2_OC_STATUS_ADDR                   MT6355_VDRAM2_ANA_CON6
#define PMIC_RGS_VDRAM2_OC_STATUS_MASK                   0x1
#define PMIC_RGS_VDRAM2_OC_STATUS_SHIFT                  12
#define PMIC_RGS_VDRAM2_ENPWM_STATUS_ADDR                MT6355_VDRAM2_ANA_CON6
#define PMIC_RGS_VDRAM2_ENPWM_STATUS_MASK                0x1
#define PMIC_RGS_VDRAM2_ENPWM_STATUS_SHIFT               13
#define PMIC_RG_VDRAM2_DISAUTOK_ADDR                     MT6355_VDRAM2_ANA_CON6
#define PMIC_RG_VDRAM2_DISAUTOK_MASK                     0x1
#define PMIC_RG_VDRAM2_DISAUTOK_SHIFT                    14
#define PMIC_RGS_VDRAM2_TRIMOK_STATUS_ADDR               MT6355_VDRAM2_ANA_CON6
#define PMIC_RGS_VDRAM2_TRIMOK_STATUS_MASK               0x1
#define PMIC_RGS_VDRAM2_TRIMOK_STATUS_SHIFT              15
#define PMIC_RGS_VDRAM2_DIG_MON_ADDR                     MT6355_VDRAM2_ANA_CON7
#define PMIC_RGS_VDRAM2_DIG_MON_MASK                     0xFF
#define PMIC_RGS_VDRAM2_DIG_MON_SHIFT                    0
#define PMIC_RG_VMODEM_MODESET_ADDR                      MT6355_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_MODESET_MASK                      0x1
#define PMIC_RG_VMODEM_MODESET_SHIFT                     1
#define PMIC_RG_VMODEM_NDIS_EN_ADDR                      MT6355_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_NDIS_EN_MASK                      0x1
#define PMIC_RG_VMODEM_NDIS_EN_SHIFT                     2
#define PMIC_RG_VMODEM_VRF18_SSTART_EN_ADDR              MT6355_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_VRF18_SSTART_EN_MASK              0x1
#define PMIC_RG_VMODEM_VRF18_SSTART_EN_SHIFT             3
#define PMIC_RG_VMODEM_AUTO_MODE_ADDR                    MT6355_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_AUTO_MODE_MASK                    0x1
#define PMIC_RG_VMODEM_AUTO_MODE_SHIFT                   4
#define PMIC_RG_VMODEM_RZSEL0_ADDR                       MT6355_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_RZSEL0_MASK                       0x7
#define PMIC_RG_VMODEM_RZSEL0_SHIFT                      0
#define PMIC_RG_VMODEM_RZSEL1_ADDR                       MT6355_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_RZSEL1_MASK                       0xF
#define PMIC_RG_VMODEM_RZSEL1_SHIFT                      3
#define PMIC_RG_VMODEM_CCSEL0_ADDR                       MT6355_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_CCSEL0_MASK                       0x3
#define PMIC_RG_VMODEM_CCSEL0_SHIFT                      7
#define PMIC_RG_VMODEM_CCSEL1_ADDR                       MT6355_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_CCSEL1_MASK                       0x3
#define PMIC_RG_VMODEM_CCSEL1_SHIFT                      9
#define PMIC_RG_VMODEM_CSL_ADDR                          MT6355_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_CSL_MASK                          0xF
#define PMIC_RG_VMODEM_CSL_SHIFT                         11
#define PMIC_RG_VMODEM_SLP_ADDR                          MT6355_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_SLP_MASK                          0x7
#define PMIC_RG_VMODEM_SLP_SHIFT                         0
#define PMIC_RG_VMODEM_ADRC_FEN_ADDR                     MT6355_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_ADRC_FEN_MASK                     0x1
#define PMIC_RG_VMODEM_ADRC_FEN_SHIFT                    3
#define PMIC_RG_VMODEM_VC_CAP_CLAMP_FEN_ADDR             MT6355_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_VC_CAP_CLAMP_FEN_MASK             0x1
#define PMIC_RG_VMODEM_VC_CAP_CLAMP_FEN_SHIFT            4
#define PMIC_RG_VMODEM_VC_CLAMP_FEN_ADDR                 MT6355_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_VC_CLAMP_FEN_MASK                 0x1
#define PMIC_RG_VMODEM_VC_CLAMP_FEN_SHIFT                5
#define PMIC_RG_VMODEM_BURST_ADDR                        MT6355_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_BURST_MASK                        0x7
#define PMIC_RG_VMODEM_BURST_SHIFT                       6
#define PMIC_RG_VMODEM_CSR_ADDR                          MT6355_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_CSR_MASK                          0x7
#define PMIC_RG_VMODEM_CSR_SHIFT                         9
#define PMIC_RG_VMODEM_ZXOS_TRIM_ADDR                    MT6355_VMODEM_ANA_CON3
#define PMIC_RG_VMODEM_ZXOS_TRIM_MASK                    0xFF
#define PMIC_RG_VMODEM_ZXOS_TRIM_SHIFT                   0
#define PMIC_RG_VMODEM_PFMSR_EH_ADDR                     MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_PFMSR_EH_MASK                     0x1
#define PMIC_RG_VMODEM_PFMSR_EH_SHIFT                    0
#define PMIC_RG_VMODEM_NLIM_GATING_ADDR                  MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_NLIM_GATING_MASK                  0x1
#define PMIC_RG_VMODEM_NLIM_GATING_SHIFT                 1
#define PMIC_RG_VMODEM_PWMSR_EH_ADDR                     MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_PWMSR_EH_MASK                     0x1
#define PMIC_RG_VMODEM_PWMSR_EH_SHIFT                    2
#define PMIC_RG_VMODEM_HS_VTHDET_ADDR                    MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_HS_VTHDET_MASK                    0x1
#define PMIC_RG_VMODEM_HS_VTHDET_SHIFT                   3
#define PMIC_RG_VMODEM_PG_GATING_ADDR                    MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_PG_GATING_MASK                    0x1
#define PMIC_RG_VMODEM_PG_GATING_SHIFT                   4
#define PMIC_RG_VMODEM_HS_ONSPEED_EH_ADDR                MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_HS_ONSPEED_EH_MASK                0x1
#define PMIC_RG_VMODEM_HS_ONSPEED_EH_SHIFT               5
#define PMIC_RG_VMODEM_NLIM_TRIMMING_ADDR                MT6355_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_NLIM_TRIMMING_MASK                0xF
#define PMIC_RG_VMODEM_NLIM_TRIMMING_SHIFT               6
#define PMIC_RG_VMODEM_SR_P_ADDR                         MT6355_VMODEM_ANA_CON5
#define PMIC_RG_VMODEM_SR_P_MASK                         0x3
#define PMIC_RG_VMODEM_SR_P_SHIFT                        0
#define PMIC_RG_VMODEM_SR_N_ADDR                         MT6355_VMODEM_ANA_CON5
#define PMIC_RG_VMODEM_SR_N_MASK                         0x3
#define PMIC_RG_VMODEM_SR_N_SHIFT                        2
#define PMIC_RG_VMODEM_PFM_RIP_ADDR                      MT6355_VMODEM_ANA_CON5
#define PMIC_RG_VMODEM_PFM_RIP_MASK                      0x7
#define PMIC_RG_VMODEM_PFM_RIP_SHIFT                     4
#define PMIC_RG_VMODEM_TRAN_BST_ADDR                     MT6355_VMODEM_ANA_CON5
#define PMIC_RG_VMODEM_TRAN_BST_MASK                     0x3F
#define PMIC_RG_VMODEM_TRAN_BST_SHIFT                    7
#define PMIC_RG_VMODEM_DTS_ENB_ADDR                      MT6355_VMODEM_ANA_CON5
#define PMIC_RG_VMODEM_DTS_ENB_MASK                      0x1
#define PMIC_RG_VMODEM_DTS_ENB_SHIFT                     13
#define PMIC_RG_VMODEM_MIN_OFF_ADDR                      MT6355_VMODEM_ANA_CON5
#define PMIC_RG_VMODEM_MIN_OFF_MASK                      0x3
#define PMIC_RG_VMODEM_MIN_OFF_SHIFT                     14
#define PMIC_RG_VMODEM_1P35UP_SEL_EN_ADDR                MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_1P35UP_SEL_EN_MASK                0x1
#define PMIC_RG_VMODEM_1P35UP_SEL_EN_SHIFT               0
#define PMIC_RG_VMODEM_DLC_AUTO_MODE_ADDR                MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_DLC_AUTO_MODE_MASK                0x1
#define PMIC_RG_VMODEM_DLC_AUTO_MODE_SHIFT               1
#define PMIC_RG_VMODEM_SRC_AUTO_MODE_ADDR                MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_SRC_AUTO_MODE_MASK                0x1
#define PMIC_RG_VMODEM_SRC_AUTO_MODE_SHIFT               2
#define PMIC_RG_VMODEM_UGP_SR_ADDR                       MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_UGP_SR_MASK                       0x3
#define PMIC_RG_VMODEM_UGP_SR_SHIFT                      3
#define PMIC_RG_VMODEM_LGP_SR_ADDR                       MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_LGP_SR_MASK                       0x3
#define PMIC_RG_VMODEM_LGP_SR_SHIFT                      5
#define PMIC_RG_VMODEM_UGP_SR_PFM_ADDR                   MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_UGP_SR_PFM_MASK                   0x3
#define PMIC_RG_VMODEM_UGP_SR_PFM_SHIFT                  7
#define PMIC_RG_VMODEM_LGP_SR_PFM_ADDR                   MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_LGP_SR_PFM_MASK                   0x3
#define PMIC_RG_VMODEM_LGP_SR_PFM_SHIFT                  9
#define PMIC_RG_VMODEM_UGD_VTHSEL_ADDR                   MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_UGD_VTHSEL_MASK                   0x3
#define PMIC_RG_VMODEM_UGD_VTHSEL_SHIFT                  11
#define PMIC_RG_VMODEM_FNLX_ADDR                         MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_FNLX_MASK                         0x1
#define PMIC_RG_VMODEM_FNLX_SHIFT                        13
#define PMIC_RG_VMODEM_VDIFF_ENLOWIQ_ADDR                MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_VDIFF_ENLOWIQ_MASK                0x1
#define PMIC_RG_VMODEM_VDIFF_ENLOWIQ_SHIFT               14
#define PMIC_RG_VMODEM_PFMOC_FWUPOFF_ADDR                MT6355_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_PFMOC_FWUPOFF_MASK                0x1
#define PMIC_RG_VMODEM_PFMOC_FWUPOFF_SHIFT               15
#define PMIC_RG_VMODEM_PWMOC_FWUPOFF_ADDR                MT6355_VMODEM_ANA_CON7
#define PMIC_RG_VMODEM_PWMOC_FWUPOFF_MASK                0x1
#define PMIC_RG_VMODEM_PWMOC_FWUPOFF_SHIFT               0
#define PMIC_RG_VMODEM_CP_FWUPOFF_ADDR                   MT6355_VMODEM_ANA_CON7
#define PMIC_RG_VMODEM_CP_FWUPOFF_MASK                   0x1
#define PMIC_RG_VMODEM_CP_FWUPOFF_SHIFT                  1
#define PMIC_RG_VMODEM_ZX_GATING_ADDR                    MT6355_VMODEM_ANA_CON7
#define PMIC_RG_VMODEM_ZX_GATING_MASK                    0x1
#define PMIC_RG_VMODEM_ZX_GATING_SHIFT                   2
#define PMIC_RG_VMODEM_RSV_ADDR                          MT6355_VMODEM_ANA_CON8
#define PMIC_RG_VMODEM_RSV_MASK                          0xFFFF
#define PMIC_RG_VMODEM_RSV_SHIFT                         0
#define PMIC_RG_VMODEM_AZC_EN_ADDR                       MT6355_VMODEM_ANA_CON9
#define PMIC_RG_VMODEM_AZC_EN_MASK                       0x1
#define PMIC_RG_VMODEM_AZC_EN_SHIFT                      0
#define PMIC_RG_VMODEM_AZC_DELAY_ADDR                    MT6355_VMODEM_ANA_CON9
#define PMIC_RG_VMODEM_AZC_DELAY_MASK                    0x3
#define PMIC_RG_VMODEM_AZC_DELAY_SHIFT                   1
#define PMIC_RG_VMODEM_AZC_HOLD_ENB_ADDR                 MT6355_VMODEM_ANA_CON9
#define PMIC_RG_VMODEM_AZC_HOLD_ENB_MASK                 0x1
#define PMIC_RG_VMODEM_AZC_HOLD_ENB_SHIFT                3
#define PMIC_RGS_VMODEM_OC_STATUS_ADDR                   MT6355_VMODEM_ANA_CON9
#define PMIC_RGS_VMODEM_OC_STATUS_MASK                   0x1
#define PMIC_RGS_VMODEM_OC_STATUS_SHIFT                  4
#define PMIC_RGS_VMODEM_DIG_MON_ADDR                     MT6355_VMODEM_ANA_CON9
#define PMIC_RGS_VMODEM_DIG_MON_MASK                     0xF
#define PMIC_RGS_VMODEM_DIG_MON_SHIFT                    5
#define PMIC_RGS_VMODEM_ENPWM_STATUS_ADDR                MT6355_VMODEM_ANA_CON9
#define PMIC_RGS_VMODEM_ENPWM_STATUS_MASK                0x1
#define PMIC_RGS_VMODEM_ENPWM_STATUS_SHIFT               9
#define PMIC_RG_VMODEM_IODETECT_EN18_ADDR                MT6355_VMODEM_ANA_CON9
#define PMIC_RG_VMODEM_IODETECT_EN18_MASK                0x1
#define PMIC_RG_VMODEM_IODETECT_EN18_SHIFT               10
#define PMIC_RG_VMODEM_PREOC_SEL_ADDR                    MT6355_VMODEM_ANA_CON9
#define PMIC_RG_VMODEM_PREOC_SEL_MASK                    0x7
#define PMIC_RG_VMODEM_PREOC_SEL_SHIFT                   11
#define PMIC_RG_VMODEM_NONAUDIBLE_EN_ADDR                MT6355_VMODEM_ANA_CON9
#define PMIC_RG_VMODEM_NONAUDIBLE_EN_MASK                0x1
#define PMIC_RG_VMODEM_NONAUDIBLE_EN_SHIFT               14
#define PMIC_RG_VS1_MIN_OFF_ADDR                         MT6355_VS1_ANA_CON0
#define PMIC_RG_VS1_MIN_OFF_MASK                         0x3
#define PMIC_RG_VS1_MIN_OFF_SHIFT                        0
#define PMIC_RG_VS1_VRF18_SSTART_EN_ADDR                 MT6355_VS1_ANA_CON0
#define PMIC_RG_VS1_VRF18_SSTART_EN_MASK                 0x1
#define PMIC_RG_VS1_VRF18_SSTART_EN_SHIFT                2
#define PMIC_RG_VS1_1P35UP_SEL_EN_ADDR                   MT6355_VS1_ANA_CON0
#define PMIC_RG_VS1_1P35UP_SEL_EN_MASK                   0x1
#define PMIC_RG_VS1_1P35UP_SEL_EN_SHIFT                  3
#define PMIC_RG_VS1_RZSEL_ADDR                           MT6355_VS1_ANA_CON0
#define PMIC_RG_VS1_RZSEL_MASK                           0x7
#define PMIC_RG_VS1_RZSEL_SHIFT                          4
#define PMIC_RG_VS1_CSR_ADDR                             MT6355_VS1_ANA_CON0
#define PMIC_RG_VS1_CSR_MASK                             0x7
#define PMIC_RG_VS1_CSR_SHIFT                            7
#define PMIC_RG_VS1_CSL_ADDR                             MT6355_VS1_ANA_CON0
#define PMIC_RG_VS1_CSL_MASK                             0xF
#define PMIC_RG_VS1_CSL_SHIFT                            10
#define PMIC_RG_VS1_SLP_ADDR                             MT6355_VS1_ANA_CON1
#define PMIC_RG_VS1_SLP_MASK                             0x7
#define PMIC_RG_VS1_SLP_SHIFT                            0
#define PMIC_RG_VS1_ZX_OS_ADDR                           MT6355_VS1_ANA_CON1
#define PMIC_RG_VS1_ZX_OS_MASK                           0xF
#define PMIC_RG_VS1_ZX_OS_SHIFT                          3
#define PMIC_RG_VS1_NDIS_EN_ADDR                         MT6355_VS1_ANA_CON1
#define PMIC_RG_VS1_NDIS_EN_MASK                         0x1
#define PMIC_RG_VS1_NDIS_EN_SHIFT                        7
#define PMIC_RG_VS1_CSM_N_ADDR                           MT6355_VS1_ANA_CON1
#define PMIC_RG_VS1_CSM_N_MASK                           0x3F
#define PMIC_RG_VS1_CSM_N_SHIFT                          8
#define PMIC_RG_VS1_CSM_P_ADDR                           MT6355_VS1_ANA_CON2
#define PMIC_RG_VS1_CSM_P_MASK                           0x3F
#define PMIC_RG_VS1_CSM_P_SHIFT                          0
#define PMIC_RG_VS1_RSV_ADDR                             MT6355_VS1_ANA_CON2
#define PMIC_RG_VS1_RSV_MASK                             0xFF
#define PMIC_RG_VS1_RSV_SHIFT                            6
#define PMIC_RG_VS1_ZXOS_TRIM_ADDR                       MT6355_VS1_ANA_CON3
#define PMIC_RG_VS1_ZXOS_TRIM_MASK                       0xFF
#define PMIC_RG_VS1_ZXOS_TRIM_SHIFT                      0
#define PMIC_RG_VS1_MODESET_ADDR                         MT6355_VS1_ANA_CON3
#define PMIC_RG_VS1_MODESET_MASK                         0x1
#define PMIC_RG_VS1_MODESET_SHIFT                        8
#define PMIC_RG_VS1_PFM_RIP_ADDR                         MT6355_VS1_ANA_CON3
#define PMIC_RG_VS1_PFM_RIP_MASK                         0x7
#define PMIC_RG_VS1_PFM_RIP_SHIFT                        9
#define PMIC_RG_VS1_TRAN_BST_ADDR                        MT6355_VS1_ANA_CON4
#define PMIC_RG_VS1_TRAN_BST_MASK                        0x3F
#define PMIC_RG_VS1_TRAN_BST_SHIFT                       0
#define PMIC_RG_VS1_DTS_ENB_ADDR                         MT6355_VS1_ANA_CON4
#define PMIC_RG_VS1_DTS_ENB_MASK                         0x1
#define PMIC_RG_VS1_DTS_ENB_SHIFT                        6
#define PMIC_RG_VS1_AUTO_MODE_ADDR                       MT6355_VS1_ANA_CON4
#define PMIC_RG_VS1_AUTO_MODE_MASK                       0x1
#define PMIC_RG_VS1_AUTO_MODE_SHIFT                      7
#define PMIC_RG_VS1_PWM_TRIG_ADDR                        MT6355_VS1_ANA_CON4
#define PMIC_RG_VS1_PWM_TRIG_MASK                        0x1
#define PMIC_RG_VS1_PWM_TRIG_SHIFT                       8
#define PMIC_RG_VS1_RSV_H_ADDR                           MT6355_VS1_ANA_CON4
#define PMIC_RG_VS1_RSV_H_MASK                           0xF
#define PMIC_RG_VS1_RSV_H_SHIFT                          9
#define PMIC_RG_VS1_RSV_L_ADDR                           MT6355_VS1_ANA_CON5
#define PMIC_RG_VS1_RSV_L_MASK                           0xF
#define PMIC_RG_VS1_RSV_L_SHIFT                          0
#define PMIC_RG_VS1_NONAUDIBLE_EN_ADDR                   MT6355_VS1_ANA_CON5
#define PMIC_RG_VS1_NONAUDIBLE_EN_MASK                   0x1
#define PMIC_RG_VS1_NONAUDIBLE_EN_SHIFT                  4
#define PMIC_RG_VS1_SR_P_ADDR                            MT6355_VS1_ANA_CON5
#define PMIC_RG_VS1_SR_P_MASK                            0x3
#define PMIC_RG_VS1_SR_P_SHIFT                           5
#define PMIC_RG_VS1_SR_N_ADDR                            MT6355_VS1_ANA_CON5
#define PMIC_RG_VS1_SR_N_MASK                            0x3
#define PMIC_RG_VS1_SR_N_SHIFT                           7
#define PMIC_RG_VS1_BURST_ADDR                           MT6355_VS1_ANA_CON5
#define PMIC_RG_VS1_BURST_MASK                           0x7
#define PMIC_RG_VS1_BURST_SHIFT                          9
#define PMIC_RGS_VS1_ENPWM_STATUS_ADDR                   MT6355_VS1_ANA_CON5
#define PMIC_RGS_VS1_ENPWM_STATUS_MASK                   0x1
#define PMIC_RGS_VS1_ENPWM_STATUS_SHIFT                  12
#define PMIC_RGS_VS1_OC_STATUS_ADDR                      MT6355_VS1_ANA_CON5
#define PMIC_RGS_VS1_OC_STATUS_MASK                      0x1
#define PMIC_RGS_VS1_OC_STATUS_SHIFT                     13
#define PMIC_RGS_VS1_DIG_MON_ADDR                        MT6355_VS1_ANA_CON6
#define PMIC_RGS_VS1_DIG_MON_MASK                        0xF
#define PMIC_RGS_VS1_DIG_MON_SHIFT                       0
#define PMIC_RG_VS2_MIN_OFF_ADDR                         MT6355_VS2_ANA_CON0
#define PMIC_RG_VS2_MIN_OFF_MASK                         0x3
#define PMIC_RG_VS2_MIN_OFF_SHIFT                        0
#define PMIC_RG_VS2_VRF18_SSTART_EN_ADDR                 MT6355_VS2_ANA_CON0
#define PMIC_RG_VS2_VRF18_SSTART_EN_MASK                 0x1
#define PMIC_RG_VS2_VRF18_SSTART_EN_SHIFT                2
#define PMIC_RG_VS2_1P35UP_SEL_EN_ADDR                   MT6355_VS2_ANA_CON0
#define PMIC_RG_VS2_1P35UP_SEL_EN_MASK                   0x1
#define PMIC_RG_VS2_1P35UP_SEL_EN_SHIFT                  3
#define PMIC_RG_VS2_RZSEL_ADDR                           MT6355_VS2_ANA_CON0
#define PMIC_RG_VS2_RZSEL_MASK                           0x7
#define PMIC_RG_VS2_RZSEL_SHIFT                          4
#define PMIC_RG_VS2_CSR_ADDR                             MT6355_VS2_ANA_CON0
#define PMIC_RG_VS2_CSR_MASK                             0x7
#define PMIC_RG_VS2_CSR_SHIFT                            7
#define PMIC_RG_VS2_CSL_ADDR                             MT6355_VS2_ANA_CON0
#define PMIC_RG_VS2_CSL_MASK                             0xF
#define PMIC_RG_VS2_CSL_SHIFT                            10
#define PMIC_RG_VS2_SLP_ADDR                             MT6355_VS2_ANA_CON1
#define PMIC_RG_VS2_SLP_MASK                             0x7
#define PMIC_RG_VS2_SLP_SHIFT                            0
#define PMIC_RG_VS2_ZX_OS_ADDR                           MT6355_VS2_ANA_CON1
#define PMIC_RG_VS2_ZX_OS_MASK                           0xF
#define PMIC_RG_VS2_ZX_OS_SHIFT                          3
#define PMIC_RG_VS2_NDIS_EN_ADDR                         MT6355_VS2_ANA_CON1
#define PMIC_RG_VS2_NDIS_EN_MASK                         0x1
#define PMIC_RG_VS2_NDIS_EN_SHIFT                        7
#define PMIC_RG_VS2_CSM_N_ADDR                           MT6355_VS2_ANA_CON1
#define PMIC_RG_VS2_CSM_N_MASK                           0x3F
#define PMIC_RG_VS2_CSM_N_SHIFT                          8
#define PMIC_RG_VS2_CSM_P_ADDR                           MT6355_VS2_ANA_CON2
#define PMIC_RG_VS2_CSM_P_MASK                           0x3F
#define PMIC_RG_VS2_CSM_P_SHIFT                          0
#define PMIC_RG_VS2_RSV_ADDR                             MT6355_VS2_ANA_CON2
#define PMIC_RG_VS2_RSV_MASK                             0xFF
#define PMIC_RG_VS2_RSV_SHIFT                            6
#define PMIC_RG_VS2_ZXOS_TRIM_ADDR                       MT6355_VS2_ANA_CON3
#define PMIC_RG_VS2_ZXOS_TRIM_MASK                       0xFF
#define PMIC_RG_VS2_ZXOS_TRIM_SHIFT                      0
#define PMIC_RG_VS2_MODESET_ADDR                         MT6355_VS2_ANA_CON3
#define PMIC_RG_VS2_MODESET_MASK                         0x1
#define PMIC_RG_VS2_MODESET_SHIFT                        8
#define PMIC_RG_VS2_PFM_RIP_ADDR                         MT6355_VS2_ANA_CON3
#define PMIC_RG_VS2_PFM_RIP_MASK                         0x7
#define PMIC_RG_VS2_PFM_RIP_SHIFT                        9
#define PMIC_RG_VS2_TRAN_BST_ADDR                        MT6355_VS2_ANA_CON4
#define PMIC_RG_VS2_TRAN_BST_MASK                        0x3F
#define PMIC_RG_VS2_TRAN_BST_SHIFT                       0
#define PMIC_RG_VS2_DTS_ENB_ADDR                         MT6355_VS2_ANA_CON4
#define PMIC_RG_VS2_DTS_ENB_MASK                         0x1
#define PMIC_RG_VS2_DTS_ENB_SHIFT                        6
#define PMIC_RG_VS2_AUTO_MODE_ADDR                       MT6355_VS2_ANA_CON4
#define PMIC_RG_VS2_AUTO_MODE_MASK                       0x1
#define PMIC_RG_VS2_AUTO_MODE_SHIFT                      7
#define PMIC_RG_VS2_PWM_TRIG_ADDR                        MT6355_VS2_ANA_CON4
#define PMIC_RG_VS2_PWM_TRIG_MASK                        0x1
#define PMIC_RG_VS2_PWM_TRIG_SHIFT                       8
#define PMIC_RG_VS2_RSV_H_ADDR                           MT6355_VS2_ANA_CON4
#define PMIC_RG_VS2_RSV_H_MASK                           0xF
#define PMIC_RG_VS2_RSV_H_SHIFT                          9
#define PMIC_RG_VS2_RSV_L_ADDR                           MT6355_VS2_ANA_CON5
#define PMIC_RG_VS2_RSV_L_MASK                           0xF
#define PMIC_RG_VS2_RSV_L_SHIFT                          0
#define PMIC_RG_VS2_NONAUDIBLE_EN_ADDR                   MT6355_VS2_ANA_CON5
#define PMIC_RG_VS2_NONAUDIBLE_EN_MASK                   0x1
#define PMIC_RG_VS2_NONAUDIBLE_EN_SHIFT                  4
#define PMIC_RG_VS2_SR_P_ADDR                            MT6355_VS2_ANA_CON5
#define PMIC_RG_VS2_SR_P_MASK                            0x3
#define PMIC_RG_VS2_SR_P_SHIFT                           5
#define PMIC_RG_VS2_SR_N_ADDR                            MT6355_VS2_ANA_CON5
#define PMIC_RG_VS2_SR_N_MASK                            0x3
#define PMIC_RG_VS2_SR_N_SHIFT                           7
#define PMIC_RG_VS2_BURST_ADDR                           MT6355_VS2_ANA_CON5
#define PMIC_RG_VS2_BURST_MASK                           0x7
#define PMIC_RG_VS2_BURST_SHIFT                          9
#define PMIC_RGS_VS2_ENPWM_STATUS_ADDR                   MT6355_VS2_ANA_CON5
#define PMIC_RGS_VS2_ENPWM_STATUS_MASK                   0x1
#define PMIC_RGS_VS2_ENPWM_STATUS_SHIFT                  12
#define PMIC_RGS_VS2_OC_STATUS_ADDR                      MT6355_VS2_ANA_CON5
#define PMIC_RGS_VS2_OC_STATUS_MASK                      0x1
#define PMIC_RGS_VS2_OC_STATUS_SHIFT                     13
#define PMIC_RGS_VS2_DIG_MON_ADDR                        MT6355_VS2_ANA_CON6
#define PMIC_RGS_VS2_DIG_MON_MASK                        0xF
#define PMIC_RGS_VS2_DIG_MON_SHIFT                       0
#define PMIC_RG_VPA_NDIS_EN_ADDR                         MT6355_VPA_ANA_CON0
#define PMIC_RG_VPA_NDIS_EN_MASK                         0x1
#define PMIC_RG_VPA_NDIS_EN_SHIFT                        1
#define PMIC_RG_VPA_MODESET_ADDR                         MT6355_VPA_ANA_CON0
#define PMIC_RG_VPA_MODESET_MASK                         0x1
#define PMIC_RG_VPA_MODESET_SHIFT                        3
#define PMIC_RG_VPA_CC_ADDR                              MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_CC_MASK                              0x3
#define PMIC_RG_VPA_CC_SHIFT                             0
#define PMIC_RG_VPA_CSR_ADDR                             MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_CSR_MASK                             0x3
#define PMIC_RG_VPA_CSR_SHIFT                            2
#define PMIC_RG_VPA_CSMIR_ADDR                           MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_CSMIR_MASK                           0x3
#define PMIC_RG_VPA_CSMIR_SHIFT                          4
#define PMIC_RG_VPA_CSL_ADDR                             MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_CSL_MASK                             0x3
#define PMIC_RG_VPA_CSL_SHIFT                            6
#define PMIC_RG_VPA_SLP_ADDR                             MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_SLP_MASK                             0x3
#define PMIC_RG_VPA_SLP_SHIFT                            8
#define PMIC_RG_VPA_AZC_EN_ADDR                          MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_AZC_EN_MASK                          0x1
#define PMIC_RG_VPA_AZC_EN_SHIFT                         10
#define PMIC_RG_VPA_CP_FWUPOFF_ADDR                      MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_CP_FWUPOFF_MASK                      0x1
#define PMIC_RG_VPA_CP_FWUPOFF_SHIFT                     11
#define PMIC_RG_VPA_AZC_DELAY_ADDR                       MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_AZC_DELAY_MASK                       0x3
#define PMIC_RG_VPA_AZC_DELAY_SHIFT                      12
#define PMIC_RG_VPA_RZSEL_ADDR                           MT6355_VPA_ANA_CON1
#define PMIC_RG_VPA_RZSEL_MASK                           0x3
#define PMIC_RG_VPA_RZSEL_SHIFT                          14
#define PMIC_RG_VPA_ZXREF_ADDR                           MT6355_VPA_ANA_CON2
#define PMIC_RG_VPA_ZXREF_MASK                           0xFF
#define PMIC_RG_VPA_ZXREF_SHIFT                          0
#define PMIC_RG_VPA_NLIM_SEL_ADDR                        MT6355_VPA_ANA_CON2
#define PMIC_RG_VPA_NLIM_SEL_MASK                        0xF
#define PMIC_RG_VPA_NLIM_SEL_SHIFT                       8
#define PMIC_RG_VPA_HZP_ADDR                             MT6355_VPA_ANA_CON2
#define PMIC_RG_VPA_HZP_MASK                             0x1
#define PMIC_RG_VPA_HZP_SHIFT                            12
#define PMIC_RG_VPA_BWEX_GAT_ADDR                        MT6355_VPA_ANA_CON2
#define PMIC_RG_VPA_BWEX_GAT_MASK                        0x1
#define PMIC_RG_VPA_BWEX_GAT_SHIFT                       13
#define PMIC_RG_VPA_SLEW_ADDR                            MT6355_VPA_ANA_CON2
#define PMIC_RG_VPA_SLEW_MASK                            0x3
#define PMIC_RG_VPA_SLEW_SHIFT                           14
#define PMIC_RG_VPA_SLEW_NMOS_ADDR                       MT6355_VPA_ANA_CON3
#define PMIC_RG_VPA_SLEW_NMOS_MASK                       0x3
#define PMIC_RG_VPA_SLEW_NMOS_SHIFT                      0
#define PMIC_RG_VPA_MIN_ON_ADDR                          MT6355_VPA_ANA_CON3
#define PMIC_RG_VPA_MIN_ON_MASK                          0x3
#define PMIC_RG_VPA_MIN_ON_SHIFT                         2
#define PMIC_RG_VPA_VBAT_DEL_ADDR                        MT6355_VPA_ANA_CON3
#define PMIC_RG_VPA_VBAT_DEL_MASK                        0x3
#define PMIC_RG_VPA_VBAT_DEL_SHIFT                       4
#define PMIC_RGS_VPA_AZC_VOS_SEL_ADDR                    MT6355_VPA_ANA_CON3
#define PMIC_RGS_VPA_AZC_VOS_SEL_MASK                    0xFF
#define PMIC_RGS_VPA_AZC_VOS_SEL_SHIFT                   6
#define PMIC_RG_VPA_MIN_PK_ADDR                          MT6355_VPA_ANA_CON3
#define PMIC_RG_VPA_MIN_PK_MASK                          0x3
#define PMIC_RG_VPA_MIN_PK_SHIFT                         14
#define PMIC_RG_VPA_RSV1_ADDR                            MT6355_VPA_ANA_CON4
#define PMIC_RG_VPA_RSV1_MASK                            0xFF
#define PMIC_RG_VPA_RSV1_SHIFT                           0
#define PMIC_RG_VPA_RSV2_ADDR                            MT6355_VPA_ANA_CON4
#define PMIC_RG_VPA_RSV2_MASK                            0xFF
#define PMIC_RG_VPA_RSV2_SHIFT                           8
#define PMIC_RGS_VPA_OC_STATUS_ADDR                      MT6355_VPA_ANA_CON5
#define PMIC_RGS_VPA_OC_STATUS_MASK                      0x1
#define PMIC_RGS_VPA_OC_STATUS_SHIFT                     0
#define PMIC_RGS_VPA_AZC_ZX_ADDR                         MT6355_VPA_ANA_CON5
#define PMIC_RGS_VPA_AZC_ZX_MASK                         0x1
#define PMIC_RGS_VPA_AZC_ZX_SHIFT                        1
#define PMIC_WDTDBG_CLR_ADDR                             MT6355_WDTDBG_CON0
#define PMIC_WDTDBG_CLR_MASK                             0x1
#define PMIC_WDTDBG_CLR_SHIFT                            0
#define PMIC_WDTDBG_CON0_RSV0_ADDR                       MT6355_WDTDBG_CON0
#define PMIC_WDTDBG_CON0_RSV0_MASK                       0x1
#define PMIC_WDTDBG_CON0_RSV0_SHIFT                      1
#define PMIC_VPROC11_VOSEL_WDTDBG_ADDR                   MT6355_WDTDBG_MON0
#define PMIC_VPROC11_VOSEL_WDTDBG_MASK                   0x7F
#define PMIC_VPROC11_VOSEL_WDTDBG_SHIFT                  0
#define PMIC_VPROC12_VOSEL_WDTDBG_ADDR                   MT6355_WDTDBG_MON0
#define PMIC_VPROC12_VOSEL_WDTDBG_MASK                   0x7F
#define PMIC_VPROC12_VOSEL_WDTDBG_SHIFT                  8
#define PMIC_VCORE_VOSEL_WDTDBG_ADDR                     MT6355_WDTDBG_MON1
#define PMIC_VCORE_VOSEL_WDTDBG_MASK                     0x7F
#define PMIC_VCORE_VOSEL_WDTDBG_SHIFT                    0
#define PMIC_VGPU_VOSEL_WDTDBG_ADDR                      MT6355_WDTDBG_MON1
#define PMIC_VGPU_VOSEL_WDTDBG_MASK                      0x7F
#define PMIC_VGPU_VOSEL_WDTDBG_SHIFT                     8
#define PMIC_VDRAM1_VOSEL_WDTDBG_ADDR                    MT6355_WDTDBG_MON2
#define PMIC_VDRAM1_VOSEL_WDTDBG_MASK                    0x7F
#define PMIC_VDRAM1_VOSEL_WDTDBG_SHIFT                   0
#define PMIC_VDRAM2_VOSEL_WDTDBG_ADDR                    MT6355_WDTDBG_MON2
#define PMIC_VDRAM2_VOSEL_WDTDBG_MASK                    0x7F
#define PMIC_VDRAM2_VOSEL_WDTDBG_SHIFT                   8
#define PMIC_VMODEM_VOSEL_WDTDBG_ADDR                    MT6355_WDTDBG_MON3
#define PMIC_VMODEM_VOSEL_WDTDBG_MASK                    0x7F
#define PMIC_VMODEM_VOSEL_WDTDBG_SHIFT                   0
#define PMIC_VS1_VOSEL_WDTDBG_ADDR                       MT6355_WDTDBG_MON3
#define PMIC_VS1_VOSEL_WDTDBG_MASK                       0x7F
#define PMIC_VS1_VOSEL_WDTDBG_SHIFT                      8
#define PMIC_VS2_VOSEL_WDTDBG_ADDR                       MT6355_WDTDBG_MON4
#define PMIC_VS2_VOSEL_WDTDBG_MASK                       0x7F
#define PMIC_VS2_VOSEL_WDTDBG_SHIFT                      0
#define PMIC_VPA_VOSEL_WDTDBG_ADDR                       MT6355_WDTDBG_MON4
#define PMIC_VPA_VOSEL_WDTDBG_MASK                       0x7F
#define PMIC_VPA_VOSEL_WDTDBG_SHIFT                      8
#define PMIC_VSRAM_PROC_VOSEL_WDTDBG_ADDR                MT6355_WDTDBG_MON5
#define PMIC_VSRAM_PROC_VOSEL_WDTDBG_MASK                0x7F
#define PMIC_VSRAM_PROC_VOSEL_WDTDBG_SHIFT               0
#define PMIC_VSRAM_CORE_VOSEL_WDTDBG_ADDR                MT6355_WDTDBG_MON5
#define PMIC_VSRAM_CORE_VOSEL_WDTDBG_MASK                0x7F
#define PMIC_VSRAM_CORE_VOSEL_WDTDBG_SHIFT               8
#define PMIC_VSRAM_GPU_VOSEL_WDTDBG_ADDR                 MT6355_WDTDBG_MON6
#define PMIC_VSRAM_GPU_VOSEL_WDTDBG_MASK                 0x7F
#define PMIC_VSRAM_GPU_VOSEL_WDTDBG_SHIFT                0
#define PMIC_VSRAM_MD_VOSEL_WDTDBG_ADDR                  MT6355_WDTDBG_MON6
#define PMIC_VSRAM_MD_VOSEL_WDTDBG_MASK                  0x7F
#define PMIC_VSRAM_MD_VOSEL_WDTDBG_SHIFT                 8
#define PMIC_RG_LDO_VIO28_EN_ADDR                        MT6355_LDO_VIO28_CON0
#define PMIC_RG_LDO_VIO28_EN_MASK                        0x1
#define PMIC_RG_LDO_VIO28_EN_SHIFT                       0
#define PMIC_RG_LDO_VIO28_LP_ADDR                        MT6355_LDO_VIO28_CON0
#define PMIC_RG_LDO_VIO28_LP_MASK                        0x1
#define PMIC_RG_LDO_VIO28_LP_SHIFT                       1
#define PMIC_RG_LDO_VIO28_SW_OP_EN_ADDR                  MT6355_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VIO28_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VIO28_HW0_OP_EN_ADDR                 MT6355_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VIO28_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VIO28_HW1_OP_EN_ADDR                 MT6355_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VIO28_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VIO28_HW2_OP_EN_ADDR                 MT6355_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VIO28_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VIO28_OP_EN_SET_ADDR                 MT6355_LDO_VIO28_OP_EN_SET
#define PMIC_RG_LDO_VIO28_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VIO28_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VIO28_OP_EN_CLR_ADDR                 MT6355_LDO_VIO28_OP_EN_CLR
#define PMIC_RG_LDO_VIO28_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VIO28_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VIO28_HW0_OP_CFG_ADDR                MT6355_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VIO28_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VIO28_HW1_OP_CFG_ADDR                MT6355_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VIO28_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VIO28_HW2_OP_CFG_ADDR                MT6355_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VIO28_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VIO28_ON_OP_ADDR                     MT6355_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VIO28_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VIO28_LP_OP_ADDR                     MT6355_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VIO28_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VIO28_OP_CFG_SET_ADDR                MT6355_LDO_VIO28_OP_CFG_SET
#define PMIC_RG_LDO_VIO28_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VIO28_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VIO28_OP_CFG_CLR_ADDR                MT6355_LDO_VIO28_OP_CFG_CLR
#define PMIC_RG_LDO_VIO28_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VIO28_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VIO28_MODE_ADDR                       MT6355_LDO_VIO28_CON1
#define PMIC_DA_QI_VIO28_MODE_MASK                       0x1
#define PMIC_DA_QI_VIO28_MODE_SHIFT                      8
#define PMIC_RG_LDO_VIO28_STBTD_ADDR                     MT6355_LDO_VIO28_CON1
#define PMIC_RG_LDO_VIO28_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VIO28_STBTD_SHIFT                    9
#define PMIC_DA_QI_VIO28_STB_ADDR                        MT6355_LDO_VIO28_CON1
#define PMIC_DA_QI_VIO28_STB_MASK                        0x1
#define PMIC_DA_QI_VIO28_STB_SHIFT                       14
#define PMIC_DA_QI_VIO28_EN_ADDR                         MT6355_LDO_VIO28_CON1
#define PMIC_DA_QI_VIO28_EN_MASK                         0x1
#define PMIC_DA_QI_VIO28_EN_SHIFT                        15
#define PMIC_RG_LDO_VIO28_OCFB_EN_ADDR                   MT6355_LDO_VIO28_CON2
#define PMIC_RG_LDO_VIO28_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VIO28_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VIO28_OCFB_EN_ADDR                    MT6355_LDO_VIO28_CON2
#define PMIC_DA_QI_VIO28_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VIO28_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VIO28_DUMMY_LOAD_ADDR                MT6355_LDO_VIO28_CON3
#define PMIC_RG_LDO_VIO28_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VIO28_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VIO28_DUMMY_LOAD_ADDR                 MT6355_LDO_VIO28_CON3
#define PMIC_DA_QI_VIO28_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VIO28_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VIO18_EN_ADDR                        MT6355_LDO_VIO18_CON0
#define PMIC_RG_LDO_VIO18_EN_MASK                        0x1
#define PMIC_RG_LDO_VIO18_EN_SHIFT                       0
#define PMIC_RG_LDO_VIO18_LP_ADDR                        MT6355_LDO_VIO18_CON0
#define PMIC_RG_LDO_VIO18_LP_MASK                        0x1
#define PMIC_RG_LDO_VIO18_LP_SHIFT                       1
#define PMIC_RG_LDO_VIO18_SW_OP_EN_ADDR                  MT6355_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VIO18_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VIO18_HW0_OP_EN_ADDR                 MT6355_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VIO18_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VIO18_HW1_OP_EN_ADDR                 MT6355_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VIO18_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VIO18_HW2_OP_EN_ADDR                 MT6355_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VIO18_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VIO18_OP_EN_SET_ADDR                 MT6355_LDO_VIO18_OP_EN_SET
#define PMIC_RG_LDO_VIO18_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VIO18_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VIO18_OP_EN_CLR_ADDR                 MT6355_LDO_VIO18_OP_EN_CLR
#define PMIC_RG_LDO_VIO18_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VIO18_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_ADDR                MT6355_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_ADDR                MT6355_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_ADDR                MT6355_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VIO18_ON_OP_ADDR                     MT6355_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VIO18_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VIO18_LP_OP_ADDR                     MT6355_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VIO18_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VIO18_OP_CFG_SET_ADDR                MT6355_LDO_VIO18_OP_CFG_SET
#define PMIC_RG_LDO_VIO18_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VIO18_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_ADDR                MT6355_LDO_VIO18_OP_CFG_CLR
#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VIO18_MODE_ADDR                       MT6355_LDO_VIO18_CON1
#define PMIC_DA_QI_VIO18_MODE_MASK                       0x1
#define PMIC_DA_QI_VIO18_MODE_SHIFT                      8
#define PMIC_RG_LDO_VIO18_STBTD_ADDR                     MT6355_LDO_VIO18_CON1
#define PMIC_RG_LDO_VIO18_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VIO18_STBTD_SHIFT                    9
#define PMIC_DA_QI_VIO18_STB_ADDR                        MT6355_LDO_VIO18_CON1
#define PMIC_DA_QI_VIO18_STB_MASK                        0x1
#define PMIC_DA_QI_VIO18_STB_SHIFT                       14
#define PMIC_DA_QI_VIO18_EN_ADDR                         MT6355_LDO_VIO18_CON1
#define PMIC_DA_QI_VIO18_EN_MASK                         0x1
#define PMIC_DA_QI_VIO18_EN_SHIFT                        15
#define PMIC_RG_LDO_VIO18_OCFB_EN_ADDR                   MT6355_LDO_VIO18_CON2
#define PMIC_RG_LDO_VIO18_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VIO18_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VIO18_OCFB_EN_ADDR                    MT6355_LDO_VIO18_CON2
#define PMIC_DA_QI_VIO18_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VIO18_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_ADDR                MT6355_LDO_VIO18_CON3
#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VIO18_DUMMY_LOAD_ADDR                 MT6355_LDO_VIO18_CON3
#define PMIC_DA_QI_VIO18_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VIO18_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VUFS18_EN_ADDR                       MT6355_LDO_VUFS18_CON0
#define PMIC_RG_LDO_VUFS18_EN_MASK                       0x1
#define PMIC_RG_LDO_VUFS18_EN_SHIFT                      0
#define PMIC_RG_LDO_VUFS18_LP_ADDR                       MT6355_LDO_VUFS18_CON0
#define PMIC_RG_LDO_VUFS18_LP_MASK                       0x1
#define PMIC_RG_LDO_VUFS18_LP_SHIFT                      1
#define PMIC_RG_LDO_VUFS18_SW_OP_EN_ADDR                 MT6355_LDO_VUFS18_OP_EN
#define PMIC_RG_LDO_VUFS18_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VUFS18_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VUFS18_HW0_OP_EN_ADDR                MT6355_LDO_VUFS18_OP_EN
#define PMIC_RG_LDO_VUFS18_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VUFS18_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VUFS18_HW1_OP_EN_ADDR                MT6355_LDO_VUFS18_OP_EN
#define PMIC_RG_LDO_VUFS18_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VUFS18_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VUFS18_HW2_OP_EN_ADDR                MT6355_LDO_VUFS18_OP_EN
#define PMIC_RG_LDO_VUFS18_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VUFS18_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VUFS18_OP_EN_SET_ADDR                MT6355_LDO_VUFS18_OP_EN_SET
#define PMIC_RG_LDO_VUFS18_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VUFS18_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VUFS18_OP_EN_CLR_ADDR                MT6355_LDO_VUFS18_OP_EN_CLR
#define PMIC_RG_LDO_VUFS18_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VUFS18_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VUFS18_HW0_OP_CFG_ADDR               MT6355_LDO_VUFS18_OP_CFG
#define PMIC_RG_LDO_VUFS18_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VUFS18_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VUFS18_HW1_OP_CFG_ADDR               MT6355_LDO_VUFS18_OP_CFG
#define PMIC_RG_LDO_VUFS18_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VUFS18_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VUFS18_HW2_OP_CFG_ADDR               MT6355_LDO_VUFS18_OP_CFG
#define PMIC_RG_LDO_VUFS18_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VUFS18_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VUFS18_ON_OP_ADDR                    MT6355_LDO_VUFS18_OP_CFG
#define PMIC_RG_LDO_VUFS18_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VUFS18_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VUFS18_LP_OP_ADDR                    MT6355_LDO_VUFS18_OP_CFG
#define PMIC_RG_LDO_VUFS18_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VUFS18_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VUFS18_OP_CFG_SET_ADDR               MT6355_LDO_VUFS18_OP_CFG_SET
#define PMIC_RG_LDO_VUFS18_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VUFS18_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VUFS18_OP_CFG_CLR_ADDR               MT6355_LDO_VUFS18_OP_CFG_CLR
#define PMIC_RG_LDO_VUFS18_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VUFS18_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VUFS18_MODE_ADDR                      MT6355_LDO_VUFS18_CON1
#define PMIC_DA_QI_VUFS18_MODE_MASK                      0x1
#define PMIC_DA_QI_VUFS18_MODE_SHIFT                     8
#define PMIC_RG_LDO_VUFS18_STBTD_ADDR                    MT6355_LDO_VUFS18_CON1
#define PMIC_RG_LDO_VUFS18_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VUFS18_STBTD_SHIFT                   9
#define PMIC_DA_QI_VUFS18_STB_ADDR                       MT6355_LDO_VUFS18_CON1
#define PMIC_DA_QI_VUFS18_STB_MASK                       0x1
#define PMIC_DA_QI_VUFS18_STB_SHIFT                      14
#define PMIC_DA_QI_VUFS18_EN_ADDR                        MT6355_LDO_VUFS18_CON1
#define PMIC_DA_QI_VUFS18_EN_MASK                        0x1
#define PMIC_DA_QI_VUFS18_EN_SHIFT                       15
#define PMIC_RG_LDO_VUFS18_OCFB_EN_ADDR                  MT6355_LDO_VUFS18_CON2
#define PMIC_RG_LDO_VUFS18_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VUFS18_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VUFS18_OCFB_EN_ADDR                   MT6355_LDO_VUFS18_CON2
#define PMIC_DA_QI_VUFS18_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VUFS18_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VUFS18_DUMMY_LOAD_ADDR               MT6355_LDO_VUFS18_CON3
#define PMIC_RG_LDO_VUFS18_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VUFS18_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VUFS18_DUMMY_LOAD_ADDR                MT6355_LDO_VUFS18_CON3
#define PMIC_DA_QI_VUFS18_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VUFS18_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VA10_EN_ADDR                         MT6355_LDO_VA10_CON0
#define PMIC_RG_LDO_VA10_EN_MASK                         0x1
#define PMIC_RG_LDO_VA10_EN_SHIFT                        0
#define PMIC_RG_LDO_VA10_LP_ADDR                         MT6355_LDO_VA10_CON0
#define PMIC_RG_LDO_VA10_LP_MASK                         0x1
#define PMIC_RG_LDO_VA10_LP_SHIFT                        1
#define PMIC_RG_VA10_VOCAL_ADDR                          MT6355_LDO_VA10_CON1
#define PMIC_RG_VA10_VOCAL_MASK                          0xF
#define PMIC_RG_VA10_VOCAL_SHIFT                         0
#define PMIC_RG_VA10_VOSEL_ADDR                          MT6355_LDO_VA10_CON1
#define PMIC_RG_VA10_VOSEL_MASK                          0xF
#define PMIC_RG_VA10_VOSEL_SHIFT                         8
#define PMIC_RG_LDO_VA10_SW_OP_EN_ADDR                   MT6355_LDO_VA10_OP_EN
#define PMIC_RG_LDO_VA10_SW_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VA10_SW_OP_EN_SHIFT                  0
#define PMIC_RG_LDO_VA10_HW0_OP_EN_ADDR                  MT6355_LDO_VA10_OP_EN
#define PMIC_RG_LDO_VA10_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA10_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_LDO_VA10_HW1_OP_EN_ADDR                  MT6355_LDO_VA10_OP_EN
#define PMIC_RG_LDO_VA10_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA10_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_LDO_VA10_HW2_OP_EN_ADDR                  MT6355_LDO_VA10_OP_EN
#define PMIC_RG_LDO_VA10_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA10_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_LDO_VA10_OP_EN_SET_ADDR                  MT6355_LDO_VA10_OP_EN_SET
#define PMIC_RG_LDO_VA10_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VA10_OP_EN_SET_SHIFT                 0
#define PMIC_RG_LDO_VA10_OP_EN_CLR_ADDR                  MT6355_LDO_VA10_OP_EN_CLR
#define PMIC_RG_LDO_VA10_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VA10_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_LDO_VA10_HW0_OP_CFG_ADDR                 MT6355_LDO_VA10_OP_CFG
#define PMIC_RG_LDO_VA10_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA10_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_LDO_VA10_HW1_OP_CFG_ADDR                 MT6355_LDO_VA10_OP_CFG
#define PMIC_RG_LDO_VA10_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA10_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_LDO_VA10_HW2_OP_CFG_ADDR                 MT6355_LDO_VA10_OP_CFG
#define PMIC_RG_LDO_VA10_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA10_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_LDO_VA10_ON_OP_ADDR                      MT6355_LDO_VA10_OP_CFG
#define PMIC_RG_LDO_VA10_ON_OP_MASK                      0x1
#define PMIC_RG_LDO_VA10_ON_OP_SHIFT                     8
#define PMIC_RG_LDO_VA10_LP_OP_ADDR                      MT6355_LDO_VA10_OP_CFG
#define PMIC_RG_LDO_VA10_LP_OP_MASK                      0x1
#define PMIC_RG_LDO_VA10_LP_OP_SHIFT                     9
#define PMIC_RG_LDO_VA10_OP_CFG_SET_ADDR                 MT6355_LDO_VA10_OP_CFG_SET
#define PMIC_RG_LDO_VA10_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VA10_OP_CFG_SET_SHIFT                0
#define PMIC_RG_LDO_VA10_OP_CFG_CLR_ADDR                 MT6355_LDO_VA10_OP_CFG_CLR
#define PMIC_RG_LDO_VA10_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VA10_OP_CFG_CLR_SHIFT                0
#define PMIC_DA_QI_VA10_MODE_ADDR                        MT6355_LDO_VA10_CON2
#define PMIC_DA_QI_VA10_MODE_MASK                        0x1
#define PMIC_DA_QI_VA10_MODE_SHIFT                       8
#define PMIC_RG_LDO_VA10_STBTD_ADDR                      MT6355_LDO_VA10_CON2
#define PMIC_RG_LDO_VA10_STBTD_MASK                      0x3
#define PMIC_RG_LDO_VA10_STBTD_SHIFT                     9
#define PMIC_DA_QI_VA10_STB_ADDR                         MT6355_LDO_VA10_CON2
#define PMIC_DA_QI_VA10_STB_MASK                         0x1
#define PMIC_DA_QI_VA10_STB_SHIFT                        14
#define PMIC_DA_QI_VA10_EN_ADDR                          MT6355_LDO_VA10_CON2
#define PMIC_DA_QI_VA10_EN_MASK                          0x1
#define PMIC_DA_QI_VA10_EN_SHIFT                         15
#define PMIC_RG_LDO_VA10_SLEEP_MODE_ADDR                 MT6355_LDO_VA10_CON3
#define PMIC_RG_LDO_VA10_SLEEP_MODE_MASK                 0x1
#define PMIC_RG_LDO_VA10_SLEEP_MODE_SHIFT                1
#define PMIC_RG_LDO_VA10_OCFB_EN_ADDR                    MT6355_LDO_VA10_CON3
#define PMIC_RG_LDO_VA10_OCFB_EN_MASK                    0x1
#define PMIC_RG_LDO_VA10_OCFB_EN_SHIFT                   9
#define PMIC_DA_QI_VA10_OCFB_EN_ADDR                     MT6355_LDO_VA10_CON3
#define PMIC_DA_QI_VA10_OCFB_EN_MASK                     0x1
#define PMIC_DA_QI_VA10_OCFB_EN_SHIFT                    10
#define PMIC_RG_LDO_VA10_DUMMY_LOAD_ADDR                 MT6355_LDO_VA10_CON4
#define PMIC_RG_LDO_VA10_DUMMY_LOAD_MASK                 0x3
#define PMIC_RG_LDO_VA10_DUMMY_LOAD_SHIFT                5
#define PMIC_DA_QI_VA10_DUMMY_LOAD_ADDR                  MT6355_LDO_VA10_CON4
#define PMIC_DA_QI_VA10_DUMMY_LOAD_MASK                  0x3
#define PMIC_DA_QI_VA10_DUMMY_LOAD_SHIFT                 14
#define PMIC_RG_LDO_VA12_EN_ADDR                         MT6355_LDO_VA12_CON0
#define PMIC_RG_LDO_VA12_EN_MASK                         0x1
#define PMIC_RG_LDO_VA12_EN_SHIFT                        0
#define PMIC_RG_LDO_VA12_LP_ADDR                         MT6355_LDO_VA12_CON0
#define PMIC_RG_LDO_VA12_LP_MASK                         0x1
#define PMIC_RG_LDO_VA12_LP_SHIFT                        1
#define PMIC_RG_LDO_VA12_SW_OP_EN_ADDR                   MT6355_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_SW_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VA12_SW_OP_EN_SHIFT                  0
#define PMIC_RG_LDO_VA12_HW0_OP_EN_ADDR                  MT6355_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA12_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_LDO_VA12_HW1_OP_EN_ADDR                  MT6355_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA12_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_LDO_VA12_HW2_OP_EN_ADDR                  MT6355_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA12_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_LDO_VA12_OP_EN_SET_ADDR                  MT6355_LDO_VA12_OP_EN_SET
#define PMIC_RG_LDO_VA12_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VA12_OP_EN_SET_SHIFT                 0
#define PMIC_RG_LDO_VA12_OP_EN_CLR_ADDR                  MT6355_LDO_VA12_OP_EN_CLR
#define PMIC_RG_LDO_VA12_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VA12_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_LDO_VA12_HW0_OP_CFG_ADDR                 MT6355_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA12_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_LDO_VA12_HW1_OP_CFG_ADDR                 MT6355_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA12_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_LDO_VA12_HW2_OP_CFG_ADDR                 MT6355_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA12_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_LDO_VA12_ON_OP_ADDR                      MT6355_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_ON_OP_MASK                      0x1
#define PMIC_RG_LDO_VA12_ON_OP_SHIFT                     8
#define PMIC_RG_LDO_VA12_LP_OP_ADDR                      MT6355_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_LP_OP_MASK                      0x1
#define PMIC_RG_LDO_VA12_LP_OP_SHIFT                     9
#define PMIC_RG_LDO_VA12_OP_CFG_SET_ADDR                 MT6355_LDO_VA12_OP_CFG_SET
#define PMIC_RG_LDO_VA12_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VA12_OP_CFG_SET_SHIFT                0
#define PMIC_RG_LDO_VA12_OP_CFG_CLR_ADDR                 MT6355_LDO_VA12_OP_CFG_CLR
#define PMIC_RG_LDO_VA12_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VA12_OP_CFG_CLR_SHIFT                0
#define PMIC_DA_QI_VA12_MODE_ADDR                        MT6355_LDO_VA12_CON1
#define PMIC_DA_QI_VA12_MODE_MASK                        0x1
#define PMIC_DA_QI_VA12_MODE_SHIFT                       8
#define PMIC_RG_LDO_VA12_STBTD_ADDR                      MT6355_LDO_VA12_CON1
#define PMIC_RG_LDO_VA12_STBTD_MASK                      0x3
#define PMIC_RG_LDO_VA12_STBTD_SHIFT                     9
#define PMIC_DA_QI_VA12_STB_ADDR                         MT6355_LDO_VA12_CON1
#define PMIC_DA_QI_VA12_STB_MASK                         0x1
#define PMIC_DA_QI_VA12_STB_SHIFT                        14
#define PMIC_DA_QI_VA12_EN_ADDR                          MT6355_LDO_VA12_CON1
#define PMIC_DA_QI_VA12_EN_MASK                          0x1
#define PMIC_DA_QI_VA12_EN_SHIFT                         15
#define PMIC_RG_LDO_VA12_OCFB_EN_ADDR                    MT6355_LDO_VA12_CON2
#define PMIC_RG_LDO_VA12_OCFB_EN_MASK                    0x1
#define PMIC_RG_LDO_VA12_OCFB_EN_SHIFT                   9
#define PMIC_DA_QI_VA12_OCFB_EN_ADDR                     MT6355_LDO_VA12_CON2
#define PMIC_DA_QI_VA12_OCFB_EN_MASK                     0x1
#define PMIC_DA_QI_VA12_OCFB_EN_SHIFT                    10
#define PMIC_RG_LDO_VA12_DUMMY_LOAD_ADDR                 MT6355_LDO_VA12_CON3
#define PMIC_RG_LDO_VA12_DUMMY_LOAD_MASK                 0x3
#define PMIC_RG_LDO_VA12_DUMMY_LOAD_SHIFT                5
#define PMIC_DA_QI_VA12_DUMMY_LOAD_ADDR                  MT6355_LDO_VA12_CON3
#define PMIC_DA_QI_VA12_DUMMY_LOAD_MASK                  0x3
#define PMIC_DA_QI_VA12_DUMMY_LOAD_SHIFT                 14
#define PMIC_RG_LDO_VA18_EN_ADDR                         MT6355_LDO_VA18_CON0
#define PMIC_RG_LDO_VA18_EN_MASK                         0x1
#define PMIC_RG_LDO_VA18_EN_SHIFT                        0
#define PMIC_RG_LDO_VA18_LP_ADDR                         MT6355_LDO_VA18_CON0
#define PMIC_RG_LDO_VA18_LP_MASK                         0x1
#define PMIC_RG_LDO_VA18_LP_SHIFT                        1
#define PMIC_RG_LDO_VA18_SW_OP_EN_ADDR                   MT6355_LDO_VA18_OP_EN
#define PMIC_RG_LDO_VA18_SW_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VA18_SW_OP_EN_SHIFT                  0
#define PMIC_RG_LDO_VA18_HW0_OP_EN_ADDR                  MT6355_LDO_VA18_OP_EN
#define PMIC_RG_LDO_VA18_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA18_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_LDO_VA18_HW1_OP_EN_ADDR                  MT6355_LDO_VA18_OP_EN
#define PMIC_RG_LDO_VA18_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA18_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_LDO_VA18_HW2_OP_EN_ADDR                  MT6355_LDO_VA18_OP_EN
#define PMIC_RG_LDO_VA18_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VA18_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_LDO_VA18_OP_EN_SET_ADDR                  MT6355_LDO_VA18_OP_EN_SET
#define PMIC_RG_LDO_VA18_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VA18_OP_EN_SET_SHIFT                 0
#define PMIC_RG_LDO_VA18_OP_EN_CLR_ADDR                  MT6355_LDO_VA18_OP_EN_CLR
#define PMIC_RG_LDO_VA18_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VA18_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_LDO_VA18_HW0_OP_CFG_ADDR                 MT6355_LDO_VA18_OP_CFG
#define PMIC_RG_LDO_VA18_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA18_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_LDO_VA18_HW1_OP_CFG_ADDR                 MT6355_LDO_VA18_OP_CFG
#define PMIC_RG_LDO_VA18_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA18_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_LDO_VA18_HW2_OP_CFG_ADDR                 MT6355_LDO_VA18_OP_CFG
#define PMIC_RG_LDO_VA18_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VA18_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_LDO_VA18_ON_OP_ADDR                      MT6355_LDO_VA18_OP_CFG
#define PMIC_RG_LDO_VA18_ON_OP_MASK                      0x1
#define PMIC_RG_LDO_VA18_ON_OP_SHIFT                     8
#define PMIC_RG_LDO_VA18_LP_OP_ADDR                      MT6355_LDO_VA18_OP_CFG
#define PMIC_RG_LDO_VA18_LP_OP_MASK                      0x1
#define PMIC_RG_LDO_VA18_LP_OP_SHIFT                     9
#define PMIC_RG_LDO_VA18_OP_CFG_SET_ADDR                 MT6355_LDO_VA18_OP_CFG_SET
#define PMIC_RG_LDO_VA18_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VA18_OP_CFG_SET_SHIFT                0
#define PMIC_RG_LDO_VA18_OP_CFG_CLR_ADDR                 MT6355_LDO_VA18_OP_CFG_CLR
#define PMIC_RG_LDO_VA18_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VA18_OP_CFG_CLR_SHIFT                0
#define PMIC_DA_QI_VA18_MODE_ADDR                        MT6355_LDO_VA18_CON1
#define PMIC_DA_QI_VA18_MODE_MASK                        0x1
#define PMIC_DA_QI_VA18_MODE_SHIFT                       8
#define PMIC_RG_LDO_VA18_STBTD_ADDR                      MT6355_LDO_VA18_CON1
#define PMIC_RG_LDO_VA18_STBTD_MASK                      0x3
#define PMIC_RG_LDO_VA18_STBTD_SHIFT                     9
#define PMIC_DA_QI_VA18_STB_ADDR                         MT6355_LDO_VA18_CON1
#define PMIC_DA_QI_VA18_STB_MASK                         0x1
#define PMIC_DA_QI_VA18_STB_SHIFT                        14
#define PMIC_DA_QI_VA18_EN_ADDR                          MT6355_LDO_VA18_CON1
#define PMIC_DA_QI_VA18_EN_MASK                          0x1
#define PMIC_DA_QI_VA18_EN_SHIFT                         15
#define PMIC_RG_LDO_VA18_AUXADC_PWDB_EN_ADDR             MT6355_LDO_VA18_CON2
#define PMIC_RG_LDO_VA18_AUXADC_PWDB_EN_MASK             0x1
#define PMIC_RG_LDO_VA18_AUXADC_PWDB_EN_SHIFT            2
#define PMIC_RG_LDO_VA18_OCFB_EN_ADDR                    MT6355_LDO_VA18_CON2
#define PMIC_RG_LDO_VA18_OCFB_EN_MASK                    0x1
#define PMIC_RG_LDO_VA18_OCFB_EN_SHIFT                   9
#define PMIC_DA_QI_VA18_OCFB_EN_ADDR                     MT6355_LDO_VA18_CON2
#define PMIC_DA_QI_VA18_OCFB_EN_MASK                     0x1
#define PMIC_DA_QI_VA18_OCFB_EN_SHIFT                    10
#define PMIC_RG_LDO_VA18_DUMMY_LOAD_ADDR                 MT6355_LDO_VA18_CON3
#define PMIC_RG_LDO_VA18_DUMMY_LOAD_MASK                 0x3
#define PMIC_RG_LDO_VA18_DUMMY_LOAD_SHIFT                5
#define PMIC_DA_QI_VA18_DUMMY_LOAD_ADDR                  MT6355_LDO_VA18_CON3
#define PMIC_DA_QI_VA18_DUMMY_LOAD_MASK                  0x3
#define PMIC_DA_QI_VA18_DUMMY_LOAD_SHIFT                 14
#define PMIC_RG_LDO_VUSB33_EN_0_ADDR                     MT6355_LDO_VUSB33_CON0_0
#define PMIC_RG_LDO_VUSB33_EN_0_MASK                     0x1
#define PMIC_RG_LDO_VUSB33_EN_0_SHIFT                    0
#define PMIC_RG_LDO_VUSB33_LP_ADDR                       MT6355_LDO_VUSB33_CON0_0
#define PMIC_RG_LDO_VUSB33_LP_MASK                       0x1
#define PMIC_RG_LDO_VUSB33_LP_SHIFT                      1
#define PMIC_RG_LDO_VUSB33_SW_OP_EN_ADDR                 MT6355_LDO_VUSB33_OP_EN
#define PMIC_RG_LDO_VUSB33_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VUSB33_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VUSB33_HW0_OP_EN_ADDR                MT6355_LDO_VUSB33_OP_EN
#define PMIC_RG_LDO_VUSB33_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VUSB33_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VUSB33_HW1_OP_EN_ADDR                MT6355_LDO_VUSB33_OP_EN
#define PMIC_RG_LDO_VUSB33_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VUSB33_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VUSB33_HW2_OP_EN_ADDR                MT6355_LDO_VUSB33_OP_EN
#define PMIC_RG_LDO_VUSB33_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VUSB33_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VUSB33_OP_EN_SET_ADDR                MT6355_LDO_VUSB33_OP_EN_SET
#define PMIC_RG_LDO_VUSB33_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VUSB33_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VUSB33_OP_EN_CLR_ADDR                MT6355_LDO_VUSB33_OP_EN_CLR
#define PMIC_RG_LDO_VUSB33_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VUSB33_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VUSB33_HW0_OP_CFG_ADDR               MT6355_LDO_VUSB33_OP_CFG
#define PMIC_RG_LDO_VUSB33_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VUSB33_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VUSB33_HW1_OP_CFG_ADDR               MT6355_LDO_VUSB33_OP_CFG
#define PMIC_RG_LDO_VUSB33_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VUSB33_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VUSB33_HW2_OP_CFG_ADDR               MT6355_LDO_VUSB33_OP_CFG
#define PMIC_RG_LDO_VUSB33_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VUSB33_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VUSB33_ON_OP_ADDR                    MT6355_LDO_VUSB33_OP_CFG
#define PMIC_RG_LDO_VUSB33_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VUSB33_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VUSB33_LP_OP_ADDR                    MT6355_LDO_VUSB33_OP_CFG
#define PMIC_RG_LDO_VUSB33_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VUSB33_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VUSB33_OP_CFG_SET_ADDR               MT6355_LDO_VUSB33_OP_CFG_SET
#define PMIC_RG_LDO_VUSB33_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VUSB33_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VUSB33_OP_CFG_CLR_ADDR               MT6355_LDO_VUSB33_OP_CFG_CLR
#define PMIC_RG_LDO_VUSB33_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VUSB33_OP_CFG_CLR_SHIFT              0
#define PMIC_RG_LDO_VUSB33_EN_1_ADDR                     MT6355_LDO_VUSB33_CON0_1
#define PMIC_RG_LDO_VUSB33_EN_1_MASK                     0x1
#define PMIC_RG_LDO_VUSB33_EN_1_SHIFT                    0
#define PMIC_DA_QI_VUSB33_MODE_ADDR                      MT6355_LDO_VUSB33_CON1
#define PMIC_DA_QI_VUSB33_MODE_MASK                      0x1
#define PMIC_DA_QI_VUSB33_MODE_SHIFT                     8
#define PMIC_RG_LDO_VUSB33_STBTD_ADDR                    MT6355_LDO_VUSB33_CON1
#define PMIC_RG_LDO_VUSB33_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VUSB33_STBTD_SHIFT                   9
#define PMIC_DA_QI_VUSB33_STB_ADDR                       MT6355_LDO_VUSB33_CON1
#define PMIC_DA_QI_VUSB33_STB_MASK                       0x1
#define PMIC_DA_QI_VUSB33_STB_SHIFT                      14
#define PMIC_DA_QI_VUSB33_EN_ADDR                        MT6355_LDO_VUSB33_CON1
#define PMIC_DA_QI_VUSB33_EN_MASK                        0x1
#define PMIC_DA_QI_VUSB33_EN_SHIFT                       15
#define PMIC_RG_LDO_VUSB33_OCFB_EN_ADDR                  MT6355_LDO_VUSB33_CON2
#define PMIC_RG_LDO_VUSB33_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VUSB33_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VUSB33_OCFB_EN_ADDR                   MT6355_LDO_VUSB33_CON2
#define PMIC_DA_QI_VUSB33_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VUSB33_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VUSB33_DUMMY_LOAD_ADDR               MT6355_LDO_VUSB33_CON3
#define PMIC_RG_LDO_VUSB33_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VUSB33_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VUSB33_DUMMY_LOAD_ADDR                MT6355_LDO_VUSB33_CON3
#define PMIC_DA_QI_VUSB33_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VUSB33_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VEMC_EN_ADDR                         MT6355_LDO_VEMC_CON0
#define PMIC_RG_LDO_VEMC_EN_MASK                         0x1
#define PMIC_RG_LDO_VEMC_EN_SHIFT                        0
#define PMIC_RG_LDO_VEMC_LP_ADDR                         MT6355_LDO_VEMC_CON0
#define PMIC_RG_LDO_VEMC_LP_MASK                         0x1
#define PMIC_RG_LDO_VEMC_LP_SHIFT                        1
#define PMIC_RG_LDO_VEMC_SW_OP_EN_ADDR                   MT6355_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_SW_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VEMC_SW_OP_EN_SHIFT                  0
#define PMIC_RG_LDO_VEMC_HW0_OP_EN_ADDR                  MT6355_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VEMC_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_LDO_VEMC_HW1_OP_EN_ADDR                  MT6355_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VEMC_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_LDO_VEMC_HW2_OP_EN_ADDR                  MT6355_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VEMC_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_LDO_VEMC_OP_EN_SET_ADDR                  MT6355_LDO_VEMC_OP_EN_SET
#define PMIC_RG_LDO_VEMC_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VEMC_OP_EN_SET_SHIFT                 0
#define PMIC_RG_LDO_VEMC_OP_EN_CLR_ADDR                  MT6355_LDO_VEMC_OP_EN_CLR
#define PMIC_RG_LDO_VEMC_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VEMC_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_ADDR                 MT6355_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_ADDR                 MT6355_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_ADDR                 MT6355_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_LDO_VEMC_ON_OP_ADDR                      MT6355_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_ON_OP_MASK                      0x1
#define PMIC_RG_LDO_VEMC_ON_OP_SHIFT                     8
#define PMIC_RG_LDO_VEMC_LP_OP_ADDR                      MT6355_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_LP_OP_MASK                      0x1
#define PMIC_RG_LDO_VEMC_LP_OP_SHIFT                     9
#define PMIC_RG_LDO_VEMC_OP_CFG_SET_ADDR                 MT6355_LDO_VEMC_OP_CFG_SET
#define PMIC_RG_LDO_VEMC_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VEMC_OP_CFG_SET_SHIFT                0
#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_ADDR                 MT6355_LDO_VEMC_OP_CFG_CLR
#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_SHIFT                0
#define PMIC_DA_QI_VEMC_MODE_ADDR                        MT6355_LDO_VEMC_CON1
#define PMIC_DA_QI_VEMC_MODE_MASK                        0x1
#define PMIC_DA_QI_VEMC_MODE_SHIFT                       8
#define PMIC_RG_LDO_VEMC_STBTD_ADDR                      MT6355_LDO_VEMC_CON1
#define PMIC_RG_LDO_VEMC_STBTD_MASK                      0x3
#define PMIC_RG_LDO_VEMC_STBTD_SHIFT                     9
#define PMIC_DA_QI_VEMC_STB_ADDR                         MT6355_LDO_VEMC_CON1
#define PMIC_DA_QI_VEMC_STB_MASK                         0x1
#define PMIC_DA_QI_VEMC_STB_SHIFT                        14
#define PMIC_DA_QI_VEMC_EN_ADDR                          MT6355_LDO_VEMC_CON1
#define PMIC_DA_QI_VEMC_EN_MASK                          0x1
#define PMIC_DA_QI_VEMC_EN_SHIFT                         15
#define PMIC_RG_LDO_VEMC_OCFB_EN_ADDR                    MT6355_LDO_VEMC_CON2
#define PMIC_RG_LDO_VEMC_OCFB_EN_MASK                    0x1
#define PMIC_RG_LDO_VEMC_OCFB_EN_SHIFT                   9
#define PMIC_DA_QI_VEMC_OCFB_EN_ADDR                     MT6355_LDO_VEMC_CON2
#define PMIC_DA_QI_VEMC_OCFB_EN_MASK                     0x1
#define PMIC_DA_QI_VEMC_OCFB_EN_SHIFT                    10
#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_ADDR                 MT6355_LDO_VEMC_CON3
#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_MASK                 0x3
#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_SHIFT                5
#define PMIC_DA_QI_VEMC_DUMMY_LOAD_ADDR                  MT6355_LDO_VEMC_CON3
#define PMIC_DA_QI_VEMC_DUMMY_LOAD_MASK                  0x3
#define PMIC_DA_QI_VEMC_DUMMY_LOAD_SHIFT                 14
#define PMIC_RG_LDO_VXO22_EN_ADDR                        MT6355_LDO_VXO22_CON0
#define PMIC_RG_LDO_VXO22_EN_MASK                        0x1
#define PMIC_RG_LDO_VXO22_EN_SHIFT                       0
#define PMIC_RG_LDO_VXO22_LP_ADDR                        MT6355_LDO_VXO22_CON0
#define PMIC_RG_LDO_VXO22_LP_MASK                        0x1
#define PMIC_RG_LDO_VXO22_LP_SHIFT                       1
#define PMIC_RG_LDO_VXO22_SW_OP_EN_ADDR                  MT6355_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VXO22_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VXO22_HW0_OP_EN_ADDR                 MT6355_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VXO22_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VXO22_HW1_OP_EN_ADDR                 MT6355_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VXO22_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VXO22_HW2_OP_EN_ADDR                 MT6355_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VXO22_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VXO22_OP_EN_SET_ADDR                 MT6355_LDO_VXO22_OP_EN_SET
#define PMIC_RG_LDO_VXO22_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VXO22_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VXO22_OP_EN_CLR_ADDR                 MT6355_LDO_VXO22_OP_EN_CLR
#define PMIC_RG_LDO_VXO22_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VXO22_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_ADDR                MT6355_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_ADDR                MT6355_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_ADDR                MT6355_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VXO22_ON_OP_ADDR                     MT6355_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VXO22_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VXO22_LP_OP_ADDR                     MT6355_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VXO22_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VXO22_OP_CFG_SET_ADDR                MT6355_LDO_VXO22_OP_CFG_SET
#define PMIC_RG_LDO_VXO22_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VXO22_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_ADDR                MT6355_LDO_VXO22_OP_CFG_CLR
#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VXO22_MODE_ADDR                       MT6355_LDO_VXO22_CON1
#define PMIC_DA_QI_VXO22_MODE_MASK                       0x1
#define PMIC_DA_QI_VXO22_MODE_SHIFT                      8
#define PMIC_RG_LDO_VXO22_STBTD_ADDR                     MT6355_LDO_VXO22_CON1
#define PMIC_RG_LDO_VXO22_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VXO22_STBTD_SHIFT                    9
#define PMIC_DA_QI_VXO22_STB_ADDR                        MT6355_LDO_VXO22_CON1
#define PMIC_DA_QI_VXO22_STB_MASK                        0x1
#define PMIC_DA_QI_VXO22_STB_SHIFT                       14
#define PMIC_DA_QI_VXO22_EN_ADDR                         MT6355_LDO_VXO22_CON1
#define PMIC_DA_QI_VXO22_EN_MASK                         0x1
#define PMIC_DA_QI_VXO22_EN_SHIFT                        15
#define PMIC_RG_LDO_VXO22_OCFB_EN_ADDR                   MT6355_LDO_VXO22_CON2
#define PMIC_RG_LDO_VXO22_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VXO22_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VXO22_OCFB_EN_ADDR                    MT6355_LDO_VXO22_CON2
#define PMIC_DA_QI_VXO22_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VXO22_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_ADDR                MT6355_LDO_VXO22_CON3
#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VXO22_DUMMY_LOAD_ADDR                 MT6355_LDO_VXO22_CON3
#define PMIC_DA_QI_VXO22_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VXO22_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VXO18_EN_ADDR                        MT6355_LDO_VXO18_CON0
#define PMIC_RG_LDO_VXO18_EN_MASK                        0x1
#define PMIC_RG_LDO_VXO18_EN_SHIFT                       0
#define PMIC_RG_LDO_VXO18_LP_ADDR                        MT6355_LDO_VXO18_CON0
#define PMIC_RG_LDO_VXO18_LP_MASK                        0x1
#define PMIC_RG_LDO_VXO18_LP_SHIFT                       1
#define PMIC_RG_LDO_VXO18_SW_OP_EN_ADDR                  MT6355_LDO_VXO18_OP_EN
#define PMIC_RG_LDO_VXO18_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VXO18_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VXO18_HW0_OP_EN_ADDR                 MT6355_LDO_VXO18_OP_EN
#define PMIC_RG_LDO_VXO18_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VXO18_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VXO18_HW1_OP_EN_ADDR                 MT6355_LDO_VXO18_OP_EN
#define PMIC_RG_LDO_VXO18_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VXO18_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VXO18_HW2_OP_EN_ADDR                 MT6355_LDO_VXO18_OP_EN
#define PMIC_RG_LDO_VXO18_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VXO18_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VXO18_OP_EN_SET_ADDR                 MT6355_LDO_VXO18_OP_EN_SET
#define PMIC_RG_LDO_VXO18_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VXO18_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VXO18_OP_EN_CLR_ADDR                 MT6355_LDO_VXO18_OP_EN_CLR
#define PMIC_RG_LDO_VXO18_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VXO18_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VXO18_HW0_OP_CFG_ADDR                MT6355_LDO_VXO18_OP_CFG
#define PMIC_RG_LDO_VXO18_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VXO18_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VXO18_HW1_OP_CFG_ADDR                MT6355_LDO_VXO18_OP_CFG
#define PMIC_RG_LDO_VXO18_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VXO18_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VXO18_HW2_OP_CFG_ADDR                MT6355_LDO_VXO18_OP_CFG
#define PMIC_RG_LDO_VXO18_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VXO18_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VXO18_ON_OP_ADDR                     MT6355_LDO_VXO18_OP_CFG
#define PMIC_RG_LDO_VXO18_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VXO18_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VXO18_LP_OP_ADDR                     MT6355_LDO_VXO18_OP_CFG
#define PMIC_RG_LDO_VXO18_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VXO18_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VXO18_OP_CFG_SET_ADDR                MT6355_LDO_VXO18_OP_CFG_SET
#define PMIC_RG_LDO_VXO18_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VXO18_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VXO18_OP_CFG_CLR_ADDR                MT6355_LDO_VXO18_OP_CFG_CLR
#define PMIC_RG_LDO_VXO18_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VXO18_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VXO18_MODE_ADDR                       MT6355_LDO_VXO18_CON1
#define PMIC_DA_QI_VXO18_MODE_MASK                       0x1
#define PMIC_DA_QI_VXO18_MODE_SHIFT                      8
#define PMIC_RG_LDO_VXO18_STBTD_ADDR                     MT6355_LDO_VXO18_CON1
#define PMIC_RG_LDO_VXO18_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VXO18_STBTD_SHIFT                    9
#define PMIC_DA_QI_VXO18_STB_ADDR                        MT6355_LDO_VXO18_CON1
#define PMIC_DA_QI_VXO18_STB_MASK                        0x1
#define PMIC_DA_QI_VXO18_STB_SHIFT                       14
#define PMIC_DA_QI_VXO18_EN_ADDR                         MT6355_LDO_VXO18_CON1
#define PMIC_DA_QI_VXO18_EN_MASK                         0x1
#define PMIC_DA_QI_VXO18_EN_SHIFT                        15
#define PMIC_RG_LDO_VXO18_OCFB_EN_ADDR                   MT6355_LDO_VXO18_CON2
#define PMIC_RG_LDO_VXO18_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VXO18_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VXO18_OCFB_EN_ADDR                    MT6355_LDO_VXO18_CON2
#define PMIC_DA_QI_VXO18_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VXO18_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VXO18_DUMMY_LOAD_ADDR                MT6355_LDO_VXO18_CON3
#define PMIC_RG_LDO_VXO18_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VXO18_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VXO18_DUMMY_LOAD_ADDR                 MT6355_LDO_VXO18_CON3
#define PMIC_DA_QI_VXO18_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VXO18_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VSIM1_EN_ADDR                        MT6355_LDO_VSIM1_CON0
#define PMIC_RG_LDO_VSIM1_EN_MASK                        0x1
#define PMIC_RG_LDO_VSIM1_EN_SHIFT                       0
#define PMIC_RG_LDO_VSIM1_LP_ADDR                        MT6355_LDO_VSIM1_CON0
#define PMIC_RG_LDO_VSIM1_LP_MASK                        0x1
#define PMIC_RG_LDO_VSIM1_LP_SHIFT                       1
#define PMIC_RG_LDO_VSIM1_SW_OP_EN_ADDR                  MT6355_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_ADDR                 MT6355_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_ADDR                 MT6355_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_ADDR                 MT6355_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR                 MT6355_LDO_VSIM1_OP_EN_SET
#define PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR                 MT6355_LDO_VSIM1_OP_EN_CLR
#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_ADDR                MT6355_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_ADDR                MT6355_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_ADDR                MT6355_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VSIM1_ON_OP_ADDR                     MT6355_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VSIM1_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VSIM1_LP_OP_ADDR                     MT6355_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VSIM1_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR                MT6355_LDO_VSIM1_OP_CFG_SET
#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR                MT6355_LDO_VSIM1_OP_CFG_CLR
#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VSIM1_MODE_ADDR                       MT6355_LDO_VSIM1_CON1
#define PMIC_DA_QI_VSIM1_MODE_MASK                       0x1
#define PMIC_DA_QI_VSIM1_MODE_SHIFT                      8
#define PMIC_RG_LDO_VSIM1_STBTD_ADDR                     MT6355_LDO_VSIM1_CON1
#define PMIC_RG_LDO_VSIM1_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VSIM1_STBTD_SHIFT                    9
#define PMIC_DA_QI_VSIM1_STB_ADDR                        MT6355_LDO_VSIM1_CON1
#define PMIC_DA_QI_VSIM1_STB_MASK                        0x1
#define PMIC_DA_QI_VSIM1_STB_SHIFT                       14
#define PMIC_DA_QI_VSIM1_EN_ADDR                         MT6355_LDO_VSIM1_CON1
#define PMIC_DA_QI_VSIM1_EN_MASK                         0x1
#define PMIC_DA_QI_VSIM1_EN_SHIFT                        15
#define PMIC_RG_LDO_VSIM1_OCFB_EN_ADDR                   MT6355_LDO_VSIM1_CON2
#define PMIC_RG_LDO_VSIM1_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VSIM1_OCFB_EN_ADDR                    MT6355_LDO_VSIM1_CON2
#define PMIC_DA_QI_VSIM1_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VSIM1_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_ADDR                MT6355_LDO_VSIM1_CON3
#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VSIM1_DUMMY_LOAD_ADDR                 MT6355_LDO_VSIM1_CON3
#define PMIC_DA_QI_VSIM1_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VSIM1_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VSIM2_EN_ADDR                        MT6355_LDO_VSIM2_CON0
#define PMIC_RG_LDO_VSIM2_EN_MASK                        0x1
#define PMIC_RG_LDO_VSIM2_EN_SHIFT                       0
#define PMIC_RG_LDO_VSIM2_LP_ADDR                        MT6355_LDO_VSIM2_CON0
#define PMIC_RG_LDO_VSIM2_LP_MASK                        0x1
#define PMIC_RG_LDO_VSIM2_LP_SHIFT                       1
#define PMIC_RG_LDO_VSIM2_SW_OP_EN_ADDR                  MT6355_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_ADDR                 MT6355_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_ADDR                 MT6355_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_ADDR                 MT6355_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR                 MT6355_LDO_VSIM2_OP_EN_SET
#define PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR                 MT6355_LDO_VSIM2_OP_EN_CLR
#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_ADDR                MT6355_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_ADDR                MT6355_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_ADDR                MT6355_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VSIM2_ON_OP_ADDR                     MT6355_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VSIM2_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VSIM2_LP_OP_ADDR                     MT6355_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VSIM2_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR                MT6355_LDO_VSIM2_OP_CFG_SET
#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR                MT6355_LDO_VSIM2_OP_CFG_CLR
#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VSIM2_MODE_ADDR                       MT6355_LDO_VSIM2_CON1
#define PMIC_DA_QI_VSIM2_MODE_MASK                       0x1
#define PMIC_DA_QI_VSIM2_MODE_SHIFT                      8
#define PMIC_RG_LDO_VSIM2_STBTD_ADDR                     MT6355_LDO_VSIM2_CON1
#define PMIC_RG_LDO_VSIM2_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VSIM2_STBTD_SHIFT                    9
#define PMIC_DA_QI_VSIM2_STB_ADDR                        MT6355_LDO_VSIM2_CON1
#define PMIC_DA_QI_VSIM2_STB_MASK                        0x1
#define PMIC_DA_QI_VSIM2_STB_SHIFT                       14
#define PMIC_DA_QI_VSIM2_EN_ADDR                         MT6355_LDO_VSIM2_CON1
#define PMIC_DA_QI_VSIM2_EN_MASK                         0x1
#define PMIC_DA_QI_VSIM2_EN_SHIFT                        15
#define PMIC_RG_LDO_VSIM2_OCFB_EN_ADDR                   MT6355_LDO_VSIM2_CON2
#define PMIC_RG_LDO_VSIM2_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VSIM2_OCFB_EN_ADDR                    MT6355_LDO_VSIM2_CON2
#define PMIC_DA_QI_VSIM2_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VSIM2_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_ADDR                MT6355_LDO_VSIM2_CON3
#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VSIM2_DUMMY_LOAD_ADDR                 MT6355_LDO_VSIM2_CON3
#define PMIC_DA_QI_VSIM2_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VSIM2_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VCAMD1_EN_ADDR                       MT6355_LDO_VCAMD1_CON0
#define PMIC_RG_LDO_VCAMD1_EN_MASK                       0x1
#define PMIC_RG_LDO_VCAMD1_EN_SHIFT                      0
#define PMIC_RG_LDO_VCAMD1_LP_ADDR                       MT6355_LDO_VCAMD1_CON0
#define PMIC_RG_LDO_VCAMD1_LP_MASK                       0x1
#define PMIC_RG_LDO_VCAMD1_LP_SHIFT                      1
#define PMIC_RG_LDO_VCAMD1_SW_OP_EN_ADDR                 MT6355_LDO_VCAMD1_OP_EN
#define PMIC_RG_LDO_VCAMD1_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMD1_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VCAMD1_HW0_OP_EN_ADDR                MT6355_LDO_VCAMD1_OP_EN
#define PMIC_RG_LDO_VCAMD1_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMD1_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VCAMD1_HW1_OP_EN_ADDR                MT6355_LDO_VCAMD1_OP_EN
#define PMIC_RG_LDO_VCAMD1_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMD1_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VCAMD1_HW2_OP_EN_ADDR                MT6355_LDO_VCAMD1_OP_EN
#define PMIC_RG_LDO_VCAMD1_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMD1_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VCAMD1_OP_EN_SET_ADDR                MT6355_LDO_VCAMD1_OP_EN_SET
#define PMIC_RG_LDO_VCAMD1_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMD1_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VCAMD1_OP_EN_CLR_ADDR                MT6355_LDO_VCAMD1_OP_EN_CLR
#define PMIC_RG_LDO_VCAMD1_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMD1_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VCAMD1_HW0_OP_CFG_ADDR               MT6355_LDO_VCAMD1_OP_CFG
#define PMIC_RG_LDO_VCAMD1_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMD1_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VCAMD1_HW1_OP_CFG_ADDR               MT6355_LDO_VCAMD1_OP_CFG
#define PMIC_RG_LDO_VCAMD1_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMD1_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VCAMD1_HW2_OP_CFG_ADDR               MT6355_LDO_VCAMD1_OP_CFG
#define PMIC_RG_LDO_VCAMD1_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMD1_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VCAMD1_ON_OP_ADDR                    MT6355_LDO_VCAMD1_OP_CFG
#define PMIC_RG_LDO_VCAMD1_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMD1_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VCAMD1_LP_OP_ADDR                    MT6355_LDO_VCAMD1_OP_CFG
#define PMIC_RG_LDO_VCAMD1_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMD1_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VCAMD1_OP_CFG_SET_ADDR               MT6355_LDO_VCAMD1_OP_CFG_SET
#define PMIC_RG_LDO_VCAMD1_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMD1_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VCAMD1_OP_CFG_CLR_ADDR               MT6355_LDO_VCAMD1_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMD1_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMD1_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VCAMD1_MODE_ADDR                      MT6355_LDO_VCAMD1_CON1
#define PMIC_DA_QI_VCAMD1_MODE_MASK                      0x1
#define PMIC_DA_QI_VCAMD1_MODE_SHIFT                     8
#define PMIC_RG_LDO_VCAMD1_STBTD_ADDR                    MT6355_LDO_VCAMD1_CON1
#define PMIC_RG_LDO_VCAMD1_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VCAMD1_STBTD_SHIFT                   9
#define PMIC_DA_QI_VCAMD1_STB_ADDR                       MT6355_LDO_VCAMD1_CON1
#define PMIC_DA_QI_VCAMD1_STB_MASK                       0x1
#define PMIC_DA_QI_VCAMD1_STB_SHIFT                      14
#define PMIC_DA_QI_VCAMD1_EN_ADDR                        MT6355_LDO_VCAMD1_CON1
#define PMIC_DA_QI_VCAMD1_EN_MASK                        0x1
#define PMIC_DA_QI_VCAMD1_EN_SHIFT                       15
#define PMIC_RG_LDO_VCAMD1_OCFB_EN_ADDR                  MT6355_LDO_VCAMD1_CON2
#define PMIC_RG_LDO_VCAMD1_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VCAMD1_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VCAMD1_OCFB_EN_ADDR                   MT6355_LDO_VCAMD1_CON2
#define PMIC_DA_QI_VCAMD1_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VCAMD1_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VCAMD1_DUMMY_LOAD_ADDR               MT6355_LDO_VCAMD1_CON3
#define PMIC_RG_LDO_VCAMD1_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VCAMD1_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VCAMD1_DUMMY_LOAD_ADDR                MT6355_LDO_VCAMD1_CON3
#define PMIC_DA_QI_VCAMD1_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VCAMD1_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VCAMD2_EN_ADDR                       MT6355_LDO_VCAMD2_CON0
#define PMIC_RG_LDO_VCAMD2_EN_MASK                       0x1
#define PMIC_RG_LDO_VCAMD2_EN_SHIFT                      0
#define PMIC_RG_LDO_VCAMD2_LP_ADDR                       MT6355_LDO_VCAMD2_CON0
#define PMIC_RG_LDO_VCAMD2_LP_MASK                       0x1
#define PMIC_RG_LDO_VCAMD2_LP_SHIFT                      1
#define PMIC_RG_LDO_VCAMD2_SW_OP_EN_ADDR                 MT6355_LDO_VCAMD2_OP_EN
#define PMIC_RG_LDO_VCAMD2_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMD2_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VCAMD2_HW0_OP_EN_ADDR                MT6355_LDO_VCAMD2_OP_EN
#define PMIC_RG_LDO_VCAMD2_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMD2_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VCAMD2_HW1_OP_EN_ADDR                MT6355_LDO_VCAMD2_OP_EN
#define PMIC_RG_LDO_VCAMD2_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMD2_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VCAMD2_HW2_OP_EN_ADDR                MT6355_LDO_VCAMD2_OP_EN
#define PMIC_RG_LDO_VCAMD2_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMD2_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VCAMD2_OP_EN_SET_ADDR                MT6355_LDO_VCAMD2_OP_EN_SET
#define PMIC_RG_LDO_VCAMD2_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMD2_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VCAMD2_OP_EN_CLR_ADDR                MT6355_LDO_VCAMD2_OP_EN_CLR
#define PMIC_RG_LDO_VCAMD2_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMD2_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VCAMD2_HW0_OP_CFG_ADDR               MT6355_LDO_VCAMD2_OP_CFG
#define PMIC_RG_LDO_VCAMD2_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMD2_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VCAMD2_HW1_OP_CFG_ADDR               MT6355_LDO_VCAMD2_OP_CFG
#define PMIC_RG_LDO_VCAMD2_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMD2_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VCAMD2_HW2_OP_CFG_ADDR               MT6355_LDO_VCAMD2_OP_CFG
#define PMIC_RG_LDO_VCAMD2_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMD2_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VCAMD2_ON_OP_ADDR                    MT6355_LDO_VCAMD2_OP_CFG
#define PMIC_RG_LDO_VCAMD2_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMD2_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VCAMD2_LP_OP_ADDR                    MT6355_LDO_VCAMD2_OP_CFG
#define PMIC_RG_LDO_VCAMD2_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMD2_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VCAMD2_OP_CFG_SET_ADDR               MT6355_LDO_VCAMD2_OP_CFG_SET
#define PMIC_RG_LDO_VCAMD2_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMD2_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VCAMD2_OP_CFG_CLR_ADDR               MT6355_LDO_VCAMD2_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMD2_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMD2_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VCAMD2_MODE_ADDR                      MT6355_LDO_VCAMD2_CON1
#define PMIC_DA_QI_VCAMD2_MODE_MASK                      0x1
#define PMIC_DA_QI_VCAMD2_MODE_SHIFT                     8
#define PMIC_RG_LDO_VCAMD2_STBTD_ADDR                    MT6355_LDO_VCAMD2_CON1
#define PMIC_RG_LDO_VCAMD2_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VCAMD2_STBTD_SHIFT                   9
#define PMIC_DA_QI_VCAMD2_STB_ADDR                       MT6355_LDO_VCAMD2_CON1
#define PMIC_DA_QI_VCAMD2_STB_MASK                       0x1
#define PMIC_DA_QI_VCAMD2_STB_SHIFT                      14
#define PMIC_DA_QI_VCAMD2_EN_ADDR                        MT6355_LDO_VCAMD2_CON1
#define PMIC_DA_QI_VCAMD2_EN_MASK                        0x1
#define PMIC_DA_QI_VCAMD2_EN_SHIFT                       15
#define PMIC_RG_LDO_VCAMD2_OCFB_EN_ADDR                  MT6355_LDO_VCAMD2_CON2
#define PMIC_RG_LDO_VCAMD2_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VCAMD2_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VCAMD2_OCFB_EN_ADDR                   MT6355_LDO_VCAMD2_CON2
#define PMIC_DA_QI_VCAMD2_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VCAMD2_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VCAMD2_DUMMY_LOAD_ADDR               MT6355_LDO_VCAMD2_CON3
#define PMIC_RG_LDO_VCAMD2_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VCAMD2_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VCAMD2_DUMMY_LOAD_ADDR                MT6355_LDO_VCAMD2_CON3
#define PMIC_DA_QI_VCAMD2_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VCAMD2_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VCAMIO_EN_ADDR                       MT6355_LDO_VCAMIO_CON0
#define PMIC_RG_LDO_VCAMIO_EN_MASK                       0x1
#define PMIC_RG_LDO_VCAMIO_EN_SHIFT                      0
#define PMIC_RG_LDO_VCAMIO_LP_ADDR                       MT6355_LDO_VCAMIO_CON0
#define PMIC_RG_LDO_VCAMIO_LP_MASK                       0x1
#define PMIC_RG_LDO_VCAMIO_LP_SHIFT                      1
#define PMIC_RG_LDO_VCAMIO_SW_OP_EN_ADDR                 MT6355_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMIO_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VCAMIO_HW0_OP_EN_ADDR                MT6355_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMIO_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_EN_ADDR                MT6355_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VCAMIO_HW2_OP_EN_ADDR                MT6355_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMIO_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VCAMIO_OP_EN_SET_ADDR                MT6355_LDO_VCAMIO_OP_EN_SET
#define PMIC_RG_LDO_VCAMIO_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VCAMIO_OP_EN_CLR_ADDR                MT6355_LDO_VCAMIO_OP_EN_CLR
#define PMIC_RG_LDO_VCAMIO_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR               MT6355_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMIO_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR               MT6355_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR               MT6355_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMIO_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VCAMIO_ON_OP_ADDR                    MT6355_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMIO_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VCAMIO_LP_OP_ADDR                    MT6355_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMIO_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VCAMIO_OP_CFG_SET_ADDR               MT6355_LDO_VCAMIO_OP_CFG_SET
#define PMIC_RG_LDO_VCAMIO_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VCAMIO_OP_CFG_CLR_ADDR               MT6355_LDO_VCAMIO_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMIO_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VCAMIO_MODE_ADDR                      MT6355_LDO_VCAMIO_CON1
#define PMIC_DA_QI_VCAMIO_MODE_MASK                      0x1
#define PMIC_DA_QI_VCAMIO_MODE_SHIFT                     8
#define PMIC_RG_LDO_VCAMIO_STBTD_ADDR                    MT6355_LDO_VCAMIO_CON1
#define PMIC_RG_LDO_VCAMIO_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VCAMIO_STBTD_SHIFT                   9
#define PMIC_DA_QI_VCAMIO_STB_ADDR                       MT6355_LDO_VCAMIO_CON1
#define PMIC_DA_QI_VCAMIO_STB_MASK                       0x1
#define PMIC_DA_QI_VCAMIO_STB_SHIFT                      14
#define PMIC_DA_QI_VCAMIO_EN_ADDR                        MT6355_LDO_VCAMIO_CON1
#define PMIC_DA_QI_VCAMIO_EN_MASK                        0x1
#define PMIC_DA_QI_VCAMIO_EN_SHIFT                       15
#define PMIC_RG_LDO_VCAMIO_OCFB_EN_ADDR                  MT6355_LDO_VCAMIO_CON2
#define PMIC_RG_LDO_VCAMIO_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VCAMIO_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VCAMIO_OCFB_EN_ADDR                   MT6355_LDO_VCAMIO_CON2
#define PMIC_DA_QI_VCAMIO_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VCAMIO_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VCAMIO_DUMMY_LOAD_ADDR               MT6355_LDO_VCAMIO_CON3
#define PMIC_RG_LDO_VCAMIO_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VCAMIO_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VCAMIO_DUMMY_LOAD_ADDR                MT6355_LDO_VCAMIO_CON3
#define PMIC_DA_QI_VCAMIO_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VCAMIO_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VMIPI_EN_ADDR                        MT6355_LDO_VMIPI_CON0
#define PMIC_RG_LDO_VMIPI_EN_MASK                        0x1
#define PMIC_RG_LDO_VMIPI_EN_SHIFT                       0
#define PMIC_RG_LDO_VMIPI_LP_ADDR                        MT6355_LDO_VMIPI_CON0
#define PMIC_RG_LDO_VMIPI_LP_MASK                        0x1
#define PMIC_RG_LDO_VMIPI_LP_SHIFT                       1
#define PMIC_RG_LDO_VMIPI_SW_OP_EN_ADDR                  MT6355_LDO_VMIPI_OP_EN
#define PMIC_RG_LDO_VMIPI_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VMIPI_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VMIPI_HW0_OP_EN_ADDR                 MT6355_LDO_VMIPI_OP_EN
#define PMIC_RG_LDO_VMIPI_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VMIPI_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VMIPI_HW1_OP_EN_ADDR                 MT6355_LDO_VMIPI_OP_EN
#define PMIC_RG_LDO_VMIPI_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VMIPI_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VMIPI_HW2_OP_EN_ADDR                 MT6355_LDO_VMIPI_OP_EN
#define PMIC_RG_LDO_VMIPI_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VMIPI_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VMIPI_OP_EN_SET_ADDR                 MT6355_LDO_VMIPI_OP_EN_SET
#define PMIC_RG_LDO_VMIPI_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VMIPI_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VMIPI_OP_EN_CLR_ADDR                 MT6355_LDO_VMIPI_OP_EN_CLR
#define PMIC_RG_LDO_VMIPI_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VMIPI_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VMIPI_HW0_OP_CFG_ADDR                MT6355_LDO_VMIPI_OP_CFG
#define PMIC_RG_LDO_VMIPI_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VMIPI_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VMIPI_HW1_OP_CFG_ADDR                MT6355_LDO_VMIPI_OP_CFG
#define PMIC_RG_LDO_VMIPI_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VMIPI_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VMIPI_HW2_OP_CFG_ADDR                MT6355_LDO_VMIPI_OP_CFG
#define PMIC_RG_LDO_VMIPI_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VMIPI_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VMIPI_ON_OP_ADDR                     MT6355_LDO_VMIPI_OP_CFG
#define PMIC_RG_LDO_VMIPI_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VMIPI_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VMIPI_LP_OP_ADDR                     MT6355_LDO_VMIPI_OP_CFG
#define PMIC_RG_LDO_VMIPI_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VMIPI_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VMIPI_OP_CFG_SET_ADDR                MT6355_LDO_VMIPI_OP_CFG_SET
#define PMIC_RG_LDO_VMIPI_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VMIPI_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VMIPI_OP_CFG_CLR_ADDR                MT6355_LDO_VMIPI_OP_CFG_CLR
#define PMIC_RG_LDO_VMIPI_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VMIPI_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VMIPI_MODE_ADDR                       MT6355_LDO_VMIPI_CON1
#define PMIC_DA_QI_VMIPI_MODE_MASK                       0x1
#define PMIC_DA_QI_VMIPI_MODE_SHIFT                      8
#define PMIC_RG_LDO_VMIPI_STBTD_ADDR                     MT6355_LDO_VMIPI_CON1
#define PMIC_RG_LDO_VMIPI_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VMIPI_STBTD_SHIFT                    9
#define PMIC_DA_QI_VMIPI_STB_ADDR                        MT6355_LDO_VMIPI_CON1
#define PMIC_DA_QI_VMIPI_STB_MASK                        0x1
#define PMIC_DA_QI_VMIPI_STB_SHIFT                       14
#define PMIC_DA_QI_VMIPI_EN_ADDR                         MT6355_LDO_VMIPI_CON1
#define PMIC_DA_QI_VMIPI_EN_MASK                         0x1
#define PMIC_DA_QI_VMIPI_EN_SHIFT                        15
#define PMIC_RG_LDO_VMIPI_OCFB_EN_ADDR                   MT6355_LDO_VMIPI_CON2
#define PMIC_RG_LDO_VMIPI_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VMIPI_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VMIPI_OCFB_EN_ADDR                    MT6355_LDO_VMIPI_CON2
#define PMIC_DA_QI_VMIPI_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VMIPI_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VMIPI_DUMMY_LOAD_ADDR                MT6355_LDO_VMIPI_CON3
#define PMIC_RG_LDO_VMIPI_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VMIPI_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VMIPI_DUMMY_LOAD_ADDR                 MT6355_LDO_VMIPI_CON3
#define PMIC_DA_QI_VMIPI_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VMIPI_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VGP_EN_ADDR                          MT6355_LDO_VGP_CON0
#define PMIC_RG_LDO_VGP_EN_MASK                          0x1
#define PMIC_RG_LDO_VGP_EN_SHIFT                         0
#define PMIC_RG_LDO_VGP_LP_ADDR                          MT6355_LDO_VGP_CON0
#define PMIC_RG_LDO_VGP_LP_MASK                          0x1
#define PMIC_RG_LDO_VGP_LP_SHIFT                         1
#define PMIC_RG_LDO_VGP_SW_OP_EN_ADDR                    MT6355_LDO_VGP_OP_EN
#define PMIC_RG_LDO_VGP_SW_OP_EN_MASK                    0x1
#define PMIC_RG_LDO_VGP_SW_OP_EN_SHIFT                   0
#define PMIC_RG_LDO_VGP_HW0_OP_EN_ADDR                   MT6355_LDO_VGP_OP_EN
#define PMIC_RG_LDO_VGP_HW0_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VGP_HW0_OP_EN_SHIFT                  1
#define PMIC_RG_LDO_VGP_HW1_OP_EN_ADDR                   MT6355_LDO_VGP_OP_EN
#define PMIC_RG_LDO_VGP_HW1_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VGP_HW1_OP_EN_SHIFT                  2
#define PMIC_RG_LDO_VGP_HW2_OP_EN_ADDR                   MT6355_LDO_VGP_OP_EN
#define PMIC_RG_LDO_VGP_HW2_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VGP_HW2_OP_EN_SHIFT                  3
#define PMIC_RG_LDO_VGP_OP_EN_SET_ADDR                   MT6355_LDO_VGP_OP_EN_SET
#define PMIC_RG_LDO_VGP_OP_EN_SET_MASK                   0xFFFF
#define PMIC_RG_LDO_VGP_OP_EN_SET_SHIFT                  0
#define PMIC_RG_LDO_VGP_OP_EN_CLR_ADDR                   MT6355_LDO_VGP_OP_EN_CLR
#define PMIC_RG_LDO_VGP_OP_EN_CLR_MASK                   0xFFFF
#define PMIC_RG_LDO_VGP_OP_EN_CLR_SHIFT                  0
#define PMIC_RG_LDO_VGP_HW0_OP_CFG_ADDR                  MT6355_LDO_VGP_OP_CFG
#define PMIC_RG_LDO_VGP_HW0_OP_CFG_MASK                  0x1
#define PMIC_RG_LDO_VGP_HW0_OP_CFG_SHIFT                 1
#define PMIC_RG_LDO_VGP_HW1_OP_CFG_ADDR                  MT6355_LDO_VGP_OP_CFG
#define PMIC_RG_LDO_VGP_HW1_OP_CFG_MASK                  0x1
#define PMIC_RG_LDO_VGP_HW1_OP_CFG_SHIFT                 2
#define PMIC_RG_LDO_VGP_HW2_OP_CFG_ADDR                  MT6355_LDO_VGP_OP_CFG
#define PMIC_RG_LDO_VGP_HW2_OP_CFG_MASK                  0x1
#define PMIC_RG_LDO_VGP_HW2_OP_CFG_SHIFT                 3
#define PMIC_RG_LDO_VGP_ON_OP_ADDR                       MT6355_LDO_VGP_OP_CFG
#define PMIC_RG_LDO_VGP_ON_OP_MASK                       0x1
#define PMIC_RG_LDO_VGP_ON_OP_SHIFT                      8
#define PMIC_RG_LDO_VGP_LP_OP_ADDR                       MT6355_LDO_VGP_OP_CFG
#define PMIC_RG_LDO_VGP_LP_OP_MASK                       0x1
#define PMIC_RG_LDO_VGP_LP_OP_SHIFT                      9
#define PMIC_RG_LDO_VGP_OP_CFG_SET_ADDR                  MT6355_LDO_VGP_OP_CFG_SET
#define PMIC_RG_LDO_VGP_OP_CFG_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VGP_OP_CFG_SET_SHIFT                 0
#define PMIC_RG_LDO_VGP_OP_CFG_CLR_ADDR                  MT6355_LDO_VGP_OP_CFG_CLR
#define PMIC_RG_LDO_VGP_OP_CFG_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VGP_OP_CFG_CLR_SHIFT                 0
#define PMIC_DA_QI_VGP_MODE_ADDR                         MT6355_LDO_VGP_CON1
#define PMIC_DA_QI_VGP_MODE_MASK                         0x1
#define PMIC_DA_QI_VGP_MODE_SHIFT                        8
#define PMIC_RG_LDO_VGP_STBTD_ADDR                       MT6355_LDO_VGP_CON1
#define PMIC_RG_LDO_VGP_STBTD_MASK                       0x3
#define PMIC_RG_LDO_VGP_STBTD_SHIFT                      9
#define PMIC_DA_QI_VGP_STB_ADDR                          MT6355_LDO_VGP_CON1
#define PMIC_DA_QI_VGP_STB_MASK                          0x1
#define PMIC_DA_QI_VGP_STB_SHIFT                         14
#define PMIC_DA_QI_VGP_EN_ADDR                           MT6355_LDO_VGP_CON1
#define PMIC_DA_QI_VGP_EN_MASK                           0x1
#define PMIC_DA_QI_VGP_EN_SHIFT                          15
#define PMIC_RG_LDO_VGP_OCFB_EN_ADDR                     MT6355_LDO_VGP_CON2
#define PMIC_RG_LDO_VGP_OCFB_EN_MASK                     0x1
#define PMIC_RG_LDO_VGP_OCFB_EN_SHIFT                    9
#define PMIC_DA_QI_VGP_OCFB_EN_ADDR                      MT6355_LDO_VGP_CON2
#define PMIC_DA_QI_VGP_OCFB_EN_MASK                      0x1
#define PMIC_DA_QI_VGP_OCFB_EN_SHIFT                     10
#define PMIC_RG_LDO_VGP_DUMMY_LOAD_ADDR                  MT6355_LDO_VGP_CON3
#define PMIC_RG_LDO_VGP_DUMMY_LOAD_MASK                  0x3
#define PMIC_RG_LDO_VGP_DUMMY_LOAD_SHIFT                 5
#define PMIC_DA_QI_VGP_DUMMY_LOAD_ADDR                   MT6355_LDO_VGP_CON3
#define PMIC_DA_QI_VGP_DUMMY_LOAD_MASK                   0x3
#define PMIC_DA_QI_VGP_DUMMY_LOAD_SHIFT                  14
#define PMIC_RG_LDO_VCN33_EN_BT_ADDR                     MT6355_LDO_VCN33_CON0_BT
#define PMIC_RG_LDO_VCN33_EN_BT_MASK                     0x1
#define PMIC_RG_LDO_VCN33_EN_BT_SHIFT                    0
#define PMIC_RG_LDO_VCN33_LP_ADDR                        MT6355_LDO_VCN33_CON0_BT
#define PMIC_RG_LDO_VCN33_LP_MASK                        0x1
#define PMIC_RG_LDO_VCN33_LP_SHIFT                       1
#define PMIC_RG_LDO_VCN33_SW_OP_EN_ADDR                  MT6355_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VCN33_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VCN33_HW0_OP_EN_ADDR                 MT6355_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN33_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VCN33_HW1_OP_EN_ADDR                 MT6355_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN33_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VCN33_HW2_OP_EN_ADDR                 MT6355_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN33_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VCN33_OP_EN_SET_ADDR                 MT6355_LDO_VCN33_OP_EN_SET
#define PMIC_RG_LDO_VCN33_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VCN33_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VCN33_OP_EN_CLR_ADDR                 MT6355_LDO_VCN33_OP_EN_CLR
#define PMIC_RG_LDO_VCN33_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VCN33_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_ADDR                MT6355_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_ADDR                MT6355_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_ADDR                MT6355_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VCN33_ON_OP_ADDR                     MT6355_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VCN33_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VCN33_LP_OP_ADDR                     MT6355_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VCN33_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VCN33_OP_CFG_SET_ADDR                MT6355_LDO_VCN33_OP_CFG_SET
#define PMIC_RG_LDO_VCN33_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCN33_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_ADDR                MT6355_LDO_VCN33_OP_CFG_CLR
#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_SHIFT               0
#define PMIC_RG_LDO_VCN33_EN_WIFI_ADDR                   MT6355_LDO_VCN33_CON0_WIFI
#define PMIC_RG_LDO_VCN33_EN_WIFI_MASK                   0x1
#define PMIC_RG_LDO_VCN33_EN_WIFI_SHIFT                  0
#define PMIC_DA_QI_VCN33_MODE_ADDR                       MT6355_LDO_VCN33_CON1
#define PMIC_DA_QI_VCN33_MODE_MASK                       0x1
#define PMIC_DA_QI_VCN33_MODE_SHIFT                      8
#define PMIC_RG_LDO_VCN33_STBTD_ADDR                     MT6355_LDO_VCN33_CON1
#define PMIC_RG_LDO_VCN33_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VCN33_STBTD_SHIFT                    9
#define PMIC_DA_QI_VCN33_STB_ADDR                        MT6355_LDO_VCN33_CON1
#define PMIC_DA_QI_VCN33_STB_MASK                        0x1
#define PMIC_DA_QI_VCN33_STB_SHIFT                       14
#define PMIC_DA_QI_VCN33_EN_ADDR                         MT6355_LDO_VCN33_CON1
#define PMIC_DA_QI_VCN33_EN_MASK                         0x1
#define PMIC_DA_QI_VCN33_EN_SHIFT                        15
#define PMIC_RG_LDO_VCN33_OCFB_EN_ADDR                   MT6355_LDO_VCN33_CON2
#define PMIC_RG_LDO_VCN33_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VCN33_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VCN33_OCFB_EN_ADDR                    MT6355_LDO_VCN33_CON2
#define PMIC_DA_QI_VCN33_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VCN33_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_ADDR                MT6355_LDO_VCN33_CON3
#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VCN33_DUMMY_LOAD_ADDR                 MT6355_LDO_VCN33_CON3
#define PMIC_DA_QI_VCN33_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VCN33_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VCN18_EN_ADDR                        MT6355_LDO_VCN18_CON0
#define PMIC_RG_LDO_VCN18_EN_MASK                        0x1
#define PMIC_RG_LDO_VCN18_EN_SHIFT                       0
#define PMIC_RG_LDO_VCN18_LP_ADDR                        MT6355_LDO_VCN18_CON0
#define PMIC_RG_LDO_VCN18_LP_MASK                        0x1
#define PMIC_RG_LDO_VCN18_LP_SHIFT                       1
#define PMIC_RG_LDO_VCN18_SW_OP_EN_ADDR                  MT6355_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VCN18_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VCN18_HW0_OP_EN_ADDR                 MT6355_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN18_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VCN18_HW1_OP_EN_ADDR                 MT6355_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN18_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VCN18_HW2_OP_EN_ADDR                 MT6355_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN18_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VCN18_OP_EN_SET_ADDR                 MT6355_LDO_VCN18_OP_EN_SET
#define PMIC_RG_LDO_VCN18_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VCN18_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VCN18_OP_EN_CLR_ADDR                 MT6355_LDO_VCN18_OP_EN_CLR
#define PMIC_RG_LDO_VCN18_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VCN18_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_ADDR                MT6355_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_ADDR                MT6355_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_ADDR                MT6355_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VCN18_ON_OP_ADDR                     MT6355_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VCN18_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VCN18_LP_OP_ADDR                     MT6355_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VCN18_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VCN18_OP_CFG_SET_ADDR                MT6355_LDO_VCN18_OP_CFG_SET
#define PMIC_RG_LDO_VCN18_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCN18_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_ADDR                MT6355_LDO_VCN18_OP_CFG_CLR
#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VCN18_MODE_ADDR                       MT6355_LDO_VCN18_CON1
#define PMIC_DA_QI_VCN18_MODE_MASK                       0x1
#define PMIC_DA_QI_VCN18_MODE_SHIFT                      8
#define PMIC_RG_LDO_VCN18_STBTD_ADDR                     MT6355_LDO_VCN18_CON1
#define PMIC_RG_LDO_VCN18_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VCN18_STBTD_SHIFT                    9
#define PMIC_DA_QI_VCN18_STB_ADDR                        MT6355_LDO_VCN18_CON1
#define PMIC_DA_QI_VCN18_STB_MASK                        0x1
#define PMIC_DA_QI_VCN18_STB_SHIFT                       14
#define PMIC_DA_QI_VCN18_EN_ADDR                         MT6355_LDO_VCN18_CON1
#define PMIC_DA_QI_VCN18_EN_MASK                         0x1
#define PMIC_DA_QI_VCN18_EN_SHIFT                        15
#define PMIC_RG_LDO_VCN18_OCFB_EN_ADDR                   MT6355_LDO_VCN18_CON2
#define PMIC_RG_LDO_VCN18_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VCN18_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VCN18_OCFB_EN_ADDR                    MT6355_LDO_VCN18_CON2
#define PMIC_DA_QI_VCN18_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VCN18_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_ADDR                MT6355_LDO_VCN18_CON3
#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VCN18_DUMMY_LOAD_ADDR                 MT6355_LDO_VCN18_CON3
#define PMIC_DA_QI_VCN18_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VCN18_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VCN28_EN_ADDR                        MT6355_LDO_VCN28_CON0
#define PMIC_RG_LDO_VCN28_EN_MASK                        0x1
#define PMIC_RG_LDO_VCN28_EN_SHIFT                       0
#define PMIC_RG_LDO_VCN28_LP_ADDR                        MT6355_LDO_VCN28_CON0
#define PMIC_RG_LDO_VCN28_LP_MASK                        0x1
#define PMIC_RG_LDO_VCN28_LP_SHIFT                       1
#define PMIC_RG_LDO_VCN28_SW_OP_EN_ADDR                  MT6355_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VCN28_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VCN28_HW0_OP_EN_ADDR                 MT6355_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN28_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VCN28_HW1_OP_EN_ADDR                 MT6355_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN28_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VCN28_HW2_OP_EN_ADDR                 MT6355_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN28_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VCN28_HW3_OP_EN_ADDR                 MT6355_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW3_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCN28_HW3_OP_EN_SHIFT                4
#define PMIC_RG_LDO_VCN28_OP_EN_SET_ADDR                 MT6355_LDO_VCN28_OP_EN_SET
#define PMIC_RG_LDO_VCN28_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VCN28_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VCN28_OP_EN_CLR_ADDR                 MT6355_LDO_VCN28_OP_EN_CLR
#define PMIC_RG_LDO_VCN28_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VCN28_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VCN28_HW0_OP_CFG_ADDR                MT6355_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN28_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VCN28_HW1_OP_CFG_ADDR                MT6355_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN28_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VCN28_HW2_OP_CFG_ADDR                MT6355_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN28_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VCN28_HW3_OP_CFG_ADDR                MT6355_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW3_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VCN28_HW3_OP_CFG_SHIFT               4
#define PMIC_RG_LDO_VCN28_ON_OP_ADDR                     MT6355_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VCN28_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VCN28_LP_OP_ADDR                     MT6355_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VCN28_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VCN28_OP_CFG_SET_ADDR                MT6355_LDO_VCN28_OP_CFG_SET
#define PMIC_RG_LDO_VCN28_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCN28_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VCN28_OP_CFG_CLR_ADDR                MT6355_LDO_VCN28_OP_CFG_CLR
#define PMIC_RG_LDO_VCN28_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCN28_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VCN28_MODE_ADDR                       MT6355_LDO_VCN28_CON1
#define PMIC_DA_QI_VCN28_MODE_MASK                       0x1
#define PMIC_DA_QI_VCN28_MODE_SHIFT                      8
#define PMIC_RG_LDO_VCN28_STBTD_ADDR                     MT6355_LDO_VCN28_CON1
#define PMIC_RG_LDO_VCN28_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VCN28_STBTD_SHIFT                    9
#define PMIC_DA_QI_VCN28_STB_ADDR                        MT6355_LDO_VCN28_CON1
#define PMIC_DA_QI_VCN28_STB_MASK                        0x1
#define PMIC_DA_QI_VCN28_STB_SHIFT                       14
#define PMIC_DA_QI_VCN28_EN_ADDR                         MT6355_LDO_VCN28_CON1
#define PMIC_DA_QI_VCN28_EN_MASK                         0x1
#define PMIC_DA_QI_VCN28_EN_SHIFT                        15
#define PMIC_RG_LDO_VCN28_OCFB_EN_ADDR                   MT6355_LDO_VCN28_CON2
#define PMIC_RG_LDO_VCN28_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VCN28_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VCN28_OCFB_EN_ADDR                    MT6355_LDO_VCN28_CON2
#define PMIC_DA_QI_VCN28_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VCN28_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VCN28_DUMMY_LOAD_ADDR                MT6355_LDO_VCN28_CON3
#define PMIC_RG_LDO_VCN28_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VCN28_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VCN28_DUMMY_LOAD_ADDR                 MT6355_LDO_VCN28_CON3
#define PMIC_DA_QI_VCN28_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VCN28_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VBIF28_EN_ADDR                       MT6355_LDO_VBIF28_CON0
#define PMIC_RG_LDO_VBIF28_EN_MASK                       0x1
#define PMIC_RG_LDO_VBIF28_EN_SHIFT                      0
#define PMIC_RG_LDO_VBIF28_LP_ADDR                       MT6355_LDO_VBIF28_CON0
#define PMIC_RG_LDO_VBIF28_LP_MASK                       0x1
#define PMIC_RG_LDO_VBIF28_LP_SHIFT                      1
#define PMIC_RG_LDO_VBIF28_SW_OP_EN_ADDR                 MT6355_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VBIF28_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VBIF28_HW0_OP_EN_ADDR                MT6355_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VBIF28_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VBIF28_HW1_OP_EN_ADDR                MT6355_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VBIF28_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VBIF28_HW2_OP_EN_ADDR                MT6355_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VBIF28_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VBIF28_OP_EN_SET_ADDR                MT6355_LDO_VBIF28_OP_EN_SET
#define PMIC_RG_LDO_VBIF28_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VBIF28_OP_EN_CLR_ADDR                MT6355_LDO_VBIF28_OP_EN_CLR
#define PMIC_RG_LDO_VBIF28_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VBIF28_HW0_OP_CFG_ADDR               MT6355_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VBIF28_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VBIF28_HW1_OP_CFG_ADDR               MT6355_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VBIF28_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VBIF28_HW2_OP_CFG_ADDR               MT6355_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VBIF28_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VBIF28_ON_OP_ADDR                    MT6355_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VBIF28_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VBIF28_LP_OP_ADDR                    MT6355_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VBIF28_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VBIF28_OP_CFG_SET_ADDR               MT6355_LDO_VBIF28_OP_CFG_SET
#define PMIC_RG_LDO_VBIF28_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VBIF28_OP_CFG_CLR_ADDR               MT6355_LDO_VBIF28_OP_CFG_CLR
#define PMIC_RG_LDO_VBIF28_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VBIF28_MODE_ADDR                      MT6355_LDO_VBIF28_CON1
#define PMIC_DA_QI_VBIF28_MODE_MASK                      0x1
#define PMIC_DA_QI_VBIF28_MODE_SHIFT                     8
#define PMIC_RG_LDO_VBIF28_STBTD_ADDR                    MT6355_LDO_VBIF28_CON1
#define PMIC_RG_LDO_VBIF28_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VBIF28_STBTD_SHIFT                   9
#define PMIC_DA_QI_VBIF28_STB_ADDR                       MT6355_LDO_VBIF28_CON1
#define PMIC_DA_QI_VBIF28_STB_MASK                       0x1
#define PMIC_DA_QI_VBIF28_STB_SHIFT                      14
#define PMIC_DA_QI_VBIF28_EN_ADDR                        MT6355_LDO_VBIF28_CON1
#define PMIC_DA_QI_VBIF28_EN_MASK                        0x1
#define PMIC_DA_QI_VBIF28_EN_SHIFT                       15
#define PMIC_RG_LDO_VBIF28_OCFB_EN_ADDR                  MT6355_LDO_VBIF28_CON2
#define PMIC_RG_LDO_VBIF28_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VBIF28_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VBIF28_OCFB_EN_ADDR                   MT6355_LDO_VBIF28_CON2
#define PMIC_DA_QI_VBIF28_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VBIF28_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VBIF28_DUMMY_LOAD_ADDR               MT6355_LDO_VBIF28_CON3
#define PMIC_RG_LDO_VBIF28_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VBIF28_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VBIF28_DUMMY_LOAD_ADDR                MT6355_LDO_VBIF28_CON3
#define PMIC_DA_QI_VBIF28_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VBIF28_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VTCXO24_EN_ADDR                      MT6355_LDO_VTCXO24_CON0
#define PMIC_RG_LDO_VTCXO24_EN_MASK                      0x1
#define PMIC_RG_LDO_VTCXO24_EN_SHIFT                     0
#define PMIC_RG_LDO_VTCXO24_LP_ADDR                      MT6355_LDO_VTCXO24_CON0
#define PMIC_RG_LDO_VTCXO24_LP_MASK                      0x1
#define PMIC_RG_LDO_VTCXO24_LP_SHIFT                     1
#define PMIC_RG_LDO_VTCXO24_SW_OP_EN_ADDR                MT6355_LDO_VTCXO24_OP_EN
#define PMIC_RG_LDO_VTCXO24_SW_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VTCXO24_SW_OP_EN_SHIFT               0
#define PMIC_RG_LDO_VTCXO24_HW0_OP_EN_ADDR               MT6355_LDO_VTCXO24_OP_EN
#define PMIC_RG_LDO_VTCXO24_HW0_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VTCXO24_HW0_OP_EN_SHIFT              1
#define PMIC_RG_LDO_VTCXO24_HW1_OP_EN_ADDR               MT6355_LDO_VTCXO24_OP_EN
#define PMIC_RG_LDO_VTCXO24_HW1_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VTCXO24_HW1_OP_EN_SHIFT              2
#define PMIC_RG_LDO_VTCXO24_HW2_OP_EN_ADDR               MT6355_LDO_VTCXO24_OP_EN
#define PMIC_RG_LDO_VTCXO24_HW2_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VTCXO24_HW2_OP_EN_SHIFT              3
#define PMIC_RG_LDO_VTCXO24_OP_EN_SET_ADDR               MT6355_LDO_VTCXO24_OP_EN_SET
#define PMIC_RG_LDO_VTCXO24_OP_EN_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VTCXO24_OP_EN_SET_SHIFT              0
#define PMIC_RG_LDO_VTCXO24_OP_EN_CLR_ADDR               MT6355_LDO_VTCXO24_OP_EN_CLR
#define PMIC_RG_LDO_VTCXO24_OP_EN_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VTCXO24_OP_EN_CLR_SHIFT              0
#define PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_ADDR              MT6355_LDO_VTCXO24_OP_CFG
#define PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VTCXO24_HW0_OP_CFG_SHIFT             1
#define PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_ADDR              MT6355_LDO_VTCXO24_OP_CFG
#define PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VTCXO24_HW1_OP_CFG_SHIFT             2
#define PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_ADDR              MT6355_LDO_VTCXO24_OP_CFG
#define PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VTCXO24_HW2_OP_CFG_SHIFT             3
#define PMIC_RG_LDO_VTCXO24_ON_OP_ADDR                   MT6355_LDO_VTCXO24_OP_CFG
#define PMIC_RG_LDO_VTCXO24_ON_OP_MASK                   0x1
#define PMIC_RG_LDO_VTCXO24_ON_OP_SHIFT                  8
#define PMIC_RG_LDO_VTCXO24_LP_OP_ADDR                   MT6355_LDO_VTCXO24_OP_CFG
#define PMIC_RG_LDO_VTCXO24_LP_OP_MASK                   0x1
#define PMIC_RG_LDO_VTCXO24_LP_OP_SHIFT                  9
#define PMIC_RG_LDO_VTCXO24_OP_CFG_SET_ADDR              MT6355_LDO_VTCXO24_OP_CFG_SET
#define PMIC_RG_LDO_VTCXO24_OP_CFG_SET_MASK              0xFFFF
#define PMIC_RG_LDO_VTCXO24_OP_CFG_SET_SHIFT             0
#define PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_ADDR              MT6355_LDO_VTCXO24_OP_CFG_CLR
#define PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_MASK              0xFFFF
#define PMIC_RG_LDO_VTCXO24_OP_CFG_CLR_SHIFT             0
#define PMIC_DA_QI_VTCXO24_MODE_ADDR                     MT6355_LDO_VTCXO24_CON1
#define PMIC_DA_QI_VTCXO24_MODE_MASK                     0x1
#define PMIC_DA_QI_VTCXO24_MODE_SHIFT                    8
#define PMIC_RG_LDO_VTCXO24_STBTD_ADDR                   MT6355_LDO_VTCXO24_CON1
#define PMIC_RG_LDO_VTCXO24_STBTD_MASK                   0x3
#define PMIC_RG_LDO_VTCXO24_STBTD_SHIFT                  9
#define PMIC_DA_QI_VTCXO24_STB_ADDR                      MT6355_LDO_VTCXO24_CON1
#define PMIC_DA_QI_VTCXO24_STB_MASK                      0x1
#define PMIC_DA_QI_VTCXO24_STB_SHIFT                     14
#define PMIC_DA_QI_VTCXO24_EN_ADDR                       MT6355_LDO_VTCXO24_CON1
#define PMIC_DA_QI_VTCXO24_EN_MASK                       0x1
#define PMIC_DA_QI_VTCXO24_EN_SHIFT                      15
#define PMIC_RG_LDO_VTCXO24_OCFB_EN_ADDR                 MT6355_LDO_VTCXO24_CON2
#define PMIC_RG_LDO_VTCXO24_OCFB_EN_MASK                 0x1
#define PMIC_RG_LDO_VTCXO24_OCFB_EN_SHIFT                9
#define PMIC_DA_QI_VTCXO24_OCFB_EN_ADDR                  MT6355_LDO_VTCXO24_CON2
#define PMIC_DA_QI_VTCXO24_OCFB_EN_MASK                  0x1
#define PMIC_DA_QI_VTCXO24_OCFB_EN_SHIFT                 10
#define PMIC_RG_LDO_VTCXO24_DUMMY_LOAD_ADDR              MT6355_LDO_VTCXO24_CON3
#define PMIC_RG_LDO_VTCXO24_DUMMY_LOAD_MASK              0x3
#define PMIC_RG_LDO_VTCXO24_DUMMY_LOAD_SHIFT             5
#define PMIC_DA_QI_VTCXO24_DUMMY_LOAD_ADDR               MT6355_LDO_VTCXO24_CON3
#define PMIC_DA_QI_VTCXO24_DUMMY_LOAD_MASK               0x3
#define PMIC_DA_QI_VTCXO24_DUMMY_LOAD_SHIFT              14
#define PMIC_RG_LDO_VLDO28_EN_AF_ADDR                    MT6355_LDO_VLDO28_CON0_AF
#define PMIC_RG_LDO_VLDO28_EN_AF_MASK                    0x1
#define PMIC_RG_LDO_VLDO28_EN_AF_SHIFT                   0
#define PMIC_RG_LDO_VLDO28_LP_ADDR                       MT6355_LDO_VLDO28_CON0_AF
#define PMIC_RG_LDO_VLDO28_LP_MASK                       0x1
#define PMIC_RG_LDO_VLDO28_LP_SHIFT                      1
#define PMIC_RG_LDO_VLDO28_SW_OP_EN_ADDR                 MT6355_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VLDO28_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VLDO28_HW0_OP_EN_ADDR                MT6355_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VLDO28_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VLDO28_HW1_OP_EN_ADDR                MT6355_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VLDO28_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VLDO28_HW2_OP_EN_ADDR                MT6355_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VLDO28_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VLDO28_OP_EN_SET_ADDR                MT6355_LDO_VLDO28_OP_EN_SET
#define PMIC_RG_LDO_VLDO28_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VLDO28_OP_EN_CLR_ADDR                MT6355_LDO_VLDO28_OP_EN_CLR
#define PMIC_RG_LDO_VLDO28_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VLDO28_HW0_OP_CFG_ADDR               MT6355_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VLDO28_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VLDO28_HW1_OP_CFG_ADDR               MT6355_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VLDO28_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VLDO28_HW2_OP_CFG_ADDR               MT6355_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VLDO28_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VLDO28_ON_OP_ADDR                    MT6355_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VLDO28_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VLDO28_LP_OP_ADDR                    MT6355_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VLDO28_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VLDO28_OP_CFG_SET_ADDR               MT6355_LDO_VLDO28_OP_CFG_SET
#define PMIC_RG_LDO_VLDO28_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VLDO28_OP_CFG_CLR_ADDR               MT6355_LDO_VLDO28_OP_CFG_CLR
#define PMIC_RG_LDO_VLDO28_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_CFG_CLR_SHIFT              0
#define PMIC_RG_LDO_VLDO28_EN_TP_ADDR                    MT6355_LDO_VLDO28_CON0_TP
#define PMIC_RG_LDO_VLDO28_EN_TP_MASK                    0x1
#define PMIC_RG_LDO_VLDO28_EN_TP_SHIFT                   0
#define PMIC_DA_QI_VLDO28_MODE_ADDR                      MT6355_LDO_VLDO28_CON1
#define PMIC_DA_QI_VLDO28_MODE_MASK                      0x1
#define PMIC_DA_QI_VLDO28_MODE_SHIFT                     8
#define PMIC_RG_LDO_VLDO28_STBTD_ADDR                    MT6355_LDO_VLDO28_CON1
#define PMIC_RG_LDO_VLDO28_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VLDO28_STBTD_SHIFT                   9
#define PMIC_DA_QI_VLDO28_STB_ADDR                       MT6355_LDO_VLDO28_CON1
#define PMIC_DA_QI_VLDO28_STB_MASK                       0x1
#define PMIC_DA_QI_VLDO28_STB_SHIFT                      14
#define PMIC_DA_QI_VLDO28_EN_ADDR                        MT6355_LDO_VLDO28_CON1
#define PMIC_DA_QI_VLDO28_EN_MASK                        0x1
#define PMIC_DA_QI_VLDO28_EN_SHIFT                       15
#define PMIC_RG_LDO_VLDO28_OCFB_EN_ADDR                  MT6355_LDO_VLDO28_CON2
#define PMIC_RG_LDO_VLDO28_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VLDO28_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VLDO28_OCFB_EN_ADDR                   MT6355_LDO_VLDO28_CON2
#define PMIC_DA_QI_VLDO28_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VLDO28_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VLDO28_DUMMY_LOAD_ADDR               MT6355_LDO_VLDO28_CON3
#define PMIC_RG_LDO_VLDO28_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VLDO28_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VLDO28_DUMMY_LOAD_ADDR                MT6355_LDO_VLDO28_CON3
#define PMIC_DA_QI_VLDO28_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VLDO28_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VGP2_EN_ADDR                         MT6355_LDO_VGP2_CON0
#define PMIC_RG_LDO_VGP2_EN_MASK                         0x1
#define PMIC_RG_LDO_VGP2_EN_SHIFT                        0
#define PMIC_RG_LDO_VGP2_LP_ADDR                         MT6355_LDO_VGP2_CON0
#define PMIC_RG_LDO_VGP2_LP_MASK                         0x1
#define PMIC_RG_LDO_VGP2_LP_SHIFT                        1
#define PMIC_RG_LDO_VGP2_SW_OP_EN_ADDR                   MT6355_LDO_VGP2_OP_EN
#define PMIC_RG_LDO_VGP2_SW_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VGP2_SW_OP_EN_SHIFT                  0
#define PMIC_RG_LDO_VGP2_HW0_OP_EN_ADDR                  MT6355_LDO_VGP2_OP_EN
#define PMIC_RG_LDO_VGP2_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VGP2_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_LDO_VGP2_HW1_OP_EN_ADDR                  MT6355_LDO_VGP2_OP_EN
#define PMIC_RG_LDO_VGP2_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VGP2_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_LDO_VGP2_HW2_OP_EN_ADDR                  MT6355_LDO_VGP2_OP_EN
#define PMIC_RG_LDO_VGP2_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VGP2_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_LDO_VGP2_OP_EN_SET_ADDR                  MT6355_LDO_VGP2_OP_EN_SET
#define PMIC_RG_LDO_VGP2_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VGP2_OP_EN_SET_SHIFT                 0
#define PMIC_RG_LDO_VGP2_OP_EN_CLR_ADDR                  MT6355_LDO_VGP2_OP_EN_CLR
#define PMIC_RG_LDO_VGP2_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VGP2_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_LDO_VGP2_HW0_OP_CFG_ADDR                 MT6355_LDO_VGP2_OP_CFG
#define PMIC_RG_LDO_VGP2_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VGP2_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_LDO_VGP2_HW1_OP_CFG_ADDR                 MT6355_LDO_VGP2_OP_CFG
#define PMIC_RG_LDO_VGP2_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VGP2_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_LDO_VGP2_HW2_OP_CFG_ADDR                 MT6355_LDO_VGP2_OP_CFG
#define PMIC_RG_LDO_VGP2_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VGP2_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_LDO_VGP2_ON_OP_ADDR                      MT6355_LDO_VGP2_OP_CFG
#define PMIC_RG_LDO_VGP2_ON_OP_MASK                      0x1
#define PMIC_RG_LDO_VGP2_ON_OP_SHIFT                     8
#define PMIC_RG_LDO_VGP2_LP_OP_ADDR                      MT6355_LDO_VGP2_OP_CFG
#define PMIC_RG_LDO_VGP2_LP_OP_MASK                      0x1
#define PMIC_RG_LDO_VGP2_LP_OP_SHIFT                     9
#define PMIC_RG_LDO_VGP2_OP_CFG_SET_ADDR                 MT6355_LDO_VGP2_OP_CFG_SET
#define PMIC_RG_LDO_VGP2_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VGP2_OP_CFG_SET_SHIFT                0
#define PMIC_RG_LDO_VGP2_OP_CFG_CLR_ADDR                 MT6355_LDO_VGP2_OP_CFG_CLR
#define PMIC_RG_LDO_VGP2_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VGP2_OP_CFG_CLR_SHIFT                0
#define PMIC_DA_QI_VGP2_MODE_ADDR                        MT6355_LDO_VGP2_CON1
#define PMIC_DA_QI_VGP2_MODE_MASK                        0x1
#define PMIC_DA_QI_VGP2_MODE_SHIFT                       8
#define PMIC_RG_LDO_VGP2_STBTD_ADDR                      MT6355_LDO_VGP2_CON1
#define PMIC_RG_LDO_VGP2_STBTD_MASK                      0x3
#define PMIC_RG_LDO_VGP2_STBTD_SHIFT                     9
#define PMIC_DA_QI_VGP2_STB_ADDR                         MT6355_LDO_VGP2_CON1
#define PMIC_DA_QI_VGP2_STB_MASK                         0x1
#define PMIC_DA_QI_VGP2_STB_SHIFT                        14
#define PMIC_DA_QI_VGP2_EN_ADDR                          MT6355_LDO_VGP2_CON1
#define PMIC_DA_QI_VGP2_EN_MASK                          0x1
#define PMIC_DA_QI_VGP2_EN_SHIFT                         15
#define PMIC_RG_LDO_VGP2_THER_SDN_EN_ADDR                MT6355_LDO_VGP2_CON2
#define PMIC_RG_LDO_VGP2_THER_SDN_EN_MASK                0x1
#define PMIC_RG_LDO_VGP2_THER_SDN_EN_SHIFT               4
#define PMIC_RG_LDO_VGP2_OCFB_EN_ADDR                    MT6355_LDO_VGP2_CON2
#define PMIC_RG_LDO_VGP2_OCFB_EN_MASK                    0x1
#define PMIC_RG_LDO_VGP2_OCFB_EN_SHIFT                   9
#define PMIC_DA_QI_VGP2_OCFB_EN_ADDR                     MT6355_LDO_VGP2_CON2
#define PMIC_DA_QI_VGP2_OCFB_EN_MASK                     0x1
#define PMIC_DA_QI_VGP2_OCFB_EN_SHIFT                    10
#define PMIC_RG_LDO_VGP2_DUMMY_LOAD_ADDR                 MT6355_LDO_VGP2_CON3
#define PMIC_RG_LDO_VGP2_DUMMY_LOAD_MASK                 0x3
#define PMIC_RG_LDO_VGP2_DUMMY_LOAD_SHIFT                5
#define PMIC_DA_QI_VGP2_DUMMY_LOAD_ADDR                  MT6355_LDO_VGP2_CON3
#define PMIC_DA_QI_VGP2_DUMMY_LOAD_MASK                  0x3
#define PMIC_DA_QI_VGP2_DUMMY_LOAD_SHIFT                 14
#define PMIC_RG_LDO_VFE28_EN_ADDR                        MT6355_LDO_VFE28_CON0
#define PMIC_RG_LDO_VFE28_EN_MASK                        0x1
#define PMIC_RG_LDO_VFE28_EN_SHIFT                       0
#define PMIC_RG_LDO_VFE28_LP_ADDR                        MT6355_LDO_VFE28_CON0
#define PMIC_RG_LDO_VFE28_LP_MASK                        0x1
#define PMIC_RG_LDO_VFE28_LP_SHIFT                       1
#define PMIC_RG_LDO_VFE28_SW_OP_EN_ADDR                  MT6355_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VFE28_HW0_OP_EN_ADDR                 MT6355_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VFE28_HW1_OP_EN_ADDR                 MT6355_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VFE28_HW2_OP_EN_ADDR                 MT6355_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR                 MT6355_LDO_VFE28_OP_EN_SET
#define PMIC_RG_LDO_VFE28_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR                 MT6355_LDO_VFE28_OP_EN_CLR
#define PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_ADDR                MT6355_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_ADDR                MT6355_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_ADDR                MT6355_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VFE28_ON_OP_ADDR                     MT6355_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VFE28_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VFE28_LP_OP_ADDR                     MT6355_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VFE28_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR                MT6355_LDO_VFE28_OP_CFG_SET
#define PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR                MT6355_LDO_VFE28_OP_CFG_CLR
#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VFE28_MODE_ADDR                       MT6355_LDO_VFE28_CON1
#define PMIC_DA_QI_VFE28_MODE_MASK                       0x1
#define PMIC_DA_QI_VFE28_MODE_SHIFT                      8
#define PMIC_RG_LDO_VFE28_STBTD_ADDR                     MT6355_LDO_VFE28_CON1
#define PMIC_RG_LDO_VFE28_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VFE28_STBTD_SHIFT                    9
#define PMIC_DA_QI_VFE28_STB_ADDR                        MT6355_LDO_VFE28_CON1
#define PMIC_DA_QI_VFE28_STB_MASK                        0x1
#define PMIC_DA_QI_VFE28_STB_SHIFT                       14
#define PMIC_DA_QI_VFE28_EN_ADDR                         MT6355_LDO_VFE28_CON1
#define PMIC_DA_QI_VFE28_EN_MASK                         0x1
#define PMIC_DA_QI_VFE28_EN_SHIFT                        15
#define PMIC_RG_LDO_VFE28_OCFB_EN_ADDR                   MT6355_LDO_VFE28_CON2
#define PMIC_RG_LDO_VFE28_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VFE28_OCFB_EN_ADDR                    MT6355_LDO_VFE28_CON2
#define PMIC_DA_QI_VFE28_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VFE28_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_ADDR                MT6355_LDO_VFE28_CON3
#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VFE28_DUMMY_LOAD_ADDR                 MT6355_LDO_VFE28_CON3
#define PMIC_DA_QI_VFE28_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VFE28_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VMCH_EN_ADDR                         MT6355_LDO_VMCH_CON0
#define PMIC_RG_LDO_VMCH_EN_MASK                         0x1
#define PMIC_RG_LDO_VMCH_EN_SHIFT                        0
#define PMIC_RG_LDO_VMCH_LP_ADDR                         MT6355_LDO_VMCH_CON0
#define PMIC_RG_LDO_VMCH_LP_MASK                         0x1
#define PMIC_RG_LDO_VMCH_LP_SHIFT                        1
#define PMIC_RG_LDO_VMCH_SW_OP_EN_ADDR                   MT6355_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_SW_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VMCH_SW_OP_EN_SHIFT                  0
#define PMIC_RG_LDO_VMCH_HW0_OP_EN_ADDR                  MT6355_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_HW0_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VMCH_HW0_OP_EN_SHIFT                 1
#define PMIC_RG_LDO_VMCH_HW1_OP_EN_ADDR                  MT6355_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_HW1_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VMCH_HW1_OP_EN_SHIFT                 2
#define PMIC_RG_LDO_VMCH_HW2_OP_EN_ADDR                  MT6355_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_HW2_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VMCH_HW2_OP_EN_SHIFT                 3
#define PMIC_RG_LDO_VMCH_OP_EN_SET_ADDR                  MT6355_LDO_VMCH_OP_EN_SET
#define PMIC_RG_LDO_VMCH_OP_EN_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VMCH_OP_EN_SET_SHIFT                 0
#define PMIC_RG_LDO_VMCH_OP_EN_CLR_ADDR                  MT6355_LDO_VMCH_OP_EN_CLR
#define PMIC_RG_LDO_VMCH_OP_EN_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VMCH_OP_EN_CLR_SHIFT                 0
#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_ADDR                 MT6355_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_SHIFT                1
#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_ADDR                 MT6355_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_SHIFT                2
#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_ADDR                 MT6355_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_MASK                 0x1
#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_SHIFT                3
#define PMIC_RG_LDO_VMCH_ON_OP_ADDR                      MT6355_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_ON_OP_MASK                      0x1
#define PMIC_RG_LDO_VMCH_ON_OP_SHIFT                     8
#define PMIC_RG_LDO_VMCH_LP_OP_ADDR                      MT6355_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_LP_OP_MASK                      0x1
#define PMIC_RG_LDO_VMCH_LP_OP_SHIFT                     9
#define PMIC_RG_LDO_VMCH_OP_CFG_SET_ADDR                 MT6355_LDO_VMCH_OP_CFG_SET
#define PMIC_RG_LDO_VMCH_OP_CFG_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VMCH_OP_CFG_SET_SHIFT                0
#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_ADDR                 MT6355_LDO_VMCH_OP_CFG_CLR
#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_SHIFT                0
#define PMIC_DA_QI_VMCH_MODE_ADDR                        MT6355_LDO_VMCH_CON1
#define PMIC_DA_QI_VMCH_MODE_MASK                        0x1
#define PMIC_DA_QI_VMCH_MODE_SHIFT                       8
#define PMIC_RG_LDO_VMCH_STBTD_ADDR                      MT6355_LDO_VMCH_CON1
#define PMIC_RG_LDO_VMCH_STBTD_MASK                      0x3
#define PMIC_RG_LDO_VMCH_STBTD_SHIFT                     9
#define PMIC_DA_QI_VMCH_STB_ADDR                         MT6355_LDO_VMCH_CON1
#define PMIC_DA_QI_VMCH_STB_MASK                         0x1
#define PMIC_DA_QI_VMCH_STB_SHIFT                        14
#define PMIC_DA_QI_VMCH_EN_ADDR                          MT6355_LDO_VMCH_CON1
#define PMIC_DA_QI_VMCH_EN_MASK                          0x1
#define PMIC_DA_QI_VMCH_EN_SHIFT                         15
#define PMIC_RG_LDO_VMCH_OCFB_EN_ADDR                    MT6355_LDO_VMCH_CON2
#define PMIC_RG_LDO_VMCH_OCFB_EN_MASK                    0x1
#define PMIC_RG_LDO_VMCH_OCFB_EN_SHIFT                   9
#define PMIC_DA_QI_VMCH_OCFB_EN_ADDR                     MT6355_LDO_VMCH_CON2
#define PMIC_DA_QI_VMCH_OCFB_EN_MASK                     0x1
#define PMIC_DA_QI_VMCH_OCFB_EN_SHIFT                    10
#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_ADDR                 MT6355_LDO_VMCH_CON3
#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_MASK                 0x3
#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_SHIFT                5
#define PMIC_DA_QI_VMCH_DUMMY_LOAD_ADDR                  MT6355_LDO_VMCH_CON3
#define PMIC_DA_QI_VMCH_DUMMY_LOAD_MASK                  0x3
#define PMIC_DA_QI_VMCH_DUMMY_LOAD_SHIFT                 14
#define PMIC_RG_LDO_VMC_EN_ADDR                          MT6355_LDO_VMC_CON0
#define PMIC_RG_LDO_VMC_EN_MASK                          0x1
#define PMIC_RG_LDO_VMC_EN_SHIFT                         0
#define PMIC_RG_LDO_VMC_LP_ADDR                          MT6355_LDO_VMC_CON0
#define PMIC_RG_LDO_VMC_LP_MASK                          0x1
#define PMIC_RG_LDO_VMC_LP_SHIFT                         1
#define PMIC_RG_LDO_VMC_SW_OP_EN_ADDR                    MT6355_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_SW_OP_EN_MASK                    0x1
#define PMIC_RG_LDO_VMC_SW_OP_EN_SHIFT                   0
#define PMIC_RG_LDO_VMC_HW0_OP_EN_ADDR                   MT6355_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_HW0_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VMC_HW0_OP_EN_SHIFT                  1
#define PMIC_RG_LDO_VMC_HW1_OP_EN_ADDR                   MT6355_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_HW1_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VMC_HW1_OP_EN_SHIFT                  2
#define PMIC_RG_LDO_VMC_HW2_OP_EN_ADDR                   MT6355_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_HW2_OP_EN_MASK                   0x1
#define PMIC_RG_LDO_VMC_HW2_OP_EN_SHIFT                  3
#define PMIC_RG_LDO_VMC_OP_EN_SET_ADDR                   MT6355_LDO_VMC_OP_EN_SET
#define PMIC_RG_LDO_VMC_OP_EN_SET_MASK                   0xFFFF
#define PMIC_RG_LDO_VMC_OP_EN_SET_SHIFT                  0
#define PMIC_RG_LDO_VMC_OP_EN_CLR_ADDR                   MT6355_LDO_VMC_OP_EN_CLR
#define PMIC_RG_LDO_VMC_OP_EN_CLR_MASK                   0xFFFF
#define PMIC_RG_LDO_VMC_OP_EN_CLR_SHIFT                  0
#define PMIC_RG_LDO_VMC_HW0_OP_CFG_ADDR                  MT6355_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_HW0_OP_CFG_MASK                  0x1
#define PMIC_RG_LDO_VMC_HW0_OP_CFG_SHIFT                 1
#define PMIC_RG_LDO_VMC_HW1_OP_CFG_ADDR                  MT6355_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_HW1_OP_CFG_MASK                  0x1
#define PMIC_RG_LDO_VMC_HW1_OP_CFG_SHIFT                 2
#define PMIC_RG_LDO_VMC_HW2_OP_CFG_ADDR                  MT6355_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_HW2_OP_CFG_MASK                  0x1
#define PMIC_RG_LDO_VMC_HW2_OP_CFG_SHIFT                 3
#define PMIC_RG_LDO_VMC_ON_OP_ADDR                       MT6355_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_ON_OP_MASK                       0x1
#define PMIC_RG_LDO_VMC_ON_OP_SHIFT                      8
#define PMIC_RG_LDO_VMC_LP_OP_ADDR                       MT6355_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_LP_OP_MASK                       0x1
#define PMIC_RG_LDO_VMC_LP_OP_SHIFT                      9
#define PMIC_RG_LDO_VMC_OP_CFG_SET_ADDR                  MT6355_LDO_VMC_OP_CFG_SET
#define PMIC_RG_LDO_VMC_OP_CFG_SET_MASK                  0xFFFF
#define PMIC_RG_LDO_VMC_OP_CFG_SET_SHIFT                 0
#define PMIC_RG_LDO_VMC_OP_CFG_CLR_ADDR                  MT6355_LDO_VMC_OP_CFG_CLR
#define PMIC_RG_LDO_VMC_OP_CFG_CLR_MASK                  0xFFFF
#define PMIC_RG_LDO_VMC_OP_CFG_CLR_SHIFT                 0
#define PMIC_DA_QI_VMC_MODE_ADDR                         MT6355_LDO_VMC_CON1
#define PMIC_DA_QI_VMC_MODE_MASK                         0x1
#define PMIC_DA_QI_VMC_MODE_SHIFT                        8
#define PMIC_RG_LDO_VMC_STBTD_ADDR                       MT6355_LDO_VMC_CON1
#define PMIC_RG_LDO_VMC_STBTD_MASK                       0x3
#define PMIC_RG_LDO_VMC_STBTD_SHIFT                      9
#define PMIC_DA_QI_VMC_STB_ADDR                          MT6355_LDO_VMC_CON1
#define PMIC_DA_QI_VMC_STB_MASK                          0x1
#define PMIC_DA_QI_VMC_STB_SHIFT                         14
#define PMIC_DA_QI_VMC_EN_ADDR                           MT6355_LDO_VMC_CON1
#define PMIC_DA_QI_VMC_EN_MASK                           0x1
#define PMIC_DA_QI_VMC_EN_SHIFT                          15
#define PMIC_RG_LDO_VMC_OCFB_EN_ADDR                     MT6355_LDO_VMC_CON2
#define PMIC_RG_LDO_VMC_OCFB_EN_MASK                     0x1
#define PMIC_RG_LDO_VMC_OCFB_EN_SHIFT                    9
#define PMIC_DA_QI_VMC_OCFB_EN_ADDR                      MT6355_LDO_VMC_CON2
#define PMIC_DA_QI_VMC_OCFB_EN_MASK                      0x1
#define PMIC_DA_QI_VMC_OCFB_EN_SHIFT                     10
#define PMIC_RG_LDO_VMC_DUMMY_LOAD_ADDR                  MT6355_LDO_VMC_CON3
#define PMIC_RG_LDO_VMC_DUMMY_LOAD_MASK                  0x3
#define PMIC_RG_LDO_VMC_DUMMY_LOAD_SHIFT                 5
#define PMIC_DA_QI_VMC_DUMMY_LOAD_ADDR                   MT6355_LDO_VMC_CON3
#define PMIC_DA_QI_VMC_DUMMY_LOAD_MASK                   0x3
#define PMIC_DA_QI_VMC_DUMMY_LOAD_SHIFT                  14
#define PMIC_RG_LDO_VRF18_1_EN_ADDR                      MT6355_LDO_VRF18_1_CON0
#define PMIC_RG_LDO_VRF18_1_EN_MASK                      0x1
#define PMIC_RG_LDO_VRF18_1_EN_SHIFT                     0
#define PMIC_RG_LDO_VRF18_1_LP_ADDR                      MT6355_LDO_VRF18_1_CON0
#define PMIC_RG_LDO_VRF18_1_LP_MASK                      0x1
#define PMIC_RG_LDO_VRF18_1_LP_SHIFT                     1
#define PMIC_RG_LDO_VRF18_1_SW_OP_EN_ADDR                MT6355_LDO_VRF18_1_OP_EN
#define PMIC_RG_LDO_VRF18_1_SW_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VRF18_1_SW_OP_EN_SHIFT               0
#define PMIC_RG_LDO_VRF18_1_HW0_OP_EN_ADDR               MT6355_LDO_VRF18_1_OP_EN
#define PMIC_RG_LDO_VRF18_1_HW0_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VRF18_1_HW0_OP_EN_SHIFT              1
#define PMIC_RG_LDO_VRF18_1_HW1_OP_EN_ADDR               MT6355_LDO_VRF18_1_OP_EN
#define PMIC_RG_LDO_VRF18_1_HW1_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VRF18_1_HW1_OP_EN_SHIFT              2
#define PMIC_RG_LDO_VRF18_1_HW2_OP_EN_ADDR               MT6355_LDO_VRF18_1_OP_EN
#define PMIC_RG_LDO_VRF18_1_HW2_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VRF18_1_HW2_OP_EN_SHIFT              3
#define PMIC_RG_LDO_VRF18_1_OP_EN_SET_ADDR               MT6355_LDO_VRF18_1_OP_EN_SET
#define PMIC_RG_LDO_VRF18_1_OP_EN_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VRF18_1_OP_EN_SET_SHIFT              0
#define PMIC_RG_LDO_VRF18_1_OP_EN_CLR_ADDR               MT6355_LDO_VRF18_1_OP_EN_CLR
#define PMIC_RG_LDO_VRF18_1_OP_EN_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VRF18_1_OP_EN_CLR_SHIFT              0
#define PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_ADDR              MT6355_LDO_VRF18_1_OP_CFG
#define PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VRF18_1_HW0_OP_CFG_SHIFT             1
#define PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_ADDR              MT6355_LDO_VRF18_1_OP_CFG
#define PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VRF18_1_HW1_OP_CFG_SHIFT             2
#define PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_ADDR              MT6355_LDO_VRF18_1_OP_CFG
#define PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VRF18_1_HW2_OP_CFG_SHIFT             3
#define PMIC_RG_LDO_VRF18_1_ON_OP_ADDR                   MT6355_LDO_VRF18_1_OP_CFG
#define PMIC_RG_LDO_VRF18_1_ON_OP_MASK                   0x1
#define PMIC_RG_LDO_VRF18_1_ON_OP_SHIFT                  8
#define PMIC_RG_LDO_VRF18_1_LP_OP_ADDR                   MT6355_LDO_VRF18_1_OP_CFG
#define PMIC_RG_LDO_VRF18_1_LP_OP_MASK                   0x1
#define PMIC_RG_LDO_VRF18_1_LP_OP_SHIFT                  9
#define PMIC_RG_LDO_VRF18_1_OP_CFG_SET_ADDR              MT6355_LDO_VRF18_1_OP_CFG_SET
#define PMIC_RG_LDO_VRF18_1_OP_CFG_SET_MASK              0xFFFF
#define PMIC_RG_LDO_VRF18_1_OP_CFG_SET_SHIFT             0
#define PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_ADDR              MT6355_LDO_VRF18_1_OP_CFG_CLR
#define PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_MASK              0xFFFF
#define PMIC_RG_LDO_VRF18_1_OP_CFG_CLR_SHIFT             0
#define PMIC_DA_QI_VRF18_1_MODE_ADDR                     MT6355_LDO_VRF18_1_CON1
#define PMIC_DA_QI_VRF18_1_MODE_MASK                     0x1
#define PMIC_DA_QI_VRF18_1_MODE_SHIFT                    8
#define PMIC_RG_LDO_VRF18_1_STBTD_ADDR                   MT6355_LDO_VRF18_1_CON1
#define PMIC_RG_LDO_VRF18_1_STBTD_MASK                   0x3
#define PMIC_RG_LDO_VRF18_1_STBTD_SHIFT                  9
#define PMIC_DA_QI_VRF18_1_STB_ADDR                      MT6355_LDO_VRF18_1_CON1
#define PMIC_DA_QI_VRF18_1_STB_MASK                      0x1
#define PMIC_DA_QI_VRF18_1_STB_SHIFT                     14
#define PMIC_DA_QI_VRF18_1_EN_ADDR                       MT6355_LDO_VRF18_1_CON1
#define PMIC_DA_QI_VRF18_1_EN_MASK                       0x1
#define PMIC_DA_QI_VRF18_1_EN_SHIFT                      15
#define PMIC_RG_LDO_VRF18_1_OCFB_EN_ADDR                 MT6355_LDO_VRF18_1_CON2
#define PMIC_RG_LDO_VRF18_1_OCFB_EN_MASK                 0x1
#define PMIC_RG_LDO_VRF18_1_OCFB_EN_SHIFT                9
#define PMIC_DA_QI_VRF18_1_OCFB_EN_ADDR                  MT6355_LDO_VRF18_1_CON2
#define PMIC_DA_QI_VRF18_1_OCFB_EN_MASK                  0x1
#define PMIC_DA_QI_VRF18_1_OCFB_EN_SHIFT                 10
#define PMIC_RG_LDO_VRF18_1_DUMMY_LOAD_ADDR              MT6355_LDO_VRF18_1_CON3
#define PMIC_RG_LDO_VRF18_1_DUMMY_LOAD_MASK              0x3
#define PMIC_RG_LDO_VRF18_1_DUMMY_LOAD_SHIFT             5
#define PMIC_DA_QI_VRF18_1_DUMMY_LOAD_ADDR               MT6355_LDO_VRF18_1_CON3
#define PMIC_DA_QI_VRF18_1_DUMMY_LOAD_MASK               0x3
#define PMIC_DA_QI_VRF18_1_DUMMY_LOAD_SHIFT              14
#define PMIC_RG_LDO_VRF18_2_EN_ADDR                      MT6355_LDO_VRF18_2_CON0
#define PMIC_RG_LDO_VRF18_2_EN_MASK                      0x1
#define PMIC_RG_LDO_VRF18_2_EN_SHIFT                     0
#define PMIC_RG_LDO_VRF18_2_LP_ADDR                      MT6355_LDO_VRF18_2_CON0
#define PMIC_RG_LDO_VRF18_2_LP_MASK                      0x1
#define PMIC_RG_LDO_VRF18_2_LP_SHIFT                     1
#define PMIC_RG_LDO_VRF18_2_SW_OP_EN_ADDR                MT6355_LDO_VRF18_2_OP_EN
#define PMIC_RG_LDO_VRF18_2_SW_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VRF18_2_SW_OP_EN_SHIFT               0
#define PMIC_RG_LDO_VRF18_2_HW0_OP_EN_ADDR               MT6355_LDO_VRF18_2_OP_EN
#define PMIC_RG_LDO_VRF18_2_HW0_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VRF18_2_HW0_OP_EN_SHIFT              1
#define PMIC_RG_LDO_VRF18_2_HW1_OP_EN_ADDR               MT6355_LDO_VRF18_2_OP_EN
#define PMIC_RG_LDO_VRF18_2_HW1_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VRF18_2_HW1_OP_EN_SHIFT              2
#define PMIC_RG_LDO_VRF18_2_HW2_OP_EN_ADDR               MT6355_LDO_VRF18_2_OP_EN
#define PMIC_RG_LDO_VRF18_2_HW2_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VRF18_2_HW2_OP_EN_SHIFT              3
#define PMIC_RG_LDO_VRF18_2_OP_EN_SET_ADDR               MT6355_LDO_VRF18_2_OP_EN_SET
#define PMIC_RG_LDO_VRF18_2_OP_EN_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VRF18_2_OP_EN_SET_SHIFT              0
#define PMIC_RG_LDO_VRF18_2_OP_EN_CLR_ADDR               MT6355_LDO_VRF18_2_OP_EN_CLR
#define PMIC_RG_LDO_VRF18_2_OP_EN_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VRF18_2_OP_EN_CLR_SHIFT              0
#define PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_ADDR              MT6355_LDO_VRF18_2_OP_CFG
#define PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VRF18_2_HW0_OP_CFG_SHIFT             1
#define PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_ADDR              MT6355_LDO_VRF18_2_OP_CFG
#define PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VRF18_2_HW1_OP_CFG_SHIFT             2
#define PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_ADDR              MT6355_LDO_VRF18_2_OP_CFG
#define PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_MASK              0x1
#define PMIC_RG_LDO_VRF18_2_HW2_OP_CFG_SHIFT             3
#define PMIC_RG_LDO_VRF18_2_ON_OP_ADDR                   MT6355_LDO_VRF18_2_OP_CFG
#define PMIC_RG_LDO_VRF18_2_ON_OP_MASK                   0x1
#define PMIC_RG_LDO_VRF18_2_ON_OP_SHIFT                  8
#define PMIC_RG_LDO_VRF18_2_LP_OP_ADDR                   MT6355_LDO_VRF18_2_OP_CFG
#define PMIC_RG_LDO_VRF18_2_LP_OP_MASK                   0x1
#define PMIC_RG_LDO_VRF18_2_LP_OP_SHIFT                  9
#define PMIC_RG_LDO_VRF18_2_OP_CFG_SET_ADDR              MT6355_LDO_VRF18_2_OP_CFG_SET
#define PMIC_RG_LDO_VRF18_2_OP_CFG_SET_MASK              0xFFFF
#define PMIC_RG_LDO_VRF18_2_OP_CFG_SET_SHIFT             0
#define PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_ADDR              MT6355_LDO_VRF18_2_OP_CFG_CLR
#define PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_MASK              0xFFFF
#define PMIC_RG_LDO_VRF18_2_OP_CFG_CLR_SHIFT             0
#define PMIC_DA_QI_VRF18_2_MODE_ADDR                     MT6355_LDO_VRF18_2_CON1
#define PMIC_DA_QI_VRF18_2_MODE_MASK                     0x1
#define PMIC_DA_QI_VRF18_2_MODE_SHIFT                    8
#define PMIC_RG_LDO_VRF18_2_STBTD_ADDR                   MT6355_LDO_VRF18_2_CON1
#define PMIC_RG_LDO_VRF18_2_STBTD_MASK                   0x3
#define PMIC_RG_LDO_VRF18_2_STBTD_SHIFT                  9
#define PMIC_DA_QI_VRF18_2_STB_ADDR                      MT6355_LDO_VRF18_2_CON1
#define PMIC_DA_QI_VRF18_2_STB_MASK                      0x1
#define PMIC_DA_QI_VRF18_2_STB_SHIFT                     14
#define PMIC_DA_QI_VRF18_2_EN_ADDR                       MT6355_LDO_VRF18_2_CON1
#define PMIC_DA_QI_VRF18_2_EN_MASK                       0x1
#define PMIC_DA_QI_VRF18_2_EN_SHIFT                      15
#define PMIC_RG_LDO_VRF18_2_OCFB_EN_ADDR                 MT6355_LDO_VRF18_2_CON2
#define PMIC_RG_LDO_VRF18_2_OCFB_EN_MASK                 0x1
#define PMIC_RG_LDO_VRF18_2_OCFB_EN_SHIFT                9
#define PMIC_DA_QI_VRF18_2_OCFB_EN_ADDR                  MT6355_LDO_VRF18_2_CON2
#define PMIC_DA_QI_VRF18_2_OCFB_EN_MASK                  0x1
#define PMIC_DA_QI_VRF18_2_OCFB_EN_SHIFT                 10
#define PMIC_RG_LDO_VRF18_2_DUMMY_LOAD_ADDR              MT6355_LDO_VRF18_2_CON3
#define PMIC_RG_LDO_VRF18_2_DUMMY_LOAD_MASK              0x3
#define PMIC_RG_LDO_VRF18_2_DUMMY_LOAD_SHIFT             5
#define PMIC_DA_QI_VRF18_2_DUMMY_LOAD_ADDR               MT6355_LDO_VRF18_2_CON3
#define PMIC_DA_QI_VRF18_2_DUMMY_LOAD_MASK               0x3
#define PMIC_DA_QI_VRF18_2_DUMMY_LOAD_SHIFT              14
#define PMIC_RG_LDO_VRF12_EN_ADDR                        MT6355_LDO_VRF12_CON0
#define PMIC_RG_LDO_VRF12_EN_MASK                        0x1
#define PMIC_RG_LDO_VRF12_EN_SHIFT                       0
#define PMIC_RG_LDO_VRF12_LP_ADDR                        MT6355_LDO_VRF12_CON0
#define PMIC_RG_LDO_VRF12_LP_MASK                        0x1
#define PMIC_RG_LDO_VRF12_LP_SHIFT                       1
#define PMIC_RG_LDO_VRF12_SW_OP_EN_ADDR                  MT6355_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_SW_OP_EN_MASK                  0x1
#define PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT                 0
#define PMIC_RG_LDO_VRF12_HW0_OP_EN_ADDR                 MT6355_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT                1
#define PMIC_RG_LDO_VRF12_HW1_OP_EN_ADDR                 MT6355_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT                2
#define PMIC_RG_LDO_VRF12_HW2_OP_EN_ADDR                 MT6355_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT                3
#define PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR                 MT6355_LDO_VRF12_OP_EN_SET
#define PMIC_RG_LDO_VRF12_OP_EN_SET_MASK                 0xFFFF
#define PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT                0
#define PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR                 MT6355_LDO_VRF12_OP_EN_CLR
#define PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK                 0xFFFF
#define PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT                0
#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_ADDR                MT6355_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT               1
#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_ADDR                MT6355_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT               2
#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_ADDR                MT6355_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK                0x1
#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT               3
#define PMIC_RG_LDO_VRF12_ON_OP_ADDR                     MT6355_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_ON_OP_MASK                     0x1
#define PMIC_RG_LDO_VRF12_ON_OP_SHIFT                    8
#define PMIC_RG_LDO_VRF12_LP_OP_ADDR                     MT6355_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_LP_OP_MASK                     0x1
#define PMIC_RG_LDO_VRF12_LP_OP_SHIFT                    9
#define PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR                MT6355_LDO_VRF12_OP_CFG_SET
#define PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT               0
#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR                MT6355_LDO_VRF12_OP_CFG_CLR
#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT               0
#define PMIC_DA_QI_VRF12_MODE_ADDR                       MT6355_LDO_VRF12_CON1
#define PMIC_DA_QI_VRF12_MODE_MASK                       0x1
#define PMIC_DA_QI_VRF12_MODE_SHIFT                      8
#define PMIC_RG_LDO_VRF12_STBTD_ADDR                     MT6355_LDO_VRF12_CON1
#define PMIC_RG_LDO_VRF12_STBTD_MASK                     0x3
#define PMIC_RG_LDO_VRF12_STBTD_SHIFT                    9
#define PMIC_DA_QI_VRF12_STB_ADDR                        MT6355_LDO_VRF12_CON1
#define PMIC_DA_QI_VRF12_STB_MASK                        0x1
#define PMIC_DA_QI_VRF12_STB_SHIFT                       14
#define PMIC_DA_QI_VRF12_EN_ADDR                         MT6355_LDO_VRF12_CON1
#define PMIC_DA_QI_VRF12_EN_MASK                         0x1
#define PMIC_DA_QI_VRF12_EN_SHIFT                        15
#define PMIC_RG_LDO_VRF12_OCFB_EN_ADDR                   MT6355_LDO_VRF12_CON2
#define PMIC_RG_LDO_VRF12_OCFB_EN_MASK                   0x1
#define PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT                  9
#define PMIC_DA_QI_VRF12_OCFB_EN_ADDR                    MT6355_LDO_VRF12_CON2
#define PMIC_DA_QI_VRF12_OCFB_EN_MASK                    0x1
#define PMIC_DA_QI_VRF12_OCFB_EN_SHIFT                   10
#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_ADDR                MT6355_LDO_VRF12_CON3
#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_MASK                0x3
#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_SHIFT               5
#define PMIC_DA_QI_VRF12_DUMMY_LOAD_ADDR                 MT6355_LDO_VRF12_CON3
#define PMIC_DA_QI_VRF12_DUMMY_LOAD_MASK                 0x3
#define PMIC_DA_QI_VRF12_DUMMY_LOAD_SHIFT                14
#define PMIC_RG_LDO_VCAMA1_EN_ADDR                       MT6355_LDO_VCAMA1_CON0
#define PMIC_RG_LDO_VCAMA1_EN_MASK                       0x1
#define PMIC_RG_LDO_VCAMA1_EN_SHIFT                      0
#define PMIC_RG_LDO_VCAMA1_LP_ADDR                       MT6355_LDO_VCAMA1_CON0
#define PMIC_RG_LDO_VCAMA1_LP_MASK                       0x1
#define PMIC_RG_LDO_VCAMA1_LP_SHIFT                      1
#define PMIC_RG_LDO_VCAMA1_SW_OP_EN_ADDR                 MT6355_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMA1_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VCAMA1_HW0_OP_EN_ADDR                MT6355_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMA1_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_EN_ADDR                MT6355_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VCAMA1_HW2_OP_EN_ADDR                MT6355_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMA1_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VCAMA1_OP_EN_SET_ADDR                MT6355_LDO_VCAMA1_OP_EN_SET
#define PMIC_RG_LDO_VCAMA1_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VCAMA1_OP_EN_CLR_ADDR                MT6355_LDO_VCAMA1_OP_EN_CLR
#define PMIC_RG_LDO_VCAMA1_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VCAMA1_HW0_OP_CFG_ADDR               MT6355_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMA1_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_CFG_ADDR               MT6355_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VCAMA1_HW2_OP_CFG_ADDR               MT6355_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMA1_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VCAMA1_ON_OP_ADDR                    MT6355_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMA1_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VCAMA1_LP_OP_ADDR                    MT6355_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMA1_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VCAMA1_OP_CFG_SET_ADDR               MT6355_LDO_VCAMA1_OP_CFG_SET
#define PMIC_RG_LDO_VCAMA1_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VCAMA1_OP_CFG_CLR_ADDR               MT6355_LDO_VCAMA1_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMA1_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VCAMA1_MODE_ADDR                      MT6355_LDO_VCAMA1_CON1
#define PMIC_DA_QI_VCAMA1_MODE_MASK                      0x1
#define PMIC_DA_QI_VCAMA1_MODE_SHIFT                     8
#define PMIC_RG_LDO_VCAMA1_STBTD_ADDR                    MT6355_LDO_VCAMA1_CON1
#define PMIC_RG_LDO_VCAMA1_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VCAMA1_STBTD_SHIFT                   9
#define PMIC_DA_QI_VCAMA1_STB_ADDR                       MT6355_LDO_VCAMA1_CON1
#define PMIC_DA_QI_VCAMA1_STB_MASK                       0x1
#define PMIC_DA_QI_VCAMA1_STB_SHIFT                      14
#define PMIC_DA_QI_VCAMA1_EN_ADDR                        MT6355_LDO_VCAMA1_CON1
#define PMIC_DA_QI_VCAMA1_EN_MASK                        0x1
#define PMIC_DA_QI_VCAMA1_EN_SHIFT                       15
#define PMIC_RG_LDO_VCAMA1_OCFB_EN_ADDR                  MT6355_LDO_VCAMA1_CON2
#define PMIC_RG_LDO_VCAMA1_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VCAMA1_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VCAMA1_OCFB_EN_ADDR                   MT6355_LDO_VCAMA1_CON2
#define PMIC_DA_QI_VCAMA1_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VCAMA1_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VCAMA1_DUMMY_LOAD_ADDR               MT6355_LDO_VCAMA1_CON3
#define PMIC_RG_LDO_VCAMA1_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VCAMA1_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VCAMA1_DUMMY_LOAD_ADDR                MT6355_LDO_VCAMA1_CON3
#define PMIC_DA_QI_VCAMA1_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VCAMA1_DUMMY_LOAD_SHIFT               14
#define PMIC_RG_LDO_VCAMA2_EN_ADDR                       MT6355_LDO_VCAMA2_CON0
#define PMIC_RG_LDO_VCAMA2_EN_MASK                       0x1
#define PMIC_RG_LDO_VCAMA2_EN_SHIFT                      0
#define PMIC_RG_LDO_VCAMA2_LP_ADDR                       MT6355_LDO_VCAMA2_CON0
#define PMIC_RG_LDO_VCAMA2_LP_MASK                       0x1
#define PMIC_RG_LDO_VCAMA2_LP_SHIFT                      1
#define PMIC_RG_LDO_VCAMA2_SW_OP_EN_ADDR                 MT6355_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_SW_OP_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMA2_SW_OP_EN_SHIFT                0
#define PMIC_RG_LDO_VCAMA2_HW0_OP_EN_ADDR                MT6355_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_HW0_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMA2_HW0_OP_EN_SHIFT               1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_EN_ADDR                MT6355_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_HW1_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_EN_SHIFT               2
#define PMIC_RG_LDO_VCAMA2_HW2_OP_EN_ADDR                MT6355_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_HW2_OP_EN_MASK                0x1
#define PMIC_RG_LDO_VCAMA2_HW2_OP_EN_SHIFT               3
#define PMIC_RG_LDO_VCAMA2_OP_EN_SET_ADDR                MT6355_LDO_VCAMA2_OP_EN_SET
#define PMIC_RG_LDO_VCAMA2_OP_EN_SET_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_EN_SET_SHIFT               0
#define PMIC_RG_LDO_VCAMA2_OP_EN_CLR_ADDR                MT6355_LDO_VCAMA2_OP_EN_CLR
#define PMIC_RG_LDO_VCAMA2_OP_EN_CLR_MASK                0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_EN_CLR_SHIFT               0
#define PMIC_RG_LDO_VCAMA2_HW0_OP_CFG_ADDR               MT6355_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_HW0_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMA2_HW0_OP_CFG_SHIFT              1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_CFG_ADDR               MT6355_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_HW1_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_CFG_SHIFT              2
#define PMIC_RG_LDO_VCAMA2_HW2_OP_CFG_ADDR               MT6355_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_HW2_OP_CFG_MASK               0x1
#define PMIC_RG_LDO_VCAMA2_HW2_OP_CFG_SHIFT              3
#define PMIC_RG_LDO_VCAMA2_ON_OP_ADDR                    MT6355_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_ON_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMA2_ON_OP_SHIFT                   8
#define PMIC_RG_LDO_VCAMA2_LP_OP_ADDR                    MT6355_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_LP_OP_MASK                    0x1
#define PMIC_RG_LDO_VCAMA2_LP_OP_SHIFT                   9
#define PMIC_RG_LDO_VCAMA2_OP_CFG_SET_ADDR               MT6355_LDO_VCAMA2_OP_CFG_SET
#define PMIC_RG_LDO_VCAMA2_OP_CFG_SET_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_CFG_SET_SHIFT              0
#define PMIC_RG_LDO_VCAMA2_OP_CFG_CLR_ADDR               MT6355_LDO_VCAMA2_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMA2_OP_CFG_CLR_MASK               0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_CFG_CLR_SHIFT              0
#define PMIC_DA_QI_VCAMA2_MODE_ADDR                      MT6355_LDO_VCAMA2_CON1
#define PMIC_DA_QI_VCAMA2_MODE_MASK                      0x1
#define PMIC_DA_QI_VCAMA2_MODE_SHIFT                     8
#define PMIC_RG_LDO_VCAMA2_STBTD_ADDR                    MT6355_LDO_VCAMA2_CON1
#define PMIC_RG_LDO_VCAMA2_STBTD_MASK                    0x3
#define PMIC_RG_LDO_VCAMA2_STBTD_SHIFT                   9
#define PMIC_DA_QI_VCAMA2_STB_ADDR                       MT6355_LDO_VCAMA2_CON1
#define PMIC_DA_QI_VCAMA2_STB_MASK                       0x1
#define PMIC_DA_QI_VCAMA2_STB_SHIFT                      14
#define PMIC_DA_QI_VCAMA2_EN_ADDR                        MT6355_LDO_VCAMA2_CON1
#define PMIC_DA_QI_VCAMA2_EN_MASK                        0x1
#define PMIC_DA_QI_VCAMA2_EN_SHIFT                       15
#define PMIC_RG_LDO_VCAMA2_OCFB_EN_ADDR                  MT6355_LDO_VCAMA2_CON2
#define PMIC_RG_LDO_VCAMA2_OCFB_EN_MASK                  0x1
#define PMIC_RG_LDO_VCAMA2_OCFB_EN_SHIFT                 9
#define PMIC_DA_QI_VCAMA2_OCFB_EN_ADDR                   MT6355_LDO_VCAMA2_CON2
#define PMIC_DA_QI_VCAMA2_OCFB_EN_MASK                   0x1
#define PMIC_DA_QI_VCAMA2_OCFB_EN_SHIFT                  10
#define PMIC_RG_LDO_VCAMA2_DUMMY_LOAD_ADDR               MT6355_LDO_VCAMA2_CON3
#define PMIC_RG_LDO_VCAMA2_DUMMY_LOAD_MASK               0x3
#define PMIC_RG_LDO_VCAMA2_DUMMY_LOAD_SHIFT              5
#define PMIC_DA_QI_VCAMA2_DUMMY_LOAD_ADDR                MT6355_LDO_VCAMA2_CON3
#define PMIC_DA_QI_VCAMA2_DUMMY_LOAD_MASK                0x3
#define PMIC_DA_QI_VCAMA2_DUMMY_LOAD_SHIFT               14
#define PMIC_LDO_DEGTD_SEL_ADDR                          MT6355_LDO_OCFB0
#define PMIC_LDO_DEGTD_SEL_MASK                          0x3
#define PMIC_LDO_DEGTD_SEL_SHIFT                         14
#define PMIC_RG_VRTC_EN_ADDR                             MT6355_VRTC_CON0
#define PMIC_RG_VRTC_EN_MASK                             0x1
#define PMIC_RG_VRTC_EN_SHIFT                            1
#define PMIC_DA_QI_VRTC_EN_ADDR                          MT6355_VRTC_CON0
#define PMIC_DA_QI_VRTC_EN_MASK                          0x1
#define PMIC_DA_QI_VRTC_EN_SHIFT                         15
#define PMIC_RG_LDO_RSV1_ADDR                            MT6355_LDO_RSV_CON0
#define PMIC_RG_LDO_RSV1_MASK                            0x3FF
#define PMIC_RG_LDO_RSV1_SHIFT                           0
#define PMIC_RG_LDO_RSV0_ADDR                            MT6355_LDO_RSV_CON0
#define PMIC_RG_LDO_RSV0_MASK                            0x3F
#define PMIC_RG_LDO_RSV0_SHIFT                           10
#define PMIC_RG_LDO_RSV2_ADDR                            MT6355_LDO_RSV_CON1
#define PMIC_RG_LDO_RSV2_MASK                            0xFFFF
#define PMIC_RG_LDO_RSV2_SHIFT                           0
#define PMIC_RG_LDO_VSRAM_PROC_EN_ADDR                   MT6355_LDO_VSRAM_PROC_CON0
#define PMIC_RG_LDO_VSRAM_PROC_EN_MASK                   0x1
#define PMIC_RG_LDO_VSRAM_PROC_EN_SHIFT                  0
#define PMIC_RG_LDO_VSRAM_PROC_LP_ADDR                   MT6355_LDO_VSRAM_PROC_CON0
#define PMIC_RG_LDO_VSRAM_PROC_LP_MASK                   0x1
#define PMIC_RG_LDO_VSRAM_PROC_LP_SHIFT                  1
#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_ADDR                MT6355_LDO_VSRAM_PROC_CON1
#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_MASK                0x7F
#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SHIFT               0
#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP_ADDR          MT6355_LDO_VSRAM_PROC_CON2
#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP_SHIFT         0
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE_ADDR          MT6355_LDO_VSRAM_PROC_CFG0
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE_SHIFT         0
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN_ADDR            MT6355_LDO_VSRAM_PROC_CFG0
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN_SHIFT           7
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE_ADDR          MT6355_LDO_VSRAM_PROC_CFG0
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE_SHIFT         8
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN_ADDR            MT6355_LDO_VSRAM_PROC_CFG0
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN_SHIFT           15
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD_ADDR         MT6355_LDO_VSRAM_PROC_CFG1
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD_MASK         0x3
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD_SHIFT        0
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL_ADDR       MT6355_LDO_VSRAM_PROC_CFG1
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL_MASK       0x3
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL_SHIFT      4
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE_ADDR       MT6355_LDO_VSRAM_PROC_CFG1
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE_MASK       0x1
#define PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE_SHIFT      6
#define PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN_ADDR             MT6355_LDO_VSRAM_PROC_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN_SHIFT            0
#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN_ADDR            MT6355_LDO_VSRAM_PROC_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN_SHIFT           1
#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN_ADDR            MT6355_LDO_VSRAM_PROC_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN_SHIFT           2
#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN_ADDR            MT6355_LDO_VSRAM_PROC_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN_SHIFT           3
#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET_ADDR            MT6355_LDO_VSRAM_PROC_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET_MASK            0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET_SHIFT           0
#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR_ADDR            MT6355_LDO_VSRAM_PROC_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR_MASK            0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR_SHIFT           0
#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG_ADDR           MT6355_LDO_VSRAM_PROC_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG_MASK           0x1
#define PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG_SHIFT          1
#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG_ADDR           MT6355_LDO_VSRAM_PROC_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG_MASK           0x1
#define PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG_SHIFT          2
#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG_ADDR           MT6355_LDO_VSRAM_PROC_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG_MASK           0x1
#define PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG_SHIFT          3
#define PMIC_RG_LDO_VSRAM_PROC_ON_OP_ADDR                MT6355_LDO_VSRAM_PROC_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC_ON_OP_MASK                0x1
#define PMIC_RG_LDO_VSRAM_PROC_ON_OP_SHIFT               8
#define PMIC_RG_LDO_VSRAM_PROC_LP_OP_ADDR                MT6355_LDO_VSRAM_PROC_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC_LP_OP_MASK                0x1
#define PMIC_RG_LDO_VSRAM_PROC_LP_OP_SHIFT               9
#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET_ADDR           MT6355_LDO_VSRAM_PROC_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET_MASK           0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET_SHIFT          0
#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR_ADDR           MT6355_LDO_VSRAM_PROC_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR_MASK           0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR_SHIFT          0
#define PMIC_DA_QI_VSRAM_PROC_MODE_ADDR                  MT6355_LDO_VSRAM_PROC_CON3
#define PMIC_DA_QI_VSRAM_PROC_MODE_MASK                  0x1
#define PMIC_DA_QI_VSRAM_PROC_MODE_SHIFT                 8
#define PMIC_RG_LDO_VSRAM_PROC_STBTD_ADDR                MT6355_LDO_VSRAM_PROC_CON3
#define PMIC_RG_LDO_VSRAM_PROC_STBTD_MASK                0x3
#define PMIC_RG_LDO_VSRAM_PROC_STBTD_SHIFT               9
#define PMIC_RG_LDO_VSRAM_PROC_OCFB_EN_ADDR              MT6355_LDO_VSRAM_PROC_CON4
#define PMIC_RG_LDO_VSRAM_PROC_OCFB_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_PROC_OCFB_EN_SHIFT             9
#define PMIC_DA_QI_VSRAM_PROC_OCFB_EN_ADDR               MT6355_LDO_VSRAM_PROC_CON4
#define PMIC_DA_QI_VSRAM_PROC_OCFB_EN_MASK               0x1
#define PMIC_DA_QI_VSRAM_PROC_OCFB_EN_SHIFT              10
#define PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD_ADDR           MT6355_LDO_VSRAM_PROC_CON5
#define PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD_MASK           0x3
#define PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD_SHIFT          5
#define PMIC_DA_QI_VSRAM_PROC_DUMMY_LOAD_ADDR            MT6355_LDO_VSRAM_PROC_CON5
#define PMIC_DA_QI_VSRAM_PROC_DUMMY_LOAD_MASK            0x3
#define PMIC_DA_QI_VSRAM_PROC_DUMMY_LOAD_SHIFT           14
#define PMIC_DA_QI_VSRAM_PROC_VOSEL_GRAY_ADDR            MT6355_LDO_VSRAM_PROC_DBG0
#define PMIC_DA_QI_VSRAM_PROC_VOSEL_GRAY_MASK            0x7F
#define PMIC_DA_QI_VSRAM_PROC_VOSEL_GRAY_SHIFT           0
#define PMIC_DA_QI_VSRAM_PROC_VOSEL_ADDR                 MT6355_LDO_VSRAM_PROC_DBG0
#define PMIC_DA_QI_VSRAM_PROC_VOSEL_MASK                 0x7F
#define PMIC_DA_QI_VSRAM_PROC_VOSEL_SHIFT                8
#define PMIC_DA_QI_VSRAM_PROC_EN_ADDR                    MT6355_LDO_VSRAM_PROC_DBG1
#define PMIC_DA_QI_VSRAM_PROC_EN_MASK                    0x1
#define PMIC_DA_QI_VSRAM_PROC_EN_SHIFT                   0
#define PMIC_DA_QI_VSRAM_PROC_STB_ADDR                   MT6355_LDO_VSRAM_PROC_DBG1
#define PMIC_DA_QI_VSRAM_PROC_STB_MASK                   0x1
#define PMIC_DA_QI_VSRAM_PROC_STB_SHIFT                  1
#define PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL_ADDR            MT6355_LDO_VSRAM_PROC_DBG1
#define PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL_MASK            0x1
#define PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL_SHIFT           2
#define PMIC_DA_NI_VSRAM_PROC_R2R_PDN_ADDR               MT6355_LDO_VSRAM_PROC_DBG1
#define PMIC_DA_NI_VSRAM_PROC_R2R_PDN_MASK               0x1
#define PMIC_DA_NI_VSRAM_PROC_R2R_PDN_SHIFT              3
#define PMIC_DA_NI_VSRAM_PROC_TRACK_NDIS_EN_ADDR         MT6355_LDO_VSRAM_PROC_DBG1
#define PMIC_DA_NI_VSRAM_PROC_TRACK_NDIS_EN_MASK         0x1
#define PMIC_DA_NI_VSRAM_PROC_TRACK_NDIS_EN_SHIFT        4
#define PMIC_RG_LDO_VSRAM_CORE_EN_ADDR                   MT6355_LDO_VSRAM_CORE_CON0
#define PMIC_RG_LDO_VSRAM_CORE_EN_MASK                   0x1
#define PMIC_RG_LDO_VSRAM_CORE_EN_SHIFT                  0
#define PMIC_RG_LDO_VSRAM_CORE_LP_ADDR                   MT6355_LDO_VSRAM_CORE_CON0
#define PMIC_RG_LDO_VSRAM_CORE_LP_MASK                   0x1
#define PMIC_RG_LDO_VSRAM_CORE_LP_SHIFT                  1
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ADDR                MT6355_LDO_VSRAM_CORE_CON1
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_MASK                0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SHIFT               0
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_ADDR          MT6355_LDO_VSRAM_CORE_CON2
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_SHIFT         0
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_FRATE_ADDR          MT6355_LDO_VSRAM_CORE_CFG0
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_FRATE_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_FRATE_SHIFT         0
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_FEN_ADDR            MT6355_LDO_VSRAM_CORE_CFG0
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_FEN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_FEN_SHIFT           7
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_RRATE_ADDR          MT6355_LDO_VSRAM_CORE_CFG0
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_RRATE_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_RRATE_SHIFT         8
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_REN_ADDR            MT6355_LDO_VSRAM_CORE_CFG0
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_REN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_CORE_SFCHG_REN_SHIFT           15
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_TD_ADDR         MT6355_LDO_VSRAM_CORE_CFG1
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_TD_MASK         0x3
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_TD_SHIFT        0
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_CTRL_ADDR       MT6355_LDO_VSRAM_CORE_CFG1
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_CTRL_MASK       0x3
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_CTRL_SHIFT      4
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_ONCE_ADDR       MT6355_LDO_VSRAM_CORE_CFG1
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_ONCE_MASK       0x1
#define PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_ONCE_SHIFT      6
#define PMIC_RG_LDO_VSRAM_CORE_SW_OP_EN_ADDR             MT6355_LDO_VSRAM_CORE_OP_EN
#define PMIC_RG_LDO_VSRAM_CORE_SW_OP_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_CORE_SW_OP_EN_SHIFT            0
#define PMIC_RG_LDO_VSRAM_CORE_HW0_OP_EN_ADDR            MT6355_LDO_VSRAM_CORE_OP_EN
#define PMIC_RG_LDO_VSRAM_CORE_HW0_OP_EN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_CORE_HW0_OP_EN_SHIFT           1
#define PMIC_RG_LDO_VSRAM_CORE_HW1_OP_EN_ADDR            MT6355_LDO_VSRAM_CORE_OP_EN
#define PMIC_RG_LDO_VSRAM_CORE_HW1_OP_EN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_CORE_HW1_OP_EN_SHIFT           2
#define PMIC_RG_LDO_VSRAM_CORE_HW2_OP_EN_ADDR            MT6355_LDO_VSRAM_CORE_OP_EN
#define PMIC_RG_LDO_VSRAM_CORE_HW2_OP_EN_MASK            0x1
#define PMIC_RG_LDO_VSRAM_CORE_HW2_OP_EN_SHIFT           3
#define PMIC_RG_LDO_VSRAM_CORE_OP_EN_SET_ADDR            MT6355_LDO_VSRAM_CORE_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_CORE_OP_EN_SET_MASK            0xFFFF
#define PMIC_RG_LDO_VSRAM_CORE_OP_EN_SET_SHIFT           0
#define PMIC_RG_LDO_VSRAM_CORE_OP_EN_CLR_ADDR            MT6355_LDO_VSRAM_CORE_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_CORE_OP_EN_CLR_MASK            0xFFFF
#define PMIC_RG_LDO_VSRAM_CORE_OP_EN_CLR_SHIFT           0
#define PMIC_RG_LDO_VSRAM_CORE_HW0_OP_CFG_ADDR           MT6355_LDO_VSRAM_CORE_OP_CFG
#define PMIC_RG_LDO_VSRAM_CORE_HW0_OP_CFG_MASK           0x1
#define PMIC_RG_LDO_VSRAM_CORE_HW0_OP_CFG_SHIFT          1
#define PMIC_RG_LDO_VSRAM_CORE_HW1_OP_CFG_ADDR           MT6355_LDO_VSRAM_CORE_OP_CFG
#define PMIC_RG_LDO_VSRAM_CORE_HW1_OP_CFG_MASK           0x1
#define PMIC_RG_LDO_VSRAM_CORE_HW1_OP_CFG_SHIFT          2
#define PMIC_RG_LDO_VSRAM_CORE_HW2_OP_CFG_ADDR           MT6355_LDO_VSRAM_CORE_OP_CFG
#define PMIC_RG_LDO_VSRAM_CORE_HW2_OP_CFG_MASK           0x1
#define PMIC_RG_LDO_VSRAM_CORE_HW2_OP_CFG_SHIFT          3
#define PMIC_RG_LDO_VSRAM_CORE_ON_OP_ADDR                MT6355_LDO_VSRAM_CORE_OP_CFG
#define PMIC_RG_LDO_VSRAM_CORE_ON_OP_MASK                0x1
#define PMIC_RG_LDO_VSRAM_CORE_ON_OP_SHIFT               8
#define PMIC_RG_LDO_VSRAM_CORE_LP_OP_ADDR                MT6355_LDO_VSRAM_CORE_OP_CFG
#define PMIC_RG_LDO_VSRAM_CORE_LP_OP_MASK                0x1
#define PMIC_RG_LDO_VSRAM_CORE_LP_OP_SHIFT               9
#define PMIC_RG_LDO_VSRAM_CORE_OP_CFG_SET_ADDR           MT6355_LDO_VSRAM_CORE_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_CORE_OP_CFG_SET_MASK           0xFFFF
#define PMIC_RG_LDO_VSRAM_CORE_OP_CFG_SET_SHIFT          0
#define PMIC_RG_LDO_VSRAM_CORE_OP_CFG_CLR_ADDR           MT6355_LDO_VSRAM_CORE_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_CORE_OP_CFG_CLR_MASK           0xFFFF
#define PMIC_RG_LDO_VSRAM_CORE_OP_CFG_CLR_SHIFT          0
#define PMIC_DA_QI_VSRAM_CORE_MODE_ADDR                  MT6355_LDO_VSRAM_CORE_CON3
#define PMIC_DA_QI_VSRAM_CORE_MODE_MASK                  0x1
#define PMIC_DA_QI_VSRAM_CORE_MODE_SHIFT                 8
#define PMIC_RG_LDO_VSRAM_CORE_STBTD_ADDR                MT6355_LDO_VSRAM_CORE_CON3
#define PMIC_RG_LDO_VSRAM_CORE_STBTD_MASK                0x3
#define PMIC_RG_LDO_VSRAM_CORE_STBTD_SHIFT               9
#define PMIC_RG_LDO_VSRAM_CORE_OCFB_EN_ADDR              MT6355_LDO_VSRAM_CORE_CON4
#define PMIC_RG_LDO_VSRAM_CORE_OCFB_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_CORE_OCFB_EN_SHIFT             9
#define PMIC_DA_QI_VSRAM_CORE_OCFB_EN_ADDR               MT6355_LDO_VSRAM_CORE_CON4
#define PMIC_DA_QI_VSRAM_CORE_OCFB_EN_MASK               0x1
#define PMIC_DA_QI_VSRAM_CORE_OCFB_EN_SHIFT              10
#define PMIC_RG_LDO_VSRAM_CORE_DUMMY_LOAD_ADDR           MT6355_LDO_VSRAM_CORE_CON5
#define PMIC_RG_LDO_VSRAM_CORE_DUMMY_LOAD_MASK           0x3
#define PMIC_RG_LDO_VSRAM_CORE_DUMMY_LOAD_SHIFT          5
#define PMIC_DA_QI_VSRAM_CORE_DUMMY_LOAD_ADDR            MT6355_LDO_VSRAM_CORE_CON5
#define PMIC_DA_QI_VSRAM_CORE_DUMMY_LOAD_MASK            0x3
#define PMIC_DA_QI_VSRAM_CORE_DUMMY_LOAD_SHIFT           14
#define PMIC_DA_QI_VSRAM_CORE_VOSEL_GRAY_ADDR            MT6355_LDO_VSRAM_CORE_DBG0
#define PMIC_DA_QI_VSRAM_CORE_VOSEL_GRAY_MASK            0x7F
#define PMIC_DA_QI_VSRAM_CORE_VOSEL_GRAY_SHIFT           0
#define PMIC_DA_QI_VSRAM_CORE_VOSEL_ADDR                 MT6355_LDO_VSRAM_CORE_DBG0
#define PMIC_DA_QI_VSRAM_CORE_VOSEL_MASK                 0x7F
#define PMIC_DA_QI_VSRAM_CORE_VOSEL_SHIFT                8
#define PMIC_DA_QI_VSRAM_CORE_EN_ADDR                    MT6355_LDO_VSRAM_CORE_DBG1
#define PMIC_DA_QI_VSRAM_CORE_EN_MASK                    0x1
#define PMIC_DA_QI_VSRAM_CORE_EN_SHIFT                   0
#define PMIC_DA_QI_VSRAM_CORE_STB_ADDR                   MT6355_LDO_VSRAM_CORE_DBG1
#define PMIC_DA_QI_VSRAM_CORE_STB_MASK                   0x1
#define PMIC_DA_QI_VSRAM_CORE_STB_SHIFT                  1
#define PMIC_DA_NI_VSRAM_CORE_VSLEEP_SEL_ADDR            MT6355_LDO_VSRAM_CORE_DBG1
#define PMIC_DA_NI_VSRAM_CORE_VSLEEP_SEL_MASK            0x1
#define PMIC_DA_NI_VSRAM_CORE_VSLEEP_SEL_SHIFT           2
#define PMIC_DA_NI_VSRAM_CORE_R2R_PDN_ADDR               MT6355_LDO_VSRAM_CORE_DBG1
#define PMIC_DA_NI_VSRAM_CORE_R2R_PDN_MASK               0x1
#define PMIC_DA_NI_VSRAM_CORE_R2R_PDN_SHIFT              3
#define PMIC_DA_NI_VSRAM_CORE_TRACK_NDIS_EN_ADDR         MT6355_LDO_VSRAM_CORE_DBG1
#define PMIC_DA_NI_VSRAM_CORE_TRACK_NDIS_EN_MASK         0x1
#define PMIC_DA_NI_VSRAM_CORE_TRACK_NDIS_EN_SHIFT        4
#define PMIC_RG_LDO_VSRAM_GPU_EN_ADDR                    MT6355_LDO_VSRAM_GPU_CON0
#define PMIC_RG_LDO_VSRAM_GPU_EN_MASK                    0x1
#define PMIC_RG_LDO_VSRAM_GPU_EN_SHIFT                   0
#define PMIC_RG_LDO_VSRAM_GPU_LP_ADDR                    MT6355_LDO_VSRAM_GPU_CON0
#define PMIC_RG_LDO_VSRAM_GPU_LP_MASK                    0x1
#define PMIC_RG_LDO_VSRAM_GPU_LP_SHIFT                   1
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_ADDR                 MT6355_LDO_VSRAM_GPU_CON1
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_MASK                 0x7F
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SHIFT                0
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_ADDR           MT6355_LDO_VSRAM_GPU_CON2
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_MASK           0x7F
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_SHIFT          0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE_ADDR           MT6355_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE_MASK           0x7F
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE_SHIFT          0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN_ADDR             MT6355_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN_SHIFT            7
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE_ADDR           MT6355_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE_MASK           0x7F
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE_SHIFT          8
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN_ADDR             MT6355_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN_SHIFT            15
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD_ADDR          MT6355_LDO_VSRAM_GPU_CFG1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD_MASK          0x3
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD_SHIFT         0
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL_ADDR        MT6355_LDO_VSRAM_GPU_CFG1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL_MASK        0x3
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL_SHIFT       4
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE_ADDR        MT6355_LDO_VSRAM_GPU_CFG1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE_MASK        0x1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE_SHIFT       6
#define PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN_ADDR              MT6355_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN_SHIFT             0
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN_ADDR             MT6355_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN_SHIFT            1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN_ADDR             MT6355_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN_SHIFT            2
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN_ADDR             MT6355_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN_SHIFT            3
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET_ADDR             MT6355_LDO_VSRAM_GPU_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET_MASK             0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET_SHIFT            0
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR_ADDR             MT6355_LDO_VSRAM_GPU_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR_MASK             0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR_SHIFT            0
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG_ADDR            MT6355_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG_MASK            0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG_SHIFT           1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG_ADDR            MT6355_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG_MASK            0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG_SHIFT           2
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG_ADDR            MT6355_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG_MASK            0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG_SHIFT           3
#define PMIC_RG_LDO_VSRAM_GPU_ON_OP_ADDR                 MT6355_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_ON_OP_MASK                 0x1
#define PMIC_RG_LDO_VSRAM_GPU_ON_OP_SHIFT                8
#define PMIC_RG_LDO_VSRAM_GPU_LP_OP_ADDR                 MT6355_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_LP_OP_MASK                 0x1
#define PMIC_RG_LDO_VSRAM_GPU_LP_OP_SHIFT                9
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET_ADDR            MT6355_LDO_VSRAM_GPU_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET_MASK            0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET_SHIFT           0
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR_ADDR            MT6355_LDO_VSRAM_GPU_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR_MASK            0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR_SHIFT           0
#define PMIC_DA_QI_VSRAM_GPU_MODE_ADDR                   MT6355_LDO_VSRAM_GPU_CON3
#define PMIC_DA_QI_VSRAM_GPU_MODE_MASK                   0x1
#define PMIC_DA_QI_VSRAM_GPU_MODE_SHIFT                  8
#define PMIC_RG_LDO_VSRAM_GPU_STBTD_ADDR                 MT6355_LDO_VSRAM_GPU_CON3
#define PMIC_RG_LDO_VSRAM_GPU_STBTD_MASK                 0x3
#define PMIC_RG_LDO_VSRAM_GPU_STBTD_SHIFT                9
#define PMIC_RG_LDO_VSRAM_GPU_OCFB_EN_ADDR               MT6355_LDO_VSRAM_GPU_CON4
#define PMIC_RG_LDO_VSRAM_GPU_OCFB_EN_MASK               0x1
#define PMIC_RG_LDO_VSRAM_GPU_OCFB_EN_SHIFT              9
#define PMIC_DA_QI_VSRAM_GPU_OCFB_EN_ADDR                MT6355_LDO_VSRAM_GPU_CON4
#define PMIC_DA_QI_VSRAM_GPU_OCFB_EN_MASK                0x1
#define PMIC_DA_QI_VSRAM_GPU_OCFB_EN_SHIFT               10
#define PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD_ADDR            MT6355_LDO_VSRAM_GPU_CON5
#define PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD_MASK            0x3
#define PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD_SHIFT           5
#define PMIC_DA_QI_VSRAM_GPU_DUMMY_LOAD_ADDR             MT6355_LDO_VSRAM_GPU_CON5
#define PMIC_DA_QI_VSRAM_GPU_DUMMY_LOAD_MASK             0x3
#define PMIC_DA_QI_VSRAM_GPU_DUMMY_LOAD_SHIFT            14
#define PMIC_DA_QI_VSRAM_GPU_VOSEL_GRAY_ADDR             MT6355_LDO_VSRAM_GPU_DBG0
#define PMIC_DA_QI_VSRAM_GPU_VOSEL_GRAY_MASK             0x7F
#define PMIC_DA_QI_VSRAM_GPU_VOSEL_GRAY_SHIFT            0
#define PMIC_DA_QI_VSRAM_GPU_VOSEL_ADDR                  MT6355_LDO_VSRAM_GPU_DBG0
#define PMIC_DA_QI_VSRAM_GPU_VOSEL_MASK                  0x7F
#define PMIC_DA_QI_VSRAM_GPU_VOSEL_SHIFT                 8
#define PMIC_DA_QI_VSRAM_GPU_EN_ADDR                     MT6355_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_QI_VSRAM_GPU_EN_MASK                     0x1
#define PMIC_DA_QI_VSRAM_GPU_EN_SHIFT                    0
#define PMIC_DA_QI_VSRAM_GPU_STB_ADDR                    MT6355_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_QI_VSRAM_GPU_STB_MASK                    0x1
#define PMIC_DA_QI_VSRAM_GPU_STB_SHIFT                   1
#define PMIC_DA_NI_VSRAM_GPU_VSLEEP_SEL_ADDR             MT6355_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_NI_VSRAM_GPU_VSLEEP_SEL_MASK             0x1
#define PMIC_DA_NI_VSRAM_GPU_VSLEEP_SEL_SHIFT            2
#define PMIC_DA_NI_VSRAM_GPU_R2R_PDN_ADDR                MT6355_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_NI_VSRAM_GPU_R2R_PDN_MASK                0x1
#define PMIC_DA_NI_VSRAM_GPU_R2R_PDN_SHIFT               3
#define PMIC_DA_NI_VSRAM_GPU_TRACK_NDIS_EN_ADDR          MT6355_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_NI_VSRAM_GPU_TRACK_NDIS_EN_MASK          0x1
#define PMIC_DA_NI_VSRAM_GPU_TRACK_NDIS_EN_SHIFT         4
#define PMIC_RG_LDO_VSRAM_MD_EN_ADDR                     MT6355_LDO_VSRAM_MD_CON0
#define PMIC_RG_LDO_VSRAM_MD_EN_MASK                     0x1
#define PMIC_RG_LDO_VSRAM_MD_EN_SHIFT                    0
#define PMIC_RG_LDO_VSRAM_MD_LP_ADDR                     MT6355_LDO_VSRAM_MD_CON0
#define PMIC_RG_LDO_VSRAM_MD_LP_MASK                     0x1
#define PMIC_RG_LDO_VSRAM_MD_LP_SHIFT                    1
#define PMIC_RG_LDO_VSRAM_MD_VOSEL_ADDR                  MT6355_LDO_VSRAM_MD_CON1
#define PMIC_RG_LDO_VSRAM_MD_VOSEL_MASK                  0x7F
#define PMIC_RG_LDO_VSRAM_MD_VOSEL_SHIFT                 0
#define PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR            MT6355_LDO_VSRAM_MD_CON2
#define PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_MASK            0x7F
#define PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP_SHIFT           0
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_FRATE_ADDR            MT6355_LDO_VSRAM_MD_CFG0
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_FRATE_MASK            0x7F
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_FRATE_SHIFT           0
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_FEN_ADDR              MT6355_LDO_VSRAM_MD_CFG0
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_FEN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_FEN_SHIFT             7
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_RRATE_ADDR            MT6355_LDO_VSRAM_MD_CFG0
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_RRATE_MASK            0x7F
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_RRATE_SHIFT           8
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_REN_ADDR              MT6355_LDO_VSRAM_MD_CFG0
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_REN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_MD_SFCHG_REN_SHIFT             15
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_TD_ADDR           MT6355_LDO_VSRAM_MD_CFG1
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_TD_MASK           0x3
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_TD_SHIFT          0
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_CTRL_ADDR         MT6355_LDO_VSRAM_MD_CFG1
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_CTRL_MASK         0x3
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_CTRL_SHIFT        4
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_ONCE_ADDR         MT6355_LDO_VSRAM_MD_CFG1
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_ONCE_MASK         0x1
#define PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_ONCE_SHIFT        6
#define PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR               MT6355_LDO_VSRAM_MD_OP_EN
#define PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_MASK               0x1
#define PMIC_RG_LDO_VSRAM_MD_SW_OP_EN_SHIFT              0
#define PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR              MT6355_LDO_VSRAM_MD_OP_EN
#define PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN_SHIFT             1
#define PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR              MT6355_LDO_VSRAM_MD_OP_EN
#define PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN_SHIFT             2
#define PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR              MT6355_LDO_VSRAM_MD_OP_EN
#define PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN_SHIFT             3
#define PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_ADDR              MT6355_LDO_VSRAM_MD_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_MASK              0xFFFF
#define PMIC_RG_LDO_VSRAM_MD_OP_EN_SET_SHIFT             0
#define PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_ADDR              MT6355_LDO_VSRAM_MD_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_MASK              0xFFFF
#define PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR_SHIFT             0
#define PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR             MT6355_LDO_VSRAM_MD_OP_CFG
#define PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_MASK             0x1
#define PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG_SHIFT            1
#define PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR             MT6355_LDO_VSRAM_MD_OP_CFG
#define PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_MASK             0x1
#define PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG_SHIFT            2
#define PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR             MT6355_LDO_VSRAM_MD_OP_CFG
#define PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_MASK             0x1
#define PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG_SHIFT            3
#define PMIC_RG_LDO_VSRAM_MD_ON_OP_ADDR                  MT6355_LDO_VSRAM_MD_OP_CFG
#define PMIC_RG_LDO_VSRAM_MD_ON_OP_MASK                  0x1
#define PMIC_RG_LDO_VSRAM_MD_ON_OP_SHIFT                 8
#define PMIC_RG_LDO_VSRAM_MD_LP_OP_ADDR                  MT6355_LDO_VSRAM_MD_OP_CFG
#define PMIC_RG_LDO_VSRAM_MD_LP_OP_MASK                  0x1
#define PMIC_RG_LDO_VSRAM_MD_LP_OP_SHIFT                 9
#define PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_ADDR             MT6355_LDO_VSRAM_MD_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_MASK             0xFFFF
#define PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET_SHIFT            0
#define PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_ADDR             MT6355_LDO_VSRAM_MD_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_MASK             0xFFFF
#define PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR_SHIFT            0
#define PMIC_DA_QI_VSRAM_MD_MODE_ADDR                    MT6355_LDO_VSRAM_MD_CON3
#define PMIC_DA_QI_VSRAM_MD_MODE_MASK                    0x1
#define PMIC_DA_QI_VSRAM_MD_MODE_SHIFT                   8
#define PMIC_RG_LDO_VSRAM_MD_STBTD_ADDR                  MT6355_LDO_VSRAM_MD_CON3
#define PMIC_RG_LDO_VSRAM_MD_STBTD_MASK                  0x3
#define PMIC_RG_LDO_VSRAM_MD_STBTD_SHIFT                 9
#define PMIC_RG_LDO_VSRAM_MD_OCFB_EN_ADDR                MT6355_LDO_VSRAM_MD_CON4
#define PMIC_RG_LDO_VSRAM_MD_OCFB_EN_MASK                0x1
#define PMIC_RG_LDO_VSRAM_MD_OCFB_EN_SHIFT               9
#define PMIC_DA_QI_VSRAM_MD_OCFB_EN_ADDR                 MT6355_LDO_VSRAM_MD_CON4
#define PMIC_DA_QI_VSRAM_MD_OCFB_EN_MASK                 0x1
#define PMIC_DA_QI_VSRAM_MD_OCFB_EN_SHIFT                10
#define PMIC_RG_LDO_VSRAM_MD_DUMMY_LOAD_ADDR             MT6355_LDO_VSRAM_MD_CON5
#define PMIC_RG_LDO_VSRAM_MD_DUMMY_LOAD_MASK             0x3
#define PMIC_RG_LDO_VSRAM_MD_DUMMY_LOAD_SHIFT            5
#define PMIC_DA_QI_VSRAM_MD_DUMMY_LOAD_ADDR              MT6355_LDO_VSRAM_MD_CON5
#define PMIC_DA_QI_VSRAM_MD_DUMMY_LOAD_MASK              0x3
#define PMIC_DA_QI_VSRAM_MD_DUMMY_LOAD_SHIFT             14
#define PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_ADDR              MT6355_LDO_VSRAM_MD_DBG0
#define PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_MASK              0x7F
#define PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY_SHIFT             0
#define PMIC_DA_QI_VSRAM_MD_VOSEL_ADDR                   MT6355_LDO_VSRAM_MD_DBG0
#define PMIC_DA_QI_VSRAM_MD_VOSEL_MASK                   0x7F
#define PMIC_DA_QI_VSRAM_MD_VOSEL_SHIFT                  8
#define PMIC_DA_QI_VSRAM_MD_EN_ADDR                      MT6355_LDO_VSRAM_MD_DBG1
#define PMIC_DA_QI_VSRAM_MD_EN_MASK                      0x1
#define PMIC_DA_QI_VSRAM_MD_EN_SHIFT                     0
#define PMIC_DA_QI_VSRAM_MD_STB_ADDR                     MT6355_LDO_VSRAM_MD_DBG1
#define PMIC_DA_QI_VSRAM_MD_STB_MASK                     0x1
#define PMIC_DA_QI_VSRAM_MD_STB_SHIFT                    1
#define PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_ADDR              MT6355_LDO_VSRAM_MD_DBG1
#define PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_MASK              0x1
#define PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL_SHIFT             2
#define PMIC_DA_NI_VSRAM_MD_R2R_PDN_ADDR                 MT6355_LDO_VSRAM_MD_DBG1
#define PMIC_DA_NI_VSRAM_MD_R2R_PDN_MASK                 0x1
#define PMIC_DA_NI_VSRAM_MD_R2R_PDN_SHIFT                3
#define PMIC_DA_NI_VSRAM_MD_TRACK_NDIS_EN_ADDR           MT6355_LDO_VSRAM_MD_DBG1
#define PMIC_DA_NI_VSRAM_MD_TRACK_NDIS_EN_MASK           0x1
#define PMIC_DA_NI_VSRAM_MD_TRACK_NDIS_EN_SHIFT          4
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_SLEEP_CTRL_ADDR     MT6355_LDO_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_SLEEP_CTRL_MASK     0x1
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_SLEEP_CTRL_SHIFT    0
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_ON_CTRL_ADDR        MT6355_LDO_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_ON_CTRL_MASK        0x1
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_ON_CTRL_SHIFT       1
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_VBUCK_ON_CTRL_ADDR  MT6355_LDO_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_VBUCK_ON_CTRL_MASK  0x1
#define PMIC_RG_LDO_VSRAM_CORE_TRACK_VBUCK_ON_CTRL_SHIFT 2
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_DELTA_ADDR          MT6355_LDO_TRACKING_CON1
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_DELTA_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_DELTA_SHIFT         0
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_OFFSET_ADDR         MT6355_LDO_TRACKING_CON1
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_OFFSET_MASK         0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_OFFSET_SHIFT        8
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_LB_ADDR          MT6355_LDO_TRACKING_CON2
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_LB_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_LB_SHIFT         0
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_HB_ADDR          MT6355_LDO_TRACKING_CON2
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_HB_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_HB_SHIFT         8
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_LB_ADDR       MT6355_LDO_TRACKING_CON3
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_LB_MASK       0x7F
#define PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_LB_SHIFT      0
#define PMIC_RG_LDO_DCM_MODE_ADDR                        MT6355_LDO_DCM
#define PMIC_RG_LDO_DCM_MODE_MASK                        0x1
#define PMIC_RG_LDO_DCM_MODE_SHIFT                       0
#define PMIC_RG_LDO_VIO28_CK_SW_MODE_ADDR                MT6355_LDO_VIO28_CG0
#define PMIC_RG_LDO_VIO28_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VIO28_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VIO28_CK_SW_EN_ADDR                  MT6355_LDO_VIO28_CG0
#define PMIC_RG_LDO_VIO28_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VIO28_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VIO28_OSC_SEL_DIS_ADDR               MT6355_LDO_VIO28_CG0
#define PMIC_RG_LDO_VIO28_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VIO28_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VIO18_CK_SW_MODE_ADDR                MT6355_LDO_VIO18_CG0
#define PMIC_RG_LDO_VIO18_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VIO18_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VIO18_CK_SW_EN_ADDR                  MT6355_LDO_VIO18_CG0
#define PMIC_RG_LDO_VIO18_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VIO18_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VIO18_OSC_SEL_DIS_ADDR               MT6355_LDO_VIO18_CG0
#define PMIC_RG_LDO_VIO18_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VIO18_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VUFS18_CK_SW_MODE_ADDR               MT6355_LDO_VUFS18_CG0
#define PMIC_RG_LDO_VUFS18_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VUFS18_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VUFS18_CK_SW_EN_ADDR                 MT6355_LDO_VUFS18_CG0
#define PMIC_RG_LDO_VUFS18_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VUFS18_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VUFS18_OSC_SEL_DIS_ADDR              MT6355_LDO_VUFS18_CG0
#define PMIC_RG_LDO_VUFS18_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VUFS18_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VA10_CK_SW_MODE_ADDR                 MT6355_LDO_VA10_CG0
#define PMIC_RG_LDO_VA10_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_LDO_VA10_CK_SW_MODE_SHIFT                0
#define PMIC_RG_LDO_VA10_CK_SW_EN_ADDR                   MT6355_LDO_VA10_CG0
#define PMIC_RG_LDO_VA10_CK_SW_EN_MASK                   0x1
#define PMIC_RG_LDO_VA10_CK_SW_EN_SHIFT                  1
#define PMIC_RG_LDO_VA10_OSC_SEL_DIS_ADDR                MT6355_LDO_VA10_CG0
#define PMIC_RG_LDO_VA10_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_LDO_VA10_OSC_SEL_DIS_SHIFT               2
#define PMIC_RG_LDO_VA12_CK_SW_MODE_ADDR                 MT6355_LDO_VA12_CG0
#define PMIC_RG_LDO_VA12_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_LDO_VA12_CK_SW_MODE_SHIFT                0
#define PMIC_RG_LDO_VA12_CK_SW_EN_ADDR                   MT6355_LDO_VA12_CG0
#define PMIC_RG_LDO_VA12_CK_SW_EN_MASK                   0x1
#define PMIC_RG_LDO_VA12_CK_SW_EN_SHIFT                  1
#define PMIC_RG_LDO_VA12_OSC_SEL_DIS_ADDR                MT6355_LDO_VA12_CG0
#define PMIC_RG_LDO_VA12_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_LDO_VA12_OSC_SEL_DIS_SHIFT               2
#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE_ADDR           MT6355_LDO_VSRAM_PROC_CG0
#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE_MASK           0x1
#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE_SHIFT          0
#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_EN_ADDR             MT6355_LDO_VSRAM_PROC_CG0
#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_PROC_CK_SW_EN_SHIFT            1
#define PMIC_RG_LDO_VSRAM_PROC_OSC_SEL_DIS_ADDR          MT6355_LDO_VSRAM_PROC_CG0
#define PMIC_RG_LDO_VSRAM_PROC_OSC_SEL_DIS_MASK          0x1
#define PMIC_RG_LDO_VSRAM_PROC_OSC_SEL_DIS_SHIFT         2
#define PMIC_RG_LDO_VSRAM_CORE_CK_SW_MODE_ADDR           MT6355_LDO_VSRAM_CORE_CG0
#define PMIC_RG_LDO_VSRAM_CORE_CK_SW_MODE_MASK           0x1
#define PMIC_RG_LDO_VSRAM_CORE_CK_SW_MODE_SHIFT          0
#define PMIC_RG_LDO_VSRAM_CORE_CK_SW_EN_ADDR             MT6355_LDO_VSRAM_CORE_CG0
#define PMIC_RG_LDO_VSRAM_CORE_CK_SW_EN_MASK             0x1
#define PMIC_RG_LDO_VSRAM_CORE_CK_SW_EN_SHIFT            1
#define PMIC_RG_LDO_VSRAM_CORE_OSC_SEL_DIS_ADDR          MT6355_LDO_VSRAM_CORE_CG0
#define PMIC_RG_LDO_VSRAM_CORE_OSC_SEL_DIS_MASK          0x1
#define PMIC_RG_LDO_VSRAM_CORE_OSC_SEL_DIS_SHIFT         2
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE_ADDR            MT6355_LDO_VSRAM_GPU_CG0
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE_MASK            0x1
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE_SHIFT           0
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_EN_ADDR              MT6355_LDO_VSRAM_GPU_CG0
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_EN_MASK              0x1
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_EN_SHIFT             1
#define PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS_ADDR           MT6355_LDO_VSRAM_GPU_CG0
#define PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS_MASK           0x1
#define PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS_SHIFT          2
#define PMIC_RG_LDO_VSRAM_MD_CK_SW_MODE_ADDR             MT6355_LDO_VSRAM_MD_CG0
#define PMIC_RG_LDO_VSRAM_MD_CK_SW_MODE_MASK             0x1
#define PMIC_RG_LDO_VSRAM_MD_CK_SW_MODE_SHIFT            0
#define PMIC_RG_LDO_VSRAM_MD_CK_SW_EN_ADDR               MT6355_LDO_VSRAM_MD_CG0
#define PMIC_RG_LDO_VSRAM_MD_CK_SW_EN_MASK               0x1
#define PMIC_RG_LDO_VSRAM_MD_CK_SW_EN_SHIFT              1
#define PMIC_RG_LDO_VSRAM_MD_OSC_SEL_DIS_ADDR            MT6355_LDO_VSRAM_MD_CG0
#define PMIC_RG_LDO_VSRAM_MD_OSC_SEL_DIS_MASK            0x1
#define PMIC_RG_LDO_VSRAM_MD_OSC_SEL_DIS_SHIFT           2
#define PMIC_RG_LDO_VA18_CK_SW_MODE_ADDR                 MT6355_LDO_VA18_CG0
#define PMIC_RG_LDO_VA18_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_LDO_VA18_CK_SW_MODE_SHIFT                0
#define PMIC_RG_LDO_VA18_CK_SW_EN_ADDR                   MT6355_LDO_VA18_CG0
#define PMIC_RG_LDO_VA18_CK_SW_EN_MASK                   0x1
#define PMIC_RG_LDO_VA18_CK_SW_EN_SHIFT                  1
#define PMIC_RG_LDO_VA18_OSC_SEL_DIS_ADDR                MT6355_LDO_VA18_CG0
#define PMIC_RG_LDO_VA18_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_LDO_VA18_OSC_SEL_DIS_SHIFT               2
#define PMIC_RG_LDO_VUSB33_CK_SW_MODE_ADDR               MT6355_LDO_VUSB33_CG0
#define PMIC_RG_LDO_VUSB33_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VUSB33_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VUSB33_CK_SW_EN_ADDR                 MT6355_LDO_VUSB33_CG0
#define PMIC_RG_LDO_VUSB33_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VUSB33_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VUSB33_OSC_SEL_DIS_ADDR              MT6355_LDO_VUSB33_CG0
#define PMIC_RG_LDO_VUSB33_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VUSB33_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VEMC_CK_SW_MODE_ADDR                 MT6355_LDO_VEMC_CG0
#define PMIC_RG_LDO_VEMC_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_LDO_VEMC_CK_SW_MODE_SHIFT                0
#define PMIC_RG_LDO_VEMC_CK_SW_EN_ADDR                   MT6355_LDO_VEMC_CG0
#define PMIC_RG_LDO_VEMC_CK_SW_EN_MASK                   0x1
#define PMIC_RG_LDO_VEMC_CK_SW_EN_SHIFT                  1
#define PMIC_RG_LDO_VEMC_OSC_SEL_DIS_ADDR                MT6355_LDO_VEMC_CG0
#define PMIC_RG_LDO_VEMC_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_LDO_VEMC_OSC_SEL_DIS_SHIFT               2
#define PMIC_RG_LDO_VXO22_CK_SW_MODE_ADDR                MT6355_LDO_VXO22_CG0
#define PMIC_RG_LDO_VXO22_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VXO22_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VXO22_CK_SW_EN_ADDR                  MT6355_LDO_VXO22_CG0
#define PMIC_RG_LDO_VXO22_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VXO22_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VXO22_OSC_SEL_DIS_ADDR               MT6355_LDO_VXO22_CG0
#define PMIC_RG_LDO_VXO22_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VXO22_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VXO18_CK_SW_MODE_ADDR                MT6355_LDO_VXO18_CG0
#define PMIC_RG_LDO_VXO18_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VXO18_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VXO18_CK_SW_EN_ADDR                  MT6355_LDO_VXO18_CG0
#define PMIC_RG_LDO_VXO18_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VXO18_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VXO18_OSC_SEL_DIS_ADDR               MT6355_LDO_VXO18_CG0
#define PMIC_RG_LDO_VXO18_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VXO18_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_ADDR                MT6355_LDO_VSIM1_CG0
#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VSIM1_CK_SW_EN_ADDR                  MT6355_LDO_VSIM1_CG0
#define PMIC_RG_LDO_VSIM1_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VSIM1_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VSIM1_OSC_SEL_DIS_ADDR               MT6355_LDO_VSIM1_CG0
#define PMIC_RG_LDO_VSIM1_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VSIM1_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_ADDR                MT6355_LDO_VSIM2_CG0
#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VSIM2_CK_SW_EN_ADDR                  MT6355_LDO_VSIM2_CG0
#define PMIC_RG_LDO_VSIM2_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VSIM2_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VSIM2_OSC_SEL_DIS_ADDR               MT6355_LDO_VSIM2_CG0
#define PMIC_RG_LDO_VSIM2_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VSIM2_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VCAMD1_CK_SW_MODE_ADDR               MT6355_LDO_VCAMD1_CG0
#define PMIC_RG_LDO_VCAMD1_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VCAMD1_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VCAMD1_CK_SW_EN_ADDR                 MT6355_LDO_VCAMD1_CG0
#define PMIC_RG_LDO_VCAMD1_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMD1_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VCAMD1_OSC_SEL_DIS_ADDR              MT6355_LDO_VCAMD1_CG0
#define PMIC_RG_LDO_VCAMD1_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VCAMD1_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VCAMD2_CK_SW_MODE_ADDR               MT6355_LDO_VCAMD2_CG0
#define PMIC_RG_LDO_VCAMD2_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VCAMD2_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VCAMD2_CK_SW_EN_ADDR                 MT6355_LDO_VCAMD2_CG0
#define PMIC_RG_LDO_VCAMD2_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMD2_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VCAMD2_OSC_SEL_DIS_ADDR              MT6355_LDO_VCAMD2_CG0
#define PMIC_RG_LDO_VCAMD2_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VCAMD2_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VCAMIO_CK_SW_MODE_ADDR               MT6355_LDO_VCAMIO_CG0
#define PMIC_RG_LDO_VCAMIO_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VCAMIO_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VCAMIO_CK_SW_EN_ADDR                 MT6355_LDO_VCAMIO_CG0
#define PMIC_RG_LDO_VCAMIO_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMIO_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VCAMIO_OSC_SEL_DIS_ADDR              MT6355_LDO_VCAMIO_CG0
#define PMIC_RG_LDO_VCAMIO_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VCAMIO_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VMIPI_CK_SW_MODE_ADDR                MT6355_LDO_VMIPI_CG0
#define PMIC_RG_LDO_VMIPI_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VMIPI_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VMIPI_CK_SW_EN_ADDR                  MT6355_LDO_VMIPI_CG0
#define PMIC_RG_LDO_VMIPI_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VMIPI_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VMIPI_OSC_SEL_DIS_ADDR               MT6355_LDO_VMIPI_CG0
#define PMIC_RG_LDO_VMIPI_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VMIPI_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VGP_CK_SW_MODE_ADDR                  MT6355_LDO_VGP_CG0
#define PMIC_RG_LDO_VGP_CK_SW_MODE_MASK                  0x1
#define PMIC_RG_LDO_VGP_CK_SW_MODE_SHIFT                 0
#define PMIC_RG_LDO_VGP_CK_SW_EN_ADDR                    MT6355_LDO_VGP_CG0
#define PMIC_RG_LDO_VGP_CK_SW_EN_MASK                    0x1
#define PMIC_RG_LDO_VGP_CK_SW_EN_SHIFT                   1
#define PMIC_RG_LDO_VGP_OSC_SEL_DIS_ADDR                 MT6355_LDO_VGP_CG0
#define PMIC_RG_LDO_VGP_OSC_SEL_DIS_MASK                 0x1
#define PMIC_RG_LDO_VGP_OSC_SEL_DIS_SHIFT                2
#define PMIC_RG_LDO_VCN33_CK_SW_MODE_ADDR                MT6355_LDO_VCN33_CG0
#define PMIC_RG_LDO_VCN33_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VCN33_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VCN33_CK_SW_EN_ADDR                  MT6355_LDO_VCN33_CG0
#define PMIC_RG_LDO_VCN33_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VCN33_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VCN33_OSC_SEL_DIS_ADDR               MT6355_LDO_VCN33_CG0
#define PMIC_RG_LDO_VCN33_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VCN33_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VCN18_CK_SW_MODE_ADDR                MT6355_LDO_VCN18_CG0
#define PMIC_RG_LDO_VCN18_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VCN18_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VCN18_CK_SW_EN_ADDR                  MT6355_LDO_VCN18_CG0
#define PMIC_RG_LDO_VCN18_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VCN18_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VCN18_OSC_SEL_DIS_ADDR               MT6355_LDO_VCN18_CG0
#define PMIC_RG_LDO_VCN18_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VCN18_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VCN28_CK_SW_MODE_ADDR                MT6355_LDO_VCN28_CG0
#define PMIC_RG_LDO_VCN28_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VCN28_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VCN28_CK_SW_EN_ADDR                  MT6355_LDO_VCN28_CG0
#define PMIC_RG_LDO_VCN28_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VCN28_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VCN28_OSC_SEL_DIS_ADDR               MT6355_LDO_VCN28_CG0
#define PMIC_RG_LDO_VCN28_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VCN28_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VGP2_CK_SW_MODE_ADDR                 MT6355_LDO_VGP2_CG0
#define PMIC_RG_LDO_VGP2_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_LDO_VGP2_CK_SW_MODE_SHIFT                0
#define PMIC_RG_LDO_VGP2_CK_SW_EN_ADDR                   MT6355_LDO_VGP2_CG0
#define PMIC_RG_LDO_VGP2_CK_SW_EN_MASK                   0x1
#define PMIC_RG_LDO_VGP2_CK_SW_EN_SHIFT                  1
#define PMIC_RG_LDO_VGP2_OSC_SEL_DIS_ADDR                MT6355_LDO_VGP2_CG0
#define PMIC_RG_LDO_VGP2_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_LDO_VGP2_OSC_SEL_DIS_SHIFT               2
#define PMIC_RG_LDO_VBIF28_CK_SW_MODE_ADDR               MT6355_LDO_VBIF28_CG0
#define PMIC_RG_LDO_VBIF28_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VBIF28_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VBIF28_CK_SW_EN_ADDR                 MT6355_LDO_VBIF28_CG0
#define PMIC_RG_LDO_VBIF28_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VBIF28_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VBIF28_OSC_SEL_DIS_ADDR              MT6355_LDO_VBIF28_CG0
#define PMIC_RG_LDO_VBIF28_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VBIF28_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VFE28_CK_SW_MODE_ADDR                MT6355_LDO_VFE28_CG0
#define PMIC_RG_LDO_VFE28_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VFE28_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VFE28_CK_SW_EN_ADDR                  MT6355_LDO_VFE28_CG0
#define PMIC_RG_LDO_VFE28_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VFE28_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VFE28_OSC_SEL_DIS_ADDR               MT6355_LDO_VFE28_CG0
#define PMIC_RG_LDO_VFE28_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VFE28_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VMCH_CK_SW_MODE_ADDR                 MT6355_LDO_VMCH_CG0
#define PMIC_RG_LDO_VMCH_CK_SW_MODE_MASK                 0x1
#define PMIC_RG_LDO_VMCH_CK_SW_MODE_SHIFT                0
#define PMIC_RG_LDO_VMCH_CK_SW_EN_ADDR                   MT6355_LDO_VMCH_CG0
#define PMIC_RG_LDO_VMCH_CK_SW_EN_MASK                   0x1
#define PMIC_RG_LDO_VMCH_CK_SW_EN_SHIFT                  1
#define PMIC_RG_LDO_VMCH_OSC_SEL_DIS_ADDR                MT6355_LDO_VMCH_CG0
#define PMIC_RG_LDO_VMCH_OSC_SEL_DIS_MASK                0x1
#define PMIC_RG_LDO_VMCH_OSC_SEL_DIS_SHIFT               2
#define PMIC_RG_LDO_VMC_CK_SW_MODE_ADDR                  MT6355_LDO_VMC_CG0
#define PMIC_RG_LDO_VMC_CK_SW_MODE_MASK                  0x1
#define PMIC_RG_LDO_VMC_CK_SW_MODE_SHIFT                 0
#define PMIC_RG_LDO_VMC_CK_SW_EN_ADDR                    MT6355_LDO_VMC_CG0
#define PMIC_RG_LDO_VMC_CK_SW_EN_MASK                    0x1
#define PMIC_RG_LDO_VMC_CK_SW_EN_SHIFT                   1
#define PMIC_RG_LDO_VMC_OSC_SEL_DIS_ADDR                 MT6355_LDO_VMC_CG0
#define PMIC_RG_LDO_VMC_OSC_SEL_DIS_MASK                 0x1
#define PMIC_RG_LDO_VMC_OSC_SEL_DIS_SHIFT                2
#define PMIC_RG_LDO_VRF18_1_CK_SW_MODE_ADDR              MT6355_LDO_VRF18_1_CG0
#define PMIC_RG_LDO_VRF18_1_CK_SW_MODE_MASK              0x1
#define PMIC_RG_LDO_VRF18_1_CK_SW_MODE_SHIFT             0
#define PMIC_RG_LDO_VRF18_1_CK_SW_EN_ADDR                MT6355_LDO_VRF18_1_CG0
#define PMIC_RG_LDO_VRF18_1_CK_SW_EN_MASK                0x1
#define PMIC_RG_LDO_VRF18_1_CK_SW_EN_SHIFT               1
#define PMIC_RG_LDO_VRF18_1_OSC_SEL_DIS_ADDR             MT6355_LDO_VRF18_1_CG0
#define PMIC_RG_LDO_VRF18_1_OSC_SEL_DIS_MASK             0x1
#define PMIC_RG_LDO_VRF18_1_OSC_SEL_DIS_SHIFT            2
#define PMIC_RG_LDO_VRF18_2_CK_SW_MODE_ADDR              MT6355_LDO_VRF18_2_CG0
#define PMIC_RG_LDO_VRF18_2_CK_SW_MODE_MASK              0x1
#define PMIC_RG_LDO_VRF18_2_CK_SW_MODE_SHIFT             0
#define PMIC_RG_LDO_VRF18_2_CK_SW_EN_ADDR                MT6355_LDO_VRF18_2_CG0
#define PMIC_RG_LDO_VRF18_2_CK_SW_EN_MASK                0x1
#define PMIC_RG_LDO_VRF18_2_CK_SW_EN_SHIFT               1
#define PMIC_RG_LDO_VRF18_2_OSC_SEL_DIS_ADDR             MT6355_LDO_VRF18_2_CG0
#define PMIC_RG_LDO_VRF18_2_OSC_SEL_DIS_MASK             0x1
#define PMIC_RG_LDO_VRF18_2_OSC_SEL_DIS_SHIFT            2
#define PMIC_RG_LDO_VTCXO24_CK_SW_MODE_ADDR              MT6355_LDO_VTCXO24_CG0
#define PMIC_RG_LDO_VTCXO24_CK_SW_MODE_MASK              0x1
#define PMIC_RG_LDO_VTCXO24_CK_SW_MODE_SHIFT             0
#define PMIC_RG_LDO_VTCXO24_CK_SW_EN_ADDR                MT6355_LDO_VTCXO24_CG0
#define PMIC_RG_LDO_VTCXO24_CK_SW_EN_MASK                0x1
#define PMIC_RG_LDO_VTCXO24_CK_SW_EN_SHIFT               1
#define PMIC_RG_LDO_VTCXO24_OSC_SEL_DIS_ADDR             MT6355_LDO_VTCXO24_CG0
#define PMIC_RG_LDO_VTCXO24_OSC_SEL_DIS_MASK             0x1
#define PMIC_RG_LDO_VTCXO24_OSC_SEL_DIS_SHIFT            2
#define PMIC_RG_LDO_VLDO28_CK_SW_MODE_ADDR               MT6355_LDO_VLDO28_CG0
#define PMIC_RG_LDO_VLDO28_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VLDO28_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VLDO28_CK_SW_EN_ADDR                 MT6355_LDO_VLDO28_CG0
#define PMIC_RG_LDO_VLDO28_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VLDO28_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VLDO28_OSC_SEL_DIS_ADDR              MT6355_LDO_VLDO28_CG0
#define PMIC_RG_LDO_VLDO28_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VLDO28_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VRF12_CK_SW_MODE_ADDR                MT6355_LDO_VRF12_CG0
#define PMIC_RG_LDO_VRF12_CK_SW_MODE_MASK                0x1
#define PMIC_RG_LDO_VRF12_CK_SW_MODE_SHIFT               0
#define PMIC_RG_LDO_VRF12_CK_SW_EN_ADDR                  MT6355_LDO_VRF12_CG0
#define PMIC_RG_LDO_VRF12_CK_SW_EN_MASK                  0x1
#define PMIC_RG_LDO_VRF12_CK_SW_EN_SHIFT                 1
#define PMIC_RG_LDO_VRF12_OSC_SEL_DIS_ADDR               MT6355_LDO_VRF12_CG0
#define PMIC_RG_LDO_VRF12_OSC_SEL_DIS_MASK               0x1
#define PMIC_RG_LDO_VRF12_OSC_SEL_DIS_SHIFT              2
#define PMIC_RG_LDO_VCAMA1_CK_SW_MODE_ADDR               MT6355_LDO_VCAMA1_CG0
#define PMIC_RG_LDO_VCAMA1_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VCAMA1_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VCAMA1_CK_SW_EN_ADDR                 MT6355_LDO_VCAMA1_CG0
#define PMIC_RG_LDO_VCAMA1_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMA1_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VCAMA1_OSC_SEL_DIS_ADDR              MT6355_LDO_VCAMA1_CG0
#define PMIC_RG_LDO_VCAMA1_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VCAMA1_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VCAMA2_CK_SW_MODE_ADDR               MT6355_LDO_VCAMA2_CG0
#define PMIC_RG_LDO_VCAMA2_CK_SW_MODE_MASK               0x1
#define PMIC_RG_LDO_VCAMA2_CK_SW_MODE_SHIFT              0
#define PMIC_RG_LDO_VCAMA2_CK_SW_EN_ADDR                 MT6355_LDO_VCAMA2_CG0
#define PMIC_RG_LDO_VCAMA2_CK_SW_EN_MASK                 0x1
#define PMIC_RG_LDO_VCAMA2_CK_SW_EN_SHIFT                1
#define PMIC_RG_LDO_VCAMA2_OSC_SEL_DIS_ADDR              MT6355_LDO_VCAMA2_CG0
#define PMIC_RG_LDO_VCAMA2_OSC_SEL_DIS_MASK              0x1
#define PMIC_RG_LDO_VCAMA2_OSC_SEL_DIS_SHIFT             2
#define PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_EN_ADDR       MT6355_LDO_VSRAM_PROC_SP
#define PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_EN_MASK       0x1
#define PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_EN_SHIFT      0
#define PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_ADDR          MT6355_LDO_VSRAM_PROC_SP
#define PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_SHIFT         1
#define PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_EN_ADDR        MT6355_LDO_VSRAM_GPU_SP
#define PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_EN_MASK        0x1
#define PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_EN_SHIFT       0
#define PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_ADDR           MT6355_LDO_VSRAM_GPU_SP
#define PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_MASK           0x7F
#define PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_SHIFT          1
#define PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_EN_ADDR         MT6355_LDO_VSRAM_MD_SP
#define PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_EN_MASK         0x1
#define PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_EN_SHIFT        0
#define PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_ADDR            MT6355_LDO_VSRAM_MD_SP
#define PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_MASK            0x7F
#define PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_SHIFT           1
#define PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_EN_ADDR       MT6355_LDO_VSRAM_CORE_SP
#define PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_EN_MASK       0x1
#define PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_EN_SHIFT      0
#define PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_ADDR          MT6355_LDO_VSRAM_CORE_SP
#define PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_SHIFT         1
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_ON_ADDR             MT6355_LDO_VSRAM_CORE_SSHUB
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_ON_MASK             0x1
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_ON_SHIFT            0
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_MODE_ADDR           MT6355_LDO_VSRAM_CORE_SSHUB
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_MODE_MASK           0x1
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_MODE_SHIFT          1
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_VOSEL_ADDR          MT6355_LDO_VSRAM_CORE_SSHUB
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_VOSEL_MASK          0x7F
#define PMIC_RG_LDO_VSRAM_CORE_SSHUB_VOSEL_SHIFT         2
#define PMIC_RG_LDO_LP_PROT_DISABLE_ADDR                 MT6355_LDO_LP_PROTECTION
#define PMIC_RG_LDO_LP_PROT_DISABLE_MASK                 0x1
#define PMIC_RG_LDO_LP_PROT_DISABLE_SHIFT                0
#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_ADDR            MT6355_LDO_DUMMY_LOAD_GATED
#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_MASK            0x1
#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_SHIFT           0
#define PMIC_RG_LDO_VSRAM_PROC_R2R_PDN_DIS_ADDR          MT6355_LDO_VSRAM_PROC_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_PROC_R2R_PDN_DIS_MASK          0x1
#define PMIC_RG_LDO_VSRAM_PROC_R2R_PDN_DIS_SHIFT         0
#define PMIC_RG_LDO_VSRAM_CORE_R2R_PDN_DIS_ADDR          MT6355_LDO_VSRAM_CORE_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_CORE_R2R_PDN_DIS_MASK          0x1
#define PMIC_RG_LDO_VSRAM_CORE_R2R_PDN_DIS_SHIFT         0
#define PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS_ADDR           MT6355_LDO_VSRAM_GPU_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS_MASK           0x1
#define PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS_SHIFT          0
#define PMIC_RG_LDO_VSRAM_MD_R2R_PDN_DIS_ADDR            MT6355_LDO_VSRAM_MD_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_MD_R2R_PDN_DIS_MASK            0x1
#define PMIC_RG_LDO_VSRAM_MD_R2R_PDN_DIS_SHIFT           0
#define PMIC_RG_VFE28_VOCAL_ADDR                         MT6355_ALDO_ANA_CON0
#define PMIC_RG_VFE28_VOCAL_MASK                         0xF
#define PMIC_RG_VFE28_VOCAL_SHIFT                        0
#define PMIC_RG_VFE28_VOSEL_ADDR                         MT6355_ALDO_ANA_CON0
#define PMIC_RG_VFE28_VOSEL_MASK                         0xF
#define PMIC_RG_VFE28_VOSEL_SHIFT                        8
#define PMIC_RG_VFE28_VOTRIM_ADDR                        MT6355_ALDO_ANA_CON1
#define PMIC_RG_VFE28_VOTRIM_MASK                        0xF
#define PMIC_RG_VFE28_VOTRIM_SHIFT                       0
#define PMIC_RGS_VFE28_CAL_INDI_ADDR                     MT6355_ALDO_ANA_CON1
#define PMIC_RGS_VFE28_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VFE28_CAL_INDI_SHIFT                    4
#define PMIC_RG_VFE28_OC_TRIM_ADDR                       MT6355_ALDO_ANA_CON1
#define PMIC_RG_VFE28_OC_TRIM_MASK                       0x7
#define PMIC_RG_VFE28_OC_TRIM_SHIFT                      8
#define PMIC_RG_VFE28_NDIS_EN_ADDR                       MT6355_ALDO_ANA_CON1
#define PMIC_RG_VFE28_NDIS_EN_MASK                       0x1
#define PMIC_RG_VFE28_NDIS_EN_SHIFT                      11
#define PMIC_RG_VFE28_STB_SEL_ADDR                       MT6355_ALDO_ANA_CON1
#define PMIC_RG_VFE28_STB_SEL_MASK                       0x1
#define PMIC_RG_VFE28_STB_SEL_SHIFT                      12
#define PMIC_RG_VFE28_RSV_ADDR                           MT6355_ALDO_ANA_CON1
#define PMIC_RG_VFE28_RSV_MASK                           0x3
#define PMIC_RG_VFE28_RSV_SHIFT                          13
#define PMIC_RG_VFE28_VOS_CAL_EN_ADDR                    MT6355_ALDO_ANA_CON1
#define PMIC_RG_VFE28_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VFE28_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VTCXO24_VOCAL_ADDR                       MT6355_ALDO_ANA_CON2
#define PMIC_RG_VTCXO24_VOCAL_MASK                       0xF
#define PMIC_RG_VTCXO24_VOCAL_SHIFT                      0
#define PMIC_RG_VTCXO24_VOSEL_ADDR                       MT6355_ALDO_ANA_CON2
#define PMIC_RG_VTCXO24_VOSEL_MASK                       0xF
#define PMIC_RG_VTCXO24_VOSEL_SHIFT                      8
#define PMIC_RG_VTCXO24_VOTRIM_ADDR                      MT6355_ALDO_ANA_CON3
#define PMIC_RG_VTCXO24_VOTRIM_MASK                      0xF
#define PMIC_RG_VTCXO24_VOTRIM_SHIFT                     0
#define PMIC_RGS_VTCXO24_CAL_INDI_ADDR                   MT6355_ALDO_ANA_CON3
#define PMIC_RGS_VTCXO24_CAL_INDI_MASK                   0x1
#define PMIC_RGS_VTCXO24_CAL_INDI_SHIFT                  4
#define PMIC_RG_VTCXO24_OC_TRIM_ADDR                     MT6355_ALDO_ANA_CON3
#define PMIC_RG_VTCXO24_OC_TRIM_MASK                     0x7
#define PMIC_RG_VTCXO24_OC_TRIM_SHIFT                    8
#define PMIC_RG_VTCXO24_NDIS_EN_ADDR                     MT6355_ALDO_ANA_CON3
#define PMIC_RG_VTCXO24_NDIS_EN_MASK                     0x1
#define PMIC_RG_VTCXO24_NDIS_EN_SHIFT                    11
#define PMIC_RG_VTCXO24_STB_SEL_ADDR                     MT6355_ALDO_ANA_CON3
#define PMIC_RG_VTCXO24_STB_SEL_MASK                     0x1
#define PMIC_RG_VTCXO24_STB_SEL_SHIFT                    12
#define PMIC_RG_VTCXO24_RSV_ADDR                         MT6355_ALDO_ANA_CON3
#define PMIC_RG_VTCXO24_RSV_MASK                         0x3
#define PMIC_RG_VTCXO24_RSV_SHIFT                        13
#define PMIC_RG_VTCXO24_VOS_CAL_EN_ADDR                  MT6355_ALDO_ANA_CON3
#define PMIC_RG_VTCXO24_VOS_CAL_EN_MASK                  0x1
#define PMIC_RG_VTCXO24_VOS_CAL_EN_SHIFT                 15
#define PMIC_RG_VXO22_VOCAL_ADDR                         MT6355_ALDO_ANA_CON4
#define PMIC_RG_VXO22_VOCAL_MASK                         0xF
#define PMIC_RG_VXO22_VOCAL_SHIFT                        0
#define PMIC_RG_VXO22_VOSEL_ADDR                         MT6355_ALDO_ANA_CON4
#define PMIC_RG_VXO22_VOSEL_MASK                         0xF
#define PMIC_RG_VXO22_VOSEL_SHIFT                        8
#define PMIC_RG_VXO22_VOTRIM_ADDR                        MT6355_ALDO_ANA_CON5
#define PMIC_RG_VXO22_VOTRIM_MASK                        0xF
#define PMIC_RG_VXO22_VOTRIM_SHIFT                       0
#define PMIC_RGS_VXO22_CAL_INDI_ADDR                     MT6355_ALDO_ANA_CON5
#define PMIC_RGS_VXO22_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VXO22_CAL_INDI_SHIFT                    4
#define PMIC_RG_VXO22_OC_TRIM_ADDR                       MT6355_ALDO_ANA_CON5
#define PMIC_RG_VXO22_OC_TRIM_MASK                       0x7
#define PMIC_RG_VXO22_OC_TRIM_SHIFT                      8
#define PMIC_RG_VXO22_NDIS_EN_ADDR                       MT6355_ALDO_ANA_CON5
#define PMIC_RG_VXO22_NDIS_EN_MASK                       0x1
#define PMIC_RG_VXO22_NDIS_EN_SHIFT                      11
#define PMIC_RG_VXO22_STB_SEL_ADDR                       MT6355_ALDO_ANA_CON5
#define PMIC_RG_VXO22_STB_SEL_MASK                       0x1
#define PMIC_RG_VXO22_STB_SEL_SHIFT                      12
#define PMIC_RG_VXO22_RSV_ADDR                           MT6355_ALDO_ANA_CON5
#define PMIC_RG_VXO22_RSV_MASK                           0x3
#define PMIC_RG_VXO22_RSV_SHIFT                          13
#define PMIC_RG_VXO22_VOS_CAL_EN_ADDR                    MT6355_ALDO_ANA_CON5
#define PMIC_RG_VXO22_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VXO22_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VCN28_VOCAL_ADDR                         MT6355_ALDO_ANA_CON6
#define PMIC_RG_VCN28_VOCAL_MASK                         0xF
#define PMIC_RG_VCN28_VOCAL_SHIFT                        0
#define PMIC_RG_VCN28_VOSEL_ADDR                         MT6355_ALDO_ANA_CON6
#define PMIC_RG_VCN28_VOSEL_MASK                         0xF
#define PMIC_RG_VCN28_VOSEL_SHIFT                        8
#define PMIC_RG_VCN28_VOTRIM_ADDR                        MT6355_ALDO_ANA_CON7
#define PMIC_RG_VCN28_VOTRIM_MASK                        0xF
#define PMIC_RG_VCN28_VOTRIM_SHIFT                       0
#define PMIC_RGS_VCN28_CAL_INDI_ADDR                     MT6355_ALDO_ANA_CON7
#define PMIC_RGS_VCN28_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VCN28_CAL_INDI_SHIFT                    4
#define PMIC_RG_VCN28_OC_TRIM_ADDR                       MT6355_ALDO_ANA_CON7
#define PMIC_RG_VCN28_OC_TRIM_MASK                       0x7
#define PMIC_RG_VCN28_OC_TRIM_SHIFT                      8
#define PMIC_RG_VCN28_NDIS_EN_ADDR                       MT6355_ALDO_ANA_CON7
#define PMIC_RG_VCN28_NDIS_EN_MASK                       0x1
#define PMIC_RG_VCN28_NDIS_EN_SHIFT                      11
#define PMIC_RG_VCN28_STB_SEL_ADDR                       MT6355_ALDO_ANA_CON7
#define PMIC_RG_VCN28_STB_SEL_MASK                       0x1
#define PMIC_RG_VCN28_STB_SEL_SHIFT                      12
#define PMIC_RG_VCN28_RSV_ADDR                           MT6355_ALDO_ANA_CON7
#define PMIC_RG_VCN28_RSV_MASK                           0x3
#define PMIC_RG_VCN28_RSV_SHIFT                          13
#define PMIC_RG_VCN28_VOS_CAL_EN_ADDR                    MT6355_ALDO_ANA_CON7
#define PMIC_RG_VCN28_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VCN28_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VCAMA1_VOCAL_ADDR                        MT6355_ALDO_ANA_CON8
#define PMIC_RG_VCAMA1_VOCAL_MASK                        0xF
#define PMIC_RG_VCAMA1_VOCAL_SHIFT                       0
#define PMIC_RG_VCAMA1_VOSEL_ADDR                        MT6355_ALDO_ANA_CON8
#define PMIC_RG_VCAMA1_VOSEL_MASK                        0xF
#define PMIC_RG_VCAMA1_VOSEL_SHIFT                       8
#define PMIC_RG_VCAMA1_VOTRIM_ADDR                       MT6355_ALDO_ANA_CON9
#define PMIC_RG_VCAMA1_VOTRIM_MASK                       0xF
#define PMIC_RG_VCAMA1_VOTRIM_SHIFT                      0
#define PMIC_RGS_VCAMA1_CAL_INDI_ADDR                    MT6355_ALDO_ANA_CON9
#define PMIC_RGS_VCAMA1_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VCAMA1_CAL_INDI_SHIFT                   4
#define PMIC_RG_VCAMA1_OC_TRIM_ADDR                      MT6355_ALDO_ANA_CON9
#define PMIC_RG_VCAMA1_OC_TRIM_MASK                      0x7
#define PMIC_RG_VCAMA1_OC_TRIM_SHIFT                     8
#define PMIC_RG_VCAMA1_NDIS_EN_ADDR                      MT6355_ALDO_ANA_CON9
#define PMIC_RG_VCAMA1_NDIS_EN_MASK                      0x1
#define PMIC_RG_VCAMA1_NDIS_EN_SHIFT                     11
#define PMIC_RG_VCAMA1_STB_SEL_ADDR                      MT6355_ALDO_ANA_CON9
#define PMIC_RG_VCAMA1_STB_SEL_MASK                      0x1
#define PMIC_RG_VCAMA1_STB_SEL_SHIFT                     12
#define PMIC_RG_VCAMA1_RSV_ADDR                          MT6355_ALDO_ANA_CON9
#define PMIC_RG_VCAMA1_RSV_MASK                          0x3
#define PMIC_RG_VCAMA1_RSV_SHIFT                         13
#define PMIC_RG_VCAMA1_VOS_CAL_EN_ADDR                   MT6355_ALDO_ANA_CON9
#define PMIC_RG_VCAMA1_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VCAMA1_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VCAMA2_VOCAL_ADDR                        MT6355_ALDO_ANA_CON10
#define PMIC_RG_VCAMA2_VOCAL_MASK                        0xF
#define PMIC_RG_VCAMA2_VOCAL_SHIFT                       0
#define PMIC_RG_VCAMA2_VOSEL_ADDR                        MT6355_ALDO_ANA_CON10
#define PMIC_RG_VCAMA2_VOSEL_MASK                        0xF
#define PMIC_RG_VCAMA2_VOSEL_SHIFT                       8
#define PMIC_RG_VCAMA2_VOTRIM_ADDR                       MT6355_ALDO_ANA_CON11
#define PMIC_RG_VCAMA2_VOTRIM_MASK                       0xF
#define PMIC_RG_VCAMA2_VOTRIM_SHIFT                      0
#define PMIC_RGS_VCAMA2_CAL_INDI_ADDR                    MT6355_ALDO_ANA_CON11
#define PMIC_RGS_VCAMA2_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VCAMA2_CAL_INDI_SHIFT                   4
#define PMIC_RG_VCAMA2_OC_TRIM_ADDR                      MT6355_ALDO_ANA_CON11
#define PMIC_RG_VCAMA2_OC_TRIM_MASK                      0x7
#define PMIC_RG_VCAMA2_OC_TRIM_SHIFT                     8
#define PMIC_RG_VCAMA2_NDIS_EN_ADDR                      MT6355_ALDO_ANA_CON11
#define PMIC_RG_VCAMA2_NDIS_EN_MASK                      0x1
#define PMIC_RG_VCAMA2_NDIS_EN_SHIFT                     11
#define PMIC_RG_VCAMA2_STB_SEL_ADDR                      MT6355_ALDO_ANA_CON11
#define PMIC_RG_VCAMA2_STB_SEL_MASK                      0x1
#define PMIC_RG_VCAMA2_STB_SEL_SHIFT                     12
#define PMIC_RG_VCAMA2_RSV_ADDR                          MT6355_ALDO_ANA_CON11
#define PMIC_RG_VCAMA2_RSV_MASK                          0x3
#define PMIC_RG_VCAMA2_RSV_SHIFT                         13
#define PMIC_RG_VCAMA2_VOS_CAL_EN_ADDR                   MT6355_ALDO_ANA_CON11
#define PMIC_RG_VCAMA2_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VCAMA2_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VA18_VOCAL_ADDR                          MT6355_ALDO_ANA_CON12
#define PMIC_RG_VA18_VOCAL_MASK                          0xF
#define PMIC_RG_VA18_VOCAL_SHIFT                         0
#define PMIC_RG_VA18_VOSEL_ADDR                          MT6355_ALDO_ANA_CON12
#define PMIC_RG_VA18_VOSEL_MASK                          0xF
#define PMIC_RG_VA18_VOSEL_SHIFT                         8
#define PMIC_RG_VA18_VOTRIM_ADDR                         MT6355_ALDO_ANA_CON13
#define PMIC_RG_VA18_VOTRIM_MASK                         0xF
#define PMIC_RG_VA18_VOTRIM_SHIFT                        0
#define PMIC_RGS_VA18_CAL_INDI_ADDR                      MT6355_ALDO_ANA_CON13
#define PMIC_RGS_VA18_CAL_INDI_MASK                      0x1
#define PMIC_RGS_VA18_CAL_INDI_SHIFT                     4
#define PMIC_RG_VA18_OC_TRIM_ADDR                        MT6355_ALDO_ANA_CON13
#define PMIC_RG_VA18_OC_TRIM_MASK                        0x7
#define PMIC_RG_VA18_OC_TRIM_SHIFT                       8
#define PMIC_RG_VA18_NDIS_EN_ADDR                        MT6355_ALDO_ANA_CON13
#define PMIC_RG_VA18_NDIS_EN_MASK                        0x1
#define PMIC_RG_VA18_NDIS_EN_SHIFT                       11
#define PMIC_RG_VA18_STB_SEL_ADDR                        MT6355_ALDO_ANA_CON13
#define PMIC_RG_VA18_STB_SEL_MASK                        0x1
#define PMIC_RG_VA18_STB_SEL_SHIFT                       12
#define PMIC_RG_VA18_RSV_ADDR                            MT6355_ALDO_ANA_CON13
#define PMIC_RG_VA18_RSV_MASK                            0x3
#define PMIC_RG_VA18_RSV_SHIFT                           13
#define PMIC_RG_VA18_VOS_CAL_EN_ADDR                     MT6355_ALDO_ANA_CON13
#define PMIC_RG_VA18_VOS_CAL_EN_MASK                     0x1
#define PMIC_RG_VA18_VOS_CAL_EN_SHIFT                    15
#define PMIC_RG_VUSB33_VOCAL_ADDR                        MT6355_ALDO_ANA_CON14
#define PMIC_RG_VUSB33_VOCAL_MASK                        0xF
#define PMIC_RG_VUSB33_VOCAL_SHIFT                       0
#define PMIC_RG_VUSB33_VOSEL_ADDR                        MT6355_ALDO_ANA_CON14
#define PMIC_RG_VUSB33_VOSEL_MASK                        0xF
#define PMIC_RG_VUSB33_VOSEL_SHIFT                       8
#define PMIC_RG_VUSB33_VOTRIM_ADDR                       MT6355_ALDO_ANA_CON15
#define PMIC_RG_VUSB33_VOTRIM_MASK                       0xF
#define PMIC_RG_VUSB33_VOTRIM_SHIFT                      0
#define PMIC_RGS_VUSB33_CAL_INDI_ADDR                    MT6355_ALDO_ANA_CON15
#define PMIC_RGS_VUSB33_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VUSB33_CAL_INDI_SHIFT                   4
#define PMIC_RG_VUSB33_OC_TRIM_ADDR                      MT6355_ALDO_ANA_CON15
#define PMIC_RG_VUSB33_OC_TRIM_MASK                      0x7
#define PMIC_RG_VUSB33_OC_TRIM_SHIFT                     8
#define PMIC_RG_VUSB33_NDIS_EN_ADDR                      MT6355_ALDO_ANA_CON15
#define PMIC_RG_VUSB33_NDIS_EN_MASK                      0x1
#define PMIC_RG_VUSB33_NDIS_EN_SHIFT                     11
#define PMIC_RG_VUSB33_STB_SEL_ADDR                      MT6355_ALDO_ANA_CON15
#define PMIC_RG_VUSB33_STB_SEL_MASK                      0x1
#define PMIC_RG_VUSB33_STB_SEL_SHIFT                     12
#define PMIC_RG_VUSB33_RSV_ADDR                          MT6355_ALDO_ANA_CON15
#define PMIC_RG_VUSB33_RSV_MASK                          0x3
#define PMIC_RG_VUSB33_RSV_SHIFT                         13
#define PMIC_RG_VUSB33_VOS_CAL_EN_ADDR                   MT6355_ALDO_ANA_CON15
#define PMIC_RG_VUSB33_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VUSB33_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VBIF28_VOCAL_ADDR                        MT6355_ALDO_ANA_CON16
#define PMIC_RG_VBIF28_VOCAL_MASK                        0xF
#define PMIC_RG_VBIF28_VOCAL_SHIFT                       0
#define PMIC_RG_VBIF28_VOSEL_ADDR                        MT6355_ALDO_ANA_CON16
#define PMIC_RG_VBIF28_VOSEL_MASK                        0xF
#define PMIC_RG_VBIF28_VOSEL_SHIFT                       8
#define PMIC_RG_VBIF28_VOTRIM_ADDR                       MT6355_ALDO_ANA_CON17
#define PMIC_RG_VBIF28_VOTRIM_MASK                       0xF
#define PMIC_RG_VBIF28_VOTRIM_SHIFT                      0
#define PMIC_RGS_VBIF28_CAL_INDI_ADDR                    MT6355_ALDO_ANA_CON17
#define PMIC_RGS_VBIF28_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VBIF28_CAL_INDI_SHIFT                   4
#define PMIC_RG_VBIF28_OC_TRIM_ADDR                      MT6355_ALDO_ANA_CON17
#define PMIC_RG_VBIF28_OC_TRIM_MASK                      0x7
#define PMIC_RG_VBIF28_OC_TRIM_SHIFT                     8
#define PMIC_RG_VBIF28_NDIS_EN_ADDR                      MT6355_ALDO_ANA_CON17
#define PMIC_RG_VBIF28_NDIS_EN_MASK                      0x1
#define PMIC_RG_VBIF28_NDIS_EN_SHIFT                     11
#define PMIC_RG_VBIF28_STB_SEL_ADDR                      MT6355_ALDO_ANA_CON17
#define PMIC_RG_VBIF28_STB_SEL_MASK                      0x1
#define PMIC_RG_VBIF28_STB_SEL_SHIFT                     12
#define PMIC_RG_VBIF28_RSV_ADDR                          MT6355_ALDO_ANA_CON17
#define PMIC_RG_VBIF28_RSV_MASK                          0x3
#define PMIC_RG_VBIF28_RSV_SHIFT                         13
#define PMIC_RG_VBIF28_VOS_CAL_EN_ADDR                   MT6355_ALDO_ANA_CON17
#define PMIC_RG_VBIF28_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VBIF28_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VGP2_VOCAL_ADDR                          MT6355_ALDO_ANA_CON18
#define PMIC_RG_VGP2_VOCAL_MASK                          0xF
#define PMIC_RG_VGP2_VOCAL_SHIFT                         0
#define PMIC_RG_VGP2_VOSEL_ADDR                          MT6355_ALDO_ANA_CON18
#define PMIC_RG_VGP2_VOSEL_MASK                          0xF
#define PMIC_RG_VGP2_VOSEL_SHIFT                         8
#define PMIC_RG_VGP2_VOTRIM_ADDR                         MT6355_ALDO_ANA_CON19
#define PMIC_RG_VGP2_VOTRIM_MASK                         0xF
#define PMIC_RG_VGP2_VOTRIM_SHIFT                        0
#define PMIC_RGS_VGP2_CAL_INDI_ADDR                      MT6355_ALDO_ANA_CON19
#define PMIC_RGS_VGP2_CAL_INDI_MASK                      0x1
#define PMIC_RGS_VGP2_CAL_INDI_SHIFT                     4
#define PMIC_RG_VGP2_OC_TRIM_ADDR                        MT6355_ALDO_ANA_CON19
#define PMIC_RG_VGP2_OC_TRIM_MASK                        0x7
#define PMIC_RG_VGP2_OC_TRIM_SHIFT                       8
#define PMIC_RG_VGP2_NDIS_EN_ADDR                        MT6355_ALDO_ANA_CON19
#define PMIC_RG_VGP2_NDIS_EN_MASK                        0x1
#define PMIC_RG_VGP2_NDIS_EN_SHIFT                       11
#define PMIC_RG_VGP2_STB_SEL_ADDR                        MT6355_ALDO_ANA_CON19
#define PMIC_RG_VGP2_STB_SEL_MASK                        0x1
#define PMIC_RG_VGP2_STB_SEL_SHIFT                       12
#define PMIC_RG_VGP2_RSV_ADDR                            MT6355_ALDO_ANA_CON19
#define PMIC_RG_VGP2_RSV_MASK                            0x3
#define PMIC_RG_VGP2_RSV_SHIFT                           13
#define PMIC_RG_VGP2_VOS_CAL_EN_ADDR                     MT6355_ALDO_ANA_CON19
#define PMIC_RG_VGP2_VOS_CAL_EN_MASK                     0x1
#define PMIC_RG_VGP2_VOS_CAL_EN_SHIFT                    15
#define PMIC_RG_VCN33_VOCAL_ADDR                         MT6355_DLDO_ANA_CON0
#define PMIC_RG_VCN33_VOCAL_MASK                         0xF
#define PMIC_RG_VCN33_VOCAL_SHIFT                        0
#define PMIC_RG_VCN33_VOSEL_ADDR                         MT6355_DLDO_ANA_CON0
#define PMIC_RG_VCN33_VOSEL_MASK                         0xF
#define PMIC_RG_VCN33_VOSEL_SHIFT                        8
#define PMIC_RG_VCN33_VOTRIM_ADDR                        MT6355_DLDO_ANA_CON1
#define PMIC_RG_VCN33_VOTRIM_MASK                        0xF
#define PMIC_RG_VCN33_VOTRIM_SHIFT                       0
#define PMIC_RGS_VCN33_CAL_INDI_ADDR                     MT6355_DLDO_ANA_CON1
#define PMIC_RGS_VCN33_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VCN33_CAL_INDI_SHIFT                    4
#define PMIC_RG_VCN33_OC_TRIM_ADDR                       MT6355_DLDO_ANA_CON1
#define PMIC_RG_VCN33_OC_TRIM_MASK                       0x7
#define PMIC_RG_VCN33_OC_TRIM_SHIFT                      8
#define PMIC_RG_VCN33_NDIS_EN_ADDR                       MT6355_DLDO_ANA_CON1
#define PMIC_RG_VCN33_NDIS_EN_MASK                       0x1
#define PMIC_RG_VCN33_NDIS_EN_SHIFT                      11
#define PMIC_RG_VCN33_STB_SEL_ADDR                       MT6355_DLDO_ANA_CON1
#define PMIC_RG_VCN33_STB_SEL_MASK                       0x1
#define PMIC_RG_VCN33_STB_SEL_SHIFT                      12
#define PMIC_RG_VCN33_RSV_ADDR                           MT6355_DLDO_ANA_CON1
#define PMIC_RG_VCN33_RSV_MASK                           0x3
#define PMIC_RG_VCN33_RSV_SHIFT                          13
#define PMIC_RG_VCN33_VOS_CAL_EN_ADDR                    MT6355_DLDO_ANA_CON1
#define PMIC_RG_VCN33_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VCN33_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VSIM1_VOCAL_ADDR                         MT6355_DLDO_ANA_CON2
#define PMIC_RG_VSIM1_VOCAL_MASK                         0xF
#define PMIC_RG_VSIM1_VOCAL_SHIFT                        0
#define PMIC_RG_VSIM1_VOSEL_ADDR                         MT6355_DLDO_ANA_CON2
#define PMIC_RG_VSIM1_VOSEL_MASK                         0xF
#define PMIC_RG_VSIM1_VOSEL_SHIFT                        8
#define PMIC_RG_VSIM1_VOTRIM_ADDR                        MT6355_DLDO_ANA_CON3
#define PMIC_RG_VSIM1_VOTRIM_MASK                        0xF
#define PMIC_RG_VSIM1_VOTRIM_SHIFT                       0
#define PMIC_RGS_VSIM1_CAL_INDI_ADDR                     MT6355_DLDO_ANA_CON3
#define PMIC_RGS_VSIM1_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VSIM1_CAL_INDI_SHIFT                    4
#define PMIC_RG_VSIM1_OC_TRIM_ADDR                       MT6355_DLDO_ANA_CON3
#define PMIC_RG_VSIM1_OC_TRIM_MASK                       0x7
#define PMIC_RG_VSIM1_OC_TRIM_SHIFT                      8
#define PMIC_RG_VSIM1_NDIS_EN_ADDR                       MT6355_DLDO_ANA_CON3
#define PMIC_RG_VSIM1_NDIS_EN_MASK                       0x1
#define PMIC_RG_VSIM1_NDIS_EN_SHIFT                      11
#define PMIC_RG_VSIM1_STB_SEL_ADDR                       MT6355_DLDO_ANA_CON3
#define PMIC_RG_VSIM1_STB_SEL_MASK                       0x1
#define PMIC_RG_VSIM1_STB_SEL_SHIFT                      12
#define PMIC_RG_VSIM1_RSV_ADDR                           MT6355_DLDO_ANA_CON3
#define PMIC_RG_VSIM1_RSV_MASK                           0x3
#define PMIC_RG_VSIM1_RSV_SHIFT                          13
#define PMIC_RG_VSIM1_VOS_CAL_EN_ADDR                    MT6355_DLDO_ANA_CON3
#define PMIC_RG_VSIM1_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VSIM1_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VSIM2_VOCAL_ADDR                         MT6355_DLDO_ANA_CON4
#define PMIC_RG_VSIM2_VOCAL_MASK                         0xF
#define PMIC_RG_VSIM2_VOCAL_SHIFT                        0
#define PMIC_RG_VSIM2_VOSEL_ADDR                         MT6355_DLDO_ANA_CON4
#define PMIC_RG_VSIM2_VOSEL_MASK                         0xF
#define PMIC_RG_VSIM2_VOSEL_SHIFT                        8
#define PMIC_RG_VSIM2_VOTRIM_ADDR                        MT6355_DLDO_ANA_CON5
#define PMIC_RG_VSIM2_VOTRIM_MASK                        0xF
#define PMIC_RG_VSIM2_VOTRIM_SHIFT                       0
#define PMIC_RGS_VSIM2_CAL_INDI_ADDR                     MT6355_DLDO_ANA_CON5
#define PMIC_RGS_VSIM2_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VSIM2_CAL_INDI_SHIFT                    4
#define PMIC_RG_VSIM2_OC_TRIM_ADDR                       MT6355_DLDO_ANA_CON5
#define PMIC_RG_VSIM2_OC_TRIM_MASK                       0x7
#define PMIC_RG_VSIM2_OC_TRIM_SHIFT                      8
#define PMIC_RG_VSIM2_NDIS_EN_ADDR                       MT6355_DLDO_ANA_CON5
#define PMIC_RG_VSIM2_NDIS_EN_MASK                       0x1
#define PMIC_RG_VSIM2_NDIS_EN_SHIFT                      11
#define PMIC_RG_VSIM2_STB_SEL_ADDR                       MT6355_DLDO_ANA_CON5
#define PMIC_RG_VSIM2_STB_SEL_MASK                       0x1
#define PMIC_RG_VSIM2_STB_SEL_SHIFT                      12
#define PMIC_RG_VSIM2_RSV_ADDR                           MT6355_DLDO_ANA_CON5
#define PMIC_RG_VSIM2_RSV_MASK                           0x3
#define PMIC_RG_VSIM2_RSV_SHIFT                          13
#define PMIC_RG_VSIM2_VOS_CAL_EN_ADDR                    MT6355_DLDO_ANA_CON5
#define PMIC_RG_VSIM2_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VSIM2_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VLDO28_VOCAL_ADDR                        MT6355_DLDO_ANA_CON6
#define PMIC_RG_VLDO28_VOCAL_MASK                        0xF
#define PMIC_RG_VLDO28_VOCAL_SHIFT                       0
#define PMIC_RG_VLDO28_VOSEL_ADDR                        MT6355_DLDO_ANA_CON6
#define PMIC_RG_VLDO28_VOSEL_MASK                        0xF
#define PMIC_RG_VLDO28_VOSEL_SHIFT                       8
#define PMIC_RG_VLDO28_VOTRIM_ADDR                       MT6355_DLDO_ANA_CON7
#define PMIC_RG_VLDO28_VOTRIM_MASK                       0xF
#define PMIC_RG_VLDO28_VOTRIM_SHIFT                      0
#define PMIC_RGS_VLDO28_CAL_INDI_ADDR                    MT6355_DLDO_ANA_CON7
#define PMIC_RGS_VLDO28_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VLDO28_CAL_INDI_SHIFT                   4
#define PMIC_RG_VLDO28_OC_TRIM_ADDR                      MT6355_DLDO_ANA_CON7
#define PMIC_RG_VLDO28_OC_TRIM_MASK                      0x7
#define PMIC_RG_VLDO28_OC_TRIM_SHIFT                     8
#define PMIC_RG_VLDO28_NDIS_EN_ADDR                      MT6355_DLDO_ANA_CON7
#define PMIC_RG_VLDO28_NDIS_EN_MASK                      0x1
#define PMIC_RG_VLDO28_NDIS_EN_SHIFT                     11
#define PMIC_RG_VLDO28_STB_SEL_ADDR                      MT6355_DLDO_ANA_CON7
#define PMIC_RG_VLDO28_STB_SEL_MASK                      0x1
#define PMIC_RG_VLDO28_STB_SEL_SHIFT                     12
#define PMIC_RG_VLDO28_RSV_ADDR                          MT6355_DLDO_ANA_CON7
#define PMIC_RG_VLDO28_RSV_MASK                          0x3
#define PMIC_RG_VLDO28_RSV_SHIFT                         13
#define PMIC_RG_VLDO28_VOS_CAL_EN_ADDR                   MT6355_DLDO_ANA_CON7
#define PMIC_RG_VLDO28_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VLDO28_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VIO28_VOCAL_ADDR                         MT6355_DLDO_ANA_CON8
#define PMIC_RG_VIO28_VOCAL_MASK                         0xF
#define PMIC_RG_VIO28_VOCAL_SHIFT                        0
#define PMIC_RG_VIO28_VOSEL_ADDR                         MT6355_DLDO_ANA_CON8
#define PMIC_RG_VIO28_VOSEL_MASK                         0xF
#define PMIC_RG_VIO28_VOSEL_SHIFT                        8
#define PMIC_RG_VIO28_VOTRIM_ADDR                        MT6355_DLDO_ANA_CON9
#define PMIC_RG_VIO28_VOTRIM_MASK                        0xF
#define PMIC_RG_VIO28_VOTRIM_SHIFT                       0
#define PMIC_RGS_VIO28_CAL_INDI_ADDR                     MT6355_DLDO_ANA_CON9
#define PMIC_RGS_VIO28_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VIO28_CAL_INDI_SHIFT                    4
#define PMIC_RG_VIO28_OC_TRIM_ADDR                       MT6355_DLDO_ANA_CON9
#define PMIC_RG_VIO28_OC_TRIM_MASK                       0x7
#define PMIC_RG_VIO28_OC_TRIM_SHIFT                      8
#define PMIC_RG_VIO28_NDIS_EN_ADDR                       MT6355_DLDO_ANA_CON9
#define PMIC_RG_VIO28_NDIS_EN_MASK                       0x1
#define PMIC_RG_VIO28_NDIS_EN_SHIFT                      11
#define PMIC_RG_VIO28_STB_SEL_ADDR                       MT6355_DLDO_ANA_CON9
#define PMIC_RG_VIO28_STB_SEL_MASK                       0x1
#define PMIC_RG_VIO28_STB_SEL_SHIFT                      12
#define PMIC_RG_VIO28_RSV_ADDR                           MT6355_DLDO_ANA_CON9
#define PMIC_RG_VIO28_RSV_MASK                           0x3
#define PMIC_RG_VIO28_RSV_SHIFT                          13
#define PMIC_RG_VIO28_VOS_CAL_EN_ADDR                    MT6355_DLDO_ANA_CON9
#define PMIC_RG_VIO28_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VIO28_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VMC_VOCAL_ADDR                           MT6355_DLDO_ANA_CON10
#define PMIC_RG_VMC_VOCAL_MASK                           0xF
#define PMIC_RG_VMC_VOCAL_SHIFT                          0
#define PMIC_RG_VMC_VOSEL_ADDR                           MT6355_DLDO_ANA_CON10
#define PMIC_RG_VMC_VOSEL_MASK                           0xF
#define PMIC_RG_VMC_VOSEL_SHIFT                          8
#define PMIC_RG_VMC_VOTRIM_ADDR                          MT6355_DLDO_ANA_CON11
#define PMIC_RG_VMC_VOTRIM_MASK                          0xF
#define PMIC_RG_VMC_VOTRIM_SHIFT                         0
#define PMIC_RGS_VMC_CAL_INDI_ADDR                       MT6355_DLDO_ANA_CON11
#define PMIC_RGS_VMC_CAL_INDI_MASK                       0x1
#define PMIC_RGS_VMC_CAL_INDI_SHIFT                      4
#define PMIC_RG_VMC_OC_TRIM_ADDR                         MT6355_DLDO_ANA_CON11
#define PMIC_RG_VMC_OC_TRIM_MASK                         0x7
#define PMIC_RG_VMC_OC_TRIM_SHIFT                        8
#define PMIC_RG_VMC_NDIS_EN_ADDR                         MT6355_DLDO_ANA_CON11
#define PMIC_RG_VMC_NDIS_EN_MASK                         0x1
#define PMIC_RG_VMC_NDIS_EN_SHIFT                        11
#define PMIC_RG_VMC_STB_SEL_ADDR                         MT6355_DLDO_ANA_CON11
#define PMIC_RG_VMC_STB_SEL_MASK                         0x1
#define PMIC_RG_VMC_STB_SEL_SHIFT                        12
#define PMIC_RG_VMC_RSV_ADDR                             MT6355_DLDO_ANA_CON11
#define PMIC_RG_VMC_RSV_MASK                             0x3
#define PMIC_RG_VMC_RSV_SHIFT                            13
#define PMIC_RG_VMC_VOS_CAL_EN_ADDR                      MT6355_DLDO_ANA_CON11
#define PMIC_RG_VMC_VOS_CAL_EN_MASK                      0x1
#define PMIC_RG_VMC_VOS_CAL_EN_SHIFT                     15
#define PMIC_RG_VMCH_VOCAL_ADDR                          MT6355_DLDO_ANA_CON12
#define PMIC_RG_VMCH_VOCAL_MASK                          0xF
#define PMIC_RG_VMCH_VOCAL_SHIFT                         0
#define PMIC_RG_VMCH_VOSEL_ADDR                          MT6355_DLDO_ANA_CON12
#define PMIC_RG_VMCH_VOSEL_MASK                          0xF
#define PMIC_RG_VMCH_VOSEL_SHIFT                         8
#define PMIC_RG_VMCH_VOTRIM_ADDR                         MT6355_DLDO_ANA_CON13
#define PMIC_RG_VMCH_VOTRIM_MASK                         0xF
#define PMIC_RG_VMCH_VOTRIM_SHIFT                        0
#define PMIC_RGS_VMCH_CAL_INDI_ADDR                      MT6355_DLDO_ANA_CON13
#define PMIC_RGS_VMCH_CAL_INDI_MASK                      0x1
#define PMIC_RGS_VMCH_CAL_INDI_SHIFT                     4
#define PMIC_RG_VMCH_OC_TRIM_ADDR                        MT6355_DLDO_ANA_CON13
#define PMIC_RG_VMCH_OC_TRIM_MASK                        0x7
#define PMIC_RG_VMCH_OC_TRIM_SHIFT                       8
#define PMIC_RG_VMCH_NDIS_EN_ADDR                        MT6355_DLDO_ANA_CON13
#define PMIC_RG_VMCH_NDIS_EN_MASK                        0x1
#define PMIC_RG_VMCH_NDIS_EN_SHIFT                       11
#define PMIC_RG_VMCH_STB_SEL_ADDR                        MT6355_DLDO_ANA_CON13
#define PMIC_RG_VMCH_STB_SEL_MASK                        0x1
#define PMIC_RG_VMCH_STB_SEL_SHIFT                       12
#define PMIC_RG_VMCH_RSV_ADDR                            MT6355_DLDO_ANA_CON13
#define PMIC_RG_VMCH_RSV_MASK                            0x3
#define PMIC_RG_VMCH_RSV_SHIFT                           13
#define PMIC_RG_VMCH_VOS_CAL_EN_ADDR                     MT6355_DLDO_ANA_CON13
#define PMIC_RG_VMCH_VOS_CAL_EN_MASK                     0x1
#define PMIC_RG_VMCH_VOS_CAL_EN_SHIFT                    15
#define PMIC_RG_VEMC_VOCAL_ADDR                          MT6355_DLDO_ANA_CON14
#define PMIC_RG_VEMC_VOCAL_MASK                          0xF
#define PMIC_RG_VEMC_VOCAL_SHIFT                         0
#define PMIC_RG_VEMC_VOSEL_ADDR                          MT6355_DLDO_ANA_CON14
#define PMIC_RG_VEMC_VOSEL_MASK                          0xF
#define PMIC_RG_VEMC_VOSEL_SHIFT                         8
#define PMIC_RG_VEMC_VOTRIM_ADDR                         MT6355_DLDO_ANA_CON15
#define PMIC_RG_VEMC_VOTRIM_MASK                         0xF
#define PMIC_RG_VEMC_VOTRIM_SHIFT                        0
#define PMIC_RGS_VEMC_CAL_INDI_ADDR                      MT6355_DLDO_ANA_CON15
#define PMIC_RGS_VEMC_CAL_INDI_MASK                      0x1
#define PMIC_RGS_VEMC_CAL_INDI_SHIFT                     4
#define PMIC_RG_VEMC_OC_TRIM_ADDR                        MT6355_DLDO_ANA_CON15
#define PMIC_RG_VEMC_OC_TRIM_MASK                        0x7
#define PMIC_RG_VEMC_OC_TRIM_SHIFT                       8
#define PMIC_RG_VEMC_NDIS_EN_ADDR                        MT6355_DLDO_ANA_CON15
#define PMIC_RG_VEMC_NDIS_EN_MASK                        0x1
#define PMIC_RG_VEMC_NDIS_EN_SHIFT                       11
#define PMIC_RG_VEMC_STB_SEL_ADDR                        MT6355_DLDO_ANA_CON15
#define PMIC_RG_VEMC_STB_SEL_MASK                        0x1
#define PMIC_RG_VEMC_STB_SEL_SHIFT                       12
#define PMIC_RG_VEMC_RSV_ADDR                            MT6355_DLDO_ANA_CON15
#define PMIC_RG_VEMC_RSV_MASK                            0x3
#define PMIC_RG_VEMC_RSV_SHIFT                           13
#define PMIC_RG_VEMC_VOS_CAL_EN_ADDR                     MT6355_DLDO_ANA_CON15
#define PMIC_RG_VEMC_VOS_CAL_EN_MASK                     0x1
#define PMIC_RG_VEMC_VOS_CAL_EN_SHIFT                    15
#define PMIC_RG_VGP_VOCAL_ADDR                           MT6355_DLDO_ANA_CON16
#define PMIC_RG_VGP_VOCAL_MASK                           0xF
#define PMIC_RG_VGP_VOCAL_SHIFT                          0
#define PMIC_RG_VGP_VOSEL_ADDR                           MT6355_DLDO_ANA_CON16
#define PMIC_RG_VGP_VOSEL_MASK                           0xF
#define PMIC_RG_VGP_VOSEL_SHIFT                          8
#define PMIC_RG_VGP_VOTRIM_ADDR                          MT6355_DLDO_ANA_CON17
#define PMIC_RG_VGP_VOTRIM_MASK                          0xF
#define PMIC_RG_VGP_VOTRIM_SHIFT                         0
#define PMIC_RGS_VGP_CAL_INDI_ADDR                       MT6355_DLDO_ANA_CON17
#define PMIC_RGS_VGP_CAL_INDI_MASK                       0x1
#define PMIC_RGS_VGP_CAL_INDI_SHIFT                      4
#define PMIC_RG_VGP_OC_TRIM_ADDR                         MT6355_DLDO_ANA_CON17
#define PMIC_RG_VGP_OC_TRIM_MASK                         0x7
#define PMIC_RG_VGP_OC_TRIM_SHIFT                        8
#define PMIC_RG_VGP_NDIS_EN_ADDR                         MT6355_DLDO_ANA_CON17
#define PMIC_RG_VGP_NDIS_EN_MASK                         0x1
#define PMIC_RG_VGP_NDIS_EN_SHIFT                        11
#define PMIC_RG_VGP_STB_SEL_ADDR                         MT6355_DLDO_ANA_CON17
#define PMIC_RG_VGP_STB_SEL_MASK                         0x1
#define PMIC_RG_VGP_STB_SEL_SHIFT                        12
#define PMIC_RG_VGP_RSV_ADDR                             MT6355_DLDO_ANA_CON17
#define PMIC_RG_VGP_RSV_MASK                             0x3
#define PMIC_RG_VGP_RSV_SHIFT                            13
#define PMIC_RG_VGP_VOS_CAL_EN_ADDR                      MT6355_DLDO_ANA_CON17
#define PMIC_RG_VGP_VOS_CAL_EN_MASK                      0x1
#define PMIC_RG_VGP_VOS_CAL_EN_SHIFT                     15
#define PMIC_RG_VRF18_1_VOCAL_ADDR                       MT6355_SLDO20_ANA_CON0
#define PMIC_RG_VRF18_1_VOCAL_MASK                       0xF
#define PMIC_RG_VRF18_1_VOCAL_SHIFT                      0
#define PMIC_RG_VRF18_1_VOSEL_ADDR                       MT6355_SLDO20_ANA_CON0
#define PMIC_RG_VRF18_1_VOSEL_MASK                       0xF
#define PMIC_RG_VRF18_1_VOSEL_SHIFT                      8
#define PMIC_RG_VRF18_1_VOTRIM_ADDR                      MT6355_SLDO20_ANA_CON1
#define PMIC_RG_VRF18_1_VOTRIM_MASK                      0xF
#define PMIC_RG_VRF18_1_VOTRIM_SHIFT                     0
#define PMIC_RGS_VRF18_1_CAL_INDI_ADDR                   MT6355_SLDO20_ANA_CON1
#define PMIC_RGS_VRF18_1_CAL_INDI_MASK                   0x1
#define PMIC_RGS_VRF18_1_CAL_INDI_SHIFT                  4
#define PMIC_RG_VRF18_1_OC_TRIM_ADDR                     MT6355_SLDO20_ANA_CON1
#define PMIC_RG_VRF18_1_OC_TRIM_MASK                     0x7
#define PMIC_RG_VRF18_1_OC_TRIM_SHIFT                    8
#define PMIC_RG_VRF18_1_NDIS_EN_ADDR                     MT6355_SLDO20_ANA_CON1
#define PMIC_RG_VRF18_1_NDIS_EN_MASK                     0x1
#define PMIC_RG_VRF18_1_NDIS_EN_SHIFT                    11
#define PMIC_RG_VRF18_1_STB_SEL_ADDR                     MT6355_SLDO20_ANA_CON1
#define PMIC_RG_VRF18_1_STB_SEL_MASK                     0x1
#define PMIC_RG_VRF18_1_STB_SEL_SHIFT                    12
#define PMIC_RG_VRF18_1_RSV_ADDR                         MT6355_SLDO20_ANA_CON1
#define PMIC_RG_VRF18_1_RSV_MASK                         0x3
#define PMIC_RG_VRF18_1_RSV_SHIFT                        13
#define PMIC_RG_VRF18_1_VOS_CAL_EN_ADDR                  MT6355_SLDO20_ANA_CON1
#define PMIC_RG_VRF18_1_VOS_CAL_EN_MASK                  0x1
#define PMIC_RG_VRF18_1_VOS_CAL_EN_SHIFT                 15
#define PMIC_RG_VRF18_2_VOCAL_ADDR                       MT6355_SLDO20_ANA_CON2
#define PMIC_RG_VRF18_2_VOCAL_MASK                       0xF
#define PMIC_RG_VRF18_2_VOCAL_SHIFT                      0
#define PMIC_RG_VRF18_2_VOSEL_ADDR                       MT6355_SLDO20_ANA_CON2
#define PMIC_RG_VRF18_2_VOSEL_MASK                       0xF
#define PMIC_RG_VRF18_2_VOSEL_SHIFT                      8
#define PMIC_RG_VRF18_2_VOTRIM_ADDR                      MT6355_SLDO20_ANA_CON3
#define PMIC_RG_VRF18_2_VOTRIM_MASK                      0xF
#define PMIC_RG_VRF18_2_VOTRIM_SHIFT                     0
#define PMIC_RGS_VRF18_2_CAL_INDI_ADDR                   MT6355_SLDO20_ANA_CON3
#define PMIC_RGS_VRF18_2_CAL_INDI_MASK                   0x1
#define PMIC_RGS_VRF18_2_CAL_INDI_SHIFT                  4
#define PMIC_RG_VRF18_2_OC_TRIM_ADDR                     MT6355_SLDO20_ANA_CON3
#define PMIC_RG_VRF18_2_OC_TRIM_MASK                     0x7
#define PMIC_RG_VRF18_2_OC_TRIM_SHIFT                    8
#define PMIC_RG_VRF18_2_NDIS_EN_ADDR                     MT6355_SLDO20_ANA_CON3
#define PMIC_RG_VRF18_2_NDIS_EN_MASK                     0x1
#define PMIC_RG_VRF18_2_NDIS_EN_SHIFT                    11
#define PMIC_RG_VRF18_2_STB_SEL_ADDR                     MT6355_SLDO20_ANA_CON3
#define PMIC_RG_VRF18_2_STB_SEL_MASK                     0x1
#define PMIC_RG_VRF18_2_STB_SEL_SHIFT                    12
#define PMIC_RG_VRF18_2_RSV_ADDR                         MT6355_SLDO20_ANA_CON3
#define PMIC_RG_VRF18_2_RSV_MASK                         0x3
#define PMIC_RG_VRF18_2_RSV_SHIFT                        13
#define PMIC_RG_VRF18_2_VOS_CAL_EN_ADDR                  MT6355_SLDO20_ANA_CON3
#define PMIC_RG_VRF18_2_VOS_CAL_EN_MASK                  0x1
#define PMIC_RG_VRF18_2_VOS_CAL_EN_SHIFT                 15
#define PMIC_RG_VCN18_VOCAL_ADDR                         MT6355_SLDO20_ANA_CON4
#define PMIC_RG_VCN18_VOCAL_MASK                         0xF
#define PMIC_RG_VCN18_VOCAL_SHIFT                        0
#define PMIC_RG_VCN18_VOSEL_ADDR                         MT6355_SLDO20_ANA_CON4
#define PMIC_RG_VCN18_VOSEL_MASK                         0xF
#define PMIC_RG_VCN18_VOSEL_SHIFT                        8
#define PMIC_RG_VCN18_VOTRIM_ADDR                        MT6355_SLDO20_ANA_CON5
#define PMIC_RG_VCN18_VOTRIM_MASK                        0xF
#define PMIC_RG_VCN18_VOTRIM_SHIFT                       0
#define PMIC_RGS_VCN18_CAL_INDI_ADDR                     MT6355_SLDO20_ANA_CON5
#define PMIC_RGS_VCN18_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VCN18_CAL_INDI_SHIFT                    4
#define PMIC_RG_VCN18_OC_TRIM_ADDR                       MT6355_SLDO20_ANA_CON5
#define PMIC_RG_VCN18_OC_TRIM_MASK                       0x7
#define PMIC_RG_VCN18_OC_TRIM_SHIFT                      8
#define PMIC_RG_VCN18_NDIS_EN_ADDR                       MT6355_SLDO20_ANA_CON5
#define PMIC_RG_VCN18_NDIS_EN_MASK                       0x1
#define PMIC_RG_VCN18_NDIS_EN_SHIFT                      11
#define PMIC_RG_VCN18_STB_SEL_ADDR                       MT6355_SLDO20_ANA_CON5
#define PMIC_RG_VCN18_STB_SEL_MASK                       0x1
#define PMIC_RG_VCN18_STB_SEL_SHIFT                      12
#define PMIC_RG_VCN18_RSV_ADDR                           MT6355_SLDO20_ANA_CON5
#define PMIC_RG_VCN18_RSV_MASK                           0x3
#define PMIC_RG_VCN18_RSV_SHIFT                          13
#define PMIC_RG_VCN18_VOS_CAL_EN_ADDR                    MT6355_SLDO20_ANA_CON5
#define PMIC_RG_VCN18_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VCN18_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VCAMIO_VOCAL_ADDR                        MT6355_SLDO20_ANA_CON6
#define PMIC_RG_VCAMIO_VOCAL_MASK                        0xF
#define PMIC_RG_VCAMIO_VOCAL_SHIFT                       0
#define PMIC_RG_VCAMIO_VOSEL_ADDR                        MT6355_SLDO20_ANA_CON6
#define PMIC_RG_VCAMIO_VOSEL_MASK                        0xF
#define PMIC_RG_VCAMIO_VOSEL_SHIFT                       8
#define PMIC_RG_VCAMIO_VOTRIM_ADDR                       MT6355_SLDO20_ANA_CON7
#define PMIC_RG_VCAMIO_VOTRIM_MASK                       0xF
#define PMIC_RG_VCAMIO_VOTRIM_SHIFT                      0
#define PMIC_RGS_VCAMIO_CAL_INDI_ADDR                    MT6355_SLDO20_ANA_CON7
#define PMIC_RGS_VCAMIO_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VCAMIO_CAL_INDI_SHIFT                   4
#define PMIC_RG_VCAMIO_OC_TRIM_ADDR                      MT6355_SLDO20_ANA_CON7
#define PMIC_RG_VCAMIO_OC_TRIM_MASK                      0x7
#define PMIC_RG_VCAMIO_OC_TRIM_SHIFT                     8
#define PMIC_RG_VCAMIO_NDIS_EN_ADDR                      MT6355_SLDO20_ANA_CON7
#define PMIC_RG_VCAMIO_NDIS_EN_MASK                      0x1
#define PMIC_RG_VCAMIO_NDIS_EN_SHIFT                     11
#define PMIC_RG_VCAMIO_STB_SEL_ADDR                      MT6355_SLDO20_ANA_CON7
#define PMIC_RG_VCAMIO_STB_SEL_MASK                      0x1
#define PMIC_RG_VCAMIO_STB_SEL_SHIFT                     12
#define PMIC_RG_VCAMIO_RSV_ADDR                          MT6355_SLDO20_ANA_CON7
#define PMIC_RG_VCAMIO_RSV_MASK                          0x3
#define PMIC_RG_VCAMIO_RSV_SHIFT                         13
#define PMIC_RG_VCAMIO_VOS_CAL_EN_ADDR                   MT6355_SLDO20_ANA_CON7
#define PMIC_RG_VCAMIO_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VCAMIO_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VMIPI_VOCAL_ADDR                         MT6355_SLDO20_ANA_CON8
#define PMIC_RG_VMIPI_VOCAL_MASK                         0xF
#define PMIC_RG_VMIPI_VOCAL_SHIFT                        0
#define PMIC_RG_VMIPI_VOSEL_ADDR                         MT6355_SLDO20_ANA_CON8
#define PMIC_RG_VMIPI_VOSEL_MASK                         0xF
#define PMIC_RG_VMIPI_VOSEL_SHIFT                        8
#define PMIC_RG_VMIPI_VOTRIM_ADDR                        MT6355_SLDO20_ANA_CON9
#define PMIC_RG_VMIPI_VOTRIM_MASK                        0xF
#define PMIC_RG_VMIPI_VOTRIM_SHIFT                       0
#define PMIC_RGS_VMIPI_CAL_INDI_ADDR                     MT6355_SLDO20_ANA_CON9
#define PMIC_RGS_VMIPI_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VMIPI_CAL_INDI_SHIFT                    4
#define PMIC_RG_VMIPI_OC_TRIM_ADDR                       MT6355_SLDO20_ANA_CON9
#define PMIC_RG_VMIPI_OC_TRIM_MASK                       0x7
#define PMIC_RG_VMIPI_OC_TRIM_SHIFT                      8
#define PMIC_RG_VMIPI_NDIS_EN_ADDR                       MT6355_SLDO20_ANA_CON9
#define PMIC_RG_VMIPI_NDIS_EN_MASK                       0x1
#define PMIC_RG_VMIPI_NDIS_EN_SHIFT                      11
#define PMIC_RG_VMIPI_STB_SEL_ADDR                       MT6355_SLDO20_ANA_CON9
#define PMIC_RG_VMIPI_STB_SEL_MASK                       0x1
#define PMIC_RG_VMIPI_STB_SEL_SHIFT                      12
#define PMIC_RG_VMIPI_RSV_ADDR                           MT6355_SLDO20_ANA_CON9
#define PMIC_RG_VMIPI_RSV_MASK                           0x3
#define PMIC_RG_VMIPI_RSV_SHIFT                          13
#define PMIC_RG_VMIPI_VOS_CAL_EN_ADDR                    MT6355_SLDO20_ANA_CON9
#define PMIC_RG_VMIPI_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VMIPI_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VUFS18_VOCAL_ADDR                        MT6355_SLDO20_ANA_CON10
#define PMIC_RG_VUFS18_VOCAL_MASK                        0xF
#define PMIC_RG_VUFS18_VOCAL_SHIFT                       0
#define PMIC_RG_VUFS18_VOSEL_ADDR                        MT6355_SLDO20_ANA_CON10
#define PMIC_RG_VUFS18_VOSEL_MASK                        0xF
#define PMIC_RG_VUFS18_VOSEL_SHIFT                       8
#define PMIC_RG_VUFS18_VOTRIM_ADDR                       MT6355_SLDO20_ANA_CON11
#define PMIC_RG_VUFS18_VOTRIM_MASK                       0xF
#define PMIC_RG_VUFS18_VOTRIM_SHIFT                      0
#define PMIC_RGS_VUFS18_CAL_INDI_ADDR                    MT6355_SLDO20_ANA_CON11
#define PMIC_RGS_VUFS18_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VUFS18_CAL_INDI_SHIFT                   4
#define PMIC_RG_VUFS18_OC_TRIM_ADDR                      MT6355_SLDO20_ANA_CON11
#define PMIC_RG_VUFS18_OC_TRIM_MASK                      0x7
#define PMIC_RG_VUFS18_OC_TRIM_SHIFT                     8
#define PMIC_RG_VUFS18_NDIS_EN_ADDR                      MT6355_SLDO20_ANA_CON11
#define PMIC_RG_VUFS18_NDIS_EN_MASK                      0x1
#define PMIC_RG_VUFS18_NDIS_EN_SHIFT                     11
#define PMIC_RG_VUFS18_STB_SEL_ADDR                      MT6355_SLDO20_ANA_CON11
#define PMIC_RG_VUFS18_STB_SEL_MASK                      0x1
#define PMIC_RG_VUFS18_STB_SEL_SHIFT                     12
#define PMIC_RG_VUFS18_RSV_ADDR                          MT6355_SLDO20_ANA_CON11
#define PMIC_RG_VUFS18_RSV_MASK                          0x3
#define PMIC_RG_VUFS18_RSV_SHIFT                         13
#define PMIC_RG_VUFS18_VOS_CAL_EN_ADDR                   MT6355_SLDO20_ANA_CON11
#define PMIC_RG_VUFS18_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VUFS18_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VIO18_VOCAL_ADDR                         MT6355_SLDO20_ANA_CON12
#define PMIC_RG_VIO18_VOCAL_MASK                         0xF
#define PMIC_RG_VIO18_VOCAL_SHIFT                        0
#define PMIC_RG_VIO18_VOSEL_ADDR                         MT6355_SLDO20_ANA_CON12
#define PMIC_RG_VIO18_VOSEL_MASK                         0xF
#define PMIC_RG_VIO18_VOSEL_SHIFT                        8
#define PMIC_RG_VIO18_VOTRIM_ADDR                        MT6355_SLDO20_ANA_CON13
#define PMIC_RG_VIO18_VOTRIM_MASK                        0xF
#define PMIC_RG_VIO18_VOTRIM_SHIFT                       0
#define PMIC_RGS_VIO18_CAL_INDI_ADDR                     MT6355_SLDO20_ANA_CON13
#define PMIC_RGS_VIO18_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VIO18_CAL_INDI_SHIFT                    4
#define PMIC_RG_VIO18_OC_TRIM_ADDR                       MT6355_SLDO20_ANA_CON13
#define PMIC_RG_VIO18_OC_TRIM_MASK                       0x7
#define PMIC_RG_VIO18_OC_TRIM_SHIFT                      8
#define PMIC_RG_VIO18_NDIS_EN_ADDR                       MT6355_SLDO20_ANA_CON13
#define PMIC_RG_VIO18_NDIS_EN_MASK                       0x1
#define PMIC_RG_VIO18_NDIS_EN_SHIFT                      11
#define PMIC_RG_VIO18_STB_SEL_ADDR                       MT6355_SLDO20_ANA_CON13
#define PMIC_RG_VIO18_STB_SEL_MASK                       0x1
#define PMIC_RG_VIO18_STB_SEL_SHIFT                      12
#define PMIC_RG_VIO18_RSV_ADDR                           MT6355_SLDO20_ANA_CON13
#define PMIC_RG_VIO18_RSV_MASK                           0x3
#define PMIC_RG_VIO18_RSV_SHIFT                          13
#define PMIC_RG_VIO18_VOS_CAL_EN_ADDR                    MT6355_SLDO20_ANA_CON13
#define PMIC_RG_VIO18_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VIO18_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VXO18_VOCAL_ADDR                         MT6355_SLDO20_ANA_CON14
#define PMIC_RG_VXO18_VOCAL_MASK                         0xF
#define PMIC_RG_VXO18_VOCAL_SHIFT                        0
#define PMIC_RG_VXO18_VOSEL_ADDR                         MT6355_SLDO20_ANA_CON14
#define PMIC_RG_VXO18_VOSEL_MASK                         0xF
#define PMIC_RG_VXO18_VOSEL_SHIFT                        8
#define PMIC_RG_VXO18_VOTRIM_ADDR                        MT6355_SLDO20_ANA_CON15
#define PMIC_RG_VXO18_VOTRIM_MASK                        0xF
#define PMIC_RG_VXO18_VOTRIM_SHIFT                       0
#define PMIC_RGS_VXO18_CAL_INDI_ADDR                     MT6355_SLDO20_ANA_CON15
#define PMIC_RGS_VXO18_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VXO18_CAL_INDI_SHIFT                    4
#define PMIC_RG_VXO18_OC_TRIM_ADDR                       MT6355_SLDO20_ANA_CON15
#define PMIC_RG_VXO18_OC_TRIM_MASK                       0x7
#define PMIC_RG_VXO18_OC_TRIM_SHIFT                      8
#define PMIC_RG_VXO18_NDIS_EN_ADDR                       MT6355_SLDO20_ANA_CON15
#define PMIC_RG_VXO18_NDIS_EN_MASK                       0x1
#define PMIC_RG_VXO18_NDIS_EN_SHIFT                      11
#define PMIC_RG_VXO18_STB_SEL_ADDR                       MT6355_SLDO20_ANA_CON15
#define PMIC_RG_VXO18_STB_SEL_MASK                       0x1
#define PMIC_RG_VXO18_STB_SEL_SHIFT                      12
#define PMIC_RG_VXO18_RSV_ADDR                           MT6355_SLDO20_ANA_CON15
#define PMIC_RG_VXO18_RSV_MASK                           0x3
#define PMIC_RG_VXO18_RSV_SHIFT                          13
#define PMIC_RG_VXO18_VOS_CAL_EN_ADDR                    MT6355_SLDO20_ANA_CON15
#define PMIC_RG_VXO18_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VXO18_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VRF12_VOCAL_ADDR                         MT6355_SLDO14_ANA_CON0
#define PMIC_RG_VRF12_VOCAL_MASK                         0xF
#define PMIC_RG_VRF12_VOCAL_SHIFT                        0
#define PMIC_RG_VRF12_VOSEL_ADDR                         MT6355_SLDO14_ANA_CON0
#define PMIC_RG_VRF12_VOSEL_MASK                         0xF
#define PMIC_RG_VRF12_VOSEL_SHIFT                        8
#define PMIC_RG_VRF12_VOTRIM_ADDR                        MT6355_SLDO14_ANA_CON1
#define PMIC_RG_VRF12_VOTRIM_MASK                        0xF
#define PMIC_RG_VRF12_VOTRIM_SHIFT                       0
#define PMIC_RGS_VRF12_CAL_INDI_ADDR                     MT6355_SLDO14_ANA_CON1
#define PMIC_RGS_VRF12_CAL_INDI_MASK                     0x1
#define PMIC_RGS_VRF12_CAL_INDI_SHIFT                    4
#define PMIC_RG_VRF12_OC_TRIM_ADDR                       MT6355_SLDO14_ANA_CON1
#define PMIC_RG_VRF12_OC_TRIM_MASK                       0x7
#define PMIC_RG_VRF12_OC_TRIM_SHIFT                      8
#define PMIC_RG_VRF12_NDIS_EN_ADDR                       MT6355_SLDO14_ANA_CON1
#define PMIC_RG_VRF12_NDIS_EN_MASK                       0x1
#define PMIC_RG_VRF12_NDIS_EN_SHIFT                      11
#define PMIC_RG_VRF12_STB_SEL_ADDR                       MT6355_SLDO14_ANA_CON1
#define PMIC_RG_VRF12_STB_SEL_MASK                       0x1
#define PMIC_RG_VRF12_STB_SEL_SHIFT                      12
#define PMIC_RG_VRF12_RSV_ADDR                           MT6355_SLDO14_ANA_CON1
#define PMIC_RG_VRF12_RSV_MASK                           0x3
#define PMIC_RG_VRF12_RSV_SHIFT                          13
#define PMIC_RG_VRF12_VOS_CAL_EN_ADDR                    MT6355_SLDO14_ANA_CON1
#define PMIC_RG_VRF12_VOS_CAL_EN_MASK                    0x1
#define PMIC_RG_VRF12_VOS_CAL_EN_SHIFT                   15
#define PMIC_RG_VCAMD1_VOCAL_ADDR                        MT6355_SLDO14_ANA_CON2
#define PMIC_RG_VCAMD1_VOCAL_MASK                        0xF
#define PMIC_RG_VCAMD1_VOCAL_SHIFT                       0
#define PMIC_RG_VCAMD1_VOSEL_ADDR                        MT6355_SLDO14_ANA_CON2
#define PMIC_RG_VCAMD1_VOSEL_MASK                        0xF
#define PMIC_RG_VCAMD1_VOSEL_SHIFT                       8
#define PMIC_RG_VCAMD1_VOTRIM_ADDR                       MT6355_SLDO14_ANA_CON3
#define PMIC_RG_VCAMD1_VOTRIM_MASK                       0xF
#define PMIC_RG_VCAMD1_VOTRIM_SHIFT                      0
#define PMIC_RGS_VCAMD1_CAL_INDI_ADDR                    MT6355_SLDO14_ANA_CON3
#define PMIC_RGS_VCAMD1_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VCAMD1_CAL_INDI_SHIFT                   4
#define PMIC_RG_VCAMD1_OC_TRIM_ADDR                      MT6355_SLDO14_ANA_CON3
#define PMIC_RG_VCAMD1_OC_TRIM_MASK                      0x7
#define PMIC_RG_VCAMD1_OC_TRIM_SHIFT                     8
#define PMIC_RG_VCAMD1_NDIS_EN_ADDR                      MT6355_SLDO14_ANA_CON3
#define PMIC_RG_VCAMD1_NDIS_EN_MASK                      0x1
#define PMIC_RG_VCAMD1_NDIS_EN_SHIFT                     11
#define PMIC_RG_VCAMD1_STB_SEL_ADDR                      MT6355_SLDO14_ANA_CON3
#define PMIC_RG_VCAMD1_STB_SEL_MASK                      0x1
#define PMIC_RG_VCAMD1_STB_SEL_SHIFT                     12
#define PMIC_RG_VCAMD1_RSV_ADDR                          MT6355_SLDO14_ANA_CON3
#define PMIC_RG_VCAMD1_RSV_MASK                          0x3
#define PMIC_RG_VCAMD1_RSV_SHIFT                         13
#define PMIC_RG_VCAMD1_VOS_CAL_EN_ADDR                   MT6355_SLDO14_ANA_CON3
#define PMIC_RG_VCAMD1_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VCAMD1_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VCAMD2_VOCAL_ADDR                        MT6355_SLDO14_ANA_CON4
#define PMIC_RG_VCAMD2_VOCAL_MASK                        0xF
#define PMIC_RG_VCAMD2_VOCAL_SHIFT                       0
#define PMIC_RG_VCAMD2_VOSEL_ADDR                        MT6355_SLDO14_ANA_CON4
#define PMIC_RG_VCAMD2_VOSEL_MASK                        0xF
#define PMIC_RG_VCAMD2_VOSEL_SHIFT                       8
#define PMIC_RG_VCAMD2_VOTRIM_ADDR                       MT6355_SLDO14_ANA_CON5
#define PMIC_RG_VCAMD2_VOTRIM_MASK                       0xF
#define PMIC_RG_VCAMD2_VOTRIM_SHIFT                      0
#define PMIC_RGS_VCAMD2_CAL_INDI_ADDR                    MT6355_SLDO14_ANA_CON5
#define PMIC_RGS_VCAMD2_CAL_INDI_MASK                    0x1
#define PMIC_RGS_VCAMD2_CAL_INDI_SHIFT                   4
#define PMIC_RG_VCAMD2_OC_TRIM_ADDR                      MT6355_SLDO14_ANA_CON5
#define PMIC_RG_VCAMD2_OC_TRIM_MASK                      0x7
#define PMIC_RG_VCAMD2_OC_TRIM_SHIFT                     8
#define PMIC_RG_VCAMD2_NDIS_EN_ADDR                      MT6355_SLDO14_ANA_CON5
#define PMIC_RG_VCAMD2_NDIS_EN_MASK                      0x1
#define PMIC_RG_VCAMD2_NDIS_EN_SHIFT                     11
#define PMIC_RG_VCAMD2_STB_SEL_ADDR                      MT6355_SLDO14_ANA_CON5
#define PMIC_RG_VCAMD2_STB_SEL_MASK                      0x1
#define PMIC_RG_VCAMD2_STB_SEL_SHIFT                     12
#define PMIC_RG_VCAMD2_RSV_ADDR                          MT6355_SLDO14_ANA_CON5
#define PMIC_RG_VCAMD2_RSV_MASK                          0x3
#define PMIC_RG_VCAMD2_RSV_SHIFT                         13
#define PMIC_RG_VCAMD2_VOS_CAL_EN_ADDR                   MT6355_SLDO14_ANA_CON5
#define PMIC_RG_VCAMD2_VOS_CAL_EN_MASK                   0x1
#define PMIC_RG_VCAMD2_VOS_CAL_EN_SHIFT                  15
#define PMIC_RG_VA10_VOTRIM_ADDR                         MT6355_SLDO14_ANA_CON6
#define PMIC_RG_VA10_VOTRIM_MASK                         0xF
#define PMIC_RG_VA10_VOTRIM_SHIFT                        0
#define PMIC_RGS_VA10_CAL_INDI_ADDR                      MT6355_SLDO14_ANA_CON6
#define PMIC_RGS_VA10_CAL_INDI_MASK                      0x1
#define PMIC_RGS_VA10_CAL_INDI_SHIFT                     4
#define PMIC_RG_VA10_OC_TRIM_ADDR                        MT6355_SLDO14_ANA_CON6
#define PMIC_RG_VA10_OC_TRIM_MASK                        0x7
#define PMIC_RG_VA10_OC_TRIM_SHIFT                       8
#define PMIC_RG_VA10_NDIS_EN_ADDR                        MT6355_SLDO14_ANA_CON6
#define PMIC_RG_VA10_NDIS_EN_MASK                        0x1
#define PMIC_RG_VA10_NDIS_EN_SHIFT                       11
#define PMIC_RG_VA10_STB_SEL_ADDR                        MT6355_SLDO14_ANA_CON6
#define PMIC_RG_VA10_STB_SEL_MASK                        0x1
#define PMIC_RG_VA10_STB_SEL_SHIFT                       12
#define PMIC_RG_VA10_RSV_ADDR                            MT6355_SLDO14_ANA_CON6
#define PMIC_RG_VA10_RSV_MASK                            0x3
#define PMIC_RG_VA10_RSV_SHIFT                           13
#define PMIC_RG_VA10_VOS_CAL_EN_ADDR                     MT6355_SLDO14_ANA_CON6
#define PMIC_RG_VA10_VOS_CAL_EN_MASK                     0x1
#define PMIC_RG_VA10_VOS_CAL_EN_SHIFT                    15
#define PMIC_RG_VA12_VOCAL_ADDR                          MT6355_SLDO14_ANA_CON7
#define PMIC_RG_VA12_VOCAL_MASK                          0xF
#define PMIC_RG_VA12_VOCAL_SHIFT                         0
#define PMIC_RG_VA12_VOSEL_ADDR                          MT6355_SLDO14_ANA_CON7
#define PMIC_RG_VA12_VOSEL_MASK                          0xF
#define PMIC_RG_VA12_VOSEL_SHIFT                         8
#define PMIC_RG_VA12_VOTRIM_ADDR                         MT6355_SLDO14_ANA_CON8
#define PMIC_RG_VA12_VOTRIM_MASK                         0xF
#define PMIC_RG_VA12_VOTRIM_SHIFT                        0
#define PMIC_RGS_VA12_CAL_INDI_ADDR                      MT6355_SLDO14_ANA_CON8
#define PMIC_RGS_VA12_CAL_INDI_MASK                      0x1
#define PMIC_RGS_VA12_CAL_INDI_SHIFT                     4
#define PMIC_RG_VA12_OC_TRIM_ADDR                        MT6355_SLDO14_ANA_CON8
#define PMIC_RG_VA12_OC_TRIM_MASK                        0x7
#define PMIC_RG_VA12_OC_TRIM_SHIFT                       8
#define PMIC_RG_VA12_NDIS_EN_ADDR                        MT6355_SLDO14_ANA_CON8
#define PMIC_RG_VA12_NDIS_EN_MASK                        0x1
#define PMIC_RG_VA12_NDIS_EN_SHIFT                       11
#define PMIC_RG_VA12_STB_SEL_ADDR                        MT6355_SLDO14_ANA_CON8
#define PMIC_RG_VA12_STB_SEL_MASK                        0x1
#define PMIC_RG_VA12_STB_SEL_SHIFT                       12
#define PMIC_RG_VA12_RSV_ADDR                            MT6355_SLDO14_ANA_CON8
#define PMIC_RG_VA12_RSV_MASK                            0x3
#define PMIC_RG_VA12_RSV_SHIFT                           13
#define PMIC_RG_VA12_VOS_CAL_EN_ADDR                     MT6355_SLDO14_ANA_CON8
#define PMIC_RG_VA12_VOS_CAL_EN_MASK                     0x1
#define PMIC_RG_VA12_VOS_CAL_EN_SHIFT                    15
#define PMIC_RG_VSRAM_PROC_OC_TRIM_ADDR                  MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_OC_TRIM_MASK                  0xF
#define PMIC_RG_VSRAM_PROC_OC_TRIM_SHIFT                 0
#define PMIC_RG_VSRAM_PROC_STB_SEL_ADDR                  MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_STB_SEL_MASK                  0x1
#define PMIC_RG_VSRAM_PROC_STB_SEL_SHIFT                 4
#define PMIC_RG_VSRAM_PROC_NDIS_EN_ADDR                  MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_NDIS_EN_MASK                  0x1
#define PMIC_RG_VSRAM_PROC_NDIS_EN_SHIFT                 5
#define PMIC_RG_VSRAM_PROC_NDIS_PLCUR_ADDR               MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_NDIS_PLCUR_MASK               0x3
#define PMIC_RG_VSRAM_PROC_NDIS_PLCUR_SHIFT              6
#define PMIC_RG_VSRAM_PROC_PLCUR_EN_ADDR                 MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_PLCUR_EN_MASK                 0x1
#define PMIC_RG_VSRAM_PROC_PLCUR_EN_SHIFT                8
#define PMIC_RG_VSRAM_PROC_RSV_H_ADDR                    MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_RSV_H_MASK                    0x7
#define PMIC_RG_VSRAM_PROC_RSV_H_SHIFT                   9
#define PMIC_RG_VSRAM_PROC_RSV_L_ADDR                    MT6355_SLDO14_ANA_CON9
#define PMIC_RG_VSRAM_PROC_RSV_L_MASK                    0x7
#define PMIC_RG_VSRAM_PROC_RSV_L_SHIFT                   12
#define PMIC_RG_VSRAM_CORE_OC_TRIM_ADDR                  MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_OC_TRIM_MASK                  0xF
#define PMIC_RG_VSRAM_CORE_OC_TRIM_SHIFT                 0
#define PMIC_RG_VSRAM_CORE_STB_SEL_ADDR                  MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_STB_SEL_MASK                  0x1
#define PMIC_RG_VSRAM_CORE_STB_SEL_SHIFT                 4
#define PMIC_RG_VSRAM_CORE_NDIS_EN_ADDR                  MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_NDIS_EN_MASK                  0x1
#define PMIC_RG_VSRAM_CORE_NDIS_EN_SHIFT                 5
#define PMIC_RG_VSRAM_CORE_NDIS_PLCUR_ADDR               MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_NDIS_PLCUR_MASK               0x3
#define PMIC_RG_VSRAM_CORE_NDIS_PLCUR_SHIFT              6
#define PMIC_RG_VSRAM_CORE_PLCUR_EN_ADDR                 MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_PLCUR_EN_MASK                 0x1
#define PMIC_RG_VSRAM_CORE_PLCUR_EN_SHIFT                8
#define PMIC_RG_VSRAM_CORE_RSV_H_ADDR                    MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_RSV_H_MASK                    0x7
#define PMIC_RG_VSRAM_CORE_RSV_H_SHIFT                   9
#define PMIC_RG_VSRAM_CORE_RSV_L_ADDR                    MT6355_SLDO14_ANA_CON10
#define PMIC_RG_VSRAM_CORE_RSV_L_MASK                    0x7
#define PMIC_RG_VSRAM_CORE_RSV_L_SHIFT                   12
#define PMIC_RG_VSRAM_GPU_OC_TRIM_ADDR                   MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_OC_TRIM_MASK                   0xF
#define PMIC_RG_VSRAM_GPU_OC_TRIM_SHIFT                  0
#define PMIC_RG_VSRAM_GPU_STB_SEL_ADDR                   MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_STB_SEL_MASK                   0x1
#define PMIC_RG_VSRAM_GPU_STB_SEL_SHIFT                  4
#define PMIC_RG_VSRAM_GPU_NDIS_EN_ADDR                   MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_NDIS_EN_MASK                   0x1
#define PMIC_RG_VSRAM_GPU_NDIS_EN_SHIFT                  5
#define PMIC_RG_VSRAM_GPU_NDIS_PLCUR_ADDR                MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_NDIS_PLCUR_MASK                0x3
#define PMIC_RG_VSRAM_GPU_NDIS_PLCUR_SHIFT               6
#define PMIC_RG_VSRAM_GPU_PLCUR_EN_ADDR                  MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_PLCUR_EN_MASK                  0x1
#define PMIC_RG_VSRAM_GPU_PLCUR_EN_SHIFT                 8
#define PMIC_RG_VSRAM_GPU_RSV_H_ADDR                     MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_RSV_H_MASK                     0x7
#define PMIC_RG_VSRAM_GPU_RSV_H_SHIFT                    9
#define PMIC_RG_VSRAM_GPU_RSV_L_ADDR                     MT6355_SLDO14_ANA_CON11
#define PMIC_RG_VSRAM_GPU_RSV_L_MASK                     0x7
#define PMIC_RG_VSRAM_GPU_RSV_L_SHIFT                    12
#define PMIC_RG_VSRAM_MD_OC_TRIM_ADDR                    MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_OC_TRIM_MASK                    0xF
#define PMIC_RG_VSRAM_MD_OC_TRIM_SHIFT                   0
#define PMIC_RG_VSRAM_MD_STB_SEL_ADDR                    MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_STB_SEL_MASK                    0x1
#define PMIC_RG_VSRAM_MD_STB_SEL_SHIFT                   4
#define PMIC_RG_VSRAM_MD_NDIS_EN_ADDR                    MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_NDIS_EN_MASK                    0x1
#define PMIC_RG_VSRAM_MD_NDIS_EN_SHIFT                   5
#define PMIC_RG_VSRAM_MD_NDIS_PLCUR_ADDR                 MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_NDIS_PLCUR_MASK                 0x3
#define PMIC_RG_VSRAM_MD_NDIS_PLCUR_SHIFT                6
#define PMIC_RG_VSRAM_MD_PLCUR_EN_ADDR                   MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_PLCUR_EN_MASK                   0x1
#define PMIC_RG_VSRAM_MD_PLCUR_EN_SHIFT                  8
#define PMIC_RG_VSRAM_MD_RSV_H_ADDR                      MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_RSV_H_MASK                      0x7
#define PMIC_RG_VSRAM_MD_RSV_H_SHIFT                     9
#define PMIC_RG_VSRAM_MD_RSV_L_ADDR                      MT6355_SLDO14_ANA_CON12
#define PMIC_RG_VSRAM_MD_RSV_L_MASK                      0x7
#define PMIC_RG_VSRAM_MD_RSV_L_SHIFT                     12
#define PMIC_AUDACCDETAUXADCSWCTRL_ADDR                  MT6355_ACCDET_CON0
#define PMIC_AUDACCDETAUXADCSWCTRL_MASK                  0x1
#define PMIC_AUDACCDETAUXADCSWCTRL_SHIFT                 10
#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_ADDR              MT6355_ACCDET_CON0
#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_MASK              0x1
#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT             11
#define PMIC_RG_AUDACCDETRSV_ADDR                        MT6355_ACCDET_CON0
#define PMIC_RG_AUDACCDETRSV_MASK                        0x3
#define PMIC_RG_AUDACCDETRSV_SHIFT                       13
#define PMIC_ACCDET_EN_ADDR                              MT6355_ACCDET_CON1
#define PMIC_ACCDET_EN_MASK                              0x1
#define PMIC_ACCDET_EN_SHIFT                             0
#define PMIC_ACCDET_SEQ_INIT_ADDR                        MT6355_ACCDET_CON1
#define PMIC_ACCDET_SEQ_INIT_MASK                        0x1
#define PMIC_ACCDET_SEQ_INIT_SHIFT                       1
#define PMIC_ACCDET_EINTDET_EN_ADDR                      MT6355_ACCDET_CON1
#define PMIC_ACCDET_EINTDET_EN_MASK                      0x1
#define PMIC_ACCDET_EINTDET_EN_SHIFT                     2
#define PMIC_ACCDET_EINT_SEQ_INIT_ADDR                   MT6355_ACCDET_CON1
#define PMIC_ACCDET_EINT_SEQ_INIT_MASK                   0x1
#define PMIC_ACCDET_EINT_SEQ_INIT_SHIFT                  3
#define PMIC_ACCDET_ANASWCTRL_SEL_ADDR                   MT6355_ACCDET_CON1
#define PMIC_ACCDET_ANASWCTRL_SEL_MASK                   0x1
#define PMIC_ACCDET_ANASWCTRL_SEL_SHIFT                  6
#define PMIC_ACCDET_CMP_PWM_EN_ADDR                      MT6355_ACCDET_CON2
#define PMIC_ACCDET_CMP_PWM_EN_MASK                      0x1
#define PMIC_ACCDET_CMP_PWM_EN_SHIFT                     0
#define PMIC_ACCDET_VTH_PWM_EN_ADDR                      MT6355_ACCDET_CON2
#define PMIC_ACCDET_VTH_PWM_EN_MASK                      0x1
#define PMIC_ACCDET_VTH_PWM_EN_SHIFT                     1
#define PMIC_ACCDET_MBIAS_PWM_EN_ADDR                    MT6355_ACCDET_CON2
#define PMIC_ACCDET_MBIAS_PWM_EN_MASK                    0x1
#define PMIC_ACCDET_MBIAS_PWM_EN_SHIFT                   2
#define PMIC_ACCDET_EINT_PWM_EN_ADDR                     MT6355_ACCDET_CON2
#define PMIC_ACCDET_EINT_PWM_EN_MASK                     0x1
#define PMIC_ACCDET_EINT_PWM_EN_SHIFT                    3
#define PMIC_ACCDET_CMP_PWM_IDLE_ADDR                    MT6355_ACCDET_CON2
#define PMIC_ACCDET_CMP_PWM_IDLE_MASK                    0x1
#define PMIC_ACCDET_CMP_PWM_IDLE_SHIFT                   4
#define PMIC_ACCDET_VTH_PWM_IDLE_ADDR                    MT6355_ACCDET_CON2
#define PMIC_ACCDET_VTH_PWM_IDLE_MASK                    0x1
#define PMIC_ACCDET_VTH_PWM_IDLE_SHIFT                   5
#define PMIC_ACCDET_MBIAS_PWM_IDLE_ADDR                  MT6355_ACCDET_CON2
#define PMIC_ACCDET_MBIAS_PWM_IDLE_MASK                  0x1
#define PMIC_ACCDET_MBIAS_PWM_IDLE_SHIFT                 6
#define PMIC_ACCDET_EINT_PWM_IDLE_ADDR                   MT6355_ACCDET_CON2
#define PMIC_ACCDET_EINT_PWM_IDLE_MASK                   0x1
#define PMIC_ACCDET_EINT_PWM_IDLE_SHIFT                  7
#define PMIC_ACCDET_PWM_WIDTH_ADDR                       MT6355_ACCDET_CON3
#define PMIC_ACCDET_PWM_WIDTH_MASK                       0xFFFF
#define PMIC_ACCDET_PWM_WIDTH_SHIFT                      0
#define PMIC_ACCDET_PWM_THRESH_ADDR                      MT6355_ACCDET_CON4
#define PMIC_ACCDET_PWM_THRESH_MASK                      0xFFFF
#define PMIC_ACCDET_PWM_THRESH_SHIFT                     0
#define PMIC_ACCDET_RISE_DELAY_ADDR                      MT6355_ACCDET_CON5
#define PMIC_ACCDET_RISE_DELAY_MASK                      0x7FFF
#define PMIC_ACCDET_RISE_DELAY_SHIFT                     0
#define PMIC_ACCDET_FALL_DELAY_ADDR                      MT6355_ACCDET_CON5
#define PMIC_ACCDET_FALL_DELAY_MASK                      0x1
#define PMIC_ACCDET_FALL_DELAY_SHIFT                     15
#define PMIC_ACCDET_DEBOUNCE0_ADDR                       MT6355_ACCDET_CON6
#define PMIC_ACCDET_DEBOUNCE0_MASK                       0xFFFF
#define PMIC_ACCDET_DEBOUNCE0_SHIFT                      0
#define PMIC_ACCDET_DEBOUNCE1_ADDR                       MT6355_ACCDET_CON7
#define PMIC_ACCDET_DEBOUNCE1_MASK                       0xFFFF
#define PMIC_ACCDET_DEBOUNCE1_SHIFT                      0
#define PMIC_ACCDET_DEBOUNCE2_ADDR                       MT6355_ACCDET_CON8
#define PMIC_ACCDET_DEBOUNCE2_MASK                       0xFFFF
#define PMIC_ACCDET_DEBOUNCE2_SHIFT                      0
#define PMIC_ACCDET_DEBOUNCE3_ADDR                       MT6355_ACCDET_CON9
#define PMIC_ACCDET_DEBOUNCE3_MASK                       0xFFFF
#define PMIC_ACCDET_DEBOUNCE3_SHIFT                      0
#define PMIC_ACCDET_DEBOUNCE4_ADDR                       MT6355_ACCDET_CON10
#define PMIC_ACCDET_DEBOUNCE4_MASK                       0xFFFF
#define PMIC_ACCDET_DEBOUNCE4_SHIFT                      0
#define PMIC_ACCDET_IVAL_CUR_IN_ADDR                     MT6355_ACCDET_CON11
#define PMIC_ACCDET_IVAL_CUR_IN_MASK                     0x3
#define PMIC_ACCDET_IVAL_CUR_IN_SHIFT                    0
#define PMIC_ACCDET_EINT_IVAL_CUR_IN_ADDR                MT6355_ACCDET_CON11
#define PMIC_ACCDET_EINT_IVAL_CUR_IN_MASK                0x1
#define PMIC_ACCDET_EINT_IVAL_CUR_IN_SHIFT               2
#define PMIC_ACCDET_IVAL_SAM_IN_ADDR                     MT6355_ACCDET_CON11
#define PMIC_ACCDET_IVAL_SAM_IN_MASK                     0x3
#define PMIC_ACCDET_IVAL_SAM_IN_SHIFT                    4
#define PMIC_ACCDET_EINT_IVAL_SAM_IN_ADDR                MT6355_ACCDET_CON11
#define PMIC_ACCDET_EINT_IVAL_SAM_IN_MASK                0x1
#define PMIC_ACCDET_EINT_IVAL_SAM_IN_SHIFT               6
#define PMIC_ACCDET_IVAL_MEM_IN_ADDR                     MT6355_ACCDET_CON11
#define PMIC_ACCDET_IVAL_MEM_IN_MASK                     0x3
#define PMIC_ACCDET_IVAL_MEM_IN_SHIFT                    8
#define PMIC_ACCDET_EINT_IVAL_MEM_IN_ADDR                MT6355_ACCDET_CON11
#define PMIC_ACCDET_EINT_IVAL_MEM_IN_MASK                0x1
#define PMIC_ACCDET_EINT_IVAL_MEM_IN_SHIFT               10
#define PMIC_ACCDET_EINT_IVAL_SEL_ADDR                   MT6355_ACCDET_CON11
#define PMIC_ACCDET_EINT_IVAL_SEL_MASK                   0x1
#define PMIC_ACCDET_EINT_IVAL_SEL_SHIFT                  14
#define PMIC_ACCDET_IVAL_SEL_ADDR                        MT6355_ACCDET_CON11
#define PMIC_ACCDET_IVAL_SEL_MASK                        0x1
#define PMIC_ACCDET_IVAL_SEL_SHIFT                       15
#define PMIC_ACCDET_IRQ_ADDR                             MT6355_ACCDET_CON12
#define PMIC_ACCDET_IRQ_MASK                             0x1
#define PMIC_ACCDET_IRQ_SHIFT                            0
#define PMIC_ACCDET_EINT_IRQ_ADDR                        MT6355_ACCDET_CON12
#define PMIC_ACCDET_EINT_IRQ_MASK                        0x1
#define PMIC_ACCDET_EINT_IRQ_SHIFT                       2
#define PMIC_ACCDET_IRQ_CLR_ADDR                         MT6355_ACCDET_CON12
#define PMIC_ACCDET_IRQ_CLR_MASK                         0x1
#define PMIC_ACCDET_IRQ_CLR_SHIFT                        8
#define PMIC_ACCDET_EINT_IRQ_CLR_ADDR                    MT6355_ACCDET_CON12
#define PMIC_ACCDET_EINT_IRQ_CLR_MASK                    0x1
#define PMIC_ACCDET_EINT_IRQ_CLR_SHIFT                   10
#define PMIC_ACCDET_EINT_IRQ_POLARITY_ADDR               MT6355_ACCDET_CON12
#define PMIC_ACCDET_EINT_IRQ_POLARITY_MASK               0x1
#define PMIC_ACCDET_EINT_IRQ_POLARITY_SHIFT              15
#define PMIC_ACCDET_TEST_MODE0_ADDR                      MT6355_ACCDET_CON13
#define PMIC_ACCDET_TEST_MODE0_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE0_SHIFT                     0
#define PMIC_ACCDET_CMP_SWSEL_ADDR                       MT6355_ACCDET_CON13
#define PMIC_ACCDET_CMP_SWSEL_MASK                       0x1
#define PMIC_ACCDET_CMP_SWSEL_SHIFT                      1
#define PMIC_ACCDET_VTH_SWSEL_ADDR                       MT6355_ACCDET_CON13
#define PMIC_ACCDET_VTH_SWSEL_MASK                       0x1
#define PMIC_ACCDET_VTH_SWSEL_SHIFT                      2
#define PMIC_ACCDET_MBIAS_SWSEL_ADDR                     MT6355_ACCDET_CON13
#define PMIC_ACCDET_MBIAS_SWSEL_MASK                     0x1
#define PMIC_ACCDET_MBIAS_SWSEL_SHIFT                    3
#define PMIC_ACCDET_TEST_MODE4_ADDR                      MT6355_ACCDET_CON13
#define PMIC_ACCDET_TEST_MODE4_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE4_SHIFT                     4
#define PMIC_ACCDET_TEST_MODE5_ADDR                      MT6355_ACCDET_CON13
#define PMIC_ACCDET_TEST_MODE5_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE5_SHIFT                     5
#define PMIC_ACCDET_PWM_SEL_ADDR                         MT6355_ACCDET_CON13
#define PMIC_ACCDET_PWM_SEL_MASK                         0x3
#define PMIC_ACCDET_PWM_SEL_SHIFT                        6
#define PMIC_ACCDET_IN_SW_ADDR                           MT6355_ACCDET_CON13
#define PMIC_ACCDET_IN_SW_MASK                           0x3
#define PMIC_ACCDET_IN_SW_SHIFT                          8
#define PMIC_ACCDET_CMP_EN_SW_ADDR                       MT6355_ACCDET_CON13
#define PMIC_ACCDET_CMP_EN_SW_MASK                       0x1
#define PMIC_ACCDET_CMP_EN_SW_SHIFT                      12
#define PMIC_ACCDET_VTH_EN_SW_ADDR                       MT6355_ACCDET_CON13
#define PMIC_ACCDET_VTH_EN_SW_MASK                       0x1
#define PMIC_ACCDET_VTH_EN_SW_SHIFT                      13
#define PMIC_ACCDET_MBIAS_EN_SW_ADDR                     MT6355_ACCDET_CON13
#define PMIC_ACCDET_MBIAS_EN_SW_MASK                     0x1
#define PMIC_ACCDET_MBIAS_EN_SW_SHIFT                    14
#define PMIC_ACCDET_PWM_EN_SW_ADDR                       MT6355_ACCDET_CON13
#define PMIC_ACCDET_PWM_EN_SW_MASK                       0x1
#define PMIC_ACCDET_PWM_EN_SW_SHIFT                      15
#define PMIC_ACCDET_IN_ADDR                              MT6355_ACCDET_CON14
#define PMIC_ACCDET_IN_MASK                              0x3
#define PMIC_ACCDET_IN_SHIFT                             0
#define PMIC_ACCDET_CUR_IN_ADDR                          MT6355_ACCDET_CON14
#define PMIC_ACCDET_CUR_IN_MASK                          0x3
#define PMIC_ACCDET_CUR_IN_SHIFT                         2
#define PMIC_ACCDET_SAM_IN_ADDR                          MT6355_ACCDET_CON14
#define PMIC_ACCDET_SAM_IN_MASK                          0x3
#define PMIC_ACCDET_SAM_IN_SHIFT                         4
#define PMIC_ACCDET_MEM_IN_ADDR                          MT6355_ACCDET_CON14
#define PMIC_ACCDET_MEM_IN_MASK                          0x3
#define PMIC_ACCDET_MEM_IN_SHIFT                         6
#define PMIC_ACCDET_STATE_ADDR                           MT6355_ACCDET_CON14
#define PMIC_ACCDET_STATE_MASK                           0x7
#define PMIC_ACCDET_STATE_SHIFT                          8
#define PMIC_ACCDET_MBIAS_CLK_ADDR                       MT6355_ACCDET_CON14
#define PMIC_ACCDET_MBIAS_CLK_MASK                       0x1
#define PMIC_ACCDET_MBIAS_CLK_SHIFT                      12
#define PMIC_ACCDET_VTH_CLK_ADDR                         MT6355_ACCDET_CON14
#define PMIC_ACCDET_VTH_CLK_MASK                         0x1
#define PMIC_ACCDET_VTH_CLK_SHIFT                        13
#define PMIC_ACCDET_CMP_CLK_ADDR                         MT6355_ACCDET_CON14
#define PMIC_ACCDET_CMP_CLK_MASK                         0x1
#define PMIC_ACCDET_CMP_CLK_SHIFT                        14
#define PMIC_DA_AUDACCDETAUXADCSWCTRL_ADDR               MT6355_ACCDET_CON14
#define PMIC_DA_AUDACCDETAUXADCSWCTRL_MASK               0x1
#define PMIC_DA_AUDACCDETAUXADCSWCTRL_SHIFT              15
#define PMIC_ACCDET_EINT_DEB_SEL_ADDR                    MT6355_ACCDET_CON15
#define PMIC_ACCDET_EINT_DEB_SEL_MASK                    0x1
#define PMIC_ACCDET_EINT_DEB_SEL_SHIFT                   0
#define PMIC_ACCDET_EINT_DEBOUNCE_ADDR                   MT6355_ACCDET_CON15
#define PMIC_ACCDET_EINT_DEBOUNCE_MASK                   0xF
#define PMIC_ACCDET_EINT_DEBOUNCE_SHIFT                  3
#define PMIC_ACCDET_EINT_PWM_THRESH_ADDR                 MT6355_ACCDET_CON15
#define PMIC_ACCDET_EINT_PWM_THRESH_MASK                 0x7
#define PMIC_ACCDET_EINT_PWM_THRESH_SHIFT                8
#define PMIC_ACCDET_EINT_PWM_WIDTH_ADDR                  MT6355_ACCDET_CON15
#define PMIC_ACCDET_EINT_PWM_WIDTH_MASK                  0x3
#define PMIC_ACCDET_EINT_PWM_WIDTH_SHIFT                 12
#define PMIC_ACCDET_EINT_PWM_FALL_DELAY_ADDR             MT6355_ACCDET_CON16
#define PMIC_ACCDET_EINT_PWM_FALL_DELAY_MASK             0x1
#define PMIC_ACCDET_EINT_PWM_FALL_DELAY_SHIFT            5
#define PMIC_ACCDET_EINT_PWM_RISE_DELAY_ADDR             MT6355_ACCDET_CON16
#define PMIC_ACCDET_EINT_PWM_RISE_DELAY_MASK             0x3FF
#define PMIC_ACCDET_EINT_PWM_RISE_DELAY_SHIFT            6
#define PMIC_ACCDET_TEST_MODE13_ADDR                     MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE13_MASK                     0x1
#define PMIC_ACCDET_TEST_MODE13_SHIFT                    1
#define PMIC_ACCDET_TEST_MODE12_ADDR                     MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE12_MASK                     0x1
#define PMIC_ACCDET_TEST_MODE12_SHIFT                    2
#define PMIC_ACCDET_TEST_MODE11_ADDR                     MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE11_MASK                     0x1
#define PMIC_ACCDET_TEST_MODE11_SHIFT                    5
#define PMIC_ACCDET_TEST_MODE10_ADDR                     MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE10_MASK                     0x1
#define PMIC_ACCDET_TEST_MODE10_SHIFT                    6
#define PMIC_ACCDET_EINTCMPOUT_SW_ADDR                   MT6355_ACCDET_CON17
#define PMIC_ACCDET_EINTCMPOUT_SW_MASK                   0x1
#define PMIC_ACCDET_EINTCMPOUT_SW_SHIFT                  7
#define PMIC_ACCDET_TEST_MODE9_ADDR                      MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE9_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE9_SHIFT                     9
#define PMIC_ACCDET_TEST_MODE8_ADDR                      MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE8_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE8_SHIFT                     10
#define PMIC_ACCDET_AUXADC_CTRL_SW_ADDR                  MT6355_ACCDET_CON17
#define PMIC_ACCDET_AUXADC_CTRL_SW_MASK                  0x1
#define PMIC_ACCDET_AUXADC_CTRL_SW_SHIFT                 11
#define PMIC_ACCDET_TEST_MODE7_ADDR                      MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE7_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE7_SHIFT                     13
#define PMIC_ACCDET_TEST_MODE6_ADDR                      MT6355_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE6_MASK                      0x1
#define PMIC_ACCDET_TEST_MODE6_SHIFT                     14
#define PMIC_ACCDET_EINTCMP_EN_SW_ADDR                   MT6355_ACCDET_CON17
#define PMIC_ACCDET_EINTCMP_EN_SW_MASK                   0x1
#define PMIC_ACCDET_EINTCMP_EN_SW_SHIFT                  15
#define PMIC_ACCDET_EINT_STATE_ADDR                      MT6355_ACCDET_CON18
#define PMIC_ACCDET_EINT_STATE_MASK                      0x7
#define PMIC_ACCDET_EINT_STATE_SHIFT                     0
#define PMIC_ACCDET_AUXADC_DEBOUNCE_END_ADDR             MT6355_ACCDET_CON18
#define PMIC_ACCDET_AUXADC_DEBOUNCE_END_MASK             0x1
#define PMIC_ACCDET_AUXADC_DEBOUNCE_END_SHIFT            3
#define PMIC_ACCDET_AUXADC_CONNECT_PRE_ADDR              MT6355_ACCDET_CON18
#define PMIC_ACCDET_AUXADC_CONNECT_PRE_MASK              0x1
#define PMIC_ACCDET_AUXADC_CONNECT_PRE_SHIFT             4
#define PMIC_ACCDET_EINT_CUR_IN_ADDR                     MT6355_ACCDET_CON18
#define PMIC_ACCDET_EINT_CUR_IN_MASK                     0x1
#define PMIC_ACCDET_EINT_CUR_IN_SHIFT                    8
#define PMIC_ACCDET_EINT_SAM_IN_ADDR                     MT6355_ACCDET_CON18
#define PMIC_ACCDET_EINT_SAM_IN_MASK                     0x1
#define PMIC_ACCDET_EINT_SAM_IN_SHIFT                    9
#define PMIC_ACCDET_EINT_MEM_IN_ADDR                     MT6355_ACCDET_CON18
#define PMIC_ACCDET_EINT_MEM_IN_MASK                     0x1
#define PMIC_ACCDET_EINT_MEM_IN_SHIFT                    10
#define PMIC_AD_EINTCMPOUT_ADDR                          MT6355_ACCDET_CON18
#define PMIC_AD_EINTCMPOUT_MASK                          0x1
#define PMIC_AD_EINTCMPOUT_SHIFT                         14
#define PMIC_DA_NI_EINTCMPEN_ADDR                        MT6355_ACCDET_CON18
#define PMIC_DA_NI_EINTCMPEN_MASK                        0x1
#define PMIC_DA_NI_EINTCMPEN_SHIFT                       15
#define PMIC_ACCDET_CUR_DEB_ADDR                         MT6355_ACCDET_CON19
#define PMIC_ACCDET_CUR_DEB_MASK                         0xFFFF
#define PMIC_ACCDET_CUR_DEB_SHIFT                        0
#define PMIC_ACCDET_EINT_CUR_DEB_ADDR                    MT6355_ACCDET_CON20
#define PMIC_ACCDET_EINT_CUR_DEB_MASK                    0x7FFF
#define PMIC_ACCDET_EINT_CUR_DEB_SHIFT                   0
#define PMIC_ACCDET_RSV_CON0_ADDR                        MT6355_ACCDET_CON21
#define PMIC_ACCDET_RSV_CON0_MASK                        0xFFFF
#define PMIC_ACCDET_RSV_CON0_SHIFT                       0
#define PMIC_ACCDET_RSV_CON1_ADDR                        MT6355_ACCDET_CON22
#define PMIC_ACCDET_RSV_CON1_MASK                        0xFFFF
#define PMIC_ACCDET_RSV_CON1_SHIFT                       0
#define PMIC_ACCDET_AUXADC_CONNECT_TIME_ADDR             MT6355_ACCDET_CON23
#define PMIC_ACCDET_AUXADC_CONNECT_TIME_MASK             0xFFFF
#define PMIC_ACCDET_AUXADC_CONNECT_TIME_SHIFT            0
#define PMIC_ACCDET_HWMODE_SEL_ADDR                      MT6355_ACCDET_CON24
#define PMIC_ACCDET_HWMODE_SEL_MASK                      0x1
#define PMIC_ACCDET_HWMODE_SEL_SHIFT                     0
#define PMIC_ACCDET_EINT_DEB_OUT_DFF_ADDR                MT6355_ACCDET_CON24
#define PMIC_ACCDET_EINT_DEB_OUT_DFF_MASK                0x1
#define PMIC_ACCDET_EINT_DEB_OUT_DFF_SHIFT               1
#define PMIC_ACCDET_EINT_REVERSE_ADDR                    MT6355_ACCDET_CON24
#define PMIC_ACCDET_EINT_REVERSE_MASK                    0x1
#define PMIC_ACCDET_EINT_REVERSE_SHIFT                   15
#define PMIC_RG_OTP_PA_ADDR                              MT6355_OTP_CON0
#define PMIC_RG_OTP_PA_MASK                              0xFF
#define PMIC_RG_OTP_PA_SHIFT                             0
#define PMIC_RG_OTP_PDIN_ADDR                            MT6355_OTP_CON1
#define PMIC_RG_OTP_PDIN_MASK                            0xFF
#define PMIC_RG_OTP_PDIN_SHIFT                           0
#define PMIC_RG_OTP_PTM_ADDR                             MT6355_OTP_CON2
#define PMIC_RG_OTP_PTM_MASK                             0x3
#define PMIC_RG_OTP_PTM_SHIFT                            0
#define PMIC_RG_OTP_PWE_ADDR                             MT6355_OTP_CON3
#define PMIC_RG_OTP_PWE_MASK                             0x3
#define PMIC_RG_OTP_PWE_SHIFT                            0
#define PMIC_RG_OTP_PPROG_ADDR                           MT6355_OTP_CON4
#define PMIC_RG_OTP_PPROG_MASK                           0x1
#define PMIC_RG_OTP_PPROG_SHIFT                          0
#define PMIC_RG_OTP_PWE_SRC_ADDR                         MT6355_OTP_CON5
#define PMIC_RG_OTP_PWE_SRC_MASK                         0x1
#define PMIC_RG_OTP_PWE_SRC_SHIFT                        0
#define PMIC_RG_OTP_PROG_PKEY_ADDR                       MT6355_OTP_CON6
#define PMIC_RG_OTP_PROG_PKEY_MASK                       0xFFFF
#define PMIC_RG_OTP_PROG_PKEY_SHIFT                      0
#define PMIC_RG_OTP_RD_PKEY_ADDR                         MT6355_OTP_CON7
#define PMIC_RG_OTP_RD_PKEY_MASK                         0xFFFF
#define PMIC_RG_OTP_RD_PKEY_SHIFT                        0
#define PMIC_RG_OTP_RD_TRIG_ADDR                         MT6355_OTP_CON8
#define PMIC_RG_OTP_RD_TRIG_MASK                         0x1
#define PMIC_RG_OTP_RD_TRIG_SHIFT                        0
#define PMIC_RG_RD_RDY_BYPASS_ADDR                       MT6355_OTP_CON9
#define PMIC_RG_RD_RDY_BYPASS_MASK                       0x1
#define PMIC_RG_RD_RDY_BYPASS_SHIFT                      0
#define PMIC_RG_SKIP_OTP_OUT_ADDR                        MT6355_OTP_CON10
#define PMIC_RG_SKIP_OTP_OUT_MASK                        0x1
#define PMIC_RG_SKIP_OTP_OUT_SHIFT                       0
#define PMIC_RG_OTP_RD_SW_ADDR                           MT6355_OTP_CON11
#define PMIC_RG_OTP_RD_SW_MASK                           0x1
#define PMIC_RG_OTP_RD_SW_SHIFT                          0
#define PMIC_RG_OTP_DOUT_SW_ADDR                         MT6355_OTP_CON12
#define PMIC_RG_OTP_DOUT_SW_MASK                         0xFFFF
#define PMIC_RG_OTP_DOUT_SW_SHIFT                        0
#define PMIC_RG_OTP_RD_BUSY_ADDR                         MT6355_OTP_CON13
#define PMIC_RG_OTP_RD_BUSY_MASK                         0x1
#define PMIC_RG_OTP_RD_BUSY_SHIFT                        0
#define PMIC_RG_OTP_RD_ACK_ADDR                          MT6355_OTP_CON13
#define PMIC_RG_OTP_RD_ACK_MASK                          0x1
#define PMIC_RG_OTP_RD_ACK_SHIFT                         2
#define PMIC_RG_OTP_PA_SW_ADDR                           MT6355_OTP_CON14
#define PMIC_RG_OTP_PA_SW_MASK                           0x7F
#define PMIC_RG_OTP_PA_SW_SHIFT                          0
#define PMIC_RG_OTP_DOUT_0_15_ADDR                       MT6355_OTP_DOUT_0_15
#define PMIC_RG_OTP_DOUT_0_15_MASK                       0xFFFF
#define PMIC_RG_OTP_DOUT_0_15_SHIFT                      0
#define PMIC_RG_OTP_DOUT_16_31_ADDR                      MT6355_OTP_DOUT_16_31
#define PMIC_RG_OTP_DOUT_16_31_MASK                      0xFFFF
#define PMIC_RG_OTP_DOUT_16_31_SHIFT                     0
#define PMIC_RG_OTP_DOUT_32_47_ADDR                      MT6355_OTP_DOUT_32_47
#define PMIC_RG_OTP_DOUT_32_47_MASK                      0xFFFF
#define PMIC_RG_OTP_DOUT_32_47_SHIFT                     0
#define PMIC_RG_OTP_DOUT_48_63_ADDR                      MT6355_OTP_DOUT_48_63
#define PMIC_RG_OTP_DOUT_48_63_MASK                      0xFFFF
#define PMIC_RG_OTP_DOUT_48_63_SHIFT                     0
#define PMIC_RG_OTP_DOUT_64_79_ADDR                      MT6355_OTP_DOUT_64_79
#define PMIC_RG_OTP_DOUT_64_79_MASK                      0xFFFF
#define PMIC_RG_OTP_DOUT_64_79_SHIFT                     0
#define PMIC_RG_OTP_DOUT_80_95_ADDR                      MT6355_OTP_DOUT_80_95
#define PMIC_RG_OTP_DOUT_80_95_MASK                      0xFFFF
#define PMIC_RG_OTP_DOUT_80_95_SHIFT                     0
#define PMIC_RG_OTP_DOUT_96_111_ADDR                     MT6355_OTP_DOUT_96_111
#define PMIC_RG_OTP_DOUT_96_111_MASK                     0xFFFF
#define PMIC_RG_OTP_DOUT_96_111_SHIFT                    0
#define PMIC_RG_OTP_DOUT_112_127_ADDR                    MT6355_OTP_DOUT_112_127
#define PMIC_RG_OTP_DOUT_112_127_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_112_127_SHIFT                   0
#define PMIC_RG_OTP_DOUT_128_143_ADDR                    MT6355_OTP_DOUT_128_143
#define PMIC_RG_OTP_DOUT_128_143_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_128_143_SHIFT                   0
#define PMIC_RG_OTP_DOUT_144_159_ADDR                    MT6355_OTP_DOUT_144_159
#define PMIC_RG_OTP_DOUT_144_159_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_144_159_SHIFT                   0
#define PMIC_RG_OTP_DOUT_160_175_ADDR                    MT6355_OTP_DOUT_160_175
#define PMIC_RG_OTP_DOUT_160_175_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_160_175_SHIFT                   0
#define PMIC_RG_OTP_DOUT_176_191_ADDR                    MT6355_OTP_DOUT_176_191
#define PMIC_RG_OTP_DOUT_176_191_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_176_191_SHIFT                   0
#define PMIC_RG_OTP_DOUT_192_207_ADDR                    MT6355_OTP_DOUT_192_207
#define PMIC_RG_OTP_DOUT_192_207_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_192_207_SHIFT                   0
#define PMIC_RG_OTP_DOUT_208_223_ADDR                    MT6355_OTP_DOUT_208_223
#define PMIC_RG_OTP_DOUT_208_223_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_208_223_SHIFT                   0
#define PMIC_RG_OTP_DOUT_224_239_ADDR                    MT6355_OTP_DOUT_224_239
#define PMIC_RG_OTP_DOUT_224_239_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_224_239_SHIFT                   0
#define PMIC_RG_OTP_DOUT_240_255_ADDR                    MT6355_OTP_DOUT_240_255
#define PMIC_RG_OTP_DOUT_240_255_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_240_255_SHIFT                   0
#define PMIC_RG_OTP_DOUT_256_271_ADDR                    MT6355_OTP_DOUT_256_271
#define PMIC_RG_OTP_DOUT_256_271_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_256_271_SHIFT                   0
#define PMIC_RG_OTP_DOUT_272_287_ADDR                    MT6355_OTP_DOUT_272_287
#define PMIC_RG_OTP_DOUT_272_287_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_272_287_SHIFT                   0
#define PMIC_RG_OTP_DOUT_288_303_ADDR                    MT6355_OTP_DOUT_288_303
#define PMIC_RG_OTP_DOUT_288_303_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_288_303_SHIFT                   0
#define PMIC_RG_OTP_DOUT_304_319_ADDR                    MT6355_OTP_DOUT_304_319
#define PMIC_RG_OTP_DOUT_304_319_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_304_319_SHIFT                   0
#define PMIC_RG_OTP_DOUT_320_335_ADDR                    MT6355_OTP_DOUT_320_335
#define PMIC_RG_OTP_DOUT_320_335_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_320_335_SHIFT                   0
#define PMIC_RG_OTP_DOUT_336_351_ADDR                    MT6355_OTP_DOUT_336_351
#define PMIC_RG_OTP_DOUT_336_351_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_336_351_SHIFT                   0
#define PMIC_RG_OTP_DOUT_352_367_ADDR                    MT6355_OTP_DOUT_352_367
#define PMIC_RG_OTP_DOUT_352_367_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_352_367_SHIFT                   0
#define PMIC_RG_OTP_DOUT_368_383_ADDR                    MT6355_OTP_DOUT_368_383
#define PMIC_RG_OTP_DOUT_368_383_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_368_383_SHIFT                   0
#define PMIC_RG_OTP_DOUT_384_399_ADDR                    MT6355_OTP_DOUT_384_399
#define PMIC_RG_OTP_DOUT_384_399_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_384_399_SHIFT                   0
#define PMIC_RG_OTP_DOUT_400_415_ADDR                    MT6355_OTP_DOUT_400_415
#define PMIC_RG_OTP_DOUT_400_415_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_400_415_SHIFT                   0
#define PMIC_RG_OTP_DOUT_416_431_ADDR                    MT6355_OTP_DOUT_416_431
#define PMIC_RG_OTP_DOUT_416_431_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_416_431_SHIFT                   0
#define PMIC_RG_OTP_DOUT_432_447_ADDR                    MT6355_OTP_DOUT_432_447
#define PMIC_RG_OTP_DOUT_432_447_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_432_447_SHIFT                   0
#define PMIC_RG_OTP_DOUT_448_463_ADDR                    MT6355_OTP_DOUT_448_463
#define PMIC_RG_OTP_DOUT_448_463_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_448_463_SHIFT                   0
#define PMIC_RG_OTP_DOUT_464_479_ADDR                    MT6355_OTP_DOUT_464_479
#define PMIC_RG_OTP_DOUT_464_479_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_464_479_SHIFT                   0
#define PMIC_RG_OTP_DOUT_480_495_ADDR                    MT6355_OTP_DOUT_480_495
#define PMIC_RG_OTP_DOUT_480_495_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_480_495_SHIFT                   0
#define PMIC_RG_OTP_DOUT_496_511_ADDR                    MT6355_OTP_DOUT_496_511
#define PMIC_RG_OTP_DOUT_496_511_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_496_511_SHIFT                   0
#define PMIC_RG_OTP_DOUT_512_527_ADDR                    MT6355_OTP_DOUT_512_527
#define PMIC_RG_OTP_DOUT_512_527_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_512_527_SHIFT                   0
#define PMIC_RG_OTP_DOUT_528_543_ADDR                    MT6355_OTP_DOUT_528_543
#define PMIC_RG_OTP_DOUT_528_543_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_528_543_SHIFT                   0
#define PMIC_RG_OTP_DOUT_544_559_ADDR                    MT6355_OTP_DOUT_544_559
#define PMIC_RG_OTP_DOUT_544_559_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_544_559_SHIFT                   0
#define PMIC_RG_OTP_DOUT_560_575_ADDR                    MT6355_OTP_DOUT_560_575
#define PMIC_RG_OTP_DOUT_560_575_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_560_575_SHIFT                   0
#define PMIC_RG_OTP_DOUT_576_591_ADDR                    MT6355_OTP_DOUT_576_591
#define PMIC_RG_OTP_DOUT_576_591_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_576_591_SHIFT                   0
#define PMIC_RG_OTP_DOUT_592_607_ADDR                    MT6355_OTP_DOUT_592_607
#define PMIC_RG_OTP_DOUT_592_607_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_592_607_SHIFT                   0
#define PMIC_RG_OTP_DOUT_608_623_ADDR                    MT6355_OTP_DOUT_608_623
#define PMIC_RG_OTP_DOUT_608_623_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_608_623_SHIFT                   0
#define PMIC_RG_OTP_DOUT_624_639_ADDR                    MT6355_OTP_DOUT_624_639
#define PMIC_RG_OTP_DOUT_624_639_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_624_639_SHIFT                   0
#define PMIC_RG_OTP_DOUT_640_655_ADDR                    MT6355_OTP_DOUT_640_655
#define PMIC_RG_OTP_DOUT_640_655_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_640_655_SHIFT                   0
#define PMIC_RG_OTP_DOUT_656_671_ADDR                    MT6355_OTP_DOUT_656_671
#define PMIC_RG_OTP_DOUT_656_671_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_656_671_SHIFT                   0
#define PMIC_RG_OTP_DOUT_672_687_ADDR                    MT6355_OTP_DOUT_672_687
#define PMIC_RG_OTP_DOUT_672_687_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_672_687_SHIFT                   0
#define PMIC_RG_OTP_DOUT_688_703_ADDR                    MT6355_OTP_DOUT_688_703
#define PMIC_RG_OTP_DOUT_688_703_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_688_703_SHIFT                   0
#define PMIC_RG_OTP_DOUT_704_719_ADDR                    MT6355_OTP_DOUT_704_719
#define PMIC_RG_OTP_DOUT_704_719_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_704_719_SHIFT                   0
#define PMIC_RG_OTP_DOUT_720_735_ADDR                    MT6355_OTP_DOUT_720_735
#define PMIC_RG_OTP_DOUT_720_735_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_720_735_SHIFT                   0
#define PMIC_RG_OTP_DOUT_736_751_ADDR                    MT6355_OTP_DOUT_736_751
#define PMIC_RG_OTP_DOUT_736_751_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_736_751_SHIFT                   0
#define PMIC_RG_OTP_DOUT_752_767_ADDR                    MT6355_OTP_DOUT_752_767
#define PMIC_RG_OTP_DOUT_752_767_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_752_767_SHIFT                   0
#define PMIC_RG_OTP_DOUT_768_783_ADDR                    MT6355_OTP_DOUT_768_783
#define PMIC_RG_OTP_DOUT_768_783_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_768_783_SHIFT                   0
#define PMIC_RG_OTP_DOUT_784_799_ADDR                    MT6355_OTP_DOUT_784_799
#define PMIC_RG_OTP_DOUT_784_799_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_784_799_SHIFT                   0
#define PMIC_RG_OTP_DOUT_800_815_ADDR                    MT6355_OTP_DOUT_800_815
#define PMIC_RG_OTP_DOUT_800_815_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_800_815_SHIFT                   0
#define PMIC_RG_OTP_DOUT_816_831_ADDR                    MT6355_OTP_DOUT_816_831
#define PMIC_RG_OTP_DOUT_816_831_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_816_831_SHIFT                   0
#define PMIC_RG_OTP_DOUT_832_847_ADDR                    MT6355_OTP_DOUT_832_847
#define PMIC_RG_OTP_DOUT_832_847_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_832_847_SHIFT                   0
#define PMIC_RG_OTP_DOUT_848_863_ADDR                    MT6355_OTP_DOUT_848_863
#define PMIC_RG_OTP_DOUT_848_863_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_848_863_SHIFT                   0
#define PMIC_RG_OTP_DOUT_864_879_ADDR                    MT6355_OTP_DOUT_864_879
#define PMIC_RG_OTP_DOUT_864_879_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_864_879_SHIFT                   0
#define PMIC_RG_OTP_DOUT_880_895_ADDR                    MT6355_OTP_DOUT_880_895
#define PMIC_RG_OTP_DOUT_880_895_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_880_895_SHIFT                   0
#define PMIC_RG_OTP_DOUT_896_911_ADDR                    MT6355_OTP_DOUT_896_911
#define PMIC_RG_OTP_DOUT_896_911_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_896_911_SHIFT                   0
#define PMIC_RG_OTP_DOUT_912_927_ADDR                    MT6355_OTP_DOUT_912_927
#define PMIC_RG_OTP_DOUT_912_927_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_912_927_SHIFT                   0
#define PMIC_RG_OTP_DOUT_928_943_ADDR                    MT6355_OTP_DOUT_928_943
#define PMIC_RG_OTP_DOUT_928_943_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_928_943_SHIFT                   0
#define PMIC_RG_OTP_DOUT_944_959_ADDR                    MT6355_OTP_DOUT_944_959
#define PMIC_RG_OTP_DOUT_944_959_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_944_959_SHIFT                   0
#define PMIC_RG_OTP_DOUT_960_975_ADDR                    MT6355_OTP_DOUT_960_975
#define PMIC_RG_OTP_DOUT_960_975_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_960_975_SHIFT                   0
#define PMIC_RG_OTP_DOUT_976_991_ADDR                    MT6355_OTP_DOUT_976_991
#define PMIC_RG_OTP_DOUT_976_991_MASK                    0xFFFF
#define PMIC_RG_OTP_DOUT_976_991_SHIFT                   0
#define PMIC_RG_OTP_DOUT_992_1007_ADDR                   MT6355_OTP_DOUT_992_1007
#define PMIC_RG_OTP_DOUT_992_1007_MASK                   0xFFFF
#define PMIC_RG_OTP_DOUT_992_1007_SHIFT                  0
#define PMIC_RG_OTP_DOUT_1008_1023_ADDR                  MT6355_OTP_DOUT_1008_1023
#define PMIC_RG_OTP_DOUT_1008_1023_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1008_1023_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1024_1039_ADDR                  MT6355_OTP_DOUT_1024_1039
#define PMIC_RG_OTP_DOUT_1024_1039_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1024_1039_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1040_1055_ADDR                  MT6355_OTP_DOUT_1040_1055
#define PMIC_RG_OTP_DOUT_1040_1055_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1040_1055_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1056_1071_ADDR                  MT6355_OTP_DOUT_1056_1071
#define PMIC_RG_OTP_DOUT_1056_1071_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1056_1071_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1072_1087_ADDR                  MT6355_OTP_DOUT_1072_1087
#define PMIC_RG_OTP_DOUT_1072_1087_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1072_1087_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1088_1103_ADDR                  MT6355_OTP_DOUT_1088_1103
#define PMIC_RG_OTP_DOUT_1088_1103_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1088_1103_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1104_1119_ADDR                  MT6355_OTP_DOUT_1104_1119
#define PMIC_RG_OTP_DOUT_1104_1119_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1104_1119_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1120_1135_ADDR                  MT6355_OTP_DOUT_1120_1135
#define PMIC_RG_OTP_DOUT_1120_1135_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1120_1135_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1136_1151_ADDR                  MT6355_OTP_DOUT_1136_1151
#define PMIC_RG_OTP_DOUT_1136_1151_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1136_1151_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1152_1167_ADDR                  MT6355_OTP_DOUT_1152_1167
#define PMIC_RG_OTP_DOUT_1152_1167_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1152_1167_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1168_1183_ADDR                  MT6355_OTP_DOUT_1168_1183
#define PMIC_RG_OTP_DOUT_1168_1183_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1168_1183_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1184_1199_ADDR                  MT6355_OTP_DOUT_1184_1199
#define PMIC_RG_OTP_DOUT_1184_1199_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1184_1199_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1200_1215_ADDR                  MT6355_OTP_DOUT_1200_1215
#define PMIC_RG_OTP_DOUT_1200_1215_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1200_1215_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1216_1231_ADDR                  MT6355_OTP_DOUT_1216_1231
#define PMIC_RG_OTP_DOUT_1216_1231_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1216_1231_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1232_1247_ADDR                  MT6355_OTP_DOUT_1232_1247
#define PMIC_RG_OTP_DOUT_1232_1247_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1232_1247_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1248_1263_ADDR                  MT6355_OTP_DOUT_1248_1263
#define PMIC_RG_OTP_DOUT_1248_1263_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1248_1263_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1264_1279_ADDR                  MT6355_OTP_DOUT_1264_1279
#define PMIC_RG_OTP_DOUT_1264_1279_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1264_1279_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1280_1295_ADDR                  MT6355_OTP_DOUT_1280_1295
#define PMIC_RG_OTP_DOUT_1280_1295_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1280_1295_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1296_1311_ADDR                  MT6355_OTP_DOUT_1296_1311
#define PMIC_RG_OTP_DOUT_1296_1311_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1296_1311_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1312_1327_ADDR                  MT6355_OTP_DOUT_1312_1327
#define PMIC_RG_OTP_DOUT_1312_1327_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1312_1327_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1328_1343_ADDR                  MT6355_OTP_DOUT_1328_1343
#define PMIC_RG_OTP_DOUT_1328_1343_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1328_1343_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1344_1359_ADDR                  MT6355_OTP_DOUT_1344_1359
#define PMIC_RG_OTP_DOUT_1344_1359_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1344_1359_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1360_1375_ADDR                  MT6355_OTP_DOUT_1360_1375
#define PMIC_RG_OTP_DOUT_1360_1375_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1360_1375_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1376_1391_ADDR                  MT6355_OTP_DOUT_1376_1391
#define PMIC_RG_OTP_DOUT_1376_1391_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1376_1391_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1392_1407_ADDR                  MT6355_OTP_DOUT_1392_1407
#define PMIC_RG_OTP_DOUT_1392_1407_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1392_1407_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1408_1423_ADDR                  MT6355_OTP_DOUT_1408_1423
#define PMIC_RG_OTP_DOUT_1408_1423_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1408_1423_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1424_1439_ADDR                  MT6355_OTP_DOUT_1424_1439
#define PMIC_RG_OTP_DOUT_1424_1439_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1424_1439_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1440_1455_ADDR                  MT6355_OTP_DOUT_1440_1455
#define PMIC_RG_OTP_DOUT_1440_1455_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1440_1455_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1456_1471_ADDR                  MT6355_OTP_DOUT_1456_1471
#define PMIC_RG_OTP_DOUT_1456_1471_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1456_1471_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1472_1487_ADDR                  MT6355_OTP_DOUT_1472_1487
#define PMIC_RG_OTP_DOUT_1472_1487_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1472_1487_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1488_1503_ADDR                  MT6355_OTP_DOUT_1488_1503
#define PMIC_RG_OTP_DOUT_1488_1503_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1488_1503_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1504_1519_ADDR                  MT6355_OTP_DOUT_1504_1519
#define PMIC_RG_OTP_DOUT_1504_1519_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1504_1519_SHIFT                 0
#define PMIC_RG_OTP_DOUT_1520_1535_ADDR                  MT6355_OTP_DOUT_1520_1535
#define PMIC_RG_OTP_DOUT_1520_1535_MASK                  0xFFFF
#define PMIC_RG_OTP_DOUT_1520_1535_SHIFT                 0
#define PMIC_RG_OTP_VAL_0_15_ADDR                        MT6355_OTP_VAL_0_15
#define PMIC_RG_OTP_VAL_0_15_MASK                        0xFFFF
#define PMIC_RG_OTP_VAL_0_15_SHIFT                       0
#define PMIC_RG_OTP_VAL_16_31_ADDR                       MT6355_OTP_VAL_16_31
#define PMIC_RG_OTP_VAL_16_31_MASK                       0xFFFF
#define PMIC_RG_OTP_VAL_16_31_SHIFT                      0
#define PMIC_RG_OTP_VAL_32_47_ADDR                       MT6355_OTP_VAL_32_47
#define PMIC_RG_OTP_VAL_32_47_MASK                       0xFFFF
#define PMIC_RG_OTP_VAL_32_47_SHIFT                      0
#define PMIC_RG_OTP_VAL_48_63_ADDR                       MT6355_OTP_VAL_48_63
#define PMIC_RG_OTP_VAL_48_63_MASK                       0xFFFF
#define PMIC_RG_OTP_VAL_48_63_SHIFT                      0
#define PMIC_RG_OTP_VAL_64_79_ADDR                       MT6355_OTP_VAL_64_79
#define PMIC_RG_OTP_VAL_64_79_MASK                       0xFFFF
#define PMIC_RG_OTP_VAL_64_79_SHIFT                      0
#define PMIC_RG_OTP_VAL_80_95_ADDR                       MT6355_OTP_VAL_80_95
#define PMIC_RG_OTP_VAL_80_95_MASK                       0xFFFF
#define PMIC_RG_OTP_VAL_80_95_SHIFT                      0
#define PMIC_RG_OTP_VAL_96_111_ADDR                      MT6355_OTP_VAL_96_111
#define PMIC_RG_OTP_VAL_96_111_MASK                      0xFFFF
#define PMIC_RG_OTP_VAL_96_111_SHIFT                     0
#define PMIC_RG_OTP_VAL_112_127_ADDR                     MT6355_OTP_VAL_112_127
#define PMIC_RG_OTP_VAL_112_127_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_112_127_SHIFT                    0
#define PMIC_RG_OTP_VAL_128_143_ADDR                     MT6355_OTP_VAL_128_143
#define PMIC_RG_OTP_VAL_128_143_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_128_143_SHIFT                    0
#define PMIC_RG_OTP_VAL_144_159_ADDR                     MT6355_OTP_VAL_144_159
#define PMIC_RG_OTP_VAL_144_159_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_144_159_SHIFT                    0
#define PMIC_RG_OTP_VAL_160_175_ADDR                     MT6355_OTP_VAL_160_175
#define PMIC_RG_OTP_VAL_160_175_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_160_175_SHIFT                    0
#define PMIC_RG_OTP_VAL_176_191_ADDR                     MT6355_OTP_VAL_176_191
#define PMIC_RG_OTP_VAL_176_191_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_176_191_SHIFT                    0
#define PMIC_RG_OTP_VAL_192_207_ADDR                     MT6355_OTP_VAL_192_207
#define PMIC_RG_OTP_VAL_192_207_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_192_207_SHIFT                    0
#define PMIC_RG_OTP_VAL_208_223_ADDR                     MT6355_OTP_VAL_208_223
#define PMIC_RG_OTP_VAL_208_223_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_208_223_SHIFT                    0
#define PMIC_RG_OTP_VAL_224_239_ADDR                     MT6355_OTP_VAL_224_239
#define PMIC_RG_OTP_VAL_224_239_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_224_239_SHIFT                    0
#define PMIC_RG_OTP_VAL_240_255_ADDR                     MT6355_OTP_VAL_240_255
#define PMIC_RG_OTP_VAL_240_255_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_240_255_SHIFT                    0
#define PMIC_RG_OTP_VAL_256_271_ADDR                     MT6355_OTP_VAL_256_271
#define PMIC_RG_OTP_VAL_256_271_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_256_271_SHIFT                    0
#define PMIC_RG_OTP_VAL_272_287_ADDR                     MT6355_OTP_VAL_272_287
#define PMIC_RG_OTP_VAL_272_287_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_272_287_SHIFT                    0
#define PMIC_RG_OTP_VAL_288_303_ADDR                     MT6355_OTP_VAL_288_303
#define PMIC_RG_OTP_VAL_288_303_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_288_303_SHIFT                    0
#define PMIC_RG_OTP_VAL_304_319_ADDR                     MT6355_OTP_VAL_304_319
#define PMIC_RG_OTP_VAL_304_319_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_304_319_SHIFT                    0
#define PMIC_RG_OTP_VAL_320_335_ADDR                     MT6355_OTP_VAL_320_335
#define PMIC_RG_OTP_VAL_320_335_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_320_335_SHIFT                    0
#define PMIC_RG_OTP_VAL_336_351_ADDR                     MT6355_OTP_VAL_336_351
#define PMIC_RG_OTP_VAL_336_351_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_336_351_SHIFT                    0
#define PMIC_RG_OTP_VAL_352_367_ADDR                     MT6355_OTP_VAL_352_367
#define PMIC_RG_OTP_VAL_352_367_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_352_367_SHIFT                    0
#define PMIC_RG_OTP_VAL_368_383_ADDR                     MT6355_OTP_VAL_368_383
#define PMIC_RG_OTP_VAL_368_383_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_368_383_SHIFT                    0
#define PMIC_RG_OTP_VAL_384_399_ADDR                     MT6355_OTP_VAL_384_399
#define PMIC_RG_OTP_VAL_384_399_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_384_399_SHIFT                    0
#define PMIC_RG_OTP_VAL_400_415_ADDR                     MT6355_OTP_VAL_400_415
#define PMIC_RG_OTP_VAL_400_415_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_400_415_SHIFT                    0
#define PMIC_RG_OTP_VAL_416_431_ADDR                     MT6355_OTP_VAL_416_431
#define PMIC_RG_OTP_VAL_416_431_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_416_431_SHIFT                    0
#define PMIC_RG_OTP_VAL_432_447_ADDR                     MT6355_OTP_VAL_432_447
#define PMIC_RG_OTP_VAL_432_447_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_432_447_SHIFT                    0
#define PMIC_RG_OTP_VAL_448_463_ADDR                     MT6355_OTP_VAL_448_463
#define PMIC_RG_OTP_VAL_448_463_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_448_463_SHIFT                    0
#define PMIC_RG_OTP_VAL_464_479_ADDR                     MT6355_OTP_VAL_464_479
#define PMIC_RG_OTP_VAL_464_479_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_464_479_SHIFT                    0
#define PMIC_RG_OTP_VAL_480_495_ADDR                     MT6355_OTP_VAL_480_495
#define PMIC_RG_OTP_VAL_480_495_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_480_495_SHIFT                    0
#define PMIC_RG_OTP_VAL_496_511_ADDR                     MT6355_OTP_VAL_496_511
#define PMIC_RG_OTP_VAL_496_511_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_496_511_SHIFT                    0
#define PMIC_RG_OTP_VAL_512_527_ADDR                     MT6355_OTP_VAL_512_527
#define PMIC_RG_OTP_VAL_512_527_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_512_527_SHIFT                    0
#define PMIC_RG_OTP_VAL_528_543_ADDR                     MT6355_OTP_VAL_528_543
#define PMIC_RG_OTP_VAL_528_543_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_528_543_SHIFT                    0
#define PMIC_RG_OTP_VAL_544_559_ADDR                     MT6355_OTP_VAL_544_559
#define PMIC_RG_OTP_VAL_544_559_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_544_559_SHIFT                    0
#define PMIC_RG_OTP_VAL_560_575_ADDR                     MT6355_OTP_VAL_560_575
#define PMIC_RG_OTP_VAL_560_575_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_560_575_SHIFT                    0
#define PMIC_RG_OTP_VAL_576_591_ADDR                     MT6355_OTP_VAL_576_591
#define PMIC_RG_OTP_VAL_576_591_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_576_591_SHIFT                    0
#define PMIC_RG_OTP_VAL_592_607_ADDR                     MT6355_OTP_VAL_592_607
#define PMIC_RG_OTP_VAL_592_607_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_592_607_SHIFT                    0
#define PMIC_RG_OTP_VAL_608_623_ADDR                     MT6355_OTP_VAL_608_623
#define PMIC_RG_OTP_VAL_608_623_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_608_623_SHIFT                    0
#define PMIC_RG_OTP_VAL_624_639_ADDR                     MT6355_OTP_VAL_624_639
#define PMIC_RG_OTP_VAL_624_639_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_624_639_SHIFT                    0
#define PMIC_RG_OTP_VAL_640_655_ADDR                     MT6355_OTP_VAL_640_655
#define PMIC_RG_OTP_VAL_640_655_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_640_655_SHIFT                    0
#define PMIC_RG_OTP_VAL_656_671_ADDR                     MT6355_OTP_VAL_656_671
#define PMIC_RG_OTP_VAL_656_671_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_656_671_SHIFT                    0
#define PMIC_RG_OTP_VAL_672_687_ADDR                     MT6355_OTP_VAL_672_687
#define PMIC_RG_OTP_VAL_672_687_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_672_687_SHIFT                    0
#define PMIC_RG_OTP_VAL_688_703_ADDR                     MT6355_OTP_VAL_688_703
#define PMIC_RG_OTP_VAL_688_703_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_688_703_SHIFT                    0
#define PMIC_RG_OTP_VAL_704_719_ADDR                     MT6355_OTP_VAL_704_719
#define PMIC_RG_OTP_VAL_704_719_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_704_719_SHIFT                    0
#define PMIC_RG_OTP_VAL_720_735_ADDR                     MT6355_OTP_VAL_720_735
#define PMIC_RG_OTP_VAL_720_735_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_720_735_SHIFT                    0
#define PMIC_RG_OTP_VAL_736_751_ADDR                     MT6355_OTP_VAL_736_751
#define PMIC_RG_OTP_VAL_736_751_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_736_751_SHIFT                    0
#define PMIC_RG_OTP_VAL_752_767_ADDR                     MT6355_OTP_VAL_752_767
#define PMIC_RG_OTP_VAL_752_767_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_752_767_SHIFT                    0
#define PMIC_RG_OTP_VAL_768_783_ADDR                     MT6355_OTP_VAL_768_783
#define PMIC_RG_OTP_VAL_768_783_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_768_783_SHIFT                    0
#define PMIC_RG_OTP_VAL_784_799_ADDR                     MT6355_OTP_VAL_784_799
#define PMIC_RG_OTP_VAL_784_799_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_784_799_SHIFT                    0
#define PMIC_RG_OTP_VAL_800_815_ADDR                     MT6355_OTP_VAL_800_815
#define PMIC_RG_OTP_VAL_800_815_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_800_815_SHIFT                    0
#define PMIC_RG_OTP_VAL_816_831_ADDR                     MT6355_OTP_VAL_816_831
#define PMIC_RG_OTP_VAL_816_831_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_816_831_SHIFT                    0
#define PMIC_RG_OTP_VAL_832_847_ADDR                     MT6355_OTP_VAL_832_847
#define PMIC_RG_OTP_VAL_832_847_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_832_847_SHIFT                    0
#define PMIC_RG_OTP_VAL_848_863_ADDR                     MT6355_OTP_VAL_848_863
#define PMIC_RG_OTP_VAL_848_863_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_848_863_SHIFT                    0
#define PMIC_RG_OTP_VAL_864_879_ADDR                     MT6355_OTP_VAL_864_879
#define PMIC_RG_OTP_VAL_864_879_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_864_879_SHIFT                    0
#define PMIC_RG_OTP_VAL_880_895_ADDR                     MT6355_OTP_VAL_880_895
#define PMIC_RG_OTP_VAL_880_895_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_880_895_SHIFT                    0
#define PMIC_RG_OTP_VAL_896_911_ADDR                     MT6355_OTP_VAL_896_911
#define PMIC_RG_OTP_VAL_896_911_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_896_911_SHIFT                    0
#define PMIC_RG_OTP_VAL_912_927_ADDR                     MT6355_OTP_VAL_912_927
#define PMIC_RG_OTP_VAL_912_927_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_912_927_SHIFT                    0
#define PMIC_RG_OTP_VAL_928_943_ADDR                     MT6355_OTP_VAL_928_943
#define PMIC_RG_OTP_VAL_928_943_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_928_943_SHIFT                    0
#define PMIC_RG_OTP_VAL_944_959_ADDR                     MT6355_OTP_VAL_944_959
#define PMIC_RG_OTP_VAL_944_959_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_944_959_SHIFT                    0
#define PMIC_RG_OTP_VAL_960_975_ADDR                     MT6355_OTP_VAL_960_975
#define PMIC_RG_OTP_VAL_960_975_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_960_975_SHIFT                    0
#define PMIC_RG_OTP_VAL_976_991_ADDR                     MT6355_OTP_VAL_976_991
#define PMIC_RG_OTP_VAL_976_991_MASK                     0xFFFF
#define PMIC_RG_OTP_VAL_976_991_SHIFT                    0
#define PMIC_RG_OTP_VAL_992_1007_ADDR                    MT6355_OTP_VAL_992_1007
#define PMIC_RG_OTP_VAL_992_1007_MASK                    0xFFFF
#define PMIC_RG_OTP_VAL_992_1007_SHIFT                   0
#define PMIC_RG_OTP_VAL_1008_1023_ADDR                   MT6355_OTP_VAL_1008_1023
#define PMIC_RG_OTP_VAL_1008_1023_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1008_1023_SHIFT                  0
#define PMIC_RG_OTP_VAL_1024_1039_ADDR                   MT6355_OTP_VAL_1024_1039
#define PMIC_RG_OTP_VAL_1024_1039_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1024_1039_SHIFT                  0
#define PMIC_RG_OTP_VAL_1040_1055_ADDR                   MT6355_OTP_VAL_1040_1055
#define PMIC_RG_OTP_VAL_1040_1055_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1040_1055_SHIFT                  0
#define PMIC_RG_OTP_VAL_1056_1071_ADDR                   MT6355_OTP_VAL_1056_1071
#define PMIC_RG_OTP_VAL_1056_1071_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1056_1071_SHIFT                  0
#define PMIC_RG_OTP_VAL_1072_1087_ADDR                   MT6355_OTP_VAL_1072_1087
#define PMIC_RG_OTP_VAL_1072_1087_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1072_1087_SHIFT                  0
#define PMIC_RG_OTP_VAL_1088_1103_ADDR                   MT6355_OTP_VAL_1088_1103
#define PMIC_RG_OTP_VAL_1088_1103_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1088_1103_SHIFT                  0
#define PMIC_RG_OTP_VAL_1104_1119_ADDR                   MT6355_OTP_VAL_1104_1119
#define PMIC_RG_OTP_VAL_1104_1119_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1104_1119_SHIFT                  0
#define PMIC_RG_OTP_VAL_1120_1135_ADDR                   MT6355_OTP_VAL_1120_1135
#define PMIC_RG_OTP_VAL_1120_1135_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1120_1135_SHIFT                  0
#define PMIC_RG_OTP_VAL_1136_1151_ADDR                   MT6355_OTP_VAL_1136_1151
#define PMIC_RG_OTP_VAL_1136_1151_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1136_1151_SHIFT                  0
#define PMIC_RG_OTP_VAL_1152_1167_ADDR                   MT6355_OTP_VAL_1152_1167
#define PMIC_RG_OTP_VAL_1152_1167_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1152_1167_SHIFT                  0
#define PMIC_RG_OTP_VAL_1168_1183_ADDR                   MT6355_OTP_VAL_1168_1183
#define PMIC_RG_OTP_VAL_1168_1183_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1168_1183_SHIFT                  0
#define PMIC_RG_OTP_VAL_1184_1199_ADDR                   MT6355_OTP_VAL_1184_1199
#define PMIC_RG_OTP_VAL_1184_1199_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1184_1199_SHIFT                  0
#define PMIC_RG_OTP_VAL_1200_1215_ADDR                   MT6355_OTP_VAL_1200_1215
#define PMIC_RG_OTP_VAL_1200_1215_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1200_1215_SHIFT                  0
#define PMIC_RG_OTP_VAL_1216_1231_ADDR                   MT6355_OTP_VAL_1216_1231
#define PMIC_RG_OTP_VAL_1216_1231_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1216_1231_SHIFT                  0
#define PMIC_RG_OTP_VAL_1232_1247_ADDR                   MT6355_OTP_VAL_1232_1247
#define PMIC_RG_OTP_VAL_1232_1247_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1232_1247_SHIFT                  0
#define PMIC_RG_OTP_VAL_1248_1263_ADDR                   MT6355_OTP_VAL_1248_1263
#define PMIC_RG_OTP_VAL_1248_1263_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1248_1263_SHIFT                  0
#define PMIC_RG_OTP_VAL_1264_1279_ADDR                   MT6355_OTP_VAL_1264_1279
#define PMIC_RG_OTP_VAL_1264_1279_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1264_1279_SHIFT                  0
#define PMIC_RG_OTP_VAL_1280_1295_ADDR                   MT6355_OTP_VAL_1280_1295
#define PMIC_RG_OTP_VAL_1280_1295_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1280_1295_SHIFT                  0
#define PMIC_RG_OTP_VAL_1296_1311_ADDR                   MT6355_OTP_VAL_1296_1311
#define PMIC_RG_OTP_VAL_1296_1311_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1296_1311_SHIFT                  0
#define PMIC_RG_OTP_VAL_1312_1327_ADDR                   MT6355_OTP_VAL_1312_1327
#define PMIC_RG_OTP_VAL_1312_1327_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1312_1327_SHIFT                  0
#define PMIC_RG_OTP_VAL_1328_1343_ADDR                   MT6355_OTP_VAL_1328_1343
#define PMIC_RG_OTP_VAL_1328_1343_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1328_1343_SHIFT                  0
#define PMIC_RG_OTP_VAL_1344_1359_ADDR                   MT6355_OTP_VAL_1344_1359
#define PMIC_RG_OTP_VAL_1344_1359_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1344_1359_SHIFT                  0
#define PMIC_RG_OTP_VAL_1360_1375_ADDR                   MT6355_OTP_VAL_1360_1375
#define PMIC_RG_OTP_VAL_1360_1375_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1360_1375_SHIFT                  0
#define PMIC_RG_OTP_VAL_1376_1391_ADDR                   MT6355_OTP_VAL_1376_1391
#define PMIC_RG_OTP_VAL_1376_1391_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1376_1391_SHIFT                  0
#define PMIC_RG_OTP_VAL_1392_1407_ADDR                   MT6355_OTP_VAL_1392_1407
#define PMIC_RG_OTP_VAL_1392_1407_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1392_1407_SHIFT                  0
#define PMIC_RG_OTP_VAL_1408_1423_ADDR                   MT6355_OTP_VAL_1408_1423
#define PMIC_RG_OTP_VAL_1408_1423_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1408_1423_SHIFT                  0
#define PMIC_RG_OTP_VAL_1424_1439_ADDR                   MT6355_OTP_VAL_1424_1439
#define PMIC_RG_OTP_VAL_1424_1439_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1424_1439_SHIFT                  0
#define PMIC_RG_OTP_VAL_1440_1455_ADDR                   MT6355_OTP_VAL_1440_1455
#define PMIC_RG_OTP_VAL_1440_1455_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1440_1455_SHIFT                  0
#define PMIC_RG_OTP_VAL_1456_1471_ADDR                   MT6355_OTP_VAL_1456_1471
#define PMIC_RG_OTP_VAL_1456_1471_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1456_1471_SHIFT                  0
#define PMIC_RG_OTP_VAL_1472_1487_ADDR                   MT6355_OTP_VAL_1472_1487
#define PMIC_RG_OTP_VAL_1472_1487_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1472_1487_SHIFT                  0
#define PMIC_RG_OTP_VAL_1488_1503_ADDR                   MT6355_OTP_VAL_1488_1503
#define PMIC_RG_OTP_VAL_1488_1503_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1488_1503_SHIFT                  0
#define PMIC_RG_OTP_VAL_1504_1519_ADDR                   MT6355_OTP_VAL_1504_1519
#define PMIC_RG_OTP_VAL_1504_1519_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1504_1519_SHIFT                  0
#define PMIC_RG_OTP_VAL_1520_1535_ADDR                   MT6355_OTP_VAL_1520_1535
#define PMIC_RG_OTP_VAL_1520_1535_MASK                   0xFFFF
#define PMIC_RG_OTP_VAL_1520_1535_SHIFT                  0
#define PMIC_XO_EXTBUF1_MODE_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF1_MODE_MASK                        0x3
#define PMIC_XO_EXTBUF1_MODE_SHIFT                       0
#define PMIC_XO_EXTBUF1_EN_M_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF1_EN_M_MASK                        0x1
#define PMIC_XO_EXTBUF1_EN_M_SHIFT                       2
#define PMIC_XO_EXTBUF2_MODE_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF2_MODE_MASK                        0x3
#define PMIC_XO_EXTBUF2_MODE_SHIFT                       3
#define PMIC_XO_EXTBUF2_EN_M_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF2_EN_M_MASK                        0x1
#define PMIC_XO_EXTBUF2_EN_M_SHIFT                       5
#define PMIC_XO_EXTBUF3_MODE_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF3_MODE_MASK                        0x3
#define PMIC_XO_EXTBUF3_MODE_SHIFT                       6
#define PMIC_XO_EXTBUF3_EN_M_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF3_EN_M_MASK                        0x1
#define PMIC_XO_EXTBUF3_EN_M_SHIFT                       8
#define PMIC_XO_EXTBUF4_MODE_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF4_MODE_MASK                        0x3
#define PMIC_XO_EXTBUF4_MODE_SHIFT                       9
#define PMIC_XO_EXTBUF4_EN_M_ADDR                        MT6355_DCXO_CW00
#define PMIC_XO_EXTBUF4_EN_M_MASK                        0x1
#define PMIC_XO_EXTBUF4_EN_M_SHIFT                       11
#define PMIC_XO_BB_LPM_EN_ADDR                           MT6355_DCXO_CW00
#define PMIC_XO_BB_LPM_EN_MASK                           0x1
#define PMIC_XO_BB_LPM_EN_SHIFT                          12
#define PMIC_XO_ENBB_MAN_ADDR                            MT6355_DCXO_CW00
#define PMIC_XO_ENBB_MAN_MASK                            0x1
#define PMIC_XO_ENBB_MAN_SHIFT                           13
#define PMIC_XO_ENBB_EN_M_ADDR                           MT6355_DCXO_CW00
#define PMIC_XO_ENBB_EN_M_MASK                           0x1
#define PMIC_XO_ENBB_EN_M_SHIFT                          14
#define PMIC_XO_CLKSEL_MAN_ADDR                          MT6355_DCXO_CW00
#define PMIC_XO_CLKSEL_MAN_MASK                          0x1
#define PMIC_XO_CLKSEL_MAN_SHIFT                         15
#define PMIC_DCXO_CW00_SET_ADDR                          MT6355_DCXO_CW00_SET
#define PMIC_DCXO_CW00_SET_MASK                          0xFFFF
#define PMIC_DCXO_CW00_SET_SHIFT                         0
#define PMIC_DCXO_CW00_CLR_ADDR                          MT6355_DCXO_CW00_CLR
#define PMIC_DCXO_CW00_CLR_MASK                          0xFFFF
#define PMIC_DCXO_CW00_CLR_SHIFT                         0
#define PMIC_XO_CLKSEL_EN_M_ADDR                         MT6355_DCXO_CW01
#define PMIC_XO_CLKSEL_EN_M_MASK                         0x1
#define PMIC_XO_CLKSEL_EN_M_SHIFT                        0
#define PMIC_XO_EXTBUF1_CKG_MAN_ADDR                     MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF1_CKG_MAN_MASK                     0x1
#define PMIC_XO_EXTBUF1_CKG_MAN_SHIFT                    1
#define PMIC_XO_EXTBUF1_CKG_EN_M_ADDR                    MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF1_CKG_EN_M_MASK                    0x1
#define PMIC_XO_EXTBUF1_CKG_EN_M_SHIFT                   2
#define PMIC_XO_EXTBUF2_CKG_MAN_ADDR                     MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF2_CKG_MAN_MASK                     0x1
#define PMIC_XO_EXTBUF2_CKG_MAN_SHIFT                    3
#define PMIC_XO_EXTBUF2_CKG_EN_M_ADDR                    MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF2_CKG_EN_M_MASK                    0x1
#define PMIC_XO_EXTBUF2_CKG_EN_M_SHIFT                   4
#define PMIC_XO_EXTBUF3_CKG_MAN_ADDR                     MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF3_CKG_MAN_MASK                     0x1
#define PMIC_XO_EXTBUF3_CKG_MAN_SHIFT                    5
#define PMIC_XO_EXTBUF3_CKG_EN_M_ADDR                    MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF3_CKG_EN_M_MASK                    0x1
#define PMIC_XO_EXTBUF3_CKG_EN_M_SHIFT                   6
#define PMIC_XO_EXTBUF4_CKG_MAN_ADDR                     MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF4_CKG_MAN_MASK                     0x1
#define PMIC_XO_EXTBUF4_CKG_MAN_SHIFT                    7
#define PMIC_XO_EXTBUF4_CKG_EN_M_ADDR                    MT6355_DCXO_CW01
#define PMIC_XO_EXTBUF4_CKG_EN_M_MASK                    0x1
#define PMIC_XO_EXTBUF4_CKG_EN_M_SHIFT                   8
#define PMIC_XO_INTBUF_MAN_ADDR                          MT6355_DCXO_CW01
#define PMIC_XO_INTBUF_MAN_MASK                          0x1
#define PMIC_XO_INTBUF_MAN_SHIFT                         9
#define PMIC_XO_PBUF_EN_M_ADDR                           MT6355_DCXO_CW01
#define PMIC_XO_PBUF_EN_M_MASK                           0x1
#define PMIC_XO_PBUF_EN_M_SHIFT                          10
#define PMIC_XO_IBUF_EN_M_ADDR                           MT6355_DCXO_CW01
#define PMIC_XO_IBUF_EN_M_MASK                           0x1
#define PMIC_XO_IBUF_EN_M_SHIFT                          11
#define PMIC_XO_LPMBUF_MAN_ADDR                          MT6355_DCXO_CW01
#define PMIC_XO_LPMBUF_MAN_MASK                          0x1
#define PMIC_XO_LPMBUF_MAN_SHIFT                         12
#define PMIC_XO_LPM_PREBUF_EN_M_ADDR                     MT6355_DCXO_CW01
#define PMIC_XO_LPM_PREBUF_EN_M_MASK                     0x1
#define PMIC_XO_LPM_PREBUF_EN_M_SHIFT                    13
#define PMIC_XO_LPBUF_EN_M_ADDR                          MT6355_DCXO_CW01
#define PMIC_XO_LPBUF_EN_M_MASK                          0x1
#define PMIC_XO_LPBUF_EN_M_SHIFT                         14
#define PMIC_XO_BBLPM_CKSEL_M_ADDR                       MT6355_DCXO_CW01
#define PMIC_XO_BBLPM_CKSEL_M_MASK                       0x1
#define PMIC_XO_BBLPM_CKSEL_M_SHIFT                      15
#define PMIC_XO_EN32K_MAN_ADDR                           MT6355_DCXO_CW02
#define PMIC_XO_EN32K_MAN_MASK                           0x1
#define PMIC_XO_EN32K_MAN_SHIFT                          0
#define PMIC_XO_EN32K_M_ADDR                             MT6355_DCXO_CW02
#define PMIC_XO_EN32K_M_MASK                             0x1
#define PMIC_XO_EN32K_M_SHIFT                            1
#define PMIC_XO_XMODE_MAN_ADDR                           MT6355_DCXO_CW02
#define PMIC_XO_XMODE_MAN_MASK                           0x1
#define PMIC_XO_XMODE_MAN_SHIFT                          2
#define PMIC_XO_XMODE_M_ADDR                             MT6355_DCXO_CW02
#define PMIC_XO_XMODE_M_MASK                             0x1
#define PMIC_XO_XMODE_M_SHIFT                            3
#define PMIC_XO_STRUP_MODE_ADDR                          MT6355_DCXO_CW02
#define PMIC_XO_STRUP_MODE_MASK                          0x1
#define PMIC_XO_STRUP_MODE_SHIFT                         4
#define PMIC_XO_AAC_FPM_TIME_ADDR                        MT6355_DCXO_CW02
#define PMIC_XO_AAC_FPM_TIME_MASK                        0x3
#define PMIC_XO_AAC_FPM_TIME_SHIFT                       5
#define PMIC_XO_AAC_MODE_LPM_ADDR                        MT6355_DCXO_CW02
#define PMIC_XO_AAC_MODE_LPM_MASK                        0x3
#define PMIC_XO_AAC_MODE_LPM_SHIFT                       7
#define PMIC_XO_AAC_MODE_FPM_ADDR                        MT6355_DCXO_CW02
#define PMIC_XO_AAC_MODE_FPM_MASK                        0x3
#define PMIC_XO_AAC_MODE_FPM_SHIFT                       9
#define PMIC_XO_EN26M_OFFSQ_EN_ADDR                      MT6355_DCXO_CW02
#define PMIC_XO_EN26M_OFFSQ_EN_MASK                      0x1
#define PMIC_XO_EN26M_OFFSQ_EN_SHIFT                     11
#define PMIC_XO_LDOCAL_EN_ADDR                           MT6355_DCXO_CW02
#define PMIC_XO_LDOCAL_EN_MASK                           0x1
#define PMIC_XO_LDOCAL_EN_SHIFT                          12
#define PMIC_XO_CBANK_SYNC_DYN_ADDR                      MT6355_DCXO_CW02
#define PMIC_XO_CBANK_SYNC_DYN_MASK                      0x1
#define PMIC_XO_CBANK_SYNC_DYN_SHIFT                     13
#define PMIC_XO_26MLP_MAN_EN_ADDR                        MT6355_DCXO_CW02
#define PMIC_XO_26MLP_MAN_EN_MASK                        0x1
#define PMIC_XO_26MLP_MAN_EN_SHIFT                       14
#define PMIC_XO_BUFLDOK_EN_ADDR                          MT6355_DCXO_CW02
#define PMIC_XO_BUFLDOK_EN_MASK                          0x1
#define PMIC_XO_BUFLDOK_EN_SHIFT                         15
#define PMIC_XO_RESERVED2_ADDR                           MT6355_DCXO_CW03
#define PMIC_XO_RESERVED2_MASK                           0x3
#define PMIC_XO_RESERVED2_SHIFT                          0
#define PMIC_XO_EXTBUF6_CKG_MAN_ADDR                     MT6355_DCXO_CW03
#define PMIC_XO_EXTBUF6_CKG_MAN_MASK                     0x1
#define PMIC_XO_EXTBUF6_CKG_MAN_SHIFT                    2
#define PMIC_XO_EXTBUF6_CKG_EN_M_ADDR                    MT6355_DCXO_CW03
#define PMIC_XO_EXTBUF6_CKG_EN_M_MASK                    0x1
#define PMIC_XO_EXTBUF6_CKG_EN_M_SHIFT                   3
#define PMIC_XO_EXTBUF7_CKG_MAN_ADDR                     MT6355_DCXO_CW03
#define PMIC_XO_EXTBUF7_CKG_MAN_MASK                     0x1
#define PMIC_XO_EXTBUF7_CKG_MAN_SHIFT                    4
#define PMIC_XO_EXTBUF7_CKG_EN_M_ADDR                    MT6355_DCXO_CW03
#define PMIC_XO_EXTBUF7_CKG_EN_M_MASK                    0x1
#define PMIC_XO_EXTBUF7_CKG_EN_M_SHIFT                   5
#define PMIC_XO_LPM_ISEL_MAN_ADDR                        MT6355_DCXO_CW03
#define PMIC_XO_LPM_ISEL_MAN_MASK                        0x1F
#define PMIC_XO_LPM_ISEL_MAN_SHIFT                       6
#define PMIC_XO_FPM_ISEL_MAN_ADDR                        MT6355_DCXO_CW03
#define PMIC_XO_FPM_ISEL_MAN_MASK                        0x1F
#define PMIC_XO_FPM_ISEL_MAN_SHIFT                       11
#define PMIC_XO_CDAC_FPM_ADDR                            MT6355_DCXO_CW04
#define PMIC_XO_CDAC_FPM_MASK                            0xFF
#define PMIC_XO_CDAC_FPM_SHIFT                           0
#define PMIC_XO_CDAC_LPM_ADDR                            MT6355_DCXO_CW04
#define PMIC_XO_CDAC_LPM_MASK                            0xFF
#define PMIC_XO_CDAC_LPM_SHIFT                           8
#define PMIC_XO_32KDIV_NFRAC_FPM_ADDR                    MT6355_DCXO_CW05
#define PMIC_XO_32KDIV_NFRAC_FPM_MASK                    0x3FFF
#define PMIC_XO_32KDIV_NFRAC_FPM_SHIFT                   0
#define PMIC_XO_COFST_FPM_ADDR                           MT6355_DCXO_CW05
#define PMIC_XO_COFST_FPM_MASK                           0x3
#define PMIC_XO_COFST_FPM_SHIFT                          14
#define PMIC_XO_32KDIV_NFRAC_LPM_ADDR                    MT6355_DCXO_CW06
#define PMIC_XO_32KDIV_NFRAC_LPM_MASK                    0x3FFF
#define PMIC_XO_32KDIV_NFRAC_LPM_SHIFT                   0
#define PMIC_XO_COFST_LPM_ADDR                           MT6355_DCXO_CW06
#define PMIC_XO_COFST_LPM_MASK                           0x3
#define PMIC_XO_COFST_LPM_SHIFT                          14
#define PMIC_XO_CORE_MAN_ADDR                            MT6355_DCXO_CW07
#define PMIC_XO_CORE_MAN_MASK                            0x1
#define PMIC_XO_CORE_MAN_SHIFT                           0
#define PMIC_XO_CORE_EN_M_ADDR                           MT6355_DCXO_CW07
#define PMIC_XO_CORE_EN_M_MASK                           0x1
#define PMIC_XO_CORE_EN_M_SHIFT                          1
#define PMIC_XO_CORE_TURBO_EN_M_ADDR                     MT6355_DCXO_CW07
#define PMIC_XO_CORE_TURBO_EN_M_MASK                     0x1
#define PMIC_XO_CORE_TURBO_EN_M_SHIFT                    2
#define PMIC_XO_CORE_AAC_EN_M_ADDR                       MT6355_DCXO_CW07
#define PMIC_XO_CORE_AAC_EN_M_MASK                       0x1
#define PMIC_XO_CORE_AAC_EN_M_SHIFT                      3
#define PMIC_XO_STARTUP_EN_M_ADDR                        MT6355_DCXO_CW07
#define PMIC_XO_STARTUP_EN_M_MASK                        0x1
#define PMIC_XO_STARTUP_EN_M_SHIFT                       4
#define PMIC_XO_CORE_VBFPM_EN_M_ADDR                     MT6355_DCXO_CW07
#define PMIC_XO_CORE_VBFPM_EN_M_MASK                     0x1
#define PMIC_XO_CORE_VBFPM_EN_M_SHIFT                    5
#define PMIC_XO_CORE_VBLPM_EN_M_ADDR                     MT6355_DCXO_CW07
#define PMIC_XO_CORE_VBLPM_EN_M_MASK                     0x1
#define PMIC_XO_CORE_VBLPM_EN_M_SHIFT                    6
#define PMIC_XO_LPMBIAS_EN_M_ADDR                        MT6355_DCXO_CW07
#define PMIC_XO_LPMBIAS_EN_M_MASK                        0x1
#define PMIC_XO_LPMBIAS_EN_M_SHIFT                       7
#define PMIC_XO_VTCGEN_EN_M_ADDR                         MT6355_DCXO_CW07
#define PMIC_XO_VTCGEN_EN_M_MASK                         0x1
#define PMIC_XO_VTCGEN_EN_M_SHIFT                        8
#define PMIC_XO_IAAC_COMP_EN_M_ADDR                      MT6355_DCXO_CW07
#define PMIC_XO_IAAC_COMP_EN_M_MASK                      0x1
#define PMIC_XO_IAAC_COMP_EN_M_SHIFT                     9
#define PMIC_XO_IFPM_COMP_EN_M_ADDR                      MT6355_DCXO_CW07
#define PMIC_XO_IFPM_COMP_EN_M_MASK                      0x1
#define PMIC_XO_IFPM_COMP_EN_M_SHIFT                     10
#define PMIC_XO_ILPM_COMP_EN_M_ADDR                      MT6355_DCXO_CW07
#define PMIC_XO_ILPM_COMP_EN_M_MASK                      0x1
#define PMIC_XO_ILPM_COMP_EN_M_SHIFT                     11
#define PMIC_XO_CORE_BYPCAS_FPM_ADDR                     MT6355_DCXO_CW07
#define PMIC_XO_CORE_BYPCAS_FPM_MASK                     0x1
#define PMIC_XO_CORE_BYPCAS_FPM_SHIFT                    12
#define PMIC_XO_CORE_GMX2_FPM_ADDR                       MT6355_DCXO_CW07
#define PMIC_XO_CORE_GMX2_FPM_MASK                       0x1
#define PMIC_XO_CORE_GMX2_FPM_SHIFT                      13
#define PMIC_XO_CORE_IDAC_FPM_ADDR                       MT6355_DCXO_CW07
#define PMIC_XO_CORE_IDAC_FPM_MASK                       0x3
#define PMIC_XO_CORE_IDAC_FPM_SHIFT                      14
#define PMIC_XO_AAC_COMP_MAN_ADDR                        MT6355_DCXO_CW08
#define PMIC_XO_AAC_COMP_MAN_MASK                        0x1
#define PMIC_XO_AAC_COMP_MAN_SHIFT                       0
#define PMIC_XO_AAC_EN_M_ADDR                            MT6355_DCXO_CW08
#define PMIC_XO_AAC_EN_M_MASK                            0x1
#define PMIC_XO_AAC_EN_M_SHIFT                           1
#define PMIC_XO_AAC_MONEN_M_ADDR                         MT6355_DCXO_CW08
#define PMIC_XO_AAC_MONEN_M_MASK                         0x1
#define PMIC_XO_AAC_MONEN_M_SHIFT                        2
#define PMIC_XO_COMP_EN_M_ADDR                           MT6355_DCXO_CW08
#define PMIC_XO_COMP_EN_M_MASK                           0x1
#define PMIC_XO_COMP_EN_M_SHIFT                          3
#define PMIC_XO_COMP_TSTEN_M_ADDR                        MT6355_DCXO_CW08
#define PMIC_XO_COMP_TSTEN_M_MASK                        0x1
#define PMIC_XO_COMP_TSTEN_M_SHIFT                       4
#define PMIC_XO_AAC_HV_FPM_ADDR                          MT6355_DCXO_CW08
#define PMIC_XO_AAC_HV_FPM_MASK                          0x1
#define PMIC_XO_AAC_HV_FPM_SHIFT                         5
#define PMIC_XO_AAC_IBIAS_FPM_ADDR                       MT6355_DCXO_CW08
#define PMIC_XO_AAC_IBIAS_FPM_MASK                       0x3
#define PMIC_XO_AAC_IBIAS_FPM_SHIFT                      6
#define PMIC_XO_AAC_VOFST_FPM_ADDR                       MT6355_DCXO_CW08
#define PMIC_XO_AAC_VOFST_FPM_MASK                       0x3
#define PMIC_XO_AAC_VOFST_FPM_SHIFT                      8
#define PMIC_XO_AAC_COMP_HV_FPM_ADDR                     MT6355_DCXO_CW08
#define PMIC_XO_AAC_COMP_HV_FPM_MASK                     0x1
#define PMIC_XO_AAC_COMP_HV_FPM_SHIFT                    10
#define PMIC_XO_AAC_VSEL_FPM_ADDR                        MT6355_DCXO_CW08
#define PMIC_XO_AAC_VSEL_FPM_MASK                        0xF
#define PMIC_XO_AAC_VSEL_FPM_SHIFT                       11
#define PMIC_XO_AAC_COMP_POL_ADDR                        MT6355_DCXO_CW08
#define PMIC_XO_AAC_COMP_POL_MASK                        0x1
#define PMIC_XO_AAC_COMP_POL_SHIFT                       15
#define PMIC_XO_CORE_BYPCAS_LPM_ADDR                     MT6355_DCXO_CW09
#define PMIC_XO_CORE_BYPCAS_LPM_MASK                     0x1
#define PMIC_XO_CORE_BYPCAS_LPM_SHIFT                    0
#define PMIC_XO_CORE_GMX2_LPM_ADDR                       MT6355_DCXO_CW09
#define PMIC_XO_CORE_GMX2_LPM_MASK                       0x1
#define PMIC_XO_CORE_GMX2_LPM_SHIFT                      1
#define PMIC_XO_CORE_IDAC_LPM_ADDR                       MT6355_DCXO_CW09
#define PMIC_XO_CORE_IDAC_LPM_MASK                       0x3
#define PMIC_XO_CORE_IDAC_LPM_SHIFT                      2
#define PMIC_XO_AAC_COMP_HV_LPM_ADDR                     MT6355_DCXO_CW09
#define PMIC_XO_AAC_COMP_HV_LPM_MASK                     0x1
#define PMIC_XO_AAC_COMP_HV_LPM_SHIFT                    4
#define PMIC_XO_AAC_VSEL_LPM_ADDR                        MT6355_DCXO_CW09
#define PMIC_XO_AAC_VSEL_LPM_MASK                        0xF
#define PMIC_XO_AAC_VSEL_LPM_SHIFT                       5
#define PMIC_XO_AAC_HV_LPM_ADDR                          MT6355_DCXO_CW09
#define PMIC_XO_AAC_HV_LPM_MASK                          0x1
#define PMIC_XO_AAC_HV_LPM_SHIFT                         9
#define PMIC_XO_AAC_IBIAS_LPM_ADDR                       MT6355_DCXO_CW09
#define PMIC_XO_AAC_IBIAS_LPM_MASK                       0x3
#define PMIC_XO_AAC_IBIAS_LPM_SHIFT                      10
#define PMIC_XO_AAC_VOFST_LPM_ADDR                       MT6355_DCXO_CW09
#define PMIC_XO_AAC_VOFST_LPM_MASK                       0x3
#define PMIC_XO_AAC_VOFST_LPM_SHIFT                      12
#define PMIC_XO_AAC_FPM_SWEN_ADDR                        MT6355_DCXO_CW09
#define PMIC_XO_AAC_FPM_SWEN_MASK                        0x1
#define PMIC_XO_AAC_FPM_SWEN_SHIFT                       14
#define PMIC_XO_SWRST_ADDR                               MT6355_DCXO_CW09
#define PMIC_XO_SWRST_MASK                               0x1
#define PMIC_XO_SWRST_SHIFT                              15
#define PMIC_XO_32KDIV_SWRST_ADDR                        MT6355_DCXO_CW10
#define PMIC_XO_32KDIV_SWRST_MASK                        0x1
#define PMIC_XO_32KDIV_SWRST_SHIFT                       0
#define PMIC_XO_32KDIV_RATIO_MAN_ADDR                    MT6355_DCXO_CW10
#define PMIC_XO_32KDIV_RATIO_MAN_MASK                    0x1
#define PMIC_XO_32KDIV_RATIO_MAN_SHIFT                   1
#define PMIC_XO_32KDIV_TEST_EN_ADDR                      MT6355_DCXO_CW10
#define PMIC_XO_32KDIV_TEST_EN_MASK                      0x1
#define PMIC_XO_32KDIV_TEST_EN_SHIFT                     2
#define PMIC_XO_CBANK_SYNC_MAN_ADDR                      MT6355_DCXO_CW10
#define PMIC_XO_CBANK_SYNC_MAN_MASK                      0x1
#define PMIC_XO_CBANK_SYNC_MAN_SHIFT                     3
#define PMIC_XO_CBANK_SYNC_EN_M_ADDR                     MT6355_DCXO_CW10
#define PMIC_XO_CBANK_SYNC_EN_M_MASK                     0x1
#define PMIC_XO_CBANK_SYNC_EN_M_SHIFT                    4
#define PMIC_XO_CTL_SYNC_MAN_ADDR                        MT6355_DCXO_CW10
#define PMIC_XO_CTL_SYNC_MAN_MASK                        0x1
#define PMIC_XO_CTL_SYNC_MAN_SHIFT                       5
#define PMIC_XO_CTL_SYNC_EN_M_ADDR                       MT6355_DCXO_CW10
#define PMIC_XO_CTL_SYNC_EN_M_MASK                       0x1
#define PMIC_XO_CTL_SYNC_EN_M_SHIFT                      6
#define PMIC_XO_LDO_MAN_ADDR                             MT6355_DCXO_CW10
#define PMIC_XO_LDO_MAN_MASK                             0x1
#define PMIC_XO_LDO_MAN_SHIFT                            7
#define PMIC_XO_LDOPBUF_EN_M_ADDR                        MT6355_DCXO_CW10
#define PMIC_XO_LDOPBUF_EN_M_MASK                        0x1
#define PMIC_XO_LDOPBUF_EN_M_SHIFT                       8
#define PMIC_XO_LDOPBUF_VSET_M_ADDR                      MT6355_DCXO_CW10
#define PMIC_XO_LDOPBUF_VSET_M_MASK                      0xF
#define PMIC_XO_LDOPBUF_VSET_M_SHIFT                     9
#define PMIC_XO_LDOVTST_EN_M_ADDR                        MT6355_DCXO_CW10
#define PMIC_XO_LDOVTST_EN_M_MASK                        0x1
#define PMIC_XO_LDOVTST_EN_M_SHIFT                       13
#define PMIC_XO_TEST_VCAL_EN_M_ADDR                      MT6355_DCXO_CW10
#define PMIC_XO_TEST_VCAL_EN_M_MASK                      0x1
#define PMIC_XO_TEST_VCAL_EN_M_SHIFT                     14
#define PMIC_XO_VBIST_EN_M_ADDR                          MT6355_DCXO_CW10
#define PMIC_XO_VBIST_EN_M_MASK                          0x1
#define PMIC_XO_VBIST_EN_M_SHIFT                         15
#define PMIC_XO_VTEST_SEL_MUX_ADDR                       MT6355_DCXO_CW11
#define PMIC_XO_VTEST_SEL_MUX_MASK                       0x1F
#define PMIC_XO_VTEST_SEL_MUX_SHIFT                      0
#define PMIC_XO_RESERVED3_ADDR                           MT6355_DCXO_CW11
#define PMIC_XO_RESERVED3_MASK                           0x7
#define PMIC_XO_RESERVED3_SHIFT                          5
#define PMIC_XO_EXTBUF6_MODE_ADDR                        MT6355_DCXO_CW11
#define PMIC_XO_EXTBUF6_MODE_MASK                        0x3
#define PMIC_XO_EXTBUF6_MODE_SHIFT                       8
#define PMIC_XO_EXTBUF6_EN_M_ADDR                        MT6355_DCXO_CW11
#define PMIC_XO_EXTBUF6_EN_M_MASK                        0x1
#define PMIC_XO_EXTBUF6_EN_M_SHIFT                       10
#define PMIC_XO_EXTBUF7_MODE_ADDR                        MT6355_DCXO_CW11
#define PMIC_XO_EXTBUF7_MODE_MASK                        0x3
#define PMIC_XO_EXTBUF7_MODE_SHIFT                       11
#define PMIC_XO_EXTBUF7_EN_M_ADDR                        MT6355_DCXO_CW11
#define PMIC_XO_EXTBUF7_EN_M_MASK                        0x1
#define PMIC_XO_EXTBUF7_EN_M_SHIFT                       13
#define PMIC_XO_BUFLDOK_MAN_ADDR                         MT6355_DCXO_CW11
#define PMIC_XO_BUFLDOK_MAN_MASK                         0x1
#define PMIC_XO_BUFLDOK_MAN_SHIFT                        14
#define PMIC_XO_BUF1LDO_CAL_M_ADDR                       MT6355_DCXO_CW11
#define PMIC_XO_BUF1LDO_CAL_M_MASK                       0x1
#define PMIC_XO_BUF1LDO_CAL_M_SHIFT                      15
#define PMIC_DCXO_CW11_SET_ADDR                          MT6355_DCXO_CW11_SET
#define PMIC_DCXO_CW11_SET_MASK                          0xFFFF
#define PMIC_DCXO_CW11_SET_SHIFT                         0
#define PMIC_DCXO_CW11_CLR_ADDR                          MT6355_DCXO_CW11_CLR
#define PMIC_DCXO_CW11_CLR_MASK                          0xFFFF
#define PMIC_DCXO_CW11_CLR_SHIFT                         0
#define PMIC_XO_BUFLDO_CAL_M_ADDR                        MT6355_DCXO_CW12
#define PMIC_XO_BUFLDO_CAL_M_MASK                        0x1
#define PMIC_XO_BUFLDO_CAL_M_SHIFT                       0
#define PMIC_XO_EXTBUF4_CLKSEL_MAN_ADDR                  MT6355_DCXO_CW12
#define PMIC_XO_EXTBUF4_CLKSEL_MAN_MASK                  0x1
#define PMIC_XO_EXTBUF4_CLKSEL_MAN_SHIFT                 1
#define PMIC_XO_VIO18PG_BUFEN_ADDR                       MT6355_DCXO_CW12
#define PMIC_XO_VIO18PG_BUFEN_MASK                       0x1
#define PMIC_XO_VIO18PG_BUFEN_SHIFT                      2
#define PMIC_XO_CAL_EN_MAN_ADDR                          MT6355_DCXO_CW12
#define PMIC_XO_CAL_EN_MAN_MASK                          0x1
#define PMIC_XO_CAL_EN_MAN_SHIFT                         3
#define PMIC_XO_CAL_EN_M_ADDR                            MT6355_DCXO_CW12
#define PMIC_XO_CAL_EN_M_MASK                            0x1
#define PMIC_XO_CAL_EN_M_SHIFT                           4
#define PMIC_RG_XO_CORE_OSCTD_ADDR                       MT6355_DCXO_CW12
#define PMIC_RG_XO_CORE_OSCTD_MASK                       0x3
#define PMIC_RG_XO_CORE_OSCTD_SHIFT                      5
#define PMIC_XO_THADC_EN_ADDR                            MT6355_DCXO_CW12
#define PMIC_XO_THADC_EN_MASK                            0x1
#define PMIC_XO_THADC_EN_SHIFT                           7
#define PMIC_RG_XO_SYNC_CKPOL_ADDR                       MT6355_DCXO_CW12
#define PMIC_RG_XO_SYNC_CKPOL_MASK                       0x1
#define PMIC_RG_XO_SYNC_CKPOL_SHIFT                      8
#define PMIC_RG_XO_CBANK_POL_ADDR                        MT6355_DCXO_CW12
#define PMIC_RG_XO_CBANK_POL_MASK                        0x1
#define PMIC_RG_XO_CBANK_POL_SHIFT                       9
#define PMIC_RG_XO_CBANK_SYNC_BYP_ADDR                   MT6355_DCXO_CW12
#define PMIC_RG_XO_CBANK_SYNC_BYP_MASK                   0x1
#define PMIC_RG_XO_CBANK_SYNC_BYP_SHIFT                  10
#define PMIC_RG_XO_CTL_POL_ADDR                          MT6355_DCXO_CW12
#define PMIC_RG_XO_CTL_POL_MASK                          0x1
#define PMIC_RG_XO_CTL_POL_SHIFT                         11
#define PMIC_RG_XO_CTL_SYNC_BYP_ADDR                     MT6355_DCXO_CW12
#define PMIC_RG_XO_CTL_SYNC_BYP_MASK                     0x1
#define PMIC_RG_XO_CTL_SYNC_BYP_SHIFT                    12
#define PMIC_RG_XO_LPBUF_INV_ADDR                        MT6355_DCXO_CW12
#define PMIC_RG_XO_LPBUF_INV_MASK                        0x1
#define PMIC_RG_XO_LPBUF_INV_SHIFT                       13
#define PMIC_RG_XO_LDOPBUF_BYP_ADDR                      MT6355_DCXO_CW12
#define PMIC_RG_XO_LDOPBUF_BYP_MASK                      0x1
#define PMIC_RG_XO_LDOPBUF_BYP_SHIFT                     14
#define PMIC_RG_XO_LDOPBUF_ENCL_ADDR                     MT6355_DCXO_CW12
#define PMIC_RG_XO_LDOPBUF_ENCL_MASK                     0x1
#define PMIC_RG_XO_LDOPBUF_ENCL_SHIFT                    15
#define PMIC_RG_XO_VGBIAS_VSET_ADDR                      MT6355_DCXO_CW13
#define PMIC_RG_XO_VGBIAS_VSET_MASK                      0x3
#define PMIC_RG_XO_VGBIAS_VSET_SHIFT                     0
#define PMIC_RG_XO_PBUF_ISET_ADDR                        MT6355_DCXO_CW13
#define PMIC_RG_XO_PBUF_ISET_MASK                        0x3
#define PMIC_RG_XO_PBUF_ISET_SHIFT                       2
#define PMIC_RG_XO_IBUF_ISET_ADDR                        MT6355_DCXO_CW13
#define PMIC_RG_XO_IBUF_ISET_MASK                        0x3
#define PMIC_RG_XO_IBUF_ISET_SHIFT                       4
#define PMIC_RG_XO_RESERVED4_ADDR                        MT6355_DCXO_CW13
#define PMIC_RG_XO_RESERVED4_MASK                        0x3
#define PMIC_RG_XO_RESERVED4_SHIFT                       6
#define PMIC_RG_XO_VOW_EN_ADDR                           MT6355_DCXO_CW13
#define PMIC_RG_XO_VOW_EN_MASK                           0x1
#define PMIC_RG_XO_VOW_EN_SHIFT                          8
#define PMIC_RG_XO_VOW_DIV_ADDR                          MT6355_DCXO_CW13
#define PMIC_RG_XO_VOW_DIV_MASK                          0x3
#define PMIC_RG_XO_VOW_DIV_SHIFT                         9
#define PMIC_RG_XO_BUFLDO24_ENCL_ADDR                    MT6355_DCXO_CW13
#define PMIC_RG_XO_BUFLDO24_ENCL_MASK                    0x1
#define PMIC_RG_XO_BUFLDO24_ENCL_SHIFT                   11
#define PMIC_RG_XO_BUFLDO24_IBX2_ADDR                    MT6355_DCXO_CW13
#define PMIC_RG_XO_BUFLDO24_IBX2_MASK                    0x1
#define PMIC_RG_XO_BUFLDO24_IBX2_SHIFT                   12
#define PMIC_RG_XO_RESERVED5_ADDR                        MT6355_DCXO_CW13
#define PMIC_RG_XO_RESERVED5_MASK                        0x7
#define PMIC_RG_XO_RESERVED5_SHIFT                       13
#define PMIC_RG_XO_BUFLDO13_ENCL_ADDR                    MT6355_DCXO_CW14
#define PMIC_RG_XO_BUFLDO13_ENCL_MASK                    0x1
#define PMIC_RG_XO_BUFLDO13_ENCL_SHIFT                   0
#define PMIC_RG_XO_BUFLDO13_IBX2_ADDR                    MT6355_DCXO_CW14
#define PMIC_RG_XO_BUFLDO13_IBX2_MASK                    0x1
#define PMIC_RG_XO_BUFLDO13_IBX2_SHIFT                   1
#define PMIC_RG_XO_BUFLDO13_IX2_ADDR                     MT6355_DCXO_CW14
#define PMIC_RG_XO_BUFLDO13_IX2_MASK                     0x1
#define PMIC_RG_XO_BUFLDO13_IX2_SHIFT                    2
#define PMIC_RG_XO_LVLDO_I_CTRL_ADDR                     MT6355_DCXO_CW14
#define PMIC_RG_XO_LVLDO_I_CTRL_MASK                     0x3
#define PMIC_RG_XO_LVLDO_I_CTRL_SHIFT                    3
#define PMIC_RG_XO_BUFLDO67_ENCL_ADDR                    MT6355_DCXO_CW14
#define PMIC_RG_XO_BUFLDO67_ENCL_MASK                    0x1
#define PMIC_RG_XO_BUFLDO67_ENCL_SHIFT                   5
#define PMIC_RG_XO_BUFLDO67_IBX2_ADDR                    MT6355_DCXO_CW14
#define PMIC_RG_XO_BUFLDO67_IBX2_MASK                    0x1
#define PMIC_RG_XO_BUFLDO67_IBX2_SHIFT                   6
#define PMIC_RG_XO_BUFLDO67_IX2_ADDR                     MT6355_DCXO_CW14
#define PMIC_RG_XO_BUFLDO67_IX2_MASK                     0x1
#define PMIC_RG_XO_BUFLDO67_IX2_SHIFT                    7
#define PMIC_RG_XO_LVLDO_RFB_ADDR                        MT6355_DCXO_CW14
#define PMIC_RG_XO_LVLDO_RFB_MASK                        0x3
#define PMIC_RG_XO_LVLDO_RFB_SHIFT                       8
#define PMIC_RG_XO_EXTBUF_INV_ADDR                       MT6355_DCXO_CW14
#define PMIC_RG_XO_EXTBUF_INV_MASK                       0x1
#define PMIC_RG_XO_EXTBUF_INV_SHIFT                      10
#define PMIC_RG_XO_RESERVED0_ADDR                        MT6355_DCXO_CW14
#define PMIC_RG_XO_RESERVED0_MASK                        0x1
#define PMIC_RG_XO_RESERVED0_SHIFT                       11
#define PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR                  MT6355_DCXO_CW14
#define PMIC_XO_EXTBUF2_CLKSEL_MAN_MASK                  0x1
#define PMIC_XO_EXTBUF2_CLKSEL_MAN_SHIFT                 12
#define PMIC_XO_AUDIO_EN_M_ADDR                          MT6355_DCXO_CW14
#define PMIC_XO_AUDIO_EN_M_MASK                          0x1
#define PMIC_XO_AUDIO_EN_M_SHIFT                         13
#define PMIC_RG_XO_AUDIO_ATTEN_ADDR                      MT6355_DCXO_CW14
#define PMIC_RG_XO_AUDIO_ATTEN_MASK                      0x3
#define PMIC_RG_XO_AUDIO_ATTEN_SHIFT                     14
#define PMIC_RG_XO_AUDIO_ISET_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_AUDIO_ISET_MASK                       0x3
#define PMIC_RG_XO_AUDIO_ISET_SHIFT                      0
#define PMIC_RG_XO_EXTBUF1_HD_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_EXTBUF1_HD_MASK                       0x3
#define PMIC_RG_XO_EXTBUF1_HD_SHIFT                      2
#define PMIC_RG_XO_EXTBUF2_HD_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_EXTBUF2_HD_MASK                       0x3
#define PMIC_RG_XO_EXTBUF2_HD_SHIFT                      4
#define PMIC_RG_XO_EXTBUF3_HD_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_EXTBUF3_HD_MASK                       0x3
#define PMIC_RG_XO_EXTBUF3_HD_SHIFT                      6
#define PMIC_RG_XO_EXTBUF4_HD_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_EXTBUF4_HD_MASK                       0x3
#define PMIC_RG_XO_EXTBUF4_HD_SHIFT                      8
#define PMIC_RG_XO_RESERVED8_ADDR                        MT6355_DCXO_CW15
#define PMIC_RG_XO_RESERVED8_MASK                        0x3
#define PMIC_RG_XO_RESERVED8_SHIFT                       10
#define PMIC_RG_XO_EXTBUF6_HD_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_EXTBUF6_HD_MASK                       0x3
#define PMIC_RG_XO_EXTBUF6_HD_SHIFT                      12
#define PMIC_RG_XO_EXTBUF7_HD_ADDR                       MT6355_DCXO_CW15
#define PMIC_RG_XO_EXTBUF7_HD_MASK                       0x3
#define PMIC_RG_XO_EXTBUF7_HD_SHIFT                      14
#define PMIC_XO_EXTBUF1_ISET_M_ADDR                      MT6355_DCXO_CW16
#define PMIC_XO_EXTBUF1_ISET_M_MASK                      0x3
#define PMIC_XO_EXTBUF1_ISET_M_SHIFT                     0
#define PMIC_XO_EXTBUF2_ISET_M_ADDR                      MT6355_DCXO_CW16
#define PMIC_XO_EXTBUF2_ISET_M_MASK                      0x3
#define PMIC_XO_EXTBUF2_ISET_M_SHIFT                     2
#define PMIC_XO_EXTBUF3_ISET_M_ADDR                      MT6355_DCXO_CW16
#define PMIC_XO_EXTBUF3_ISET_M_MASK                      0x3
#define PMIC_XO_EXTBUF3_ISET_M_SHIFT                     4
#define PMIC_XO_EXTBUF4_ISET_M_ADDR                      MT6355_DCXO_CW16
#define PMIC_XO_EXTBUF4_ISET_M_MASK                      0x3
#define PMIC_XO_EXTBUF4_ISET_M_SHIFT                     6
#define PMIC_XO_RESERVED9_ADDR                           MT6355_DCXO_CW16
#define PMIC_XO_RESERVED9_MASK                           0x3
#define PMIC_XO_RESERVED9_SHIFT                          8
#define PMIC_XO_EXTBUF6_ISET_M_ADDR                      MT6355_DCXO_CW16
#define PMIC_XO_EXTBUF6_ISET_M_MASK                      0x3
#define PMIC_XO_EXTBUF6_ISET_M_SHIFT                     10
#define PMIC_XO_EXTBUF7_ISET_M_ADDR                      MT6355_DCXO_CW16
#define PMIC_XO_EXTBUF7_ISET_M_MASK                      0x3
#define PMIC_XO_EXTBUF7_ISET_M_SHIFT                     12
#define PMIC_RG_XO_LPM_PREBUF_ISET_ADDR                  MT6355_DCXO_CW16
#define PMIC_RG_XO_LPM_PREBUF_ISET_MASK                  0x3
#define PMIC_RG_XO_LPM_PREBUF_ISET_SHIFT                 14
#define PMIC_RG_XO_RESERVED1_ADDR                        MT6355_DCXO_CW17
#define PMIC_RG_XO_RESERVED1_MASK                        0x3
#define PMIC_RG_XO_RESERVED1_SHIFT                       0
#define PMIC_XO_THADC_EN_MAN_ADDR                        MT6355_DCXO_CW17
#define PMIC_XO_THADC_EN_MAN_MASK                        0x1
#define PMIC_XO_THADC_EN_MAN_SHIFT                       2
#define PMIC_RG_XO_TSOURCE_EN_ADDR                       MT6355_DCXO_CW17
#define PMIC_RG_XO_TSOURCE_EN_MASK                       0x1
#define PMIC_RG_XO_TSOURCE_EN_SHIFT                      3
#define PMIC_XO_BUFLDO13_VSET_M_ADDR                     MT6355_DCXO_CW17
#define PMIC_XO_BUFLDO13_VSET_M_MASK                     0xF
#define PMIC_XO_BUFLDO13_VSET_M_SHIFT                    4
#define PMIC_XO_BUFLDO24_VSET_M_ADDR                     MT6355_DCXO_CW17
#define PMIC_XO_BUFLDO24_VSET_M_MASK                     0xF
#define PMIC_XO_BUFLDO24_VSET_M_SHIFT                    8
#define PMIC_XO_BUFLDO67_VSET_M_ADDR                     MT6355_DCXO_CW17
#define PMIC_XO_BUFLDO67_VSET_M_MASK                     0xF
#define PMIC_XO_BUFLDO67_VSET_M_SHIFT                    12
#define PMIC_XO_STATIC_AUXOUT_SEL_ADDR                   MT6355_DCXO_CW18
#define PMIC_XO_STATIC_AUXOUT_SEL_MASK                   0x3F
#define PMIC_XO_STATIC_AUXOUT_SEL_SHIFT                  0
#define PMIC_XO_AUXOUT_SEL_ADDR                          MT6355_DCXO_CW18
#define PMIC_XO_AUXOUT_SEL_MASK                          0x3FF
#define PMIC_XO_AUXOUT_SEL_SHIFT                         6
#define PMIC_XO_STATIC_AUXOUT_ADDR                       MT6355_DCXO_CW19
#define PMIC_XO_STATIC_AUXOUT_MASK                       0xFFFF
#define PMIC_XO_STATIC_AUXOUT_SHIFT                      0
#define PMIC_RG_XO_PCTAT_COMP_EN_ADDR                    MT6355_DCXO_CW20
#define PMIC_RG_XO_PCTAT_COMP_EN_MASK                    0x1
#define PMIC_RG_XO_PCTAT_COMP_EN_SHIFT                   0
#define PMIC_RG_XO_PCTAT_RDEG_SEL_ADDR                   MT6355_DCXO_CW20
#define PMIC_RG_XO_PCTAT_RDEG_SEL_MASK                   0x1
#define PMIC_RG_XO_PCTAT_RDEG_SEL_SHIFT                  1
#define PMIC_RG_XO_GS_VTEMP_ADDR                         MT6355_DCXO_CW20
#define PMIC_RG_XO_GS_VTEMP_MASK                         0x7
#define PMIC_RG_XO_GS_VTEMP_SHIFT                        2
#define PMIC_RG_XO_HEATER_SEL_ADDR                       MT6355_DCXO_CW20
#define PMIC_RG_XO_HEATER_SEL_MASK                       0x3
#define PMIC_RG_XO_HEATER_SEL_SHIFT                      5
#define PMIC_RG_XO_CORNER_DETECT_EN_ADDR                 MT6355_DCXO_CW20
#define PMIC_RG_XO_CORNER_DETECT_EN_MASK                 0x1
#define PMIC_RG_XO_CORNER_DETECT_EN_SHIFT                7
#define PMIC_RG_XO_CORNER_DETECT_EN_MAN_ADDR             MT6355_DCXO_CW20
#define PMIC_RG_XO_CORNER_DETECT_EN_MAN_MASK             0x1
#define PMIC_RG_XO_CORNER_DETECT_EN_MAN_SHIFT            8
#define PMIC_RG_XO_RESRVED10_ADDR                        MT6355_DCXO_CW20
#define PMIC_RG_XO_RESRVED10_MASK                        0x7F
#define PMIC_RG_XO_RESRVED10_SHIFT                       9
#define PMIC_RG_XO_CORNER_SETTING_TUNE_ADDR              MT6355_DCXO_CW21
#define PMIC_RG_XO_CORNER_SETTING_TUNE_MASK              0x3FF
#define PMIC_RG_XO_CORNER_SETTING_TUNE_SHIFT             0
#define PMIC_RG_XO_RESRVED11_ADDR                        MT6355_DCXO_CW21
#define PMIC_RG_XO_RESRVED11_MASK                        0x3F
#define PMIC_RG_XO_RESRVED11_SHIFT                       10
#define PMIC_RG_AD_XO_CORNER_CAL_DONE_ADDR               MT6355_DCXO_CW22
#define PMIC_RG_AD_XO_CORNER_CAL_DONE_MASK               0x1
#define PMIC_RG_AD_XO_CORNER_CAL_DONE_SHIFT              0
#define PMIC_RG_AD_XO_CORNER_SEL_ADDR                    MT6355_DCXO_CW22
#define PMIC_RG_AD_XO_CORNER_SEL_MASK                    0xF
#define PMIC_RG_AD_XO_CORNER_SEL_SHIFT                   1
#define PMIC_RG_VCDT_HV_EN_ADDR                          MT6355_CHR_CON0
#define PMIC_RG_VCDT_HV_EN_MASK                          0x1
#define PMIC_RG_VCDT_HV_EN_SHIFT                         0
#define PMIC_RG_VCDT_DEB_SEL_ADDR                        MT6355_CHR_CON0
#define PMIC_RG_VCDT_DEB_SEL_MASK                        0x1
#define PMIC_RG_VCDT_DEB_SEL_SHIFT                       2
#define PMIC_RG_PCHR_FT_CTRL_ADDR                        MT6355_CHR_CON0
#define PMIC_RG_PCHR_FT_CTRL_MASK                        0x1
#define PMIC_RG_PCHR_FT_CTRL_SHIFT                       4
#define PMIC_RGS_CHRDET_ADDR                             MT6355_CHR_CON0
#define PMIC_RGS_CHRDET_MASK                             0x1
#define PMIC_RGS_CHRDET_SHIFT                            5
#define PMIC_RGS_VCDT_LV_DET_ADDR                        MT6355_CHR_CON0
#define PMIC_RGS_VCDT_LV_DET_MASK                        0x1
#define PMIC_RGS_VCDT_LV_DET_SHIFT                       6
#define PMIC_RGS_VCDT_HV_DET_ADDR                        MT6355_CHR_CON0
#define PMIC_RGS_VCDT_HV_DET_MASK                        0x1
#define PMIC_RGS_VCDT_HV_DET_SHIFT                       7
#define PMIC_RG_VCDT_LV_VTH_ADDR                         MT6355_CHR_CON1
#define PMIC_RG_VCDT_LV_VTH_MASK                         0xF
#define PMIC_RG_VCDT_LV_VTH_SHIFT                        0
#define PMIC_RG_VCDT_HV_VTH_ADDR                         MT6355_CHR_CON1
#define PMIC_RG_VCDT_HV_VTH_MASK                         0xF
#define PMIC_RG_VCDT_HV_VTH_SHIFT                        4
#define PMIC_RGS_PCHR_FLAG_OUT_ADDR                      MT6355_CHR_CON2
#define PMIC_RGS_PCHR_FLAG_OUT_MASK                      0xF
#define PMIC_RGS_PCHR_FLAG_OUT_SHIFT                     0
#define PMIC_RG_PCHR_FLAG_EN_ADDR                        MT6355_CHR_CON2
#define PMIC_RG_PCHR_FLAG_EN_MASK                        0x1
#define PMIC_RG_PCHR_FLAG_EN_SHIFT                       4
#define PMIC_RG_PCHR_FLAG_SEL_ADDR                       MT6355_CHR_CON3
#define PMIC_RG_PCHR_FLAG_SEL_MASK                       0xF
#define PMIC_RG_PCHR_FLAG_SEL_SHIFT                      0
#define PMIC_RG_PCHR_RSV_ADDR                            MT6355_CHR_CON4
#define PMIC_RG_PCHR_RSV_MASK                            0xFF
#define PMIC_RG_PCHR_RSV_SHIFT                           0
#define PMIC_RG_ENVTEM_D_ADDR                            MT6355_CHR_CON5
#define PMIC_RG_ENVTEM_D_MASK                            0x1
#define PMIC_RG_ENVTEM_D_SHIFT                           0
#define PMIC_RG_ENVTEM_EN_ADDR                           MT6355_CHR_CON5
#define PMIC_RG_ENVTEM_EN_MASK                           0x1
#define PMIC_RG_ENVTEM_EN_SHIFT                          1
#define PMIC_RG_CHR_CON6_RSV_ADDR                        MT6355_CHR_CON6
#define PMIC_RG_CHR_CON6_RSV_MASK                        0xFFFF
#define PMIC_RG_CHR_CON6_RSV_SHIFT                       0
#define PMIC_RG_ADCIN_VSEN_MUX_EN_ADDR                   MT6355_CHR_CON7
#define PMIC_RG_ADCIN_VSEN_MUX_EN_MASK                   0x1
#define PMIC_RG_ADCIN_VSEN_MUX_EN_SHIFT                  8
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_ADDR             MT6355_CHR_CON7
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK             0x1
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT            9
#define PMIC_RG_ADCIN_VBAT_EN_ADDR                       MT6355_CHR_CON7
#define PMIC_RG_ADCIN_VBAT_EN_MASK                       0x1
#define PMIC_RG_ADCIN_VBAT_EN_SHIFT                      10
#define PMIC_RG_ADCIN_VSEN_EN_ADDR                       MT6355_CHR_CON7
#define PMIC_RG_ADCIN_VSEN_EN_MASK                       0x1
#define PMIC_RG_ADCIN_VSEN_EN_SHIFT                      11
#define PMIC_RG_ADCIN_CHR_EN_ADDR                        MT6355_CHR_CON7
#define PMIC_RG_ADCIN_CHR_EN_MASK                        0x1
#define PMIC_RG_ADCIN_CHR_EN_SHIFT                       12
#define PMIC_DA_QI_BATON_LT_EN_ADDR                      MT6355_PCHR_VREF_ANA_DA0
#define PMIC_DA_QI_BATON_LT_EN_MASK                      0x1
#define PMIC_DA_QI_BATON_LT_EN_SHIFT                     0
#define PMIC_DA_QI_BGR_EXT_BUF_EN_ADDR                   MT6355_PCHR_VREF_ANA_DA0
#define PMIC_DA_QI_BGR_EXT_BUF_EN_MASK                   0x1
#define PMIC_DA_QI_BGR_EXT_BUF_EN_SHIFT                  1
#define PMIC_BATON_TDET_EN_ADDR                          MT6355_PCHR_VREF_ANA_DA0
#define PMIC_BATON_TDET_EN_MASK                          0x1
#define PMIC_BATON_TDET_EN_SHIFT                         2
#define PMIC_RG_BGR_UNCHOP_ADDR                          MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_UNCHOP_MASK                          0x1
#define PMIC_RG_BGR_UNCHOP_SHIFT                         0
#define PMIC_RG_BGR_UNCHOP_PH_ADDR                       MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_UNCHOP_PH_MASK                       0x1
#define PMIC_RG_BGR_UNCHOP_PH_SHIFT                      1
#define PMIC_RG_BGR_RSEL_ADDR                            MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_RSEL_MASK                            0xF
#define PMIC_RG_BGR_RSEL_SHIFT                           2
#define PMIC_RG_BGR_TRIM_EN_ADDR                         MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_TRIM_EN_MASK                         0x1
#define PMIC_RG_BGR_TRIM_EN_SHIFT                        6
#define PMIC_RG_BGR_TEST_RSTB_ADDR                       MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_TEST_RSTB_MASK                       0x1
#define PMIC_RG_BGR_TEST_RSTB_SHIFT                      7
#define PMIC_RG_BGR_TRIM_ADDR                            MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_TRIM_MASK                            0x1F
#define PMIC_RG_BGR_TRIM_SHIFT                           8
#define PMIC_RG_BGR_TEST_EN_ADDR                         MT6355_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_TEST_EN_MASK                         0x1
#define PMIC_RG_BGR_TEST_EN_SHIFT                        13
#define PMIC_RG_VCDT_TRIM_ADDR                           MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_VCDT_TRIM_MASK                           0xF
#define PMIC_RG_VCDT_TRIM_SHIFT                          0
#define PMIC_RG_BATON_EN_ADDR                            MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_BATON_EN_MASK                            0x1
#define PMIC_RG_BATON_EN_SHIFT                           4
#define PMIC_RG_BATON_HT_TRIM_ADDR                       MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_BATON_HT_TRIM_MASK                       0x7
#define PMIC_RG_BATON_HT_TRIM_SHIFT                      5
#define PMIC_RG_HW_VTH1_ADDR                             MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_HW_VTH1_MASK                             0x3
#define PMIC_RG_HW_VTH1_SHIFT                            8
#define PMIC_RG_HW_VTH2_ADDR                             MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_HW_VTH2_MASK                             0x3
#define PMIC_RG_HW_VTH2_SHIFT                            10
#define PMIC_RG_HW_VTH_CTRL_ADDR                         MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_HW_VTH_CTRL_MASK                         0x1
#define PMIC_RG_HW_VTH_CTRL_SHIFT                        12
#define PMIC_RG_OTG_BVALID_EN_ADDR                       MT6355_PCHR_VREF_ANA_CON1
#define PMIC_RG_OTG_BVALID_EN_MASK                       0x1
#define PMIC_RG_OTG_BVALID_EN_SHIFT                      13
#define PMIC_RG_UVLO_VTHL_ADDR                           MT6355_PCHR_VREF_ANA_CON2
#define PMIC_RG_UVLO_VTHL_MASK                           0x1F
#define PMIC_RG_UVLO_VTHL_SHIFT                          0
#define PMIC_RG_UVLO_VH_LAT_ADDR                         MT6355_PCHR_VREF_ANA_CON2
#define PMIC_RG_UVLO_VH_LAT_MASK                         0x1
#define PMIC_RG_UVLO_VH_LAT_SHIFT                        5
#define PMIC_RG_LBAT_INT_VTH_ADDR                        MT6355_PCHR_VREF_ANA_CON2
#define PMIC_RG_LBAT_INT_VTH_MASK                        0x1F
#define PMIC_RG_LBAT_INT_VTH_SHIFT                       6
#define PMIC_RG_PCHR_RV_ADDR                             MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RG_PCHR_RV_MASK                             0xF
#define PMIC_RG_PCHR_RV_SHIFT                            0
#define PMIC_RGS_BATON_UNDET_ADDR                        MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RGS_BATON_UNDET_MASK                        0x1
#define PMIC_RGS_BATON_UNDET_SHIFT                       4
#define PMIC_RGS_OTG_BVALID_DET_ADDR                     MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RGS_OTG_BVALID_DET_MASK                     0x1
#define PMIC_RGS_OTG_BVALID_DET_SHIFT                    5
#define PMIC_RGS_CHR_LDO_DET_ADDR                        MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RGS_CHR_LDO_DET_MASK                        0x1
#define PMIC_RGS_CHR_LDO_DET_SHIFT                       6
#define PMIC_RGS_BATON_HV_ADDR                           MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RGS_BATON_HV_MASK                           0x1
#define PMIC_RGS_BATON_HV_SHIFT                          7
#define PMIC_RG_PCHR_ANA3_RSV_ADDR                       MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RG_PCHR_ANA3_RSV_MASK                       0x1
#define PMIC_RG_PCHR_ANA3_RSV_SHIFT                      8
#define PMIC_RG_VCDT_UVLO_VTH_ADDR                       MT6355_PCHR_VREF_ANA_CON3
#define PMIC_RG_VCDT_UVLO_VTH_MASK                       0xF
#define PMIC_RG_VCDT_UVLO_VTH_SHIFT                      9
#define PMIC_GPIO_DIR0_ADDR                              MT6355_GPIO_DIR0
#define PMIC_GPIO_DIR0_MASK                              0x3FFF
#define PMIC_GPIO_DIR0_SHIFT                             0
#define PMIC_GPIO_DIR0_SET_ADDR                          MT6355_GPIO_DIR0_SET
#define PMIC_GPIO_DIR0_SET_MASK                          0xFFFF
#define PMIC_GPIO_DIR0_SET_SHIFT                         0
#define PMIC_GPIO_DIR0_CLR_ADDR                          MT6355_GPIO_DIR0_CLR
#define PMIC_GPIO_DIR0_CLR_MASK                          0xFFFF
#define PMIC_GPIO_DIR0_CLR_SHIFT                         0
#define PMIC_GPIO_PULLEN0_ADDR                           MT6355_GPIO_PULLEN0
#define PMIC_GPIO_PULLEN0_MASK                           0x3FFF
#define PMIC_GPIO_PULLEN0_SHIFT                          0
#define PMIC_GPIO_PULLEN0_SET_ADDR                       MT6355_GPIO_PULLEN0_SET
#define PMIC_GPIO_PULLEN0_SET_MASK                       0xFFFF
#define PMIC_GPIO_PULLEN0_SET_SHIFT                      0
#define PMIC_GPIO_PULLEN0_CLR_ADDR                       MT6355_GPIO_PULLEN0_CLR
#define PMIC_GPIO_PULLEN0_CLR_MASK                       0xFFFF
#define PMIC_GPIO_PULLEN0_CLR_SHIFT                      0
#define PMIC_GPIO_PULLSEL0_ADDR                          MT6355_GPIO_PULLSEL0
#define PMIC_GPIO_PULLSEL0_MASK                          0x3FFF
#define PMIC_GPIO_PULLSEL0_SHIFT                         0
#define PMIC_GPIO_PULLSEL0_SET_ADDR                      MT6355_GPIO_PULLSEL0_SET
#define PMIC_GPIO_PULLSEL0_SET_MASK                      0xFFFF
#define PMIC_GPIO_PULLSEL0_SET_SHIFT                     0
#define PMIC_GPIO_PULLSEL0_CLR_ADDR                      MT6355_GPIO_PULLSEL0_CLR
#define PMIC_GPIO_PULLSEL0_CLR_MASK                      0xFFFF
#define PMIC_GPIO_PULLSEL0_CLR_SHIFT                     0
#define PMIC_GPIO_DINV0_ADDR                             MT6355_GPIO_DINV0
#define PMIC_GPIO_DINV0_MASK                             0x3FFF
#define PMIC_GPIO_DINV0_SHIFT                            0
#define PMIC_GPIO_DINV0_SET_ADDR                         MT6355_GPIO_DINV0_SET
#define PMIC_GPIO_DINV0_SET_MASK                         0xFFFF
#define PMIC_GPIO_DINV0_SET_SHIFT                        0
#define PMIC_GPIO_DINV0_CLR_ADDR                         MT6355_GPIO_DINV0_CLR
#define PMIC_GPIO_DINV0_CLR_MASK                         0xFFFF
#define PMIC_GPIO_DINV0_CLR_SHIFT                        0
#define PMIC_GPIO_DOUT0_ADDR                             MT6355_GPIO_DOUT0
#define PMIC_GPIO_DOUT0_MASK                             0x3FFF
#define PMIC_GPIO_DOUT0_SHIFT                            0
#define PMIC_GPIO_DOUT0_SET_ADDR                         MT6355_GPIO_DOUT0_SET
#define PMIC_GPIO_DOUT0_SET_MASK                         0xFFFF
#define PMIC_GPIO_DOUT0_SET_SHIFT                        0
#define PMIC_GPIO_DOUT0_CLR_ADDR                         MT6355_GPIO_DOUT0_CLR
#define PMIC_GPIO_DOUT0_CLR_MASK                         0xFFFF
#define PMIC_GPIO_DOUT0_CLR_SHIFT                        0
#define PMIC_GPIO_PI0_ADDR                               MT6355_GPIO_PI0
#define PMIC_GPIO_PI0_MASK                               0x3FFF
#define PMIC_GPIO_PI0_SHIFT                              0
#define PMIC_GPIO_POE0_ADDR                              MT6355_GPIO_POE0
#define PMIC_GPIO_POE0_MASK                              0x3FFF
#define PMIC_GPIO_POE0_SHIFT                             0
#define PMIC_GPIO0_MODE_ADDR                             MT6355_GPIO_MODE0
#define PMIC_GPIO0_MODE_MASK                             0x7
#define PMIC_GPIO0_MODE_SHIFT                            0
#define PMIC_GPIO1_MODE_ADDR                             MT6355_GPIO_MODE0
#define PMIC_GPIO1_MODE_MASK                             0x7
#define PMIC_GPIO1_MODE_SHIFT                            3
#define PMIC_GPIO2_MODE_ADDR                             MT6355_GPIO_MODE0
#define PMIC_GPIO2_MODE_MASK                             0x7
#define PMIC_GPIO2_MODE_SHIFT                            6
#define PMIC_GPIO3_MODE_ADDR                             MT6355_GPIO_MODE0
#define PMIC_GPIO3_MODE_MASK                             0x7
#define PMIC_GPIO3_MODE_SHIFT                            9
#define PMIC_GPIO4_MODE_ADDR                             MT6355_GPIO_MODE0
#define PMIC_GPIO4_MODE_MASK                             0x7
#define PMIC_GPIO4_MODE_SHIFT                            12
#define PMIC_GPIO_MODE0_SET_ADDR                         MT6355_GPIO_MODE0_SET
#define PMIC_GPIO_MODE0_SET_MASK                         0xFFFF
#define PMIC_GPIO_MODE0_SET_SHIFT                        0
#define PMIC_GPIO_MODE0_CLR_ADDR                         MT6355_GPIO_MODE0_CLR
#define PMIC_GPIO_MODE0_CLR_MASK                         0xFFFF
#define PMIC_GPIO_MODE0_CLR_SHIFT                        0
#define PMIC_GPIO5_MODE_ADDR                             MT6355_GPIO_MODE1
#define PMIC_GPIO5_MODE_MASK                             0x7
#define PMIC_GPIO5_MODE_SHIFT                            0
#define PMIC_GPIO6_MODE_ADDR                             MT6355_GPIO_MODE1
#define PMIC_GPIO6_MODE_MASK                             0x7
#define PMIC_GPIO6_MODE_SHIFT                            3
#define PMIC_GPIO7_MODE_ADDR                             MT6355_GPIO_MODE1
#define PMIC_GPIO7_MODE_MASK                             0x7
#define PMIC_GPIO7_MODE_SHIFT                            6
#define PMIC_GPIO8_MODE_ADDR                             MT6355_GPIO_MODE1
#define PMIC_GPIO8_MODE_MASK                             0x7
#define PMIC_GPIO8_MODE_SHIFT                            9
#define PMIC_GPIO9_MODE_ADDR                             MT6355_GPIO_MODE1
#define PMIC_GPIO9_MODE_MASK                             0x7
#define PMIC_GPIO9_MODE_SHIFT                            12
#define PMIC_GPIO_MODE1_SET_ADDR                         MT6355_GPIO_MODE1_SET
#define PMIC_GPIO_MODE1_SET_MASK                         0xFFFF
#define PMIC_GPIO_MODE1_SET_SHIFT                        0
#define PMIC_GPIO_MODE1_CLR_ADDR                         MT6355_GPIO_MODE1_CLR
#define PMIC_GPIO_MODE1_CLR_MASK                         0xFFFF
#define PMIC_GPIO_MODE1_CLR_SHIFT                        0
#define PMIC_GPIO10_MODE_ADDR                            MT6355_GPIO_MODE2
#define PMIC_GPIO10_MODE_MASK                            0x7
#define PMIC_GPIO10_MODE_SHIFT                           0
#define PMIC_GPIO11_MODE_ADDR                            MT6355_GPIO_MODE2
#define PMIC_GPIO11_MODE_MASK                            0x7
#define PMIC_GPIO11_MODE_SHIFT                           3
#define PMIC_GPIO12_MODE_ADDR                            MT6355_GPIO_MODE2
#define PMIC_GPIO12_MODE_MASK                            0x7
#define PMIC_GPIO12_MODE_SHIFT                           6
#define PMIC_GPIO13_MODE_ADDR                            MT6355_GPIO_MODE2
#define PMIC_GPIO13_MODE_MASK                            0x7
#define PMIC_GPIO13_MODE_SHIFT                           9
#define PMIC_GPIO_MODE2_SET_ADDR                         MT6355_GPIO_MODE2_SET
#define PMIC_GPIO_MODE2_SET_MASK                         0xFFFF
#define PMIC_GPIO_MODE2_SET_SHIFT                        0
#define PMIC_GPIO_MODE2_CLR_ADDR                         MT6355_GPIO_MODE2_CLR
#define PMIC_GPIO_MODE2_CLR_MASK                         0xFFFF
#define PMIC_GPIO_MODE2_CLR_SHIFT                        0
#define PMIC_GPIO_RSV_ADDR                               MT6355_GPIO_RSV
#define PMIC_GPIO_RSV_MASK                               0xFFFF
#define PMIC_GPIO_RSV_SHIFT                              0
#define PMIC_RTC_SEC_DUMMY_ADDR                          MT6355_RTC_SEC_DUMMY_CON0
#define PMIC_RTC_SEC_DUMMY_MASK                          0xFFFF
#define PMIC_RTC_SEC_DUMMY_SHIFT                         0
#define PMIC_RTC_DUMMY_ADDR                              MT6355_RTC_DUMMY_CON0
#define PMIC_RTC_DUMMY_MASK                              0xFFFF
#define PMIC_RTC_DUMMY_SHIFT                             0
#define PMIC_EOSC_CALI_START_ADDR                        MT6355_EOSC_CALI_CON0
#define PMIC_EOSC_CALI_START_MASK                        0x1
#define PMIC_EOSC_CALI_START_SHIFT                       0
#define PMIC_EOSC_CALI_TD_ADDR                           MT6355_EOSC_CALI_CON0
#define PMIC_EOSC_CALI_TD_MASK                           0x7
#define PMIC_EOSC_CALI_TD_SHIFT                          5
#define PMIC_EOSC_CALI_TEST_ADDR                         MT6355_EOSC_CALI_CON0
#define PMIC_EOSC_CALI_TEST_MASK                         0xF
#define PMIC_EOSC_CALI_TEST_SHIFT                        9
#define PMIC_EOSC_CALI_DCXO_RDY_TD_ADDR                  MT6355_EOSC_CALI_CON1
#define PMIC_EOSC_CALI_DCXO_RDY_TD_MASK                  0x7
#define PMIC_EOSC_CALI_DCXO_RDY_TD_SHIFT                 0
#define PMIC_FRC_VTCXO0_ON_ADDR                          MT6355_EOSC_CALI_CON1
#define PMIC_FRC_VTCXO0_ON_MASK                          0x1
#define PMIC_FRC_VTCXO0_ON_SHIFT                         8
#define PMIC_EOSC_CALI_RSV_ADDR                          MT6355_EOSC_CALI_CON1
#define PMIC_EOSC_CALI_RSV_MASK                          0xF
#define PMIC_EOSC_CALI_RSV_SHIFT                         11
#define PMIC_MIX_EOSC32_STP_LPDTB_ADDR                   MT6355_RTC_MIX_CON0
#define PMIC_MIX_EOSC32_STP_LPDTB_MASK                   0x1
#define PMIC_MIX_EOSC32_STP_LPDTB_SHIFT                  1
#define PMIC_MIX_EOSC32_STP_LPDEN_ADDR                   MT6355_RTC_MIX_CON0
#define PMIC_MIX_EOSC32_STP_LPDEN_MASK                   0x1
#define PMIC_MIX_EOSC32_STP_LPDEN_SHIFT                  2
#define PMIC_MIX_XOSC32_STP_PWDB_ADDR                    MT6355_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_PWDB_MASK                    0x1
#define PMIC_MIX_XOSC32_STP_PWDB_SHIFT                   3
#define PMIC_MIX_XOSC32_STP_LPDTB_ADDR                   MT6355_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_LPDTB_MASK                   0x1
#define PMIC_MIX_XOSC32_STP_LPDTB_SHIFT                  4
#define PMIC_MIX_XOSC32_STP_LPDEN_ADDR                   MT6355_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_LPDEN_MASK                   0x1
#define PMIC_MIX_XOSC32_STP_LPDEN_SHIFT                  5
#define PMIC_MIX_XOSC32_STP_LPDRST_ADDR                  MT6355_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_LPDRST_MASK                  0x1
#define PMIC_MIX_XOSC32_STP_LPDRST_SHIFT                 6
#define PMIC_MIX_XOSC32_STP_CALI_ADDR                    MT6355_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_CALI_MASK                    0x1F
#define PMIC_MIX_XOSC32_STP_CALI_SHIFT                   7
#define PMIC_STMP_MODE_ADDR                              MT6355_RTC_MIX_CON0
#define PMIC_STMP_MODE_MASK                              0x1
#define PMIC_STMP_MODE_SHIFT                             12
#define PMIC_MIX_EOSC32_STP_CHOP_EN_ADDR                 MT6355_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_STP_CHOP_EN_MASK                 0x1
#define PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT                0
#define PMIC_MIX_DCXO_STP_LVSH_EN_ADDR                   MT6355_RTC_MIX_CON1
#define PMIC_MIX_DCXO_STP_LVSH_EN_MASK                   0x1
#define PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT                  1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_ADDR                  MT6355_RTC_MIX_CON1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_MASK                  0x1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT                 2
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_ADDR               MT6355_RTC_MIX_CON1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK               0x1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT              3
#define PMIC_MIX_RTC_STP_XOSC32_ENB_ADDR                 MT6355_RTC_MIX_CON1
#define PMIC_MIX_RTC_STP_XOSC32_ENB_MASK                 0x1
#define PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT                4
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_ADDR        MT6355_RTC_MIX_CON1
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK        0x1
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT       5
#define PMIC_MIX_EOSC32_STP_RSV_ADDR                     MT6355_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_STP_RSV_MASK                     0x3
#define PMIC_MIX_EOSC32_STP_RSV_SHIFT                    6
#define PMIC_MIX_EOSC32_VCT_EN_ADDR                      MT6355_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_VCT_EN_MASK                      0x1
#define PMIC_MIX_EOSC32_VCT_EN_SHIFT                     8
#define PMIC_MIX_EOSC32_OPT_ADDR                         MT6355_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_OPT_MASK                         0x3
#define PMIC_MIX_EOSC32_OPT_SHIFT                        9
#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_ADDR               MT6355_RTC_MIX_CON1
#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_MASK               0x1
#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_SHIFT              11
#define PMIC_MIX_RTC_GPIO_COREDETB_ADDR                  MT6355_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_COREDETB_MASK                  0x1
#define PMIC_MIX_RTC_GPIO_COREDETB_SHIFT                 12
#define PMIC_MIX_RTC_GPIO_F32KOB_ADDR                    MT6355_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_F32KOB_MASK                    0x1
#define PMIC_MIX_RTC_GPIO_F32KOB_SHIFT                   13
#define PMIC_MIX_RTC_GPIO_GPO_ADDR                       MT6355_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_GPO_MASK                       0x1
#define PMIC_MIX_RTC_GPIO_GPO_SHIFT                      14
#define PMIC_MIX_RTC_GPIO_OE_ADDR                        MT6355_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_OE_MASK                        0x1
#define PMIC_MIX_RTC_GPIO_OE_SHIFT                       15
#define PMIC_MIX_RTC_STP_DEBUG_OUT_ADDR                  MT6355_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_DEBUG_OUT_MASK                  0x3
#define PMIC_MIX_RTC_STP_DEBUG_OUT_SHIFT                 0
#define PMIC_MIX_RTC_STP_DEBUG_SEL_ADDR                  MT6355_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_DEBUG_SEL_MASK                  0x3
#define PMIC_MIX_RTC_STP_DEBUG_SEL_SHIFT                 4
#define PMIC_MIX_RTC_STP_K_EOSC32_EN_ADDR                MT6355_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_K_EOSC32_EN_MASK                0x1
#define PMIC_MIX_RTC_STP_K_EOSC32_EN_SHIFT               7
#define PMIC_MIX_RTC_STP_EMBCK_SEL_ADDR                  MT6355_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_EMBCK_SEL_MASK                  0x1
#define PMIC_MIX_RTC_STP_EMBCK_SEL_SHIFT                 8
#define PMIC_MIX_STP_BBWAKEUP_ADDR                       MT6355_RTC_MIX_CON2
#define PMIC_MIX_STP_BBWAKEUP_MASK                       0x1
#define PMIC_MIX_STP_BBWAKEUP_SHIFT                      9
#define PMIC_MIX_STP_RTC_DDLO_ADDR                       MT6355_RTC_MIX_CON2
#define PMIC_MIX_STP_RTC_DDLO_MASK                       0x1
#define PMIC_MIX_STP_RTC_DDLO_SHIFT                      10
#define PMIC_MIX_RTC_XOSC32_ENB_ADDR                     MT6355_RTC_MIX_CON2
#define PMIC_MIX_RTC_XOSC32_ENB_MASK                     0x1
#define PMIC_MIX_RTC_XOSC32_ENB_SHIFT                    11
#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_ADDR               MT6355_RTC_MIX_CON2
#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_MASK               0x1
#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT              12
#define PMIC_VRTC_PWM_MODE_ADDR                          MT6355_VRTC_PWM_CON0
#define PMIC_VRTC_PWM_MODE_MASK                          0x1
#define PMIC_VRTC_PWM_MODE_SHIFT                         0
#define PMIC_VRTC_PWM_RSV_ADDR                           MT6355_VRTC_PWM_CON0
#define PMIC_VRTC_PWM_RSV_MASK                           0x7
#define PMIC_VRTC_PWM_RSV_SHIFT                          1
#define PMIC_VRTC_PWM_L_DUTY_ADDR                        MT6355_VRTC_PWM_CON0
#define PMIC_VRTC_PWM_L_DUTY_MASK                        0xF
#define PMIC_VRTC_PWM_L_DUTY_SHIFT                       4
#define PMIC_VRTC_PWM_H_DUTY_ADDR                        MT6355_VRTC_PWM_CON0
#define PMIC_VRTC_PWM_H_DUTY_MASK                        0xF
#define PMIC_VRTC_PWM_H_DUTY_SHIFT                       8
#define PMIC_VRTC_CAP_SEL_ADDR                           MT6355_VRTC_PWM_CON0
#define PMIC_VRTC_CAP_SEL_MASK                           0x1
#define PMIC_VRTC_CAP_SEL_SHIFT                          12
#define PMIC_BIF_COMMAND_0_ADDR                          MT6355_BIF_CON0
#define PMIC_BIF_COMMAND_0_MASK                          0x7FF
#define PMIC_BIF_COMMAND_0_SHIFT                         0
#define PMIC_BIF_COMMAND_1_ADDR                          MT6355_BIF_CON1
#define PMIC_BIF_COMMAND_1_MASK                          0x7FF
#define PMIC_BIF_COMMAND_1_SHIFT                         0
#define PMIC_BIF_COMMAND_2_ADDR                          MT6355_BIF_CON2
#define PMIC_BIF_COMMAND_2_MASK                          0x7FF
#define PMIC_BIF_COMMAND_2_SHIFT                         0
#define PMIC_BIF_COMMAND_3_ADDR                          MT6355_BIF_CON3
#define PMIC_BIF_COMMAND_3_MASK                          0x7FF
#define PMIC_BIF_COMMAND_3_SHIFT                         0
#define PMIC_BIF_COMMAND_4_ADDR                          MT6355_BIF_CON4
#define PMIC_BIF_COMMAND_4_MASK                          0x7FF
#define PMIC_BIF_COMMAND_4_SHIFT                         0
#define PMIC_BIF_COMMAND_5_ADDR                          MT6355_BIF_CON5
#define PMIC_BIF_COMMAND_5_MASK                          0x7FF
#define PMIC_BIF_COMMAND_5_SHIFT                         0
#define PMIC_BIF_COMMAND_6_ADDR                          MT6355_BIF_CON6
#define PMIC_BIF_COMMAND_6_MASK                          0x7FF
#define PMIC_BIF_COMMAND_6_SHIFT                         0
#define PMIC_BIF_COMMAND_7_ADDR                          MT6355_BIF_CON7
#define PMIC_BIF_COMMAND_7_MASK                          0x7FF
#define PMIC_BIF_COMMAND_7_SHIFT                         0
#define PMIC_BIF_COMMAND_8_ADDR                          MT6355_BIF_CON8
#define PMIC_BIF_COMMAND_8_MASK                          0x7FF
#define PMIC_BIF_COMMAND_8_SHIFT                         0
#define PMIC_BIF_COMMAND_9_ADDR                          MT6355_BIF_CON9
#define PMIC_BIF_COMMAND_9_MASK                          0x7FF
#define PMIC_BIF_COMMAND_9_SHIFT                         0
#define PMIC_BIF_COMMAND_10_ADDR                         MT6355_BIF_CON10
#define PMIC_BIF_COMMAND_10_MASK                         0x7FF
#define PMIC_BIF_COMMAND_10_SHIFT                        0
#define PMIC_BIF_COMMAND_11_ADDR                         MT6355_BIF_CON11
#define PMIC_BIF_COMMAND_11_MASK                         0x7FF
#define PMIC_BIF_COMMAND_11_SHIFT                        0
#define PMIC_BIF_COMMAND_12_ADDR                         MT6355_BIF_CON12
#define PMIC_BIF_COMMAND_12_MASK                         0x7FF
#define PMIC_BIF_COMMAND_12_SHIFT                        0
#define PMIC_BIF_COMMAND_13_ADDR                         MT6355_BIF_CON13
#define PMIC_BIF_COMMAND_13_MASK                         0x7FF
#define PMIC_BIF_COMMAND_13_SHIFT                        0
#define PMIC_BIF_COMMAND_14_ADDR                         MT6355_BIF_CON14
#define PMIC_BIF_COMMAND_14_MASK                         0x7FF
#define PMIC_BIF_COMMAND_14_SHIFT                        0
#define PMIC_BIF_RSV_ADDR                                MT6355_BIF_CON15
#define PMIC_BIF_RSV_MASK                                0x7F
#define PMIC_BIF_RSV_SHIFT                               0
#define PMIC_BIF_COMMAND_TYPE_ADDR                       MT6355_BIF_CON15
#define PMIC_BIF_COMMAND_TYPE_MASK                       0x3
#define PMIC_BIF_COMMAND_TYPE_SHIFT                      8
#define PMIC_BIF_TRASFER_NUM_ADDR                        MT6355_BIF_CON15
#define PMIC_BIF_TRASFER_NUM_MASK                        0xF
#define PMIC_BIF_TRASFER_NUM_SHIFT                       12
#define PMIC_BIF_LOGIC_0_SET_ADDR                        MT6355_BIF_CON16
#define PMIC_BIF_LOGIC_0_SET_MASK                        0xF
#define PMIC_BIF_LOGIC_0_SET_SHIFT                       0
#define PMIC_BIF_LOGIC_1_SET_ADDR                        MT6355_BIF_CON16
#define PMIC_BIF_LOGIC_1_SET_MASK                        0x1F
#define PMIC_BIF_LOGIC_1_SET_SHIFT                       4
#define PMIC_BIF_STOP_SET_ADDR                           MT6355_BIF_CON16
#define PMIC_BIF_STOP_SET_MASK                           0x3F
#define PMIC_BIF_STOP_SET_SHIFT                          10
#define PMIC_BIF_DEBOUNCE_EN_ADDR                        MT6355_BIF_CON17
#define PMIC_BIF_DEBOUNCE_EN_MASK                        0x1
#define PMIC_BIF_DEBOUNCE_EN_SHIFT                       4
#define PMIC_BIF_READ_EXPECT_NUM_ADDR                    MT6355_BIF_CON17
#define PMIC_BIF_READ_EXPECT_NUM_MASK                    0xF
#define PMIC_BIF_READ_EXPECT_NUM_SHIFT                   12
#define PMIC_BIF_TRASACT_TRIGGER_ADDR                    MT6355_BIF_CON18
#define PMIC_BIF_TRASACT_TRIGGER_MASK                    0x1
#define PMIC_BIF_TRASACT_TRIGGER_SHIFT                   0
#define PMIC_BIF_DATA_NUM_ADDR                           MT6355_BIF_CON19
#define PMIC_BIF_DATA_NUM_MASK                           0xF
#define PMIC_BIF_DATA_NUM_SHIFT                          0
#define PMIC_BIF_RESPONSE_ADDR                           MT6355_BIF_CON19
#define PMIC_BIF_RESPONSE_MASK                           0x1
#define PMIC_BIF_RESPONSE_SHIFT                          12
#define PMIC_BIF_DATA_0_ADDR                             MT6355_BIF_CON20
#define PMIC_BIF_DATA_0_MASK                             0xFF
#define PMIC_BIF_DATA_0_SHIFT                            0
#define PMIC_BIF_ACK_0_ADDR                              MT6355_BIF_CON20
#define PMIC_BIF_ACK_0_MASK                              0x1
#define PMIC_BIF_ACK_0_SHIFT                             8
#define PMIC_BIF_ERROR_0_ADDR                            MT6355_BIF_CON20
#define PMIC_BIF_ERROR_0_MASK                            0x1
#define PMIC_BIF_ERROR_0_SHIFT                           15
#define PMIC_BIF_DATA_1_ADDR                             MT6355_BIF_CON21
#define PMIC_BIF_DATA_1_MASK                             0xFF
#define PMIC_BIF_DATA_1_SHIFT                            0
#define PMIC_BIF_ACK_1_ADDR                              MT6355_BIF_CON21
#define PMIC_BIF_ACK_1_MASK                              0x1
#define PMIC_BIF_ACK_1_SHIFT                             8
#define PMIC_BIF_ERROR_1_ADDR                            MT6355_BIF_CON21
#define PMIC_BIF_ERROR_1_MASK                            0x1
#define PMIC_BIF_ERROR_1_SHIFT                           15
#define PMIC_BIF_DATA_2_ADDR                             MT6355_BIF_CON22
#define PMIC_BIF_DATA_2_MASK                             0xFF
#define PMIC_BIF_DATA_2_SHIFT                            0
#define PMIC_BIF_ACK_2_ADDR                              MT6355_BIF_CON22
#define PMIC_BIF_ACK_2_MASK                              0x1
#define PMIC_BIF_ACK_2_SHIFT                             8
#define PMIC_BIF_ERROR_2_ADDR                            MT6355_BIF_CON22
#define PMIC_BIF_ERROR_2_MASK                            0x1
#define PMIC_BIF_ERROR_2_SHIFT                           15
#define PMIC_BIF_DATA_3_ADDR                             MT6355_BIF_CON23
#define PMIC_BIF_DATA_3_MASK                             0xFF
#define PMIC_BIF_DATA_3_SHIFT                            0
#define PMIC_BIF_ACK_3_ADDR                              MT6355_BIF_CON23
#define PMIC_BIF_ACK_3_MASK                              0x1
#define PMIC_BIF_ACK_3_SHIFT                             8
#define PMIC_BIF_ERROR_3_ADDR                            MT6355_BIF_CON23
#define PMIC_BIF_ERROR_3_MASK                            0x1
#define PMIC_BIF_ERROR_3_SHIFT                           15
#define PMIC_BIF_DATA_4_ADDR                             MT6355_BIF_CON24
#define PMIC_BIF_DATA_4_MASK                             0xFF
#define PMIC_BIF_DATA_4_SHIFT                            0
#define PMIC_BIF_ACK_4_ADDR                              MT6355_BIF_CON24
#define PMIC_BIF_ACK_4_MASK                              0x1
#define PMIC_BIF_ACK_4_SHIFT                             8
#define PMIC_BIF_ERROR_4_ADDR                            MT6355_BIF_CON24
#define PMIC_BIF_ERROR_4_MASK                            0x1
#define PMIC_BIF_ERROR_4_SHIFT                           15
#define PMIC_BIF_DATA_5_ADDR                             MT6355_BIF_CON25
#define PMIC_BIF_DATA_5_MASK                             0xFF
#define PMIC_BIF_DATA_5_SHIFT                            0
#define PMIC_BIF_ACK_5_ADDR                              MT6355_BIF_CON25
#define PMIC_BIF_ACK_5_MASK                              0x1
#define PMIC_BIF_ACK_5_SHIFT                             8
#define PMIC_BIF_ERROR_5_ADDR                            MT6355_BIF_CON25
#define PMIC_BIF_ERROR_5_MASK                            0x1
#define PMIC_BIF_ERROR_5_SHIFT                           15
#define PMIC_BIF_DATA_6_ADDR                             MT6355_BIF_CON26
#define PMIC_BIF_DATA_6_MASK                             0xFF
#define PMIC_BIF_DATA_6_SHIFT                            0
#define PMIC_BIF_ACK_6_ADDR                              MT6355_BIF_CON26
#define PMIC_BIF_ACK_6_MASK                              0x1
#define PMIC_BIF_ACK_6_SHIFT                             8
#define PMIC_BIF_ERROR_6_ADDR                            MT6355_BIF_CON26
#define PMIC_BIF_ERROR_6_MASK                            0x1
#define PMIC_BIF_ERROR_6_SHIFT                           15
#define PMIC_BIF_DATA_7_ADDR                             MT6355_BIF_CON27
#define PMIC_BIF_DATA_7_MASK                             0xFF
#define PMIC_BIF_DATA_7_SHIFT                            0
#define PMIC_BIF_ACK_7_ADDR                              MT6355_BIF_CON27
#define PMIC_BIF_ACK_7_MASK                              0x1
#define PMIC_BIF_ACK_7_SHIFT                             8
#define PMIC_BIF_ERROR_7_ADDR                            MT6355_BIF_CON27
#define PMIC_BIF_ERROR_7_MASK                            0x1
#define PMIC_BIF_ERROR_7_SHIFT                           15
#define PMIC_BIF_DATA_8_ADDR                             MT6355_BIF_CON28
#define PMIC_BIF_DATA_8_MASK                             0xFF
#define PMIC_BIF_DATA_8_SHIFT                            0
#define PMIC_BIF_ACK_8_ADDR                              MT6355_BIF_CON28
#define PMIC_BIF_ACK_8_MASK                              0x1
#define PMIC_BIF_ACK_8_SHIFT                             8
#define PMIC_BIF_ERROR_8_ADDR                            MT6355_BIF_CON28
#define PMIC_BIF_ERROR_8_MASK                            0x1
#define PMIC_BIF_ERROR_8_SHIFT                           15
#define PMIC_BIF_DATA_9_ADDR                             MT6355_BIF_CON29
#define PMIC_BIF_DATA_9_MASK                             0xFF
#define PMIC_BIF_DATA_9_SHIFT                            0
#define PMIC_BIF_ACK_9_ADDR                              MT6355_BIF_CON29
#define PMIC_BIF_ACK_9_MASK                              0x1
#define PMIC_BIF_ACK_9_SHIFT                             8
#define PMIC_BIF_ERROR_9_ADDR                            MT6355_BIF_CON29
#define PMIC_BIF_ERROR_9_MASK                            0x1
#define PMIC_BIF_ERROR_9_SHIFT                           15
#define PMIC_BIF_TEST_MODE0_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE0_MASK                         0x1
#define PMIC_BIF_TEST_MODE0_SHIFT                        0
#define PMIC_BIF_TEST_MODE1_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE1_MASK                         0x1
#define PMIC_BIF_TEST_MODE1_SHIFT                        1
#define PMIC_BIF_TEST_MODE2_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE2_MASK                         0x1
#define PMIC_BIF_TEST_MODE2_SHIFT                        2
#define PMIC_BIF_TEST_MODE3_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE3_MASK                         0x1
#define PMIC_BIF_TEST_MODE3_SHIFT                        3
#define PMIC_BIF_TEST_MODE4_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE4_MASK                         0x1
#define PMIC_BIF_TEST_MODE4_SHIFT                        4
#define PMIC_BIF_TEST_MODE5_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE5_MASK                         0x1
#define PMIC_BIF_TEST_MODE5_SHIFT                        5
#define PMIC_BIF_TEST_MODE6_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE6_MASK                         0x1
#define PMIC_BIF_TEST_MODE6_SHIFT                        6
#define PMIC_BIF_TEST_MODE7_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE7_MASK                         0x1
#define PMIC_BIF_TEST_MODE7_SHIFT                        7
#define PMIC_BIF_TEST_MODE8_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TEST_MODE8_MASK                         0x1
#define PMIC_BIF_TEST_MODE8_SHIFT                        8
#define PMIC_BIF_BAT_LOST_SW_ADDR                        MT6355_BIF_CON30
#define PMIC_BIF_BAT_LOST_SW_MASK                        0x1
#define PMIC_BIF_BAT_LOST_SW_SHIFT                       11
#define PMIC_BIF_RX_DATA_SW_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_RX_DATA_SW_MASK                         0x1
#define PMIC_BIF_RX_DATA_SW_SHIFT                        12
#define PMIC_BIF_TX_DATA_SW_ADDR                         MT6355_BIF_CON30
#define PMIC_BIF_TX_DATA_SW_MASK                         0x1
#define PMIC_BIF_TX_DATA_SW_SHIFT                        13
#define PMIC_BIF_RX_EN_SW_ADDR                           MT6355_BIF_CON30
#define PMIC_BIF_RX_EN_SW_MASK                           0x1
#define PMIC_BIF_RX_EN_SW_SHIFT                          14
#define PMIC_BIF_TX_EN_SW_ADDR                           MT6355_BIF_CON30
#define PMIC_BIF_TX_EN_SW_MASK                           0x1
#define PMIC_BIF_TX_EN_SW_SHIFT                          15
#define PMIC_BIF_BACK_NORMAL_ADDR                        MT6355_BIF_CON31
#define PMIC_BIF_BACK_NORMAL_MASK                        0x1
#define PMIC_BIF_BACK_NORMAL_SHIFT                       0
#define PMIC_BIF_IRQ_CLR_ADDR                            MT6355_BIF_CON31
#define PMIC_BIF_IRQ_CLR_MASK                            0x1
#define PMIC_BIF_IRQ_CLR_SHIFT                           1
#define PMIC_BIF_IRQ_ADDR                                MT6355_BIF_CON31
#define PMIC_BIF_IRQ_MASK                                0x1
#define PMIC_BIF_IRQ_SHIFT                               11
#define PMIC_BIF_TIMEOUT_ADDR                            MT6355_BIF_CON31
#define PMIC_BIF_TIMEOUT_MASK                            0x1
#define PMIC_BIF_TIMEOUT_SHIFT                           12
#define PMIC_BIF_BAT_UNDET_ADDR                          MT6355_BIF_CON31
#define PMIC_BIF_BAT_UNDET_MASK                          0x1
#define PMIC_BIF_BAT_UNDET_SHIFT                         13
#define PMIC_BIF_TOTAL_VALID_ADDR                        MT6355_BIF_CON31
#define PMIC_BIF_TOTAL_VALID_MASK                        0x1
#define PMIC_BIF_TOTAL_VALID_SHIFT                       14
#define PMIC_BIF_BUS_STATUS_ADDR                         MT6355_BIF_CON31
#define PMIC_BIF_BUS_STATUS_MASK                         0x1
#define PMIC_BIF_BUS_STATUS_SHIFT                        15
#define PMIC_BIF_POWER_UP_COUNT_ADDR                     MT6355_BIF_CON32
#define PMIC_BIF_POWER_UP_COUNT_MASK                     0x1F
#define PMIC_BIF_POWER_UP_COUNT_SHIFT                    0
#define PMIC_BIF_POWER_UP_ADDR                           MT6355_BIF_CON32
#define PMIC_BIF_POWER_UP_MASK                           0x1
#define PMIC_BIF_POWER_UP_SHIFT                          15
#define PMIC_BIF_RX_ERROR_UNKNOW_ADDR                    MT6355_BIF_CON33
#define PMIC_BIF_RX_ERROR_UNKNOW_MASK                    0x1
#define PMIC_BIF_RX_ERROR_UNKNOW_SHIFT                   2
#define PMIC_BIF_RX_ERROR_INSUFF_ADDR                    MT6355_BIF_CON33
#define PMIC_BIF_RX_ERROR_INSUFF_MASK                    0x1
#define PMIC_BIF_RX_ERROR_INSUFF_SHIFT                   3
#define PMIC_BIF_RX_ERROR_LOWPHASE_ADDR                  MT6355_BIF_CON33
#define PMIC_BIF_RX_ERROR_LOWPHASE_MASK                  0x1
#define PMIC_BIF_RX_ERROR_LOWPHASE_SHIFT                 4
#define PMIC_BIF_RX_STATE_ADDR                           MT6355_BIF_CON33
#define PMIC_BIF_RX_STATE_MASK                           0x7
#define PMIC_BIF_RX_STATE_SHIFT                          5
#define PMIC_BIF_FLOW_CTL_STATE_ADDR                     MT6355_BIF_CON33
#define PMIC_BIF_FLOW_CTL_STATE_MASK                     0x3
#define PMIC_BIF_FLOW_CTL_STATE_SHIFT                    8
#define PMIC_BIF_TX_STATE_ADDR                           MT6355_BIF_CON33
#define PMIC_BIF_TX_STATE_MASK                           0x3
#define PMIC_BIF_TX_STATE_SHIFT                          10
#define PMIC_AD_QI_BIF_RX_DATA_ADDR                      MT6355_BIF_CON33
#define PMIC_AD_QI_BIF_RX_DATA_MASK                      0x1
#define PMIC_AD_QI_BIF_RX_DATA_SHIFT                     12
#define PMIC_DA_QI_BIF_RX_EN_ADDR                        MT6355_BIF_CON33
#define PMIC_DA_QI_BIF_RX_EN_MASK                        0x1
#define PMIC_DA_QI_BIF_RX_EN_SHIFT                       13
#define PMIC_DA_QI_BIF_TX_DATA_ADDR                      MT6355_BIF_CON33
#define PMIC_DA_QI_BIF_TX_DATA_MASK                      0x1
#define PMIC_DA_QI_BIF_TX_DATA_SHIFT                     14
#define PMIC_DA_QI_BIF_TX_EN_ADDR                        MT6355_BIF_CON33
#define PMIC_DA_QI_BIF_TX_EN_MASK                        0x1
#define PMIC_DA_QI_BIF_TX_EN_SHIFT                       15
#define PMIC_BIF_TX_DATA_FIANL_ADDR                      MT6355_BIF_CON34
#define PMIC_BIF_TX_DATA_FIANL_MASK                      0xFFFF
#define PMIC_BIF_TX_DATA_FIANL_SHIFT                     0
#define PMIC_BIF_RX_DATA_SAMPLING_ADDR                   MT6355_BIF_CON35
#define PMIC_BIF_RX_DATA_SAMPLING_MASK                   0xFFFF
#define PMIC_BIF_RX_DATA_SAMPLING_SHIFT                  0
#define PMIC_BIF_RX_DATA_RECOVERY_ADDR                   MT6355_BIF_CON36
#define PMIC_BIF_RX_DATA_RECOVERY_MASK                   0x3FFF
#define PMIC_BIF_RX_DATA_RECOVERY_SHIFT                  0
#define PMIC_RG_BATON_HT_EN_ADDR                         MT6355_BIF_CON36
#define PMIC_RG_BATON_HT_EN_MASK                         0x1
#define PMIC_RG_BATON_HT_EN_SHIFT                        14
#define PMIC_RG_BATON_HT_EN_DLY_TIME_ADDR                MT6355_BIF_CON36
#define PMIC_RG_BATON_HT_EN_DLY_TIME_MASK                0x1
#define PMIC_RG_BATON_HT_EN_DLY_TIME_SHIFT               15
#define PMIC_BIF_TIMEOUT_SET_ADDR                        MT6355_BIF_CON37
#define PMIC_BIF_TIMEOUT_SET_MASK                        0xFFFF
#define PMIC_BIF_TIMEOUT_SET_SHIFT                       0
#define PMIC_BIF_RX_DEG_WND_ADDR                         MT6355_BIF_CON38
#define PMIC_BIF_RX_DEG_WND_MASK                         0x3FF
#define PMIC_BIF_RX_DEG_WND_SHIFT                        0
#define PMIC_BIF_RX_DEG_EN_ADDR                          MT6355_BIF_CON38
#define PMIC_BIF_RX_DEG_EN_MASK                          0x1
#define PMIC_BIF_RX_DEG_EN_SHIFT                         15
#define PMIC_BIF_RSV1_ADDR                               MT6355_BIF_CON39
#define PMIC_BIF_RSV1_MASK                               0xFF
#define PMIC_BIF_RSV1_SHIFT                              0
#define PMIC_BIF_RSV0_ADDR                               MT6355_BIF_CON39
#define PMIC_BIF_RSV0_MASK                               0xFF
#define PMIC_BIF_RSV0_SHIFT                              8
#define PMIC_DA_QI_BATON_HT_EN_ADDR                      MT6355_BIF_BAT_CON0
#define PMIC_DA_QI_BATON_HT_EN_MASK                      0x1
#define PMIC_DA_QI_BATON_HT_EN_SHIFT                     5
#define PMIC_RG_BATON_DEBOUNCE_WND_ADDR                  MT6355_BIF_BAT_CON1
#define PMIC_RG_BATON_DEBOUNCE_WND_MASK                  0x3
#define PMIC_RG_BATON_DEBOUNCE_WND_SHIFT                 0
#define PMIC_RG_BATON_DEBOUNCE_THD_ADDR                  MT6355_BIF_BAT_CON1
#define PMIC_RG_BATON_DEBOUNCE_THD_MASK                  0x3
#define PMIC_RG_BATON_DEBOUNCE_THD_SHIFT                 2
#define PMIC_RG_BATON_VBIF_STB_ADDR                      MT6355_BIF_BAT_CON1
#define PMIC_RG_BATON_VBIF_STB_MASK                      0x1
#define PMIC_RG_BATON_VBIF_STB_SHIFT                     4
#define PMIC_RG_BATON_CHRDET_TEST_MODE_ADDR              MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_CHRDET_TEST_MODE_MASK              0x1
#define PMIC_RG_BATON_CHRDET_TEST_MODE_SHIFT             0
#define PMIC_RG_BATON_UNDET_TEST_MODE_ADDR               MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_UNDET_TEST_MODE_MASK               0x1
#define PMIC_RG_BATON_UNDET_TEST_MODE_SHIFT              1
#define PMIC_RG_BATON_AUXADC_TEST_MODE_ADDR              MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_AUXADC_TEST_MODE_MASK              0x1
#define PMIC_RG_BATON_AUXADC_TEST_MODE_SHIFT             2
#define PMIC_RG_BATON_FGADC_TEST_MODE_ADDR               MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_FGADC_TEST_MODE_MASK               0x1
#define PMIC_RG_BATON_FGADC_TEST_MODE_SHIFT              3
#define PMIC_RG_BATON_RTC_TEST_MODE_ADDR                 MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_RTC_TEST_MODE_MASK                 0x1
#define PMIC_RG_BATON_RTC_TEST_MODE_SHIFT                4
#define PMIC_RG_BATON_BIF_TEST_MODE_ADDR                 MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_BIF_TEST_MODE_MASK                 0x1
#define PMIC_RG_BATON_BIF_TEST_MODE_SHIFT                5
#define PMIC_RG_BATON_RSV_ADDR                           MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_RSV_MASK                           0x3
#define PMIC_RG_BATON_RSV_SHIFT                          6
#define PMIC_RG_BATON_CHRDET_SW_ADDR                     MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_CHRDET_SW_MASK                     0x1
#define PMIC_RG_BATON_CHRDET_SW_SHIFT                    8
#define PMIC_RG_BATON_UNDET_SW_ADDR                      MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_UNDET_SW_MASK                      0x1
#define PMIC_RG_BATON_UNDET_SW_SHIFT                     9
#define PMIC_RG_BATON_AUXADC_SW_ADDR                     MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_AUXADC_SW_MASK                     0x1
#define PMIC_RG_BATON_AUXADC_SW_SHIFT                    10
#define PMIC_RG_BATON_FGADC_SW_ADDR                      MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_FGADC_SW_MASK                      0x1
#define PMIC_RG_BATON_FGADC_SW_SHIFT                     11
#define PMIC_RG_BATON_RTC_SW_ADDR                        MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_RTC_SW_MASK                        0x1
#define PMIC_RG_BATON_RTC_SW_SHIFT                       12
#define PMIC_RG_BATON_BIF_SW_ADDR                        MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_BIF_SW_MASK                        0x1
#define PMIC_RG_BATON_BIF_SW_SHIFT                       13
#define PMIC_RG_BATON_RSV_SW_ADDR                        MT6355_BIF_BAT_CON2
#define PMIC_RG_BATON_RSV_SW_MASK                        0x3
#define PMIC_RG_BATON_RSV_SW_SHIFT                       14
#define PMIC_BATON_STATUS_ADDR                           MT6355_BIF_BAT_CON3
#define PMIC_BATON_STATUS_MASK                           0x1
#define PMIC_BATON_STATUS_SHIFT                          0
#define PMIC_BATON_AUXADC_SET_ADDR                       MT6355_BIF_BAT_CON3
#define PMIC_BATON_AUXADC_SET_MASK                       0x1
#define PMIC_BATON_AUXADC_SET_SHIFT                      1
#define PMIC_BATON_DEB_VALID_ADDR                        MT6355_BIF_BAT_CON3
#define PMIC_BATON_DEB_VALID_MASK                        0x1
#define PMIC_BATON_DEB_VALID_SHIFT                       2
#define PMIC_BATON_BIF_STATUS_ADDR                       MT6355_BIF_BAT_CON3
#define PMIC_BATON_BIF_STATUS_MASK                       0x1
#define PMIC_BATON_BIF_STATUS_SHIFT                      3
#define PMIC_BATON_RTC_STATUS_ADDR                       MT6355_BIF_BAT_CON3
#define PMIC_BATON_RTC_STATUS_MASK                       0x1
#define PMIC_BATON_RTC_STATUS_SHIFT                      4
#define PMIC_BATON_FGADC_STATUS_ADDR                     MT6355_BIF_BAT_CON3
#define PMIC_BATON_FGADC_STATUS_MASK                     0x1
#define PMIC_BATON_FGADC_STATUS_SHIFT                    5
#define PMIC_BATON_AUXADC_TRIG_ADDR                      MT6355_BIF_BAT_CON3
#define PMIC_BATON_AUXADC_TRIG_MASK                      0x1
#define PMIC_BATON_AUXADC_TRIG_SHIFT                     6
#define PMIC_BATON_CHRDET_DEB_ADDR                       MT6355_BIF_BAT_CON3
#define PMIC_BATON_CHRDET_DEB_MASK                       0x1
#define PMIC_BATON_CHRDET_DEB_SHIFT                      7
#define PMIC_BATON_IVGEN_ENB_ADDR                        MT6355_BIF_BAT_CON3
#define PMIC_BATON_IVGEN_ENB_MASK                        0x1
#define PMIC_BATON_IVGEN_ENB_SHIFT                       8
#define PMIC_BATON_VBIF28_STB_ADDR                       MT6355_BIF_BAT_CON3
#define PMIC_BATON_VBIF28_STB_MASK                       0x1
#define PMIC_BATON_VBIF28_STB_SHIFT                      9
#define PMIC_BATON_VBIF28_EN_ADDR                        MT6355_BIF_BAT_CON3
#define PMIC_BATON_VBIF28_EN_MASK                        0x1
#define PMIC_BATON_VBIF28_EN_SHIFT                       10
#define PMIC_BATON_RSV_0_ADDR                            MT6355_BIF_BAT_CON3
#define PMIC_BATON_RSV_0_MASK                            0x1F
#define PMIC_BATON_RSV_0_SHIFT                           11
#define PMIC_RG_BIF_BATID_SW_EN_ADDR                     MT6355_BIF_ANA_CON0
#define PMIC_RG_BIF_BATID_SW_EN_MASK                     0x1
#define PMIC_RG_BIF_BATID_SW_EN_SHIFT                    0
#define PMIC_FG_ON_ADDR                                  MT6355_FGADC_CON0
#define PMIC_FG_ON_MASK                                  0x1
#define PMIC_FG_ON_SHIFT                                 0
#define PMIC_FG_CAL_ADDR                                 MT6355_FGADC_CON0
#define PMIC_FG_CAL_MASK                                 0x3
#define PMIC_FG_CAL_SHIFT                                2
#define PMIC_FG_AUTOCALRATE_ADDR                         MT6355_FGADC_CON0
#define PMIC_FG_AUTOCALRATE_MASK                         0x7
#define PMIC_FG_AUTOCALRATE_SHIFT                        4
#define PMIC_FG_SON_SLP_EN_ADDR                          MT6355_FGADC_CON0
#define PMIC_FG_SON_SLP_EN_MASK                          0x1
#define PMIC_FG_SON_SLP_EN_SHIFT                         8
#define PMIC_FG_SOFF_SLP_EN_ADDR                         MT6355_FGADC_CON0
#define PMIC_FG_SOFF_SLP_EN_MASK                         0x1
#define PMIC_FG_SOFF_SLP_EN_SHIFT                        9
#define PMIC_FG_ZCV_DET_EN_ADDR                          MT6355_FGADC_CON0
#define PMIC_FG_ZCV_DET_EN_MASK                          0x1
#define PMIC_FG_ZCV_DET_EN_SHIFT                         10
#define PMIC_FG_AUXADC_R_ADDR                            MT6355_FGADC_CON0
#define PMIC_FG_AUXADC_R_MASK                            0x1
#define PMIC_FG_AUXADC_R_SHIFT                           11
#define PMIC_FG_IAVG_MODE_ADDR                           MT6355_FGADC_CON0
#define PMIC_FG_IAVG_MODE_MASK                           0xF
#define PMIC_FG_IAVG_MODE_SHIFT                          12
#define PMIC_FG_SW_READ_PRE_ADDR                         MT6355_FGADC_CON1
#define PMIC_FG_SW_READ_PRE_MASK                         0x1
#define PMIC_FG_SW_READ_PRE_SHIFT                        0
#define PMIC_FG_SW_RSTCLR_ADDR                           MT6355_FGADC_CON1
#define PMIC_FG_SW_RSTCLR_MASK                           0x1
#define PMIC_FG_SW_RSTCLR_SHIFT                          1
#define PMIC_FG_SW_CR_ADDR                               MT6355_FGADC_CON1
#define PMIC_FG_SW_CR_MASK                               0x1
#define PMIC_FG_SW_CR_SHIFT                              2
#define PMIC_FG_SW_CLEAR_ADDR                            MT6355_FGADC_CON1
#define PMIC_FG_SW_CLEAR_MASK                            0x1
#define PMIC_FG_SW_CLEAR_SHIFT                           3
#define PMIC_FG_OFFSET_RST_ADDR                          MT6355_FGADC_CON1
#define PMIC_FG_OFFSET_RST_MASK                          0x1
#define PMIC_FG_OFFSET_RST_SHIFT                         8
#define PMIC_FG_TIME_RST_ADDR                            MT6355_FGADC_CON1
#define PMIC_FG_TIME_RST_MASK                            0x1
#define PMIC_FG_TIME_RST_SHIFT                           9
#define PMIC_FG_CHARGE_RST_ADDR                          MT6355_FGADC_CON1
#define PMIC_FG_CHARGE_RST_MASK                          0x1
#define PMIC_FG_CHARGE_RST_SHIFT                         10
#define PMIC_FG_N_CHARGE_RST_ADDR                        MT6355_FGADC_CON1
#define PMIC_FG_N_CHARGE_RST_MASK                        0x1
#define PMIC_FG_N_CHARGE_RST_SHIFT                       11
#define PMIC_FG_SOFF_RST_ADDR                            MT6355_FGADC_CON1
#define PMIC_FG_SOFF_RST_MASK                            0x1
#define PMIC_FG_SOFF_RST_SHIFT                           12
#define PMIC_FG_LATCHDATA_ST_ADDR                        MT6355_FGADC_CON1
#define PMIC_FG_LATCHDATA_ST_MASK                        0x1
#define PMIC_FG_LATCHDATA_ST_SHIFT                       15
#define PMIC_EVENT_FG_BAT0_L_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_BAT0_L_MASK                        0x1
#define PMIC_EVENT_FG_BAT0_L_SHIFT                       0
#define PMIC_EVENT_FG_BAT0_H_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_BAT0_H_MASK                        0x1
#define PMIC_EVENT_FG_BAT0_H_SHIFT                       1
#define PMIC_EVENT_FG_BAT1_L_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_BAT1_L_MASK                        0x1
#define PMIC_EVENT_FG_BAT1_L_SHIFT                       2
#define PMIC_EVENT_FG_BAT1_H_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_BAT1_H_MASK                        0x1
#define PMIC_EVENT_FG_BAT1_H_SHIFT                       3
#define PMIC_EVENT_FG_CUR_L_ADDR                         MT6355_FGADC_CON2
#define PMIC_EVENT_FG_CUR_L_MASK                         0x1
#define PMIC_EVENT_FG_CUR_L_SHIFT                        4
#define PMIC_EVENT_FG_CUR_H_ADDR                         MT6355_FGADC_CON2
#define PMIC_EVENT_FG_CUR_H_MASK                         0x1
#define PMIC_EVENT_FG_CUR_H_SHIFT                        5
#define PMIC_EVENT_FG_IAVG_L_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_IAVG_L_MASK                        0x1
#define PMIC_EVENT_FG_IAVG_L_SHIFT                       6
#define PMIC_EVENT_FG_IAVG_H_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_IAVG_H_MASK                        0x1
#define PMIC_EVENT_FG_IAVG_H_SHIFT                       7
#define PMIC_EVENT_FG_N_CHARGE_L_ADDR                    MT6355_FGADC_CON2
#define PMIC_EVENT_FG_N_CHARGE_L_MASK                    0x1
#define PMIC_EVENT_FG_N_CHARGE_L_SHIFT                   8
#define PMIC_EVENT_FG_TIME_H_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_TIME_H_MASK                        0x1
#define PMIC_EVENT_FG_TIME_H_SHIFT                       11
#define PMIC_EVENT_FG_DISCHARGE_ADDR                     MT6355_FGADC_CON2
#define PMIC_EVENT_FG_DISCHARGE_MASK                     0x1
#define PMIC_EVENT_FG_DISCHARGE_SHIFT                    12
#define PMIC_EVENT_FG_CHARGE_ADDR                        MT6355_FGADC_CON2
#define PMIC_EVENT_FG_CHARGE_MASK                        0x1
#define PMIC_EVENT_FG_CHARGE_SHIFT                       13
#define PMIC_EVENT_FG_ZCV_ADDR                           MT6355_FGADC_CON2
#define PMIC_EVENT_FG_ZCV_MASK                           0x1
#define PMIC_EVENT_FG_ZCV_SHIFT                          14
#define PMIC_FG_OSR1_ADDR                                MT6355_FGADC_CON3
#define PMIC_FG_OSR1_MASK                                0xF
#define PMIC_FG_OSR1_SHIFT                               0
#define PMIC_FG_OSR2_ADDR                                MT6355_FGADC_CON3
#define PMIC_FG_OSR2_MASK                                0x3
#define PMIC_FG_OSR2_SHIFT                               8
#define PMIC_FG_FIR1BYPASS_ADDR                          MT6355_FGADC_CON4
#define PMIC_FG_FIR1BYPASS_MASK                          0x1
#define PMIC_FG_FIR1BYPASS_SHIFT                         0
#define PMIC_FG_FIR2BYPASS_ADDR                          MT6355_FGADC_CON4
#define PMIC_FG_FIR2BYPASS_MASK                          0x1
#define PMIC_FG_FIR2BYPASS_SHIFT                         1
#define PMIC_FG_ADJ_OFFSET_EN_ADDR                       MT6355_FGADC_CON4
#define PMIC_FG_ADJ_OFFSET_EN_MASK                       0x1
#define PMIC_FG_ADJ_OFFSET_EN_SHIFT                      2
#define PMIC_FG_ADC_AUTORST_ADDR                         MT6355_FGADC_CON4
#define PMIC_FG_ADC_AUTORST_MASK                         0x1
#define PMIC_FG_ADC_AUTORST_SHIFT                        3
#define PMIC_FG_ADC_RSTDETECT_ADDR                       MT6355_FGADC_CON4
#define PMIC_FG_ADC_RSTDETECT_MASK                       0x1
#define PMIC_FG_ADC_RSTDETECT_SHIFT                      4
#define PMIC_FG_VA18_AON_ADDR                            MT6355_FGADC_CON4
#define PMIC_FG_VA18_AON_MASK                            0x1
#define PMIC_FG_VA18_AON_SHIFT                           5
#define PMIC_FG_VA18_AOFF_ADDR                           MT6355_FGADC_CON4
#define PMIC_FG_VA18_AOFF_MASK                           0x1
#define PMIC_FG_VA18_AOFF_SHIFT                          6
#define PMIC_FG_SON_SW_ADDR                              MT6355_FGADC_CON4
#define PMIC_FG_SON_SW_MASK                              0x1
#define PMIC_FG_SON_SW_SHIFT                             7
#define PMIC_FG_SON_SW_MODE_ADDR                         MT6355_FGADC_CON4
#define PMIC_FG_SON_SW_MODE_MASK                         0x1
#define PMIC_FG_SON_SW_MODE_SHIFT                        8
#define PMIC_FGADC_CON4_RSV_ADDR                         MT6355_FGADC_CON4
#define PMIC_FGADC_CON4_RSV_MASK                         0x7F
#define PMIC_FGADC_CON4_RSV_SHIFT                        9
#define PMIC_FG_RSTB_STATUS_ADDR                         MT6355_FGADC_RST_CON0
#define PMIC_FG_RSTB_STATUS_MASK                         0x1
#define PMIC_FG_RSTB_STATUS_SHIFT                        0
#define PMIC_FG_R_CURR_ADDR                              MT6355_FGADC_R_CON0
#define PMIC_FG_R_CURR_MASK                              0xFFFF
#define PMIC_FG_R_CURR_SHIFT                             0
#define PMIC_FG_CURRENT_OUT_ADDR                         MT6355_FGADC_CUR_CON0
#define PMIC_FG_CURRENT_OUT_MASK                         0xFFFF
#define PMIC_FG_CURRENT_OUT_SHIFT                        0
#define PMIC_FG_CUR_LTH_ADDR                             MT6355_FGADC_CUR_CON1
#define PMIC_FG_CUR_LTH_MASK                             0xFFFF
#define PMIC_FG_CUR_LTH_SHIFT                            0
#define PMIC_FG_CUR_HTH_ADDR                             MT6355_FGADC_CUR_CON2
#define PMIC_FG_CUR_HTH_MASK                             0xFFFF
#define PMIC_FG_CUR_HTH_SHIFT                            0
#define PMIC_FG_CIC2_ADDR                                MT6355_FGADC_CUR_CON3
#define PMIC_FG_CIC2_MASK                                0xFFFF
#define PMIC_FG_CIC2_SHIFT                               0
#define PMIC_FG_CAR_31_16_ADDR                           MT6355_FGADC_CAR_CON0
#define PMIC_FG_CAR_31_16_MASK                           0xFFFF
#define PMIC_FG_CAR_31_16_SHIFT                          0
#define PMIC_FG_CAR_15_00_ADDR                           MT6355_FGADC_CAR_CON1
#define PMIC_FG_CAR_15_00_MASK                           0xFFFF
#define PMIC_FG_CAR_15_00_SHIFT                          0
#define PMIC_FG_BAT0_LTH_31_16_ADDR                      MT6355_FGADC_CAR_CON2
#define PMIC_FG_BAT0_LTH_31_16_MASK                      0xFFFF
#define PMIC_FG_BAT0_LTH_31_16_SHIFT                     0
#define PMIC_FG_BAT0_LTH_15_14_ADDR                      MT6355_FGADC_CAR_CON3
#define PMIC_FG_BAT0_LTH_15_14_MASK                      0x3
#define PMIC_FG_BAT0_LTH_15_14_SHIFT                     14
#define PMIC_FG_BAT0_HTH_31_16_ADDR                      MT6355_FGADC_CAR_CON4
#define PMIC_FG_BAT0_HTH_31_16_MASK                      0xFFFF
#define PMIC_FG_BAT0_HTH_31_16_SHIFT                     0
#define PMIC_FG_BAT0_HTH_15_14_ADDR                      MT6355_FGADC_CAR_CON5
#define PMIC_FG_BAT0_HTH_15_14_MASK                      0x3
#define PMIC_FG_BAT0_HTH_15_14_SHIFT                     14
#define PMIC_FG_BAT1_LTH_31_16_ADDR                      MT6355_FGADC_CAR_CON6
#define PMIC_FG_BAT1_LTH_31_16_MASK                      0xFFFF
#define PMIC_FG_BAT1_LTH_31_16_SHIFT                     0
#define PMIC_FG_BAT1_LTH_15_14_ADDR                      MT6355_FGADC_CAR_CON7
#define PMIC_FG_BAT1_LTH_15_14_MASK                      0x3
#define PMIC_FG_BAT1_LTH_15_14_SHIFT                     14
#define PMIC_FG_BAT1_HTH_31_16_ADDR                      MT6355_FGADC_CAR_CON8
#define PMIC_FG_BAT1_HTH_31_16_MASK                      0xFFFF
#define PMIC_FG_BAT1_HTH_31_16_SHIFT                     0
#define PMIC_FG_BAT1_HTH_15_14_ADDR                      MT6355_FGADC_CAR_CON9
#define PMIC_FG_BAT1_HTH_15_14_MASK                      0x3
#define PMIC_FG_BAT1_HTH_15_14_SHIFT                     14
#define PMIC_FG_NCAR_31_16_ADDR                          MT6355_FGADC_NCAR_CON0
#define PMIC_FG_NCAR_31_16_MASK                          0xFFFF
#define PMIC_FG_NCAR_31_16_SHIFT                         0
#define PMIC_FG_NCAR_15_00_ADDR                          MT6355_FGADC_NCAR_CON1
#define PMIC_FG_NCAR_15_00_MASK                          0xFFFF
#define PMIC_FG_NCAR_15_00_SHIFT                         0
#define PMIC_FG_N_CHARGE_LTH_31_16_ADDR                  MT6355_FGADC_NCAR_CON2
#define PMIC_FG_N_CHARGE_LTH_31_16_MASK                  0xFFFF
#define PMIC_FG_N_CHARGE_LTH_31_16_SHIFT                 0
#define PMIC_FG_N_CHARGE_LTH_15_14_ADDR                  MT6355_FGADC_NCAR_CON3
#define PMIC_FG_N_CHARGE_LTH_15_14_MASK                  0x3
#define PMIC_FG_N_CHARGE_LTH_15_14_SHIFT                 14
#define PMIC_FG_IAVG_27_16_ADDR                          MT6355_FGADC_IAVG_CON0
#define PMIC_FG_IAVG_27_16_MASK                          0xFFF
#define PMIC_FG_IAVG_27_16_SHIFT                         0
#define PMIC_FG_IAVG_VLD_ADDR                            MT6355_FGADC_IAVG_CON0
#define PMIC_FG_IAVG_VLD_MASK                            0x1
#define PMIC_FG_IAVG_VLD_SHIFT                           15
#define PMIC_FG_IAVG_15_00_ADDR                          MT6355_FGADC_IAVG_CON1
#define PMIC_FG_IAVG_15_00_MASK                          0xFFFF
#define PMIC_FG_IAVG_15_00_SHIFT                         0
#define PMIC_FG_IAVG_LTH_28_16_ADDR                      MT6355_FGADC_IAVG_CON2
#define PMIC_FG_IAVG_LTH_28_16_MASK                      0x1FFF
#define PMIC_FG_IAVG_LTH_28_16_SHIFT                     0
#define PMIC_FG_IAVG_LTH_15_00_ADDR                      MT6355_FGADC_IAVG_CON3
#define PMIC_FG_IAVG_LTH_15_00_MASK                      0xFFFF
#define PMIC_FG_IAVG_LTH_15_00_SHIFT                     0
#define PMIC_FG_IAVG_HTH_28_16_ADDR                      MT6355_FGADC_IAVG_CON4
#define PMIC_FG_IAVG_HTH_28_16_MASK                      0x1FFF
#define PMIC_FG_IAVG_HTH_28_16_SHIFT                     0
#define PMIC_FG_IAVG_HTH_15_00_ADDR                      MT6355_FGADC_IAVG_CON5
#define PMIC_FG_IAVG_HTH_15_00_MASK                      0xFFFF
#define PMIC_FG_IAVG_HTH_15_00_SHIFT                     0
#define PMIC_FG_NTER_29_16_ADDR                          MT6355_FGADC_NTER_CON0
#define PMIC_FG_NTER_29_16_MASK                          0x3FFF
#define PMIC_FG_NTER_29_16_SHIFT                         0
#define PMIC_FG_NTER_15_00_ADDR                          MT6355_FGADC_NTER_CON1
#define PMIC_FG_NTER_15_00_MASK                          0xFFFF
#define PMIC_FG_NTER_15_00_SHIFT                         0
#define PMIC_FG_TIME_HTH_29_16_ADDR                      MT6355_FGADC_NTER_CON2
#define PMIC_FG_TIME_HTH_29_16_MASK                      0x3FFF
#define PMIC_FG_TIME_HTH_29_16_SHIFT                     0
#define PMIC_FG_TIME_HTH_15_00_ADDR                      MT6355_FGADC_NTER_CON3
#define PMIC_FG_TIME_HTH_15_00_MASK                      0xFFFF
#define PMIC_FG_TIME_HTH_15_00_SHIFT                     0
#define PMIC_FG_OFFSET_ADDR                              MT6355_FGADC_OFFSET_CON0
#define PMIC_FG_OFFSET_MASK                              0xFFFF
#define PMIC_FG_OFFSET_SHIFT                             0
#define PMIC_FG_ADJUST_OFFSET_VALUE_ADDR                 MT6355_FGADC_OFFSET_CON1
#define PMIC_FG_ADJUST_OFFSET_VALUE_MASK                 0xFFFF
#define PMIC_FG_ADJUST_OFFSET_VALUE_SHIFT                0
#define PMIC_FG_GAIN_ADDR                                MT6355_FGADC_GAIN_CON0
#define PMIC_FG_GAIN_MASK                                0x1FFF
#define PMIC_FG_GAIN_SHIFT                               0
#define PMIC_FG_SON_SLP_CUR_TH_ADDR                      MT6355_FGADC_SON_CON0
#define PMIC_FG_SON_SLP_CUR_TH_MASK                      0xFFFF
#define PMIC_FG_SON_SLP_CUR_TH_SHIFT                     0
#define PMIC_FG_SON_SLP_TIME_ADDR                        MT6355_FGADC_SON_CON1
#define PMIC_FG_SON_SLP_TIME_MASK                        0x3FF
#define PMIC_FG_SON_SLP_TIME_SHIFT                       0
#define PMIC_FG_SON_DET_TIME_ADDR                        MT6355_FGADC_SON_CON2
#define PMIC_FG_SON_DET_TIME_MASK                        0x3FF
#define PMIC_FG_SON_DET_TIME_SHIFT                       0
#define PMIC_FG_FP_FTIME_ADDR                            MT6355_FGADC_SON_CON3
#define PMIC_FG_FP_FTIME_MASK                            0xFF
#define PMIC_FG_FP_FTIME_SHIFT                           0
#define PMIC_FG_SOFF_SLP_CUR_TH_ADDR                     MT6355_FGADC_SOFF_CON0
#define PMIC_FG_SOFF_SLP_CUR_TH_MASK                     0xFFFF
#define PMIC_FG_SOFF_SLP_CUR_TH_SHIFT                    0
#define PMIC_FG_SOFF_SLP_TIME_ADDR                       MT6355_FGADC_SOFF_CON1
#define PMIC_FG_SOFF_SLP_TIME_MASK                       0x3FF
#define PMIC_FG_SOFF_SLP_TIME_SHIFT                      0
#define PMIC_FG_SOFF_DET_TIME_ADDR                       MT6355_FGADC_SOFF_CON2
#define PMIC_FG_SOFF_DET_TIME_MASK                       0x3FF
#define PMIC_FG_SOFF_DET_TIME_SHIFT                      0
#define PMIC_FG_SOFF_TIME_29_16_ADDR                     MT6355_FGADC_SOFF_CON3
#define PMIC_FG_SOFF_TIME_29_16_MASK                     0x3FFF
#define PMIC_FG_SOFF_TIME_29_16_SHIFT                    0
#define PMIC_FG_SOFF_ADDR                                MT6355_FGADC_SOFF_CON3
#define PMIC_FG_SOFF_MASK                                0x1
#define PMIC_FG_SOFF_SHIFT                               15
#define PMIC_FG_SOFF_TIME_15_00_ADDR                     MT6355_FGADC_SOFF_CON4
#define PMIC_FG_SOFF_TIME_15_00_MASK                     0xFFFF
#define PMIC_FG_SOFF_TIME_15_00_SHIFT                    0
#define PMIC_FG_PWR_TIME0_ADDR                           MT6355_FGADC_PWR_CON0
#define PMIC_FG_PWR_TIME0_MASK                           0xFF
#define PMIC_FG_PWR_TIME0_SHIFT                          0
#define PMIC_FG_PWR_TIME1_ADDR                           MT6355_FGADC_PWR_CON0
#define PMIC_FG_PWR_TIME1_MASK                           0xFF
#define PMIC_FG_PWR_TIME1_SHIFT                          8
#define PMIC_FG_PWR_TIME2_ADDR                           MT6355_FGADC_PWR_CON1
#define PMIC_FG_PWR_TIME2_MASK                           0xFF
#define PMIC_FG_PWR_TIME2_SHIFT                          0
#define PMIC_FG_ZCV_DET_IV_ADDR                          MT6355_FGADC_ZCV_CON0
#define PMIC_FG_ZCV_DET_IV_MASK                          0xF
#define PMIC_FG_ZCV_DET_IV_SHIFT                         0
#define PMIC_FG_ZCV_CAR_TH_30_16_ADDR                    MT6355_FGADC_ZCV_CON1
#define PMIC_FG_ZCV_CAR_TH_30_16_MASK                    0x7FFF
#define PMIC_FG_ZCV_CAR_TH_30_16_SHIFT                   0
#define PMIC_FG_ZCV_CAR_TH_15_00_ADDR                    MT6355_FGADC_ZCV_CON2
#define PMIC_FG_ZCV_CAR_TH_15_00_MASK                    0xFFFF
#define PMIC_FG_ZCV_CAR_TH_15_00_SHIFT                   0
#define PMIC_FG_ZCV_CAR_31_16_ADDR                       MT6355_FGADC_ZCV_CON3
#define PMIC_FG_ZCV_CAR_31_16_MASK                       0xFFFF
#define PMIC_FG_ZCV_CAR_31_16_SHIFT                      0
#define PMIC_FG_ZCV_CAR_15_00_ADDR                       MT6355_FGADC_ZCV_CON4
#define PMIC_FG_ZCV_CAR_15_00_MASK                       0xFFFF
#define PMIC_FG_ZCV_CAR_15_00_SHIFT                      0
#define PMIC_FG_ZCV_CURR_ADDR                            MT6355_FGADC_ZCV_CON5
#define PMIC_FG_ZCV_CURR_MASK                            0xFFFF
#define PMIC_FG_ZCV_CURR_SHIFT                           0
#define PMIC_RG_FGANALOGTEST_3_1_ADDR                    MT6355_FGADC_ANA_CON0
#define PMIC_RG_FGANALOGTEST_3_1_MASK                    0x7
#define PMIC_RG_FGANALOGTEST_3_1_SHIFT                   1
#define PMIC_RG_FGRINTMODE_ADDR                          MT6355_FGADC_ANA_CON0
#define PMIC_RG_FGRINTMODE_MASK                          0x1
#define PMIC_RG_FGRINTMODE_SHIFT                         4
#define PMIC_RG_SPARE_ADDR                               MT6355_FGADC_ANA_CON0
#define PMIC_RG_SPARE_MASK                               0xFF
#define PMIC_RG_SPARE_SHIFT                              5
#define PMIC_RG_FG_OFFSET_SWAP_ADDR                      MT6355_FGADC_ANA_CON1
#define PMIC_RG_FG_OFFSET_SWAP_MASK                      0x7
#define PMIC_RG_FG_OFFSET_SWAP_SHIFT                     0
#define PMIC_FG_MODE_ADDR                                MT6355_FGADC_TEST_CON0
#define PMIC_FG_MODE_MASK                                0x1
#define PMIC_FG_MODE_SHIFT                               0
#define PMIC_FG_RST_SW_ADDR                              MT6355_FGADC_TEST_CON0
#define PMIC_FG_RST_SW_MASK                              0x1
#define PMIC_FG_RST_SW_SHIFT                             1
#define PMIC_FG_FGCAL_EN_SW_ADDR                         MT6355_FGADC_TEST_CON0
#define PMIC_FG_FGCAL_EN_SW_MASK                         0x1
#define PMIC_FG_FGCAL_EN_SW_SHIFT                        2
#define PMIC_FG_FGADC_EN_SW_ADDR                         MT6355_FGADC_TEST_CON0
#define PMIC_FG_FGADC_EN_SW_MASK                         0x1
#define PMIC_FG_FGADC_EN_SW_SHIFT                        3
#define PMIC_FG_RNG_BIT_MODE_ADDR                        MT6355_FGADC_TEST_CON0
#define PMIC_FG_RNG_BIT_MODE_MASK                        0x1
#define PMIC_FG_RNG_BIT_MODE_SHIFT                       4
#define PMIC_FG_RNG_BIT_SW_ADDR                          MT6355_FGADC_TEST_CON0
#define PMIC_FG_RNG_BIT_SW_MASK                          0x1
#define PMIC_FG_RNG_BIT_SW_SHIFT                         5
#define PMIC_FG_RNG_EN_MODE_ADDR                         MT6355_FGADC_TEST_CON0
#define PMIC_FG_RNG_EN_MODE_MASK                         0x1
#define PMIC_FG_RNG_EN_MODE_SHIFT                        6
#define PMIC_FG_RNG_EN_SW_ADDR                           MT6355_FGADC_TEST_CON0
#define PMIC_FG_RNG_EN_SW_MASK                           0x1
#define PMIC_FG_RNG_EN_SW_SHIFT                          7
#define PMIC_FG_DWA_T0_ADDR                              MT6355_FGADC_TEST_CON0
#define PMIC_FG_DWA_T0_MASK                              0x3
#define PMIC_FG_DWA_T0_SHIFT                             8
#define PMIC_FG_DWA_T1_ADDR                              MT6355_FGADC_TEST_CON0
#define PMIC_FG_DWA_T1_MASK                              0x3
#define PMIC_FG_DWA_T1_SHIFT                             10
#define PMIC_FG_DWA_RST_MODE_ADDR                        MT6355_FGADC_TEST_CON0
#define PMIC_FG_DWA_RST_MODE_MASK                        0x1
#define PMIC_FG_DWA_RST_MODE_SHIFT                       12
#define PMIC_FG_DWA_RST_SW_ADDR                          MT6355_FGADC_TEST_CON0
#define PMIC_FG_DWA_RST_SW_MASK                          0x1
#define PMIC_FG_DWA_RST_SW_SHIFT                         13
#define PMIC_FG_DWA_RST_ADDR                             MT6355_FGADC_TEST_CON0
#define PMIC_FG_DWA_RST_MASK                             0x1
#define PMIC_FG_DWA_RST_SHIFT                            15
#define PMIC_FG_RSV_CON0_RSV_ADDR                        MT6355_FGADC_RSV_CON0
#define PMIC_FG_RSV_CON0_RSV_MASK                        0xFFFF
#define PMIC_FG_RSV_CON0_RSV_SHIFT                       0
#define PMIC_FG_RSV_CON1_RSV_ADDR                        MT6355_FGADC_RSV_CON1
#define PMIC_FG_RSV_CON1_RSV_MASK                        0xFFFF
#define PMIC_FG_RSV_CON1_RSV_SHIFT                       0
#define PMIC_FG_RSV_CON2_RSV_ADDR                        MT6355_FGADC_RSV_CON2
#define PMIC_FG_RSV_CON2_RSV_MASK                        0xFFFF
#define PMIC_FG_RSV_CON2_RSV_SHIFT                       0
#define PMIC_FG_RSV_CON3_RSV_ADDR                        MT6355_FGADC_RSV_CON3
#define PMIC_FG_RSV_CON3_RSV_MASK                        0xFFFF
#define PMIC_FG_RSV_CON3_RSV_SHIFT                       0
#define PMIC_SYSTEM_INFO_CON0_ADDR                       MT6355_SYSTEM_INFO_CON0
#define PMIC_SYSTEM_INFO_CON0_MASK                       0xFFFF
#define PMIC_SYSTEM_INFO_CON0_SHIFT                      0
#define PMIC_SYSTEM_INFO_CON1_ADDR                       MT6355_SYSTEM_INFO_CON1
#define PMIC_SYSTEM_INFO_CON1_MASK                       0xFFFF
#define PMIC_SYSTEM_INFO_CON1_SHIFT                      0
#define PMIC_SYSTEM_INFO_CON2_ADDR                       MT6355_SYSTEM_INFO_CON2
#define PMIC_SYSTEM_INFO_CON2_MASK                       0xFFFF
#define PMIC_SYSTEM_INFO_CON2_SHIFT                      0
#define PMIC_SYSTEM_INFO_CON3_ADDR                       MT6355_SYSTEM_INFO_CON3
#define PMIC_SYSTEM_INFO_CON3_MASK                       0xFFFF
#define PMIC_SYSTEM_INFO_CON3_SHIFT                      0
#define PMIC_SYSTEM_INFO_CON4_ADDR                       MT6355_SYSTEM_INFO_CON4
#define PMIC_SYSTEM_INFO_CON4_MASK                       0xFFFF
#define PMIC_SYSTEM_INFO_CON4_SHIFT                      0
#define PMIC_RG_FGADC_GAINERROR_CAL_ADDR                 MT6355_FGADC_EFUSE_CON0
#define PMIC_RG_FGADC_GAINERROR_CAL_MASK                 0x1FFF
#define PMIC_RG_FGADC_GAINERROR_CAL_SHIFT                0
#define PMIC_AUXADC_ADC_OUT_CH0_ADDR                     MT6355_AUXADC_ADC0
#define PMIC_AUXADC_ADC_OUT_CH0_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH0_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH0_ADDR                     MT6355_AUXADC_ADC0
#define PMIC_AUXADC_ADC_RDY_CH0_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH0_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH1_ADDR                     MT6355_AUXADC_ADC1
#define PMIC_AUXADC_ADC_OUT_CH1_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH1_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH1_ADDR                     MT6355_AUXADC_ADC1
#define PMIC_AUXADC_ADC_RDY_CH1_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH1_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH2_ADDR                     MT6355_AUXADC_ADC2
#define PMIC_AUXADC_ADC_OUT_CH2_MASK                     0xFFF
#define PMIC_AUXADC_ADC_OUT_CH2_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH2_ADDR                     MT6355_AUXADC_ADC2
#define PMIC_AUXADC_ADC_RDY_CH2_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH2_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH3_ADDR                     MT6355_AUXADC_ADC3
#define PMIC_AUXADC_ADC_OUT_CH3_MASK                     0xFFF
#define PMIC_AUXADC_ADC_OUT_CH3_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH3_ADDR                     MT6355_AUXADC_ADC3
#define PMIC_AUXADC_ADC_RDY_CH3_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH3_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH4_ADDR                     MT6355_AUXADC_ADC4
#define PMIC_AUXADC_ADC_OUT_CH4_MASK                     0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH4_ADDR                     MT6355_AUXADC_ADC4
#define PMIC_AUXADC_ADC_RDY_CH4_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH4_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH5_ADDR                     MT6355_AUXADC_ADC5
#define PMIC_AUXADC_ADC_OUT_CH5_MASK                     0xFFF
#define PMIC_AUXADC_ADC_OUT_CH5_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH5_ADDR                     MT6355_AUXADC_ADC5
#define PMIC_AUXADC_ADC_RDY_CH5_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH5_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH6_ADDR                     MT6355_AUXADC_ADC6
#define PMIC_AUXADC_ADC_OUT_CH6_MASK                     0xFFF
#define PMIC_AUXADC_ADC_OUT_CH6_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH6_ADDR                     MT6355_AUXADC_ADC6
#define PMIC_AUXADC_ADC_RDY_CH6_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH6_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH7_ADDR                     MT6355_AUXADC_ADC7
#define PMIC_AUXADC_ADC_OUT_CH7_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH7_ADDR                     MT6355_AUXADC_ADC7
#define PMIC_AUXADC_ADC_RDY_CH7_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH7_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH8_ADDR                     MT6355_AUXADC_ADC8
#define PMIC_AUXADC_ADC_OUT_CH8_MASK                     0xFFF
#define PMIC_AUXADC_ADC_OUT_CH8_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH8_ADDR                     MT6355_AUXADC_ADC8
#define PMIC_AUXADC_ADC_RDY_CH8_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH8_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH9_ADDR                     MT6355_AUXADC_ADC9
#define PMIC_AUXADC_ADC_OUT_CH9_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH9_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_CH9_ADDR                     MT6355_AUXADC_ADC9
#define PMIC_AUXADC_ADC_RDY_CH9_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_CH9_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_CH10_ADDR                    MT6355_AUXADC_ADC10
#define PMIC_AUXADC_ADC_OUT_CH10_MASK                    0xFFF
#define PMIC_AUXADC_ADC_OUT_CH10_SHIFT                   0
#define PMIC_AUXADC_ADC_RDY_CH10_ADDR                    MT6355_AUXADC_ADC10
#define PMIC_AUXADC_ADC_RDY_CH10_MASK                    0x1
#define PMIC_AUXADC_ADC_RDY_CH10_SHIFT                   15
#define PMIC_AUXADC_ADC_OUT_CH11_ADDR                    MT6355_AUXADC_ADC11
#define PMIC_AUXADC_ADC_OUT_CH11_MASK                    0xFFF
#define PMIC_AUXADC_ADC_OUT_CH11_SHIFT                   0
#define PMIC_AUXADC_ADC_RDY_CH11_ADDR                    MT6355_AUXADC_ADC11
#define PMIC_AUXADC_ADC_RDY_CH11_MASK                    0x1
#define PMIC_AUXADC_ADC_RDY_CH11_SHIFT                   15
#define PMIC_AUXADC_ADC_OUT_CH12_15_ADDR                 MT6355_AUXADC_ADC12
#define PMIC_AUXADC_ADC_OUT_CH12_15_MASK                 0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH12_15_SHIFT                0
#define PMIC_AUXADC_ADC_RDY_CH12_15_ADDR                 MT6355_AUXADC_ADC12
#define PMIC_AUXADC_ADC_RDY_CH12_15_MASK                 0x1
#define PMIC_AUXADC_ADC_RDY_CH12_15_SHIFT                15
#define PMIC_AUXADC_ADC_OUT_THR_HW_ADDR                  MT6355_AUXADC_ADC13
#define PMIC_AUXADC_ADC_OUT_THR_HW_MASK                  0xFFF
#define PMIC_AUXADC_ADC_OUT_THR_HW_SHIFT                 0
#define PMIC_AUXADC_ADC_RDY_THR_HW_ADDR                  MT6355_AUXADC_ADC13
#define PMIC_AUXADC_ADC_RDY_THR_HW_MASK                  0x1
#define PMIC_AUXADC_ADC_RDY_THR_HW_SHIFT                 15
#define PMIC_AUXADC_ADC_OUT_LBAT_ADDR                    MT6355_AUXADC_ADC14
#define PMIC_AUXADC_ADC_OUT_LBAT_MASK                    0xFFF
#define PMIC_AUXADC_ADC_OUT_LBAT_SHIFT                   0
#define PMIC_AUXADC_ADC_RDY_LBAT_ADDR                    MT6355_AUXADC_ADC14
#define PMIC_AUXADC_ADC_RDY_LBAT_MASK                    0x1
#define PMIC_AUXADC_ADC_RDY_LBAT_SHIFT                   15
#define PMIC_AUXADC_ADC_OUT_LBAT2_ADDR                   MT6355_AUXADC_ADC15
#define PMIC_AUXADC_ADC_OUT_LBAT2_MASK                   0xFFF
#define PMIC_AUXADC_ADC_OUT_LBAT2_SHIFT                  0
#define PMIC_AUXADC_ADC_RDY_LBAT2_ADDR                   MT6355_AUXADC_ADC15
#define PMIC_AUXADC_ADC_RDY_LBAT2_MASK                   0x1
#define PMIC_AUXADC_ADC_RDY_LBAT2_SHIFT                  15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_ADDR              MT6355_AUXADC_ADC16
#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_MASK              0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_SHIFT             0
#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_ADDR              MT6355_AUXADC_ADC16
#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_MASK              0x1
#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_SHIFT             15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_ADDR               MT6355_AUXADC_ADC17
#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_ADDR               MT6355_AUXADC_ADC17
#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_ADDR               MT6355_AUXADC_ADC18
#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_ADDR               MT6355_AUXADC_ADC18
#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_ADDR               MT6355_AUXADC_ADC19
#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_MASK               0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_ADDR               MT6355_AUXADC_ADC19
#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_ADDR              MT6355_AUXADC_ADC20
#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_MASK              0x7FFF
#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_SHIFT             0
#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_ADDR              MT6355_AUXADC_ADC20
#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_MASK              0x1
#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_SHIFT             15
#define PMIC_AUXADC_ADC_OUT_PWRON_SWCHR_ADDR             MT6355_AUXADC_ADC21
#define PMIC_AUXADC_ADC_OUT_PWRON_SWCHR_MASK             0x7FFF
#define PMIC_AUXADC_ADC_OUT_PWRON_SWCHR_SHIFT            0
#define PMIC_AUXADC_ADC_RDY_PWRON_SWCHR_ADDR             MT6355_AUXADC_ADC21
#define PMIC_AUXADC_ADC_RDY_PWRON_SWCHR_MASK             0x1
#define PMIC_AUXADC_ADC_RDY_PWRON_SWCHR_SHIFT            15
#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_ADDR             MT6355_AUXADC_ADC22
#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_MASK             0x7FFF
#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_SHIFT            0
#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_ADDR             MT6355_AUXADC_ADC22
#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_MASK             0x1
#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_SHIFT            15
#define PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR_ADDR            MT6355_AUXADC_ADC23
#define PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR_MASK            0x7FFF
#define PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR_SHIFT           0
#define PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR_ADDR            MT6355_AUXADC_ADC23
#define PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR_MASK            0x1
#define PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR_SHIFT           15
#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_ADDR               MT6355_AUXADC_ADC24
#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_ADDR               MT6355_AUXADC_ADC24
#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_ADDR               MT6355_AUXADC_ADC25
#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_ADDR               MT6355_AUXADC_ADC25
#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_ADDR               MT6355_AUXADC_ADC26
#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_ADDR               MT6355_AUXADC_ADC26
#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_ADDR               MT6355_AUXADC_ADC27
#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_ADDR               MT6355_AUXADC_ADC27
#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_ADDR                MT6355_AUXADC_ADC28
#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_MASK                0xFFF
#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_SHIFT               0
#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_ADDR                MT6355_AUXADC_ADC28
#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_MASK                0x1
#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_SHIFT               15
#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_ADDR              MT6355_AUXADC_ADC29
#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_MASK              0x7FFF
#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_SHIFT             0
#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_ADDR              MT6355_AUXADC_ADC29
#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_MASK              0x1
#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_SHIFT             15
#define PMIC_AUXADC_ADC_OUT_FGADC_SWCHR_ADDR             MT6355_AUXADC_ADC30
#define PMIC_AUXADC_ADC_OUT_FGADC_SWCHR_MASK             0x7FFF
#define PMIC_AUXADC_ADC_OUT_FGADC_SWCHR_SHIFT            0
#define PMIC_AUXADC_ADC_RDY_FGADC_SWCHR_ADDR             MT6355_AUXADC_ADC30
#define PMIC_AUXADC_ADC_RDY_FGADC_SWCHR_MASK             0x1
#define PMIC_AUXADC_ADC_RDY_FGADC_SWCHR_SHIFT            15
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_ADDR         MT6355_AUXADC_ADC31
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_MASK         0x7FFF
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_SHIFT        0
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_ADDR         MT6355_AUXADC_ADC31
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_MASK         0x1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_SHIFT        15
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_SWCHR_ADDR        MT6355_AUXADC_ADC32
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_SWCHR_MASK        0x7FFF
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_SWCHR_SHIFT       0
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_SWCHR_ADDR        MT6355_AUXADC_ADC32
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_SWCHR_MASK        0x1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_SWCHR_SHIFT       15
#define PMIC_AUXADC_ADC_OUT_IMP_ADDR                     MT6355_AUXADC_ADC33
#define PMIC_AUXADC_ADC_OUT_IMP_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_IMP_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_IMP_ADDR                     MT6355_AUXADC_ADC33
#define PMIC_AUXADC_ADC_RDY_IMP_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_IMP_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_IMP_AVG_ADDR                 MT6355_AUXADC_ADC34
#define PMIC_AUXADC_ADC_OUT_IMP_AVG_MASK                 0x7FFF
#define PMIC_AUXADC_ADC_OUT_IMP_AVG_SHIFT                0
#define PMIC_AUXADC_ADC_RDY_IMP_AVG_ADDR                 MT6355_AUXADC_ADC34
#define PMIC_AUXADC_ADC_RDY_IMP_AVG_MASK                 0x1
#define PMIC_AUXADC_ADC_RDY_IMP_AVG_SHIFT                15
#define PMIC_AUXADC_ADC_OUT_RAW_ADDR                     MT6355_AUXADC_ADC35
#define PMIC_AUXADC_ADC_OUT_RAW_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_RAW_SHIFT                    0
#define PMIC_AUXADC_ADC_OUT_MDRT_ADDR                    MT6355_AUXADC_ADC36
#define PMIC_AUXADC_ADC_OUT_MDRT_MASK                    0x7FFF
#define PMIC_AUXADC_ADC_OUT_MDRT_SHIFT                   0
#define PMIC_AUXADC_ADC_RDY_MDRT_ADDR                    MT6355_AUXADC_ADC36
#define PMIC_AUXADC_ADC_RDY_MDRT_MASK                    0x1
#define PMIC_AUXADC_ADC_RDY_MDRT_SHIFT                   15
#define PMIC_AUXADC_ADC_OUT_MDBG_ADDR                    MT6355_AUXADC_ADC37
#define PMIC_AUXADC_ADC_OUT_MDBG_MASK                    0x7FFF
#define PMIC_AUXADC_ADC_OUT_MDBG_SHIFT                   0
#define PMIC_AUXADC_ADC_RDY_MDBG_ADDR                    MT6355_AUXADC_ADC37
#define PMIC_AUXADC_ADC_RDY_MDBG_MASK                    0x1
#define PMIC_AUXADC_ADC_RDY_MDBG_SHIFT                   15
#define PMIC_AUXADC_ADC_OUT_JEITA_ADDR                   MT6355_AUXADC_ADC38
#define PMIC_AUXADC_ADC_OUT_JEITA_MASK                   0xFFF
#define PMIC_AUXADC_ADC_OUT_JEITA_SHIFT                  0
#define PMIC_AUXADC_ADC_RDY_JEITA_ADDR                   MT6355_AUXADC_ADC38
#define PMIC_AUXADC_ADC_RDY_JEITA_MASK                   0x1
#define PMIC_AUXADC_ADC_RDY_JEITA_SHIFT                  15
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_ADDR             MT6355_AUXADC_ADC39
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_MASK             0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_SHIFT            0
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_ADDR             MT6355_AUXADC_ADC39
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_MASK             0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_SHIFT            15
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_ADDR              MT6355_AUXADC_ADC40
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_MASK              0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_SHIFT             0
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_ADDR              MT6355_AUXADC_ADC40
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_MASK              0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_SHIFT             15
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_ADDR              MT6355_AUXADC_ADC41
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_MASK              0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_SHIFT             0
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_ADDR              MT6355_AUXADC_ADC41
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_MASK              0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_SHIFT             15
#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_ADDR               MT6355_AUXADC_ADC42
#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MASK               0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_SHIFT              0
#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR               MT6355_AUXADC_ADC42
#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_SHIFT              15
#define PMIC_AUXADC_ADC_OUT_NAG_ADDR                     MT6355_AUXADC_ADC43
#define PMIC_AUXADC_ADC_OUT_NAG_MASK                     0x7FFF
#define PMIC_AUXADC_ADC_OUT_NAG_SHIFT                    0
#define PMIC_AUXADC_ADC_RDY_NAG_ADDR                     MT6355_AUXADC_ADC43
#define PMIC_AUXADC_ADC_RDY_NAG_MASK                     0x1
#define PMIC_AUXADC_ADC_RDY_NAG_SHIFT                    15
#define PMIC_AUXADC_ADC_OUT_BATID_ADDR                   MT6355_AUXADC_ADC44
#define PMIC_AUXADC_ADC_OUT_BATID_MASK                   0xFFF
#define PMIC_AUXADC_ADC_OUT_BATID_SHIFT                  0
#define PMIC_AUXADC_ADC_RDY_BATID_ADDR                   MT6355_AUXADC_ADC44
#define PMIC_AUXADC_ADC_RDY_BATID_MASK                   0x1
#define PMIC_AUXADC_ADC_RDY_BATID_SHIFT                  15
#define PMIC_AUXADC_BUF_OUT_00_ADDR                      MT6355_AUXADC_BUF0
#define PMIC_AUXADC_BUF_OUT_00_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_00_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_00_ADDR                      MT6355_AUXADC_BUF0
#define PMIC_AUXADC_BUF_RDY_00_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_00_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_01_ADDR                      MT6355_AUXADC_BUF1
#define PMIC_AUXADC_BUF_OUT_01_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_01_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_01_ADDR                      MT6355_AUXADC_BUF1
#define PMIC_AUXADC_BUF_RDY_01_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_01_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_02_ADDR                      MT6355_AUXADC_BUF2
#define PMIC_AUXADC_BUF_OUT_02_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_02_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_02_ADDR                      MT6355_AUXADC_BUF2
#define PMIC_AUXADC_BUF_RDY_02_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_02_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_03_ADDR                      MT6355_AUXADC_BUF3
#define PMIC_AUXADC_BUF_OUT_03_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_03_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_03_ADDR                      MT6355_AUXADC_BUF3
#define PMIC_AUXADC_BUF_RDY_03_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_03_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_04_ADDR                      MT6355_AUXADC_BUF4
#define PMIC_AUXADC_BUF_OUT_04_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_04_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_04_ADDR                      MT6355_AUXADC_BUF4
#define PMIC_AUXADC_BUF_RDY_04_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_04_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_05_ADDR                      MT6355_AUXADC_BUF5
#define PMIC_AUXADC_BUF_OUT_05_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_05_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_05_ADDR                      MT6355_AUXADC_BUF5
#define PMIC_AUXADC_BUF_RDY_05_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_05_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_06_ADDR                      MT6355_AUXADC_BUF6
#define PMIC_AUXADC_BUF_OUT_06_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_06_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_06_ADDR                      MT6355_AUXADC_BUF6
#define PMIC_AUXADC_BUF_RDY_06_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_06_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_07_ADDR                      MT6355_AUXADC_BUF7
#define PMIC_AUXADC_BUF_OUT_07_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_07_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_07_ADDR                      MT6355_AUXADC_BUF7
#define PMIC_AUXADC_BUF_RDY_07_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_07_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_08_ADDR                      MT6355_AUXADC_BUF8
#define PMIC_AUXADC_BUF_OUT_08_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_08_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_08_ADDR                      MT6355_AUXADC_BUF8
#define PMIC_AUXADC_BUF_RDY_08_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_08_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_09_ADDR                      MT6355_AUXADC_BUF9
#define PMIC_AUXADC_BUF_OUT_09_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_09_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_09_ADDR                      MT6355_AUXADC_BUF9
#define PMIC_AUXADC_BUF_RDY_09_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_09_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_10_ADDR                      MT6355_AUXADC_BUF10
#define PMIC_AUXADC_BUF_OUT_10_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_10_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_10_ADDR                      MT6355_AUXADC_BUF10
#define PMIC_AUXADC_BUF_RDY_10_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_10_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_11_ADDR                      MT6355_AUXADC_BUF11
#define PMIC_AUXADC_BUF_OUT_11_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_11_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_11_ADDR                      MT6355_AUXADC_BUF11
#define PMIC_AUXADC_BUF_RDY_11_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_11_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_12_ADDR                      MT6355_AUXADC_BUF12
#define PMIC_AUXADC_BUF_OUT_12_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_12_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_12_ADDR                      MT6355_AUXADC_BUF12
#define PMIC_AUXADC_BUF_RDY_12_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_12_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_13_ADDR                      MT6355_AUXADC_BUF13
#define PMIC_AUXADC_BUF_OUT_13_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_13_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_13_ADDR                      MT6355_AUXADC_BUF13
#define PMIC_AUXADC_BUF_RDY_13_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_13_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_14_ADDR                      MT6355_AUXADC_BUF14
#define PMIC_AUXADC_BUF_OUT_14_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_14_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_14_ADDR                      MT6355_AUXADC_BUF14
#define PMIC_AUXADC_BUF_RDY_14_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_14_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_15_ADDR                      MT6355_AUXADC_BUF15
#define PMIC_AUXADC_BUF_OUT_15_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_15_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_15_ADDR                      MT6355_AUXADC_BUF15
#define PMIC_AUXADC_BUF_RDY_15_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_15_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_16_ADDR                      MT6355_AUXADC_BUF16
#define PMIC_AUXADC_BUF_OUT_16_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_16_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_16_ADDR                      MT6355_AUXADC_BUF16
#define PMIC_AUXADC_BUF_RDY_16_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_16_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_17_ADDR                      MT6355_AUXADC_BUF17
#define PMIC_AUXADC_BUF_OUT_17_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_17_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_17_ADDR                      MT6355_AUXADC_BUF17
#define PMIC_AUXADC_BUF_RDY_17_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_17_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_18_ADDR                      MT6355_AUXADC_BUF18
#define PMIC_AUXADC_BUF_OUT_18_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_18_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_18_ADDR                      MT6355_AUXADC_BUF18
#define PMIC_AUXADC_BUF_RDY_18_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_18_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_19_ADDR                      MT6355_AUXADC_BUF19
#define PMIC_AUXADC_BUF_OUT_19_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_19_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_19_ADDR                      MT6355_AUXADC_BUF19
#define PMIC_AUXADC_BUF_RDY_19_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_19_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_20_ADDR                      MT6355_AUXADC_BUF20
#define PMIC_AUXADC_BUF_OUT_20_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_20_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_20_ADDR                      MT6355_AUXADC_BUF20
#define PMIC_AUXADC_BUF_RDY_20_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_20_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_21_ADDR                      MT6355_AUXADC_BUF21
#define PMIC_AUXADC_BUF_OUT_21_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_21_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_21_ADDR                      MT6355_AUXADC_BUF21
#define PMIC_AUXADC_BUF_RDY_21_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_21_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_22_ADDR                      MT6355_AUXADC_BUF22
#define PMIC_AUXADC_BUF_OUT_22_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_22_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_22_ADDR                      MT6355_AUXADC_BUF22
#define PMIC_AUXADC_BUF_RDY_22_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_22_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_23_ADDR                      MT6355_AUXADC_BUF23
#define PMIC_AUXADC_BUF_OUT_23_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_23_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_23_ADDR                      MT6355_AUXADC_BUF23
#define PMIC_AUXADC_BUF_RDY_23_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_23_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_24_ADDR                      MT6355_AUXADC_BUF24
#define PMIC_AUXADC_BUF_OUT_24_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_24_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_24_ADDR                      MT6355_AUXADC_BUF24
#define PMIC_AUXADC_BUF_RDY_24_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_24_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_25_ADDR                      MT6355_AUXADC_BUF25
#define PMIC_AUXADC_BUF_OUT_25_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_25_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_25_ADDR                      MT6355_AUXADC_BUF25
#define PMIC_AUXADC_BUF_RDY_25_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_25_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_26_ADDR                      MT6355_AUXADC_BUF26
#define PMIC_AUXADC_BUF_OUT_26_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_26_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_26_ADDR                      MT6355_AUXADC_BUF26
#define PMIC_AUXADC_BUF_RDY_26_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_26_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_27_ADDR                      MT6355_AUXADC_BUF27
#define PMIC_AUXADC_BUF_OUT_27_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_27_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_27_ADDR                      MT6355_AUXADC_BUF27
#define PMIC_AUXADC_BUF_RDY_27_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_27_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_28_ADDR                      MT6355_AUXADC_BUF28
#define PMIC_AUXADC_BUF_OUT_28_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_28_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_28_ADDR                      MT6355_AUXADC_BUF28
#define PMIC_AUXADC_BUF_RDY_28_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_28_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_29_ADDR                      MT6355_AUXADC_BUF29
#define PMIC_AUXADC_BUF_OUT_29_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_29_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_29_ADDR                      MT6355_AUXADC_BUF29
#define PMIC_AUXADC_BUF_RDY_29_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_29_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_30_ADDR                      MT6355_AUXADC_BUF30
#define PMIC_AUXADC_BUF_OUT_30_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_30_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_30_ADDR                      MT6355_AUXADC_BUF30
#define PMIC_AUXADC_BUF_RDY_30_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_30_SHIFT                     15
#define PMIC_AUXADC_BUF_OUT_31_ADDR                      MT6355_AUXADC_BUF31
#define PMIC_AUXADC_BUF_OUT_31_MASK                      0x7FFF
#define PMIC_AUXADC_BUF_OUT_31_SHIFT                     0
#define PMIC_AUXADC_BUF_RDY_31_ADDR                      MT6355_AUXADC_BUF31
#define PMIC_AUXADC_BUF_RDY_31_MASK                      0x1
#define PMIC_AUXADC_BUF_RDY_31_SHIFT                     15
#define PMIC_AUXADC_ADC_BUSY_IN_ADDR                     MT6355_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_MASK                     0xFFF
#define PMIC_AUXADC_ADC_BUSY_IN_SHIFT                    0
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_ADDR                MT6355_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_MASK                0x1
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_SHIFT               12
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_ADDR               MT6355_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_MASK               0x1
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT              13
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_ADDR            MT6355_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_MASK            0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_SHIFT           14
#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_ADDR              MT6355_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_MASK              0x1
#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_SHIFT             15
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_ADDR           MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_MASK           0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_SHIFT          0
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_ADDR         MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_MASK         0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_SHIFT        1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_ADDR         MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_MASK         0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_SHIFT        2
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_ADDR            MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MASK            0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_SHIFT           3
#define PMIC_AUXADC_ADC_BUSY_IN_JEITA_ADDR               MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_JEITA_MASK               0x1
#define PMIC_AUXADC_ADC_BUSY_IN_JEITA_SHIFT              4
#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_ADDR                MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_MASK                0x1
#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_SHIFT               5
#define PMIC_AUXADC_ADC_BUSY_IN_MDBG_ADDR                MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_MDBG_MASK                0x1
#define PMIC_AUXADC_ADC_BUSY_IN_MDBG_SHIFT               6
#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_ADDR               MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_MASK               0x1
#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_SHIFT              7
#define PMIC_AUXADC_ADC_BUSY_IN_IMP_ADDR                 MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_IMP_MASK                 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_IMP_SHIFT                8
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_ADDR          MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_MASK          0x1
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_SHIFT         9
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_SWCHR_ADDR         MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_SWCHR_MASK         0x1
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_SWCHR_SHIFT        10
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_ADDR              MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_MASK              0x1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_SHIFT             11
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_ADDR              MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_MASK              0x1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_SHIFT             12
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_ADDR                 MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MASK                 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_SHIFT                13
#define PMIC_AUXADC_ADC_BUSY_IN_THR_HW_ADDR              MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_THR_HW_MASK              0x1
#define PMIC_AUXADC_ADC_BUSY_IN_THR_HW_SHIFT             14
#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_ADDR              MT6355_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_MASK              0x1
#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_SHIFT             15
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_ADDR     MT6355_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_MASK     0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_SHIFT    0
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_SWCHR_ADDR    MT6355_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_SWCHR_MASK    0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_SWCHR_SHIFT   1
#define PMIC_AUXADC_ADC_BUSY_IN_BATID_ADDR               MT6355_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_BATID_MASK               0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BATID_SHIFT              2
#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_ADDR               MT6355_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_MASK               0x1
#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_SHIFT              3
#define PMIC_AUXADC_ADC_BUSY_IN_NAG_ADDR                 MT6355_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_NAG_MASK                 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_NAG_SHIFT                15
#define PMIC_AUXADC_RQST_CH0_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH0_MASK                        0x1
#define PMIC_AUXADC_RQST_CH0_SHIFT                       0
#define PMIC_AUXADC_RQST_CH1_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH1_MASK                        0x1
#define PMIC_AUXADC_RQST_CH1_SHIFT                       1
#define PMIC_AUXADC_RQST_CH2_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH2_MASK                        0x1
#define PMIC_AUXADC_RQST_CH2_SHIFT                       2
#define PMIC_AUXADC_RQST_CH3_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH3_MASK                        0x1
#define PMIC_AUXADC_RQST_CH3_SHIFT                       3
#define PMIC_AUXADC_RQST_CH4_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH4_MASK                        0x1
#define PMIC_AUXADC_RQST_CH4_SHIFT                       4
#define PMIC_AUXADC_RQST_CH5_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH5_MASK                        0x1
#define PMIC_AUXADC_RQST_CH5_SHIFT                       5
#define PMIC_AUXADC_RQST_CH6_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH6_MASK                        0x1
#define PMIC_AUXADC_RQST_CH6_SHIFT                       6
#define PMIC_AUXADC_RQST_CH7_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH7_MASK                        0x1
#define PMIC_AUXADC_RQST_CH7_SHIFT                       7
#define PMIC_AUXADC_RQST_CH8_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH8_MASK                        0x1
#define PMIC_AUXADC_RQST_CH8_SHIFT                       8
#define PMIC_AUXADC_RQST_CH9_ADDR                        MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH9_MASK                        0x1
#define PMIC_AUXADC_RQST_CH9_SHIFT                       9
#define PMIC_AUXADC_RQST_CH10_ADDR                       MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH10_MASK                       0x1
#define PMIC_AUXADC_RQST_CH10_SHIFT                      10
#define PMIC_AUXADC_RQST_CH11_ADDR                       MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH11_MASK                       0x1
#define PMIC_AUXADC_RQST_CH11_SHIFT                      11
#define PMIC_AUXADC_RQST_CH12_ADDR                       MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH12_MASK                       0x1
#define PMIC_AUXADC_RQST_CH12_SHIFT                      12
#define PMIC_AUXADC_RQST_CH13_ADDR                       MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH13_MASK                       0x1
#define PMIC_AUXADC_RQST_CH13_SHIFT                      13
#define PMIC_AUXADC_RQST_CH14_ADDR                       MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH14_MASK                       0x1
#define PMIC_AUXADC_RQST_CH14_SHIFT                      14
#define PMIC_AUXADC_RQST_CH15_ADDR                       MT6355_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH15_MASK                       0x1
#define PMIC_AUXADC_RQST_CH15_SHIFT                      15
#define PMIC_AUXADC_RQST0_SET_ADDR                       MT6355_AUXADC_RQST0_SET
#define PMIC_AUXADC_RQST0_SET_MASK                       0xFFFF
#define PMIC_AUXADC_RQST0_SET_SHIFT                      0
#define PMIC_AUXADC_RQST0_CLR_ADDR                       MT6355_AUXADC_RQST0_CLR
#define PMIC_AUXADC_RQST0_CLR_MASK                       0xFFFF
#define PMIC_AUXADC_RQST0_CLR_SHIFT                      0
#define PMIC_AUXADC_RQST_CH0_BY_MD_ADDR                  MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH0_BY_MD_MASK                  0x1
#define PMIC_AUXADC_RQST_CH0_BY_MD_SHIFT                 0
#define PMIC_AUXADC_RQST_CH1_BY_MD_ADDR                  MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH1_BY_MD_MASK                  0x1
#define PMIC_AUXADC_RQST_CH1_BY_MD_SHIFT                 1
#define PMIC_AUXADC_RQST_RSV0_ADDR                       MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_RSV0_MASK                       0x1
#define PMIC_AUXADC_RQST_RSV0_SHIFT                      2
#define PMIC_AUXADC_RQST_BATID_ADDR                      MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_BATID_MASK                      0x1
#define PMIC_AUXADC_RQST_BATID_SHIFT                     3
#define PMIC_AUXADC_RQST_CH4_BY_MD_ADDR                  MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH4_BY_MD_MASK                  0x1
#define PMIC_AUXADC_RQST_CH4_BY_MD_SHIFT                 4
#define PMIC_AUXADC_RQST_CH7_BY_MD_ADDR                  MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH7_BY_MD_MASK                  0x1
#define PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT                 7
#define PMIC_AUXADC_RQST_CH7_BY_GPS_ADDR                 MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH7_BY_GPS_MASK                 0x1
#define PMIC_AUXADC_RQST_CH7_BY_GPS_SHIFT                8
#define PMIC_AUXADC_RQST_DCXO_BY_MD_ADDR                 MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_DCXO_BY_MD_MASK                 0x1
#define PMIC_AUXADC_RQST_DCXO_BY_MD_SHIFT                9
#define PMIC_AUXADC_RQST_DCXO_BY_GPS_ADDR                MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_DCXO_BY_GPS_MASK                0x1
#define PMIC_AUXADC_RQST_DCXO_BY_GPS_SHIFT               10
#define PMIC_AUXADC_RQST_RSV1_ADDR                       MT6355_AUXADC_RQST1
#define PMIC_AUXADC_RQST_RSV1_MASK                       0x1F
#define PMIC_AUXADC_RQST_RSV1_SHIFT                      11
#define PMIC_AUXADC_RQST1_SET_ADDR                       MT6355_AUXADC_RQST1_SET
#define PMIC_AUXADC_RQST1_SET_MASK                       0xFFFF
#define PMIC_AUXADC_RQST1_SET_SHIFT                      0
#define PMIC_AUXADC_RQST1_CLR_ADDR                       MT6355_AUXADC_RQST1_CLR
#define PMIC_AUXADC_RQST1_CLR_MASK                       0xFFFF
#define PMIC_AUXADC_RQST1_CLR_SHIFT                      0
#define PMIC_AUXADC_CK_ON_EXTD_ADDR                      MT6355_AUXADC_CON0
#define PMIC_AUXADC_CK_ON_EXTD_MASK                      0x3F
#define PMIC_AUXADC_CK_ON_EXTD_SHIFT                     0
#define PMIC_AUXADC_SRCLKEN_SRC_SEL_ADDR                 MT6355_AUXADC_CON0
#define PMIC_AUXADC_SRCLKEN_SRC_SEL_MASK                 0x3
#define PMIC_AUXADC_SRCLKEN_SRC_SEL_SHIFT                6
#define PMIC_AUXADC_ADC_PWDB_ADDR                        MT6355_AUXADC_CON0
#define PMIC_AUXADC_ADC_PWDB_MASK                        0x1
#define PMIC_AUXADC_ADC_PWDB_SHIFT                       8
#define PMIC_AUXADC_ADC_PWDB_SWCTRL_ADDR                 MT6355_AUXADC_CON0
#define PMIC_AUXADC_ADC_PWDB_SWCTRL_MASK                 0x1
#define PMIC_AUXADC_ADC_PWDB_SWCTRL_SHIFT                9
#define PMIC_AUXADC_STRUP_CK_ON_ENB_ADDR                 MT6355_AUXADC_CON0
#define PMIC_AUXADC_STRUP_CK_ON_ENB_MASK                 0x1
#define PMIC_AUXADC_STRUP_CK_ON_ENB_SHIFT                10
#define PMIC_AUXADC_SRCLKEN_CK_EN_ADDR                   MT6355_AUXADC_CON0
#define PMIC_AUXADC_SRCLKEN_CK_EN_MASK                   0x1
#define PMIC_AUXADC_SRCLKEN_CK_EN_SHIFT                  12
#define PMIC_AUXADC_CK_AON_GPS_ADDR                      MT6355_AUXADC_CON0
#define PMIC_AUXADC_CK_AON_GPS_MASK                      0x1
#define PMIC_AUXADC_CK_AON_GPS_SHIFT                     13
#define PMIC_AUXADC_CK_AON_MD_ADDR                       MT6355_AUXADC_CON0
#define PMIC_AUXADC_CK_AON_MD_MASK                       0x1
#define PMIC_AUXADC_CK_AON_MD_SHIFT                      14
#define PMIC_AUXADC_CK_AON_ADDR                          MT6355_AUXADC_CON0
#define PMIC_AUXADC_CK_AON_MASK                          0x1
#define PMIC_AUXADC_CK_AON_SHIFT                         15
#define PMIC_AUXADC_CON0_SET_ADDR                        MT6355_AUXADC_CON0_SET
#define PMIC_AUXADC_CON0_SET_MASK                        0xFFFF
#define PMIC_AUXADC_CON0_SET_SHIFT                       0
#define PMIC_AUXADC_CON0_CLR_ADDR                        MT6355_AUXADC_CON0_CLR
#define PMIC_AUXADC_CON0_CLR_MASK                        0xFFFF
#define PMIC_AUXADC_CON0_CLR_SHIFT                       0
#define PMIC_AUXADC_AVG_NUM_SMALL_ADDR                   MT6355_AUXADC_CON1
#define PMIC_AUXADC_AVG_NUM_SMALL_MASK                   0x7
#define PMIC_AUXADC_AVG_NUM_SMALL_SHIFT                  0
#define PMIC_AUXADC_AVG_NUM_LARGE_ADDR                   MT6355_AUXADC_CON1
#define PMIC_AUXADC_AVG_NUM_LARGE_MASK                   0x7
#define PMIC_AUXADC_AVG_NUM_LARGE_SHIFT                  3
#define PMIC_AUXADC_SPL_NUM_ADDR                         MT6355_AUXADC_CON1
#define PMIC_AUXADC_SPL_NUM_MASK                         0x3FF
#define PMIC_AUXADC_SPL_NUM_SHIFT                        6
#define PMIC_AUXADC_AVG_NUM_SEL_ADDR                     MT6355_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_MASK                     0xFFF
#define PMIC_AUXADC_AVG_NUM_SEL_SHIFT                    0
#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_ADDR               MT6355_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_MASK               0x1
#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_SHIFT              12
#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_ADDR                MT6355_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_MASK                0x1
#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_SHIFT               13
#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_ADDR            MT6355_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_MASK            0x1
#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_SHIFT           14
#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_ADDR              MT6355_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_MASK              0x1
#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_SHIFT             15
#define PMIC_AUXADC_SPL_NUM_LARGE_ADDR                   MT6355_AUXADC_CON3
#define PMIC_AUXADC_SPL_NUM_LARGE_MASK                   0x3FF
#define PMIC_AUXADC_SPL_NUM_LARGE_SHIFT                  0
#define PMIC_AUXADC_SPL_NUM_SLEEP_ADDR                   MT6355_AUXADC_CON4
#define PMIC_AUXADC_SPL_NUM_SLEEP_MASK                   0x3FF
#define PMIC_AUXADC_SPL_NUM_SLEEP_SHIFT                  0
#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_ADDR               MT6355_AUXADC_CON4
#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_MASK               0x1
#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_SHIFT              15
#define PMIC_AUXADC_SPL_NUM_SEL_ADDR                     MT6355_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_MASK                     0xFFF
#define PMIC_AUXADC_SPL_NUM_SEL_SHIFT                    0
#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_ADDR               MT6355_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_MASK               0x1
#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_SHIFT              12
#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_ADDR                MT6355_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_MASK                0x1
#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_SHIFT               13
#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_ADDR            MT6355_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_MASK            0x1
#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_SHIFT           14
#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_ADDR              MT6355_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_MASK              0x1
#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_SHIFT             15
#define PMIC_AUXADC_SPL_NUM_CH0_ADDR                     MT6355_AUXADC_CON6
#define PMIC_AUXADC_SPL_NUM_CH0_MASK                     0x3FF
#define PMIC_AUXADC_SPL_NUM_CH0_SHIFT                    0
#define PMIC_AUXADC_SPL_NUM_CH3_ADDR                     MT6355_AUXADC_CON7
#define PMIC_AUXADC_SPL_NUM_CH3_MASK                     0x3FF
#define PMIC_AUXADC_SPL_NUM_CH3_SHIFT                    0
#define PMIC_AUXADC_SPL_NUM_CH7_ADDR                     MT6355_AUXADC_CON8
#define PMIC_AUXADC_SPL_NUM_CH7_MASK                     0x3FF
#define PMIC_AUXADC_SPL_NUM_CH7_SHIFT                    0
#define PMIC_AUXADC_AVG_NUM_LBAT_ADDR                    MT6355_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_LBAT_MASK                    0x7
#define PMIC_AUXADC_AVG_NUM_LBAT_SHIFT                   0
#define PMIC_AUXADC_AVG_NUM_CH7_ADDR                     MT6355_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_CH7_MASK                     0x7
#define PMIC_AUXADC_AVG_NUM_CH7_SHIFT                    4
#define PMIC_AUXADC_AVG_NUM_CH3_ADDR                     MT6355_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_CH3_MASK                     0x7
#define PMIC_AUXADC_AVG_NUM_CH3_SHIFT                    8
#define PMIC_AUXADC_AVG_NUM_CH0_ADDR                     MT6355_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_CH0_MASK                     0x7
#define PMIC_AUXADC_AVG_NUM_CH0_SHIFT                    12
#define PMIC_AUXADC_AVG_NUM_HPC_ADDR                     MT6355_AUXADC_CON10
#define PMIC_AUXADC_AVG_NUM_HPC_MASK                     0x7
#define PMIC_AUXADC_AVG_NUM_HPC_SHIFT                    0
#define PMIC_AUXADC_AVG_NUM_DCXO_ADDR                    MT6355_AUXADC_CON10
#define PMIC_AUXADC_AVG_NUM_DCXO_MASK                    0x7
#define PMIC_AUXADC_AVG_NUM_DCXO_SHIFT                   4
#define PMIC_AUXADC_TRIM_CH0_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH0_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH0_SEL_SHIFT                   0
#define PMIC_AUXADC_TRIM_CH1_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH1_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH1_SEL_SHIFT                   2
#define PMIC_AUXADC_TRIM_CH2_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH2_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH2_SEL_SHIFT                   4
#define PMIC_AUXADC_TRIM_CH3_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH3_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH3_SEL_SHIFT                   6
#define PMIC_AUXADC_TRIM_CH4_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH4_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH4_SEL_SHIFT                   8
#define PMIC_AUXADC_TRIM_CH5_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH5_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH5_SEL_SHIFT                   10
#define PMIC_AUXADC_TRIM_CH6_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH6_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH6_SEL_SHIFT                   12
#define PMIC_AUXADC_TRIM_CH7_SEL_ADDR                    MT6355_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH7_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH7_SEL_SHIFT                   14
#define PMIC_AUXADC_TRIM_CH8_SEL_ADDR                    MT6355_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH8_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH8_SEL_SHIFT                   0
#define PMIC_AUXADC_TRIM_CH9_SEL_ADDR                    MT6355_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH9_SEL_MASK                    0x3
#define PMIC_AUXADC_TRIM_CH9_SEL_SHIFT                   2
#define PMIC_AUXADC_TRIM_CH10_SEL_ADDR                   MT6355_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH10_SEL_MASK                   0x3
#define PMIC_AUXADC_TRIM_CH10_SEL_SHIFT                  4
#define PMIC_AUXADC_TRIM_CH11_SEL_ADDR                   MT6355_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH11_SEL_MASK                   0x3
#define PMIC_AUXADC_TRIM_CH11_SEL_SHIFT                  6
#define PMIC_AUXADC_ADC_2S_COMP_ENB_ADDR                 MT6355_AUXADC_CON12
#define PMIC_AUXADC_ADC_2S_COMP_ENB_MASK                 0x1
#define PMIC_AUXADC_ADC_2S_COMP_ENB_SHIFT                14
#define PMIC_AUXADC_ADC_TRIM_COMP_ADDR                   MT6355_AUXADC_CON12
#define PMIC_AUXADC_ADC_TRIM_COMP_MASK                   0x1
#define PMIC_AUXADC_ADC_TRIM_COMP_SHIFT                  15
#define PMIC_AUXADC_SW_GAIN_TRIM_ADDR                    MT6355_AUXADC_CON13
#define PMIC_AUXADC_SW_GAIN_TRIM_MASK                    0x7FFF
#define PMIC_AUXADC_SW_GAIN_TRIM_SHIFT                   0
#define PMIC_AUXADC_SW_OFFSET_TRIM_ADDR                  MT6355_AUXADC_CON14
#define PMIC_AUXADC_SW_OFFSET_TRIM_MASK                  0x7FFF
#define PMIC_AUXADC_SW_OFFSET_TRIM_SHIFT                 0
#define PMIC_AUXADC_RNG_EN_ADDR                          MT6355_AUXADC_CON15
#define PMIC_AUXADC_RNG_EN_MASK                          0x1
#define PMIC_AUXADC_RNG_EN_SHIFT                         0
#define PMIC_AUXADC_TEST_MODE_ADDR                       MT6355_AUXADC_CON15
#define PMIC_AUXADC_TEST_MODE_MASK                       0x1
#define PMIC_AUXADC_TEST_MODE_SHIFT                      3
#define PMIC_AUXADC_BIT_SEL_ADDR                         MT6355_AUXADC_CON15
#define PMIC_AUXADC_BIT_SEL_MASK                         0x1
#define PMIC_AUXADC_BIT_SEL_SHIFT                        4
#define PMIC_AUXADC_START_SW_ADDR                        MT6355_AUXADC_CON15
#define PMIC_AUXADC_START_SW_MASK                        0x1
#define PMIC_AUXADC_START_SW_SHIFT                       5
#define PMIC_AUXADC_START_SWCTRL_ADDR                    MT6355_AUXADC_CON15
#define PMIC_AUXADC_START_SWCTRL_MASK                    0x1
#define PMIC_AUXADC_START_SWCTRL_SHIFT                   6
#define PMIC_AUXADC_TS_VBE_SEL_ADDR                      MT6355_AUXADC_CON15
#define PMIC_AUXADC_TS_VBE_SEL_MASK                      0x1
#define PMIC_AUXADC_TS_VBE_SEL_SHIFT                     7
#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_ADDR               MT6355_AUXADC_CON15
#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_MASK               0x1
#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_SHIFT              8
#define PMIC_AUXADC_VBUF_EN_ADDR                         MT6355_AUXADC_CON15
#define PMIC_AUXADC_VBUF_EN_MASK                         0x1
#define PMIC_AUXADC_VBUF_EN_SHIFT                        9
#define PMIC_AUXADC_VBUF_EN_SWCTRL_ADDR                  MT6355_AUXADC_CON15
#define PMIC_AUXADC_VBUF_EN_SWCTRL_MASK                  0x1
#define PMIC_AUXADC_VBUF_EN_SWCTRL_SHIFT                 10
#define PMIC_AUXADC_OUT_SEL_ADDR                         MT6355_AUXADC_CON15
#define PMIC_AUXADC_OUT_SEL_MASK                         0x1
#define PMIC_AUXADC_OUT_SEL_SHIFT                        11
#define PMIC_AUXADC_DA_DAC_ADDR                          MT6355_AUXADC_CON16
#define PMIC_AUXADC_DA_DAC_MASK                          0xFFF
#define PMIC_AUXADC_DA_DAC_SHIFT                         0
#define PMIC_AUXADC_DA_DAC_SWCTRL_ADDR                   MT6355_AUXADC_CON16
#define PMIC_AUXADC_DA_DAC_SWCTRL_MASK                   0x1
#define PMIC_AUXADC_DA_DAC_SWCTRL_SHIFT                  12
#define PMIC_AD_AUXADC_COMP_ADDR                         MT6355_AUXADC_CON16
#define PMIC_AD_AUXADC_COMP_MASK                         0x1
#define PMIC_AD_AUXADC_COMP_SHIFT                        15
#define PMIC_RG_AUXADC_CALI_ADDR                         MT6355_AUXADC_CON17
#define PMIC_RG_AUXADC_CALI_MASK                         0xF
#define PMIC_RG_AUXADC_CALI_SHIFT                        0
#define PMIC_RG_AUX_RSV_ADDR                             MT6355_AUXADC_CON17
#define PMIC_RG_AUX_RSV_MASK                             0xF
#define PMIC_RG_AUX_RSV_SHIFT                            4
#define PMIC_RG_VBUF_BYP_ADDR                            MT6355_AUXADC_CON17
#define PMIC_RG_VBUF_BYP_MASK                            0x1
#define PMIC_RG_VBUF_BYP_SHIFT                           8
#define PMIC_RG_VBUF_CALEN_ADDR                          MT6355_AUXADC_CON17
#define PMIC_RG_VBUF_CALEN_MASK                          0x1
#define PMIC_RG_VBUF_CALEN_SHIFT                         9
#define PMIC_RG_VBUF_EXTEN_ADDR                          MT6355_AUXADC_CON17
#define PMIC_RG_VBUF_EXTEN_MASK                          0x1
#define PMIC_RG_VBUF_EXTEN_SHIFT                         10
#define PMIC_AUXADC_ADCIN_VSEN_EN_ADDR                   MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_VSEN_EN_MASK                   0x1
#define PMIC_AUXADC_ADCIN_VSEN_EN_SHIFT                  0
#define PMIC_AUXADC_ADCIN_VBAT_EN_ADDR                   MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_VBAT_EN_MASK                   0x1
#define PMIC_AUXADC_ADCIN_VBAT_EN_SHIFT                  1
#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_ADDR               MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_MASK               0x1
#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT              2
#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_ADDR         MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_MASK         0x1
#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_SHIFT        3
#define PMIC_AUXADC_ADCIN_CHR_EN_ADDR                    MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_CHR_EN_MASK                    0x1
#define PMIC_AUXADC_ADCIN_CHR_EN_SHIFT                   4
#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_ADDR             MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_MASK             0x1
#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_SHIFT            5
#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_ADDR             MT6355_AUXADC_CON18
#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_MASK             0x1
#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_SHIFT            6
#define PMIC_AUXADC_XO_THADC_EN_ADDR                     MT6355_AUXADC_CON18
#define PMIC_AUXADC_XO_THADC_EN_MASK                     0x1
#define PMIC_AUXADC_XO_THADC_EN_SHIFT                    7
#define PMIC_AUXADC_ADCIN_BATID_SW_EN_ADDR               MT6355_AUXADC_CON18
#define PMIC_AUXADC_ADCIN_BATID_SW_EN_MASK               0x1
#define PMIC_AUXADC_ADCIN_BATID_SW_EN_SHIFT              8
#define PMIC_AUXADC_DIG0_RSV0_ADDR                       MT6355_AUXADC_CON18
#define PMIC_AUXADC_DIG0_RSV0_MASK                       0x3
#define PMIC_AUXADC_DIG0_RSV0_SHIFT                      9
#define PMIC_AUXADC_CHSEL_ADDR                           MT6355_AUXADC_CON18
#define PMIC_AUXADC_CHSEL_MASK                           0xF
#define PMIC_AUXADC_CHSEL_SHIFT                          11
#define PMIC_AUXADC_SWCTRL_EN_ADDR                       MT6355_AUXADC_CON18
#define PMIC_AUXADC_SWCTRL_EN_MASK                       0x1
#define PMIC_AUXADC_SWCTRL_EN_SHIFT                      15
#define PMIC_AUXADC_SOURCE_LBAT_SEL_ADDR                 MT6355_AUXADC_CON19
#define PMIC_AUXADC_SOURCE_LBAT_SEL_MASK                 0x1
#define PMIC_AUXADC_SOURCE_LBAT_SEL_SHIFT                0
#define PMIC_AUXADC_SOURCE_LBAT2_SEL_ADDR                MT6355_AUXADC_CON19
#define PMIC_AUXADC_SOURCE_LBAT2_SEL_MASK                0x1
#define PMIC_AUXADC_SOURCE_LBAT2_SEL_SHIFT               1
#define PMIC_AUXADC_START_EXTD_ADDR                      MT6355_AUXADC_CON19
#define PMIC_AUXADC_START_EXTD_MASK                      0x7F
#define PMIC_AUXADC_START_EXTD_SHIFT                     2
#define PMIC_AUXADC_DAC_EXTD_ADDR                        MT6355_AUXADC_CON19
#define PMIC_AUXADC_DAC_EXTD_MASK                        0xF
#define PMIC_AUXADC_DAC_EXTD_SHIFT                       11
#define PMIC_AUXADC_DAC_EXTD_EN_ADDR                     MT6355_AUXADC_CON19
#define PMIC_AUXADC_DAC_EXTD_EN_MASK                     0x1
#define PMIC_AUXADC_DAC_EXTD_EN_SHIFT                    15
#define PMIC_AUXADC_PMU_THR_PDN_SW_ADDR                  MT6355_AUXADC_CON20
#define PMIC_AUXADC_PMU_THR_PDN_SW_MASK                  0x1
#define PMIC_AUXADC_PMU_THR_PDN_SW_SHIFT                 10
#define PMIC_AUXADC_PMU_THR_PDN_SEL_ADDR                 MT6355_AUXADC_CON20
#define PMIC_AUXADC_PMU_THR_PDN_SEL_MASK                 0x1
#define PMIC_AUXADC_PMU_THR_PDN_SEL_SHIFT                11
#define PMIC_AUXADC_PMU_THR_PDN_STATUS_ADDR              MT6355_AUXADC_CON20
#define PMIC_AUXADC_PMU_THR_PDN_STATUS_MASK              0x1
#define PMIC_AUXADC_PMU_THR_PDN_STATUS_SHIFT             12
#define PMIC_AUXADC_DIG0_RSV1_ADDR                       MT6355_AUXADC_CON20
#define PMIC_AUXADC_DIG0_RSV1_MASK                       0x7
#define PMIC_AUXADC_DIG0_RSV1_SHIFT                      13
#define PMIC_AUXADC_START_SHADE_NUM_ADDR                 MT6355_AUXADC_CON21
#define PMIC_AUXADC_START_SHADE_NUM_MASK                 0x3FF
#define PMIC_AUXADC_START_SHADE_NUM_SHIFT                0
#define PMIC_AUXADC_START_SHADE_EN_ADDR                  MT6355_AUXADC_CON21
#define PMIC_AUXADC_START_SHADE_EN_MASK                  0x1
#define PMIC_AUXADC_START_SHADE_EN_SHIFT                 14
#define PMIC_AUXADC_START_SHADE_SEL_ADDR                 MT6355_AUXADC_CON21
#define PMIC_AUXADC_START_SHADE_SEL_MASK                 0x1
#define PMIC_AUXADC_START_SHADE_SEL_SHIFT                15
#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_ADDR              MT6355_AUXADC_CON22
#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_MASK              0x1
#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT             0
#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_ADDR               MT6355_AUXADC_CON22
#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_SHIFT              1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_ADDR          MT6355_AUXADC_CON22
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_MASK          0x1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_SHIFT         2
#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_ADDR               MT6355_AUXADC_CON22
#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_MASK               0x1
#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_SHIFT              3
#define PMIC_AUXADC_DATA_REUSE_SEL_ADDR                  MT6355_AUXADC_CON23
#define PMIC_AUXADC_DATA_REUSE_SEL_MASK                  0x3
#define PMIC_AUXADC_DATA_REUSE_SEL_SHIFT                 0
#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_ADDR              MT6355_AUXADC_CON23
#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_MASK              0x3
#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_SHIFT             2
#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_ADDR              MT6355_AUXADC_CON23
#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_MASK              0x3
#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_SHIFT             4
#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_ADDR             MT6355_AUXADC_CON23
#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_MASK             0x3
#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_SHIFT            6
#define PMIC_AUXADC_DATA_REUSE_EN_ADDR                   MT6355_AUXADC_CON23
#define PMIC_AUXADC_DATA_REUSE_EN_MASK                   0x1
#define PMIC_AUXADC_DATA_REUSE_EN_SHIFT                  8
#define PMIC_AUXADC_CH0_DATA_REUSE_EN_ADDR               MT6355_AUXADC_CON23
#define PMIC_AUXADC_CH0_DATA_REUSE_EN_MASK               0x1
#define PMIC_AUXADC_CH0_DATA_REUSE_EN_SHIFT              9
#define PMIC_AUXADC_CH1_DATA_REUSE_EN_ADDR               MT6355_AUXADC_CON23
#define PMIC_AUXADC_CH1_DATA_REUSE_EN_MASK               0x1
#define PMIC_AUXADC_CH1_DATA_REUSE_EN_SHIFT              10
#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_ADDR              MT6355_AUXADC_CON23
#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_MASK              0x1
#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_SHIFT             11
#define PMIC_AUXADC_AUTORPT_PRD_ADDR                     MT6355_AUXADC_AUTORPT0
#define PMIC_AUXADC_AUTORPT_PRD_MASK                     0x3FF
#define PMIC_AUXADC_AUTORPT_PRD_SHIFT                    0
#define PMIC_AUXADC_AUTORPT_EN_ADDR                      MT6355_AUXADC_AUTORPT0
#define PMIC_AUXADC_AUTORPT_EN_MASK                      0x1
#define PMIC_AUXADC_AUTORPT_EN_SHIFT                     15
#define PMIC_AUXADC_LBAT_DEBT_MAX_ADDR                   MT6355_AUXADC_LBAT0
#define PMIC_AUXADC_LBAT_DEBT_MAX_MASK                   0xFF
#define PMIC_AUXADC_LBAT_DEBT_MAX_SHIFT                  0
#define PMIC_AUXADC_LBAT_DEBT_MIN_ADDR                   MT6355_AUXADC_LBAT0
#define PMIC_AUXADC_LBAT_DEBT_MIN_MASK                   0xFF
#define PMIC_AUXADC_LBAT_DEBT_MIN_SHIFT                  8
#define PMIC_AUXADC_LBAT_DET_PRD_15_0_ADDR               MT6355_AUXADC_LBAT1
#define PMIC_AUXADC_LBAT_DET_PRD_15_0_MASK               0xFFFF
#define PMIC_AUXADC_LBAT_DET_PRD_15_0_SHIFT              0
#define PMIC_AUXADC_LBAT_DET_PRD_19_16_ADDR              MT6355_AUXADC_LBAT2
#define PMIC_AUXADC_LBAT_DET_PRD_19_16_MASK              0xF
#define PMIC_AUXADC_LBAT_DET_PRD_19_16_SHIFT             0
#define PMIC_AUXADC_LBAT_VOLT_MAX_ADDR                   MT6355_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_VOLT_MAX_MASK                   0xFFF
#define PMIC_AUXADC_LBAT_VOLT_MAX_SHIFT                  0
#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_ADDR                 MT6355_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_MASK                 0x1
#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_SHIFT                12
#define PMIC_AUXADC_LBAT_EN_MAX_ADDR                     MT6355_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_EN_MAX_MASK                     0x1
#define PMIC_AUXADC_LBAT_EN_MAX_SHIFT                    13
#define PMIC_AUXADC_LBAT_MAX_IRQ_B_ADDR                  MT6355_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_MAX_IRQ_B_MASK                  0x1
#define PMIC_AUXADC_LBAT_MAX_IRQ_B_SHIFT                 15
#define PMIC_AUXADC_LBAT_VOLT_MIN_ADDR                   MT6355_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_VOLT_MIN_MASK                   0xFFF
#define PMIC_AUXADC_LBAT_VOLT_MIN_SHIFT                  0
#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_ADDR                 MT6355_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_MASK                 0x1
#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_SHIFT                12
#define PMIC_AUXADC_LBAT_EN_MIN_ADDR                     MT6355_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_EN_MIN_MASK                     0x1
#define PMIC_AUXADC_LBAT_EN_MIN_SHIFT                    13
#define PMIC_AUXADC_LBAT_MIN_IRQ_B_ADDR                  MT6355_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_MIN_IRQ_B_MASK                  0x1
#define PMIC_AUXADC_LBAT_MIN_IRQ_B_SHIFT                 15
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_ADDR         MT6355_AUXADC_LBAT5
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_MASK         0x1FF
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_SHIFT        0
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_ADDR         MT6355_AUXADC_LBAT6
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_MASK         0x1FF
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_SHIFT        0
#define PMIC_AUXADC_ACCDET_AUTO_SPL_ADDR                 MT6355_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_AUTO_SPL_MASK                 0x1
#define PMIC_AUXADC_ACCDET_AUTO_SPL_SHIFT                0
#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_ADDR            MT6355_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_MASK            0x1
#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT           1
#define PMIC_AUXADC_ACCDET_DIG1_RSV0_ADDR                MT6355_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_DIG1_RSV0_MASK                0x3F
#define PMIC_AUXADC_ACCDET_DIG1_RSV0_SHIFT               2
#define PMIC_AUXADC_ACCDET_DIG0_RSV0_ADDR                MT6355_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_DIG0_RSV0_MASK                0xFF
#define PMIC_AUXADC_ACCDET_DIG0_RSV0_SHIFT               8
#define PMIC_AUXADC_THR_DEBT_MAX_ADDR                    MT6355_AUXADC_THR0
#define PMIC_AUXADC_THR_DEBT_MAX_MASK                    0xFF
#define PMIC_AUXADC_THR_DEBT_MAX_SHIFT                   0
#define PMIC_AUXADC_THR_DEBT_MIN_ADDR                    MT6355_AUXADC_THR0
#define PMIC_AUXADC_THR_DEBT_MIN_MASK                    0xFF
#define PMIC_AUXADC_THR_DEBT_MIN_SHIFT                   8
#define PMIC_AUXADC_THR_DET_PRD_15_0_ADDR                MT6355_AUXADC_THR1
#define PMIC_AUXADC_THR_DET_PRD_15_0_MASK                0xFFFF
#define PMIC_AUXADC_THR_DET_PRD_15_0_SHIFT               0
#define PMIC_AUXADC_THR_DET_PRD_19_16_ADDR               MT6355_AUXADC_THR2
#define PMIC_AUXADC_THR_DET_PRD_19_16_MASK               0xF
#define PMIC_AUXADC_THR_DET_PRD_19_16_SHIFT              0
#define PMIC_AUXADC_THR_VOLT_MAX_ADDR                    MT6355_AUXADC_THR3
#define PMIC_AUXADC_THR_VOLT_MAX_MASK                    0xFFF
#define PMIC_AUXADC_THR_VOLT_MAX_SHIFT                   0
#define PMIC_AUXADC_THR_IRQ_EN_MAX_ADDR                  MT6355_AUXADC_THR3
#define PMIC_AUXADC_THR_IRQ_EN_MAX_MASK                  0x1
#define PMIC_AUXADC_THR_IRQ_EN_MAX_SHIFT                 12
#define PMIC_AUXADC_THR_EN_MAX_ADDR                      MT6355_AUXADC_THR3
#define PMIC_AUXADC_THR_EN_MAX_MASK                      0x1
#define PMIC_AUXADC_THR_EN_MAX_SHIFT                     13
#define PMIC_AUXADC_THR_MAX_IRQ_B_ADDR                   MT6355_AUXADC_THR3
#define PMIC_AUXADC_THR_MAX_IRQ_B_MASK                   0x1
#define PMIC_AUXADC_THR_MAX_IRQ_B_SHIFT                  15
#define PMIC_AUXADC_THR_VOLT_MIN_ADDR                    MT6355_AUXADC_THR4
#define PMIC_AUXADC_THR_VOLT_MIN_MASK                    0xFFF
#define PMIC_AUXADC_THR_VOLT_MIN_SHIFT                   0
#define PMIC_AUXADC_THR_IRQ_EN_MIN_ADDR                  MT6355_AUXADC_THR4
#define PMIC_AUXADC_THR_IRQ_EN_MIN_MASK                  0x1
#define PMIC_AUXADC_THR_IRQ_EN_MIN_SHIFT                 12
#define PMIC_AUXADC_THR_EN_MIN_ADDR                      MT6355_AUXADC_THR4
#define PMIC_AUXADC_THR_EN_MIN_MASK                      0x1
#define PMIC_AUXADC_THR_EN_MIN_SHIFT                     13
#define PMIC_AUXADC_THR_MIN_IRQ_B_ADDR                   MT6355_AUXADC_THR4
#define PMIC_AUXADC_THR_MIN_IRQ_B_MASK                   0x1
#define PMIC_AUXADC_THR_MIN_IRQ_B_SHIFT                  15
#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_ADDR          MT6355_AUXADC_THR5
#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_MASK          0x1FF
#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_SHIFT         0
#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_ADDR          MT6355_AUXADC_THR6
#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_MASK          0x1FF
#define PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_SHIFT         0
#define PMIC_EFUSE_GAIN_CH4_TRIM_ADDR                    MT6355_AUXADC_EFUSE0
#define PMIC_EFUSE_GAIN_CH4_TRIM_MASK                    0xFFF
#define PMIC_EFUSE_GAIN_CH4_TRIM_SHIFT                   0
#define PMIC_EFUSE_OFFSET_CH4_TRIM_ADDR                  MT6355_AUXADC_EFUSE1
#define PMIC_EFUSE_OFFSET_CH4_TRIM_MASK                  0x7FF
#define PMIC_EFUSE_OFFSET_CH4_TRIM_SHIFT                 0
#define PMIC_EFUSE_GAIN_CH0_TRIM_ADDR                    MT6355_AUXADC_EFUSE2
#define PMIC_EFUSE_GAIN_CH0_TRIM_MASK                    0xFFF
#define PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT                   0
#define PMIC_EFUSE_OFFSET_CH0_TRIM_ADDR                  MT6355_AUXADC_EFUSE3
#define PMIC_EFUSE_OFFSET_CH0_TRIM_MASK                  0x7FF
#define PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT                 0
#define PMIC_EFUSE_GAIN_CH7_TRIM_ADDR                    MT6355_AUXADC_EFUSE4
#define PMIC_EFUSE_GAIN_CH7_TRIM_MASK                    0xFFF
#define PMIC_EFUSE_GAIN_CH7_TRIM_SHIFT                   0
#define PMIC_EFUSE_OFFSET_CH7_TRIM_ADDR                  MT6355_AUXADC_EFUSE5
#define PMIC_EFUSE_OFFSET_CH7_TRIM_MASK                  0x7FF
#define PMIC_EFUSE_OFFSET_CH7_TRIM_SHIFT                 0
#define PMIC_AUXADC_FGADC_START_SW_ADDR                  MT6355_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_START_SW_MASK                  0x1
#define PMIC_AUXADC_FGADC_START_SW_SHIFT                 0
#define PMIC_AUXADC_FGADC_START_SEL_ADDR                 MT6355_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_START_SEL_MASK                 0x1
#define PMIC_AUXADC_FGADC_START_SEL_SHIFT                1
#define PMIC_AUXADC_FGADC_R_SW_ADDR                      MT6355_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_R_SW_MASK                      0x1
#define PMIC_AUXADC_FGADC_R_SW_SHIFT                     2
#define PMIC_AUXADC_FGADC_R_SEL_ADDR                     MT6355_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_R_SEL_MASK                     0x1
#define PMIC_AUXADC_FGADC_R_SEL_SHIFT                    3
#define PMIC_AUXADC_BAT_PLUGIN_START_SW_ADDR             MT6355_AUXADC_DBG0
#define PMIC_AUXADC_BAT_PLUGIN_START_SW_MASK             0x1
#define PMIC_AUXADC_BAT_PLUGIN_START_SW_SHIFT            4
#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_ADDR            MT6355_AUXADC_DBG0
#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_MASK            0x1
#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_SHIFT           5
#define PMIC_AUXADC_DBG_DIG0_RSV2_ADDR                   MT6355_AUXADC_DBG0
#define PMIC_AUXADC_DBG_DIG0_RSV2_MASK                   0xF
#define PMIC_AUXADC_DBG_DIG0_RSV2_SHIFT                  6
#define PMIC_AUXADC_DBG_DIG1_RSV2_ADDR                   MT6355_AUXADC_DBG0
#define PMIC_AUXADC_DBG_DIG1_RSV2_MASK                   0x3F
#define PMIC_AUXADC_DBG_DIG1_RSV2_SHIFT                  10
#define PMIC_AUXADC_IMPEDANCE_CNT_ADDR                   MT6355_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_CNT_MASK                   0x3F
#define PMIC_AUXADC_IMPEDANCE_CNT_SHIFT                  0
#define PMIC_AUXADC_IMPEDANCE_CHSEL_ADDR                 MT6355_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_CHSEL_MASK                 0x1
#define PMIC_AUXADC_IMPEDANCE_CHSEL_SHIFT                6
#define PMIC_AUXADC_IMPEDANCE_IRQ_CLR_ADDR               MT6355_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_IRQ_CLR_MASK               0x1
#define PMIC_AUXADC_IMPEDANCE_IRQ_CLR_SHIFT              7
#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_ADDR            MT6355_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_MASK            0x1
#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT           8
#define PMIC_AUXADC_CLR_IMP_CNT_STOP_ADDR                MT6355_AUXADC_IMP0
#define PMIC_AUXADC_CLR_IMP_CNT_STOP_MASK                0x1
#define PMIC_AUXADC_CLR_IMP_CNT_STOP_SHIFT               14
#define PMIC_AUXADC_IMPEDANCE_MODE_ADDR                  MT6355_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_MODE_MASK                  0x1
#define PMIC_AUXADC_IMPEDANCE_MODE_SHIFT                 15
#define PMIC_AUXADC_IMP_AUTORPT_PRD_ADDR                 MT6355_AUXADC_IMP1
#define PMIC_AUXADC_IMP_AUTORPT_PRD_MASK                 0x3FF
#define PMIC_AUXADC_IMP_AUTORPT_PRD_SHIFT                0
#define PMIC_AUXADC_IMP_AUTORPT_EN_ADDR                  MT6355_AUXADC_IMP1
#define PMIC_AUXADC_IMP_AUTORPT_EN_MASK                  0x1
#define PMIC_AUXADC_IMP_AUTORPT_EN_SHIFT                 15
#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_ADDR               MT6355_AUXADC_BAT_TEMP_0
#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_MASK               0x1
#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_SHIFT              0
#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_ADDR               MT6355_AUXADC_BAT_TEMP_1
#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_MASK               0xFF
#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_SHIFT              0
#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_ADDR               MT6355_AUXADC_BAT_TEMP_1
#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_MASK               0xFF
#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_SHIFT              8
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0_ADDR           MT6355_AUXADC_BAT_TEMP_2
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0_MASK           0xFFFF
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0_SHIFT          0
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16_ADDR          MT6355_AUXADC_BAT_TEMP_3
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16_MASK          0xF
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16_SHIFT         0
#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_ADDR               MT6355_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_MASK               0xFFF
#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_SHIFT              0
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_ADDR             MT6355_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_MASK             0x1
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_SHIFT            12
#define PMIC_AUXADC_BAT_TEMP_EN_MAX_ADDR                 MT6355_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_EN_MAX_MASK                 0x1
#define PMIC_AUXADC_BAT_TEMP_EN_MAX_SHIFT                13
#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_ADDR              MT6355_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_MASK              0x1
#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_SHIFT             15
#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_ADDR               MT6355_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_MASK               0xFFF
#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_SHIFT              0
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_ADDR             MT6355_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_MASK             0x1
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_SHIFT            12
#define PMIC_AUXADC_BAT_TEMP_EN_MIN_ADDR                 MT6355_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_EN_MIN_MASK                 0x1
#define PMIC_AUXADC_BAT_TEMP_EN_MIN_SHIFT                13
#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_ADDR              MT6355_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_MASK              0x1
#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_SHIFT             15
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_ADDR     MT6355_AUXADC_BAT_TEMP_6
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_MASK     0x1FF
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_SHIFT    0
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_ADDR     MT6355_AUXADC_BAT_TEMP_7
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_MASK     0x1FF
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_SHIFT    0
#define PMIC_AUXADC_LBAT2_DEBT_MAX_ADDR                  MT6355_AUXADC_LBAT2_1
#define PMIC_AUXADC_LBAT2_DEBT_MAX_MASK                  0xFF
#define PMIC_AUXADC_LBAT2_DEBT_MAX_SHIFT                 0
#define PMIC_AUXADC_LBAT2_DEBT_MIN_ADDR                  MT6355_AUXADC_LBAT2_1
#define PMIC_AUXADC_LBAT2_DEBT_MIN_MASK                  0xFF
#define PMIC_AUXADC_LBAT2_DEBT_MIN_SHIFT                 8
#define PMIC_AUXADC_LBAT2_DET_PRD_15_0_ADDR              MT6355_AUXADC_LBAT2_2
#define PMIC_AUXADC_LBAT2_DET_PRD_15_0_MASK              0xFFFF
#define PMIC_AUXADC_LBAT2_DET_PRD_15_0_SHIFT             0
#define PMIC_AUXADC_LBAT2_DET_PRD_19_16_ADDR             MT6355_AUXADC_LBAT2_3
#define PMIC_AUXADC_LBAT2_DET_PRD_19_16_MASK             0xF
#define PMIC_AUXADC_LBAT2_DET_PRD_19_16_SHIFT            0
#define PMIC_AUXADC_LBAT2_VOLT_MAX_ADDR                  MT6355_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_VOLT_MAX_MASK                  0xFFF
#define PMIC_AUXADC_LBAT2_VOLT_MAX_SHIFT                 0
#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_ADDR                MT6355_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_MASK                0x1
#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT               12
#define PMIC_AUXADC_LBAT2_EN_MAX_ADDR                    MT6355_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_EN_MAX_MASK                    0x1
#define PMIC_AUXADC_LBAT2_EN_MAX_SHIFT                   13
#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_ADDR                 MT6355_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_MASK                 0x1
#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_SHIFT                15
#define PMIC_AUXADC_LBAT2_VOLT_MIN_ADDR                  MT6355_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_VOLT_MIN_MASK                  0xFFF
#define PMIC_AUXADC_LBAT2_VOLT_MIN_SHIFT                 0
#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_ADDR                MT6355_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_MASK                0x1
#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT               12
#define PMIC_AUXADC_LBAT2_EN_MIN_ADDR                    MT6355_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_EN_MIN_MASK                    0x1
#define PMIC_AUXADC_LBAT2_EN_MIN_SHIFT                   13
#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_ADDR                 MT6355_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_MASK                 0x1
#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_SHIFT                15
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_ADDR        MT6355_AUXADC_LBAT2_6
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK        0x1FF
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT       0
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_ADDR        MT6355_AUXADC_LBAT2_7
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK        0x1FF
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT       0
#define PMIC_AUXADC_MDBG_DET_PRD_ADDR                    MT6355_AUXADC_MDBG_0
#define PMIC_AUXADC_MDBG_DET_PRD_MASK                    0x3FF
#define PMIC_AUXADC_MDBG_DET_PRD_SHIFT                   0
#define PMIC_AUXADC_MDBG_DET_EN_ADDR                     MT6355_AUXADC_MDBG_0
#define PMIC_AUXADC_MDBG_DET_EN_MASK                     0x1
#define PMIC_AUXADC_MDBG_DET_EN_SHIFT                    15
#define PMIC_AUXADC_MDBG_R_PTR_ADDR                      MT6355_AUXADC_MDBG_1
#define PMIC_AUXADC_MDBG_R_PTR_MASK                      0x3F
#define PMIC_AUXADC_MDBG_R_PTR_SHIFT                     0
#define PMIC_AUXADC_MDBG_W_PTR_ADDR                      MT6355_AUXADC_MDBG_1
#define PMIC_AUXADC_MDBG_W_PTR_MASK                      0x3F
#define PMIC_AUXADC_MDBG_W_PTR_SHIFT                     8
#define PMIC_AUXADC_MDBG_BUF_LENGTH_ADDR                 MT6355_AUXADC_MDBG_2
#define PMIC_AUXADC_MDBG_BUF_LENGTH_MASK                 0x3F
#define PMIC_AUXADC_MDBG_BUF_LENGTH_SHIFT                0
#define PMIC_AUXADC_MDRT_DET_PRD_ADDR                    MT6355_AUXADC_MDRT_0
#define PMIC_AUXADC_MDRT_DET_PRD_MASK                    0x3FF
#define PMIC_AUXADC_MDRT_DET_PRD_SHIFT                   0
#define PMIC_AUXADC_MDRT_DET_EN_ADDR                     MT6355_AUXADC_MDRT_0
#define PMIC_AUXADC_MDRT_DET_EN_MASK                     0x1
#define PMIC_AUXADC_MDRT_DET_EN_SHIFT                    15
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_ADDR         MT6355_AUXADC_MDRT_1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_MASK         0xFFF
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_SHIFT        0
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_ADDR         MT6355_AUXADC_MDRT_1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_MASK         0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_SHIFT        15
#define PMIC_AUXADC_MDRT_DET_WKUP_START_ADDR             MT6355_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_WKUP_START_MASK             0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SHIFT            0
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_ADDR         MT6355_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_MASK         0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_SHIFT        1
#define PMIC_AUXADC_MDRT_DET_WKUP_EN_ADDR                MT6355_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_WKUP_EN_MASK                0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_EN_SHIFT               2
#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_ADDR            MT6355_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_MASK            0x1
#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_SHIFT           3
#define PMIC_AUXADC_MDRT_DET_RDY_ST_PRD_ADDR             MT6355_AUXADC_MDRT_3
#define PMIC_AUXADC_MDRT_DET_RDY_ST_PRD_MASK             0x3FF
#define PMIC_AUXADC_MDRT_DET_RDY_ST_PRD_SHIFT            0
#define PMIC_AUXADC_MDRT_DET_RDY_ST_EN_ADDR              MT6355_AUXADC_MDRT_3
#define PMIC_AUXADC_MDRT_DET_RDY_ST_EN_MASK              0x1
#define PMIC_AUXADC_MDRT_DET_RDY_ST_EN_SHIFT             15
#define PMIC_AUXADC_MDRT_DET_START_SEL_ADDR              MT6355_AUXADC_MDRT_4
#define PMIC_AUXADC_MDRT_DET_START_SEL_MASK              0x1
#define PMIC_AUXADC_MDRT_DET_START_SEL_SHIFT             0
#define PMIC_AUXADC_JEITA_IRQ_EN_ADDR                    MT6355_AUXADC_JEITA_0
#define PMIC_AUXADC_JEITA_IRQ_EN_MASK                    0x1
#define PMIC_AUXADC_JEITA_IRQ_EN_SHIFT                   0
#define PMIC_AUXADC_JEITA_EN_ADDR                        MT6355_AUXADC_JEITA_0
#define PMIC_AUXADC_JEITA_EN_MASK                        0x1
#define PMIC_AUXADC_JEITA_EN_SHIFT                       1
#define PMIC_AUXADC_JEITA_DET_PRD_ADDR                   MT6355_AUXADC_JEITA_0
#define PMIC_AUXADC_JEITA_DET_PRD_MASK                   0xF
#define PMIC_AUXADC_JEITA_DET_PRD_SHIFT                  2
#define PMIC_AUXADC_JEITA_DEBT_ADDR                      MT6355_AUXADC_JEITA_0
#define PMIC_AUXADC_JEITA_DEBT_MASK                      0xF
#define PMIC_AUXADC_JEITA_DEBT_SHIFT                     6
#define PMIC_AUXADC_JEITA_MIPI_DIS_ADDR                  MT6355_AUXADC_JEITA_0
#define PMIC_AUXADC_JEITA_MIPI_DIS_MASK                  0x1
#define PMIC_AUXADC_JEITA_MIPI_DIS_SHIFT                 10
#define PMIC_AUXADC_JEITA_FROZE_EN_ADDR                  MT6355_AUXADC_JEITA_0
#define PMIC_AUXADC_JEITA_FROZE_EN_MASK                  0x1
#define PMIC_AUXADC_JEITA_FROZE_EN_SHIFT                 11
#define PMIC_AUXADC_JEITA_VOLT_HOT_ADDR                  MT6355_AUXADC_JEITA_1
#define PMIC_AUXADC_JEITA_VOLT_HOT_MASK                  0xFFF
#define PMIC_AUXADC_JEITA_VOLT_HOT_SHIFT                 0
#define PMIC_AUXADC_JEITA_HOT_IRQ_ADDR                   MT6355_AUXADC_JEITA_1
#define PMIC_AUXADC_JEITA_HOT_IRQ_MASK                   0x1
#define PMIC_AUXADC_JEITA_HOT_IRQ_SHIFT                  15
#define PMIC_AUXADC_JEITA_VOLT_WARM_ADDR                 MT6355_AUXADC_JEITA_2
#define PMIC_AUXADC_JEITA_VOLT_WARM_MASK                 0xFFF
#define PMIC_AUXADC_JEITA_VOLT_WARM_SHIFT                0
#define PMIC_AUXADC_JEITA_WARM_IRQ_ADDR                  MT6355_AUXADC_JEITA_2
#define PMIC_AUXADC_JEITA_WARM_IRQ_MASK                  0x1
#define PMIC_AUXADC_JEITA_WARM_IRQ_SHIFT                 15
#define PMIC_AUXADC_JEITA_VOLT_COOL_ADDR                 MT6355_AUXADC_JEITA_3
#define PMIC_AUXADC_JEITA_VOLT_COOL_MASK                 0xFFF
#define PMIC_AUXADC_JEITA_VOLT_COOL_SHIFT                0
#define PMIC_AUXADC_JEITA_COOL_IRQ_ADDR                  MT6355_AUXADC_JEITA_3
#define PMIC_AUXADC_JEITA_COOL_IRQ_MASK                  0x1
#define PMIC_AUXADC_JEITA_COOL_IRQ_SHIFT                 15
#define PMIC_AUXADC_JEITA_VOLT_COLD_ADDR                 MT6355_AUXADC_JEITA_4
#define PMIC_AUXADC_JEITA_VOLT_COLD_MASK                 0xFFF
#define PMIC_AUXADC_JEITA_VOLT_COLD_SHIFT                0
#define PMIC_AUXADC_JEITA_COLD_IRQ_ADDR                  MT6355_AUXADC_JEITA_4
#define PMIC_AUXADC_JEITA_COLD_IRQ_MASK                  0x1
#define PMIC_AUXADC_JEITA_COLD_IRQ_SHIFT                 15
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COLD_ADDR       MT6355_AUXADC_JEITA_5
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COLD_MASK       0xF
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COLD_SHIFT      0
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COOL_ADDR       MT6355_AUXADC_JEITA_5
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COOL_MASK       0xF
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COOL_SHIFT      4
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_WARM_ADDR       MT6355_AUXADC_JEITA_5
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_WARM_MASK       0xF
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_WARM_SHIFT      8
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_HOT_ADDR        MT6355_AUXADC_JEITA_5
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_HOT_MASK        0xF
#define PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_HOT_SHIFT       12
#define PMIC_AUXADC_DCXO_MDRT_DET_PRD_ADDR               MT6355_AUXADC_DCXO_MDRT_0
#define PMIC_AUXADC_DCXO_MDRT_DET_PRD_MASK               0x3FF
#define PMIC_AUXADC_DCXO_MDRT_DET_PRD_SHIFT              0
#define PMIC_AUXADC_DCXO_MDRT_DET_EN_ADDR                MT6355_AUXADC_DCXO_MDRT_0
#define PMIC_AUXADC_DCXO_MDRT_DET_EN_MASK                0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_EN_SHIFT               15
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_ADDR    MT6355_AUXADC_DCXO_MDRT_1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_MASK    0xFFF
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_SHIFT   0
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_ADDR    MT6355_AUXADC_DCXO_MDRT_1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_MASK    0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_SHIFT   15
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_ADDR           MT6355_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_MASK           0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_SHIFT          0
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_ADDR    MT6355_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_MASK    0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_SHIFT   1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_ADDR        MT6355_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_MASK        0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SHIFT       2
#define PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_ADDR       MT6355_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_MASK       0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_SHIFT      3
#define PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL_ADDR             MT6355_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL_MASK             0x1
#define PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL_SHIFT            4
#define PMIC_AUXADC_NAG_EN_ADDR                          MT6355_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_EN_MASK                          0x1
#define PMIC_AUXADC_NAG_EN_SHIFT                         0
#define PMIC_AUXADC_NAG_CLR_ADDR                         MT6355_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_CLR_MASK                         0x1
#define PMIC_AUXADC_NAG_CLR_SHIFT                        1
#define PMIC_AUXADC_NAG_VBAT1_SEL_ADDR                   MT6355_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_VBAT1_SEL_MASK                   0x1
#define PMIC_AUXADC_NAG_VBAT1_SEL_SHIFT                  2
#define PMIC_AUXADC_NAG_PRD_ADDR                         MT6355_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_PRD_MASK                         0x7F
#define PMIC_AUXADC_NAG_PRD_SHIFT                        3
#define PMIC_AUXADC_NAG_IRQ_EN_ADDR                      MT6355_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_IRQ_EN_MASK                      0x1
#define PMIC_AUXADC_NAG_IRQ_EN_SHIFT                     10
#define PMIC_AUXADC_NAG_C_DLTV_IRQ_ADDR                  MT6355_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_C_DLTV_IRQ_MASK                  0x1
#define PMIC_AUXADC_NAG_C_DLTV_IRQ_SHIFT                 15
#define PMIC_AUXADC_NAG_ZCV_ADDR                         MT6355_AUXADC_NAG_1
#define PMIC_AUXADC_NAG_ZCV_MASK                         0x7FFF
#define PMIC_AUXADC_NAG_ZCV_SHIFT                        0
#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_ADDR              MT6355_AUXADC_NAG_2
#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_MASK              0xFFFF
#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_SHIFT             0
#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_ADDR             MT6355_AUXADC_NAG_3
#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_MASK             0x7FF
#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_SHIFT            0
#define PMIC_AUXADC_NAG_CNT_15_0_ADDR                    MT6355_AUXADC_NAG_4
#define PMIC_AUXADC_NAG_CNT_15_0_MASK                    0xFFFF
#define PMIC_AUXADC_NAG_CNT_15_0_SHIFT                   0
#define PMIC_AUXADC_NAG_CNT_25_16_ADDR                   MT6355_AUXADC_NAG_5
#define PMIC_AUXADC_NAG_CNT_25_16_MASK                   0x3FF
#define PMIC_AUXADC_NAG_CNT_25_16_SHIFT                  0
#define PMIC_AUXADC_NAG_DLTV_ADDR                        MT6355_AUXADC_NAG_6
#define PMIC_AUXADC_NAG_DLTV_MASK                        0xFFFF
#define PMIC_AUXADC_NAG_DLTV_SHIFT                       0
#define PMIC_AUXADC_NAG_C_DLTV_15_0_ADDR                 MT6355_AUXADC_NAG_7
#define PMIC_AUXADC_NAG_C_DLTV_15_0_MASK                 0xFFFF
#define PMIC_AUXADC_NAG_C_DLTV_15_0_SHIFT                0
#define PMIC_AUXADC_NAG_C_DLTV_26_16_ADDR                MT6355_AUXADC_NAG_8
#define PMIC_AUXADC_NAG_C_DLTV_26_16_MASK                0x7FF
#define PMIC_AUXADC_NAG_C_DLTV_26_16_SHIFT               0
#define PMIC_AUXADC_EFUSE_DEGC_CALI_ADDR                 MT6355_AUXADC_EFUSE_1
#define PMIC_AUXADC_EFUSE_DEGC_CALI_MASK                 0x3F
#define PMIC_AUXADC_EFUSE_DEGC_CALI_SHIFT                0
#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_ADDR               MT6355_AUXADC_EFUSE_1
#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_MASK               0x1
#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_SHIFT              8
#define PMIC_AUXADC_EFUSE_1RSV0_ADDR                     MT6355_AUXADC_EFUSE_1
#define PMIC_AUXADC_EFUSE_1RSV0_MASK                     0x7F
#define PMIC_AUXADC_EFUSE_1RSV0_SHIFT                    9
#define PMIC_AUXADC_EFUSE_O_VTS_ADDR                     MT6355_AUXADC_EFUSE_2
#define PMIC_AUXADC_EFUSE_O_VTS_MASK                     0x1FFF
#define PMIC_AUXADC_EFUSE_O_VTS_SHIFT                    0
#define PMIC_AUXADC_EFUSE_2RSV0_ADDR                     MT6355_AUXADC_EFUSE_2
#define PMIC_AUXADC_EFUSE_2RSV0_MASK                     0x7
#define PMIC_AUXADC_EFUSE_2RSV0_SHIFT                    13
#define PMIC_AUXADC_EFUSE_O_SLOPE_ADDR                   MT6355_AUXADC_EFUSE_3
#define PMIC_AUXADC_EFUSE_O_SLOPE_MASK                   0x3F
#define PMIC_AUXADC_EFUSE_O_SLOPE_SHIFT                  0
#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_ADDR              MT6355_AUXADC_EFUSE_3
#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_MASK              0x1
#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_SHIFT             8
#define PMIC_AUXADC_EFUSE_3RSV0_ADDR                     MT6355_AUXADC_EFUSE_3
#define PMIC_AUXADC_EFUSE_3RSV0_MASK                     0x7F
#define PMIC_AUXADC_EFUSE_3RSV0_SHIFT                    9
#define PMIC_AUXADC_EFUSE_AUXADC_RSV_ADDR                MT6355_AUXADC_EFUSE_4
#define PMIC_AUXADC_EFUSE_AUXADC_RSV_MASK                0xF
#define PMIC_AUXADC_EFUSE_AUXADC_RSV_SHIFT               0
#define PMIC_AUXADC_EFUSE_ID_ADDR                        MT6355_AUXADC_EFUSE_4
#define PMIC_AUXADC_EFUSE_ID_MASK                        0x1
#define PMIC_AUXADC_EFUSE_ID_SHIFT                       4
#define PMIC_AUXADC_EFUSE_4RSV0_ADDR                     MT6355_AUXADC_EFUSE_4
#define PMIC_AUXADC_EFUSE_4RSV0_MASK                     0x7FF
#define PMIC_AUXADC_EFUSE_4RSV0_SHIFT                    5
#define PMIC_AUXADC_RSV_1RSV0_ADDR                       MT6355_AUXADC_RSV_1
#define PMIC_AUXADC_RSV_1RSV0_MASK                       0xFFFF
#define PMIC_AUXADC_RSV_1RSV0_SHIFT                      0
#define PMIC_DA_ADCIN_VBAT_EN_ADDR                       MT6355_AUXADC_ANA_0
#define PMIC_DA_ADCIN_VBAT_EN_MASK                       0x1
#define PMIC_DA_ADCIN_VBAT_EN_SHIFT                      0
#define PMIC_DA_AUXADC_VBAT_EN_ADDR                      MT6355_AUXADC_ANA_0
#define PMIC_DA_AUXADC_VBAT_EN_MASK                      0x1
#define PMIC_DA_AUXADC_VBAT_EN_SHIFT                     1
#define PMIC_DA_ADCIN_VSEN_MUX_EN_ADDR                   MT6355_AUXADC_ANA_0
#define PMIC_DA_ADCIN_VSEN_MUX_EN_MASK                   0x1
#define PMIC_DA_ADCIN_VSEN_MUX_EN_SHIFT                  2
#define PMIC_DA_ADCIN_VSEN_EN_ADDR                       MT6355_AUXADC_ANA_0
#define PMIC_DA_ADCIN_VSEN_EN_MASK                       0x1
#define PMIC_DA_ADCIN_VSEN_EN_SHIFT                      3
#define PMIC_DA_ADCIN_CHR_EN_ADDR                        MT6355_AUXADC_ANA_0
#define PMIC_DA_ADCIN_CHR_EN_MASK                        0x1
#define PMIC_DA_ADCIN_CHR_EN_SHIFT                       4
#define PMIC_DA_BATON_TDET_EN_ADDR                       MT6355_AUXADC_ANA_0
#define PMIC_DA_BATON_TDET_EN_MASK                       0x1
#define PMIC_DA_BATON_TDET_EN_SHIFT                      5
#define PMIC_DA_ADCIN_BATID_SW_EN_ADDR                   MT6355_AUXADC_ANA_0
#define PMIC_DA_ADCIN_BATID_SW_EN_MASK                   0x1
#define PMIC_DA_ADCIN_BATID_SW_EN_SHIFT                  6
#define PMIC_RG_AUXADC_IMP_CK_SW_MODE_ADDR               MT6355_AUXADC_IMP_CG0
#define PMIC_RG_AUXADC_IMP_CK_SW_MODE_MASK               0x1
#define PMIC_RG_AUXADC_IMP_CK_SW_MODE_SHIFT              0
#define PMIC_RG_AUXADC_IMP_CK_SW_EN_ADDR                 MT6355_AUXADC_IMP_CG0
#define PMIC_RG_AUXADC_IMP_CK_SW_EN_MASK                 0x1
#define PMIC_RG_AUXADC_IMP_CK_SW_EN_SHIFT                1
#define PMIC_RG_AUXADC_LBAT_CK_SW_MODE_ADDR              MT6355_AUXADC_LBAT_CG0
#define PMIC_RG_AUXADC_LBAT_CK_SW_MODE_MASK              0x1
#define PMIC_RG_AUXADC_LBAT_CK_SW_MODE_SHIFT             0
#define PMIC_RG_AUXADC_LBAT_CK_SW_EN_ADDR                MT6355_AUXADC_LBAT_CG0
#define PMIC_RG_AUXADC_LBAT_CK_SW_EN_MASK                0x1
#define PMIC_RG_AUXADC_LBAT_CK_SW_EN_SHIFT               1
#define PMIC_RG_AUXADC_THR_CK_SW_MODE_ADDR               MT6355_AUXADC_THR_CG0
#define PMIC_RG_AUXADC_THR_CK_SW_MODE_MASK               0x1
#define PMIC_RG_AUXADC_THR_CK_SW_MODE_SHIFT              0
#define PMIC_RG_AUXADC_THR_CK_SW_EN_ADDR                 MT6355_AUXADC_THR_CG0
#define PMIC_RG_AUXADC_THR_CK_SW_EN_MASK                 0x1
#define PMIC_RG_AUXADC_THR_CK_SW_EN_SHIFT                1
#define PMIC_RG_AUXADC_BAT_TEMP_CK_SW_MODE_ADDR          MT6355_AUXADC_BAT_TEMP_CG0
#define PMIC_RG_AUXADC_BAT_TEMP_CK_SW_MODE_MASK          0x1
#define PMIC_RG_AUXADC_BAT_TEMP_CK_SW_MODE_SHIFT         0
#define PMIC_RG_AUXADC_BAT_TEMP_CK_SW_EN_ADDR            MT6355_AUXADC_BAT_TEMP_CG0
#define PMIC_RG_AUXADC_BAT_TEMP_CK_SW_EN_MASK            0x1
#define PMIC_RG_AUXADC_BAT_TEMP_CK_SW_EN_SHIFT           1
#define PMIC_RG_AUXADC_LBAT2_CK_SW_MODE_ADDR             MT6355_AUXADC_LBAT2_CG0
#define PMIC_RG_AUXADC_LBAT2_CK_SW_MODE_MASK             0x1
#define PMIC_RG_AUXADC_LBAT2_CK_SW_MODE_SHIFT            0
#define PMIC_RG_AUXADC_LBAT2_CK_SW_EN_ADDR               MT6355_AUXADC_LBAT2_CG0
#define PMIC_RG_AUXADC_LBAT2_CK_SW_EN_MASK               0x1
#define PMIC_RG_AUXADC_LBAT2_CK_SW_EN_SHIFT              1
#define PMIC_RG_AUXADC_JEITA_CK_SW_MODE_ADDR             MT6355_AUXADC_JEITA_CG0
#define PMIC_RG_AUXADC_JEITA_CK_SW_MODE_MASK             0x1
#define PMIC_RG_AUXADC_JEITA_CK_SW_MODE_SHIFT            0
#define PMIC_RG_AUXADC_JEITA_CK_SW_EN_ADDR               MT6355_AUXADC_JEITA_CG0
#define PMIC_RG_AUXADC_JEITA_CK_SW_EN_MASK               0x1
#define PMIC_RG_AUXADC_JEITA_CK_SW_EN_SHIFT              1
#define PMIC_RG_AUXADC_NAG_CK_SW_MODE_ADDR               MT6355_AUXADC_NAG_CG0
#define PMIC_RG_AUXADC_NAG_CK_SW_MODE_MASK               0x1
#define PMIC_RG_AUXADC_NAG_CK_SW_MODE_SHIFT              0
#define PMIC_RG_AUXADC_NAG_CK_SW_EN_ADDR                 MT6355_AUXADC_NAG_CG0
#define PMIC_RG_AUXADC_NAG_CK_SW_EN_MASK                 0x1
#define PMIC_RG_AUXADC_NAG_CK_SW_EN_SHIFT                1
#define PMIC_RG_AUXADC_NEW_PRIORITY_LIST_SEL_ADDR        MT6355_AUXADC_PRI_NEW
#define PMIC_RG_AUXADC_NEW_PRIORITY_LIST_SEL_MASK        0x1
#define PMIC_RG_AUXADC_NEW_PRIORITY_LIST_SEL_SHIFT       0
#define PMIC_RG_ISINK_TRIM_EN_ADDR                       MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK_TRIM_EN_MASK                       0x1
#define PMIC_RG_ISINK_TRIM_EN_SHIFT                      0
#define PMIC_RG_ISINK_TRIM_SEL_ADDR                      MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK_TRIM_SEL_MASK                      0x7
#define PMIC_RG_ISINK_TRIM_SEL_SHIFT                     1
#define PMIC_RG_ISINK_TRIM_BIAS_ADDR                     MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK_TRIM_BIAS_MASK                     0x7
#define PMIC_RG_ISINK_TRIM_BIAS_SHIFT                    4
#define PMIC_RG_ISINK_RSV_ADDR                           MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK_RSV_MASK                           0xF
#define PMIC_RG_ISINK_RSV_SHIFT                          7
#define PMIC_RG_ISINK0_CHOP_EN_ADDR                      MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK0_CHOP_EN_MASK                      0x1
#define PMIC_RG_ISINK0_CHOP_EN_SHIFT                     11
#define PMIC_RG_ISINK1_CHOP_EN_ADDR                      MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK1_CHOP_EN_MASK                      0x1
#define PMIC_RG_ISINK1_CHOP_EN_SHIFT                     12
#define PMIC_RG_ISINK2_CHOP_EN_ADDR                      MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK2_CHOP_EN_MASK                      0x1
#define PMIC_RG_ISINK2_CHOP_EN_SHIFT                     13
#define PMIC_RG_ISINK3_CHOP_EN_ADDR                      MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK3_CHOP_EN_MASK                      0x1
#define PMIC_RG_ISINK3_CHOP_EN_SHIFT                     14
#define PMIC_RG_ISINK0_DOUBLE_ADDR                       MT6355_DRIVER_ANA_CON0
#define PMIC_RG_ISINK0_DOUBLE_MASK                       0x1
#define PMIC_RG_ISINK0_DOUBLE_SHIFT                      15
#define PMIC_RG_ISINK1_DOUBLE_ADDR                       MT6355_DRIVER_ANA_CON1
#define PMIC_RG_ISINK1_DOUBLE_MASK                       0x1
#define PMIC_RG_ISINK1_DOUBLE_SHIFT                      0
#define PMIC_RG_ISINK2_DOUBLE_ADDR                       MT6355_DRIVER_ANA_CON1
#define PMIC_RG_ISINK2_DOUBLE_MASK                       0x1
#define PMIC_RG_ISINK2_DOUBLE_SHIFT                      1
#define PMIC_RG_ISINK3_DOUBLE_ADDR                       MT6355_DRIVER_ANA_CON1
#define PMIC_RG_ISINK3_DOUBLE_MASK                       0x1
#define PMIC_RG_ISINK3_DOUBLE_SHIFT                      2
#define PMIC_ISINK0_RSV1_ADDR                            MT6355_ISINK0_CON1
#define PMIC_ISINK0_RSV1_MASK                            0xF
#define PMIC_ISINK0_RSV1_SHIFT                           0
#define PMIC_ISINK0_RSV0_ADDR                            MT6355_ISINK0_CON1
#define PMIC_ISINK0_RSV0_MASK                            0x7
#define PMIC_ISINK0_RSV0_SHIFT                           4
#define PMIC_ISINK_CH0_STEP_ADDR                         MT6355_ISINK0_CON1
#define PMIC_ISINK_CH0_STEP_MASK                         0x7
#define PMIC_ISINK_CH0_STEP_SHIFT                        12
#define PMIC_ISINK1_RSV1_ADDR                            MT6355_ISINK1_CON1
#define PMIC_ISINK1_RSV1_MASK                            0xF
#define PMIC_ISINK1_RSV1_SHIFT                           0
#define PMIC_ISINK1_RSV0_ADDR                            MT6355_ISINK1_CON1
#define PMIC_ISINK1_RSV0_MASK                            0x7
#define PMIC_ISINK1_RSV0_SHIFT                           4
#define PMIC_ISINK_CH1_STEP_ADDR                         MT6355_ISINK1_CON1
#define PMIC_ISINK_CH1_STEP_MASK                         0x7
#define PMIC_ISINK_CH1_STEP_SHIFT                        12
#define PMIC_ISINK2_RSV1_ADDR                            MT6355_ISINK2_CON1
#define PMIC_ISINK2_RSV1_MASK                            0xF
#define PMIC_ISINK2_RSV1_SHIFT                           0
#define PMIC_ISINK2_RSV0_ADDR                            MT6355_ISINK2_CON1
#define PMIC_ISINK2_RSV0_MASK                            0x7
#define PMIC_ISINK2_RSV0_SHIFT                           4
#define PMIC_ISINK_CH2_STEP_ADDR                         MT6355_ISINK2_CON1
#define PMIC_ISINK_CH2_STEP_MASK                         0x7
#define PMIC_ISINK_CH2_STEP_SHIFT                        12
#define PMIC_ISINK3_RSV1_ADDR                            MT6355_ISINK3_CON1
#define PMIC_ISINK3_RSV1_MASK                            0xF
#define PMIC_ISINK3_RSV1_SHIFT                           0
#define PMIC_ISINK3_RSV0_ADDR                            MT6355_ISINK3_CON1
#define PMIC_ISINK3_RSV0_MASK                            0x7
#define PMIC_ISINK3_RSV0_SHIFT                           4
#define PMIC_ISINK_CH3_STEP_ADDR                         MT6355_ISINK3_CON1
#define PMIC_ISINK_CH3_STEP_MASK                         0x7
#define PMIC_ISINK_CH3_STEP_SHIFT                        12
#define PMIC_AD_NI_ISINK0_STATUS_ADDR                    MT6355_ISINK_ANA1_SMPL
#define PMIC_AD_NI_ISINK0_STATUS_MASK                    0x1
#define PMIC_AD_NI_ISINK0_STATUS_SHIFT                   0
#define PMIC_AD_NI_ISINK1_STATUS_ADDR                    MT6355_ISINK_ANA1_SMPL
#define PMIC_AD_NI_ISINK1_STATUS_MASK                    0x1
#define PMIC_AD_NI_ISINK1_STATUS_SHIFT                   1
#define PMIC_AD_NI_ISINK2_STATUS_ADDR                    MT6355_ISINK_ANA1_SMPL
#define PMIC_AD_NI_ISINK2_STATUS_MASK                    0x1
#define PMIC_AD_NI_ISINK2_STATUS_SHIFT                   2
#define PMIC_AD_NI_ISINK3_STATUS_ADDR                    MT6355_ISINK_ANA1_SMPL
#define PMIC_AD_NI_ISINK3_STATUS_MASK                    0x1
#define PMIC_AD_NI_ISINK3_STATUS_SHIFT                   3
#define PMIC_ISINK_CH3_EN_ADDR                           MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH3_EN_MASK                           0x1
#define PMIC_ISINK_CH3_EN_SHIFT                          0
#define PMIC_ISINK_CH2_EN_ADDR                           MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH2_EN_MASK                           0x1
#define PMIC_ISINK_CH2_EN_SHIFT                          1
#define PMIC_ISINK_CH1_EN_ADDR                           MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH1_EN_MASK                           0x1
#define PMIC_ISINK_CH1_EN_SHIFT                          2
#define PMIC_ISINK_CH0_EN_ADDR                           MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH0_EN_MASK                           0x1
#define PMIC_ISINK_CH0_EN_SHIFT                          3
#define PMIC_ISINK_CHOP3_EN_ADDR                         MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CHOP3_EN_MASK                         0x1
#define PMIC_ISINK_CHOP3_EN_SHIFT                        4
#define PMIC_ISINK_CHOP2_EN_ADDR                         MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CHOP2_EN_MASK                         0x1
#define PMIC_ISINK_CHOP2_EN_SHIFT                        5
#define PMIC_ISINK_CHOP1_EN_ADDR                         MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CHOP1_EN_MASK                         0x1
#define PMIC_ISINK_CHOP1_EN_SHIFT                        6
#define PMIC_ISINK_CHOP0_EN_ADDR                         MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CHOP0_EN_MASK                         0x1
#define PMIC_ISINK_CHOP0_EN_SHIFT                        7
#define PMIC_ISINK_CH3_BIAS_EN_ADDR                      MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH3_BIAS_EN_MASK                      0x1
#define PMIC_ISINK_CH3_BIAS_EN_SHIFT                     8
#define PMIC_ISINK_CH2_BIAS_EN_ADDR                      MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH2_BIAS_EN_MASK                      0x1
#define PMIC_ISINK_CH2_BIAS_EN_SHIFT                     9
#define PMIC_ISINK_CH1_BIAS_EN_ADDR                      MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH1_BIAS_EN_MASK                      0x1
#define PMIC_ISINK_CH1_BIAS_EN_SHIFT                     10
#define PMIC_ISINK_CH0_BIAS_EN_ADDR                      MT6355_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH0_BIAS_EN_MASK                      0x1
#define PMIC_ISINK_CH0_BIAS_EN_SHIFT                     11
#define PMIC_RG_AUDDACLPWRUP_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDDACLPWRUP_VAUDP32_MASK                0x1
#define PMIC_RG_AUDDACLPWRUP_VAUDP32_SHIFT               0
#define PMIC_RG_AUDDACRPWRUP_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDDACRPWRUP_VAUDP32_MASK                0x1
#define PMIC_RG_AUDDACRPWRUP_VAUDP32_SHIFT               1
#define PMIC_RG_AUD_DAC_PWR_UP_VA32_ADDR                 MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUD_DAC_PWR_UP_VA32_MASK                 0x1
#define PMIC_RG_AUD_DAC_PWR_UP_VA32_SHIFT                2
#define PMIC_RG_AUD_DAC_PWL_UP_VA32_ADDR                 MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUD_DAC_PWL_UP_VA32_MASK                 0x1
#define PMIC_RG_AUD_DAC_PWL_UP_VA32_SHIFT                3
#define PMIC_RG_AUDHPLPWRUP_VAUDP32_ADDR                 MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLPWRUP_VAUDP32_MASK                 0x1
#define PMIC_RG_AUDHPLPWRUP_VAUDP32_SHIFT                4
#define PMIC_RG_AUDHPRPWRUP_VAUDP32_ADDR                 MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRPWRUP_VAUDP32_MASK                 0x1
#define PMIC_RG_AUDHPRPWRUP_VAUDP32_SHIFT                5
#define PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK           0x1
#define PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP32_SHIFT          6
#define PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK           0x1
#define PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP32_SHIFT          7
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK           0x3
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP32_SHIFT          8
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK           0x3
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP32_SHIFT          10
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP32_ADDR             MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP32_MASK             0x1
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP32_SHIFT            12
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP32_ADDR             MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP32_MASK             0x1
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP32_SHIFT            13
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP32_MASK            0x1
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP32_SHIFT           14
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP32_MASK            0x1
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP32_SHIFT           15
#define PMIC_RG_AUDHPLOUTPWRUP_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPLOUTPWRUP_VAUDP32_MASK              0x1
#define PMIC_RG_AUDHPLOUTPWRUP_VAUDP32_SHIFT             0
#define PMIC_RG_AUDHPROUTPWRUP_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPROUTPWRUP_VAUDP32_MASK              0x1
#define PMIC_RG_AUDHPROUTPWRUP_VAUDP32_SHIFT             1
#define PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK           0x1
#define PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP32_SHIFT          2
#define PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK           0x1
#define PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP32_SHIFT          3
#define PMIC_RG_HPLAUXFBRSW_EN_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_HPLAUXFBRSW_EN_VAUDP32_MASK              0x1
#define PMIC_RG_HPLAUXFBRSW_EN_VAUDP32_SHIFT             4
#define PMIC_RG_HPRAUXFBRSW_EN_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_HPRAUXFBRSW_EN_VAUDP32_MASK              0x1
#define PMIC_RG_HPRAUXFBRSW_EN_VAUDP32_SHIFT             5
#define PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP32_ADDR          MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK          0x1
#define PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP32_SHIFT         6
#define PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP32_ADDR          MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK          0x1
#define PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP32_SHIFT         7
#define PMIC_RG_HPLOUTSTGCTRL_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_HPLOUTSTGCTRL_VAUDP32_MASK               0x7
#define PMIC_RG_HPLOUTSTGCTRL_VAUDP32_SHIFT              8
#define PMIC_RG_HPROUTSTGCTRL_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON1
#define PMIC_RG_HPROUTSTGCTRL_VAUDP32_MASK               0x7
#define PMIC_RG_HPROUTSTGCTRL_VAUDP32_SHIFT              11
#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_ADDR             MT6355_AUDDEC_ANA_CON2
#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_MASK             0x7
#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_SHIFT            0
#define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_ADDR             MT6355_AUDDEC_ANA_CON2
#define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_MASK             0x7
#define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_SHIFT            4
#define PMIC_RG_AUDHPSTARTUP_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON2
#define PMIC_RG_AUDHPSTARTUP_VAUDP32_MASK                0x1
#define PMIC_RG_AUDHPSTARTUP_VAUDP32_SHIFT               13
#define PMIC_RG_AUDREFN_DERES_EN_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON2
#define PMIC_RG_AUDREFN_DERES_EN_VAUDP32_MASK            0x1
#define PMIC_RG_AUDREFN_DERES_EN_VAUDP32_SHIFT           14
#define PMIC_RG_HPPSHORT2VCM_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON2
#define PMIC_RG_HPPSHORT2VCM_VAUDP32_MASK                0x1
#define PMIC_RG_HPPSHORT2VCM_VAUDP32_SHIFT               15
#define PMIC_RG_AUDHPLTRIM_VAUDP32_ADDR                  MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_AUDHPLTRIM_VAUDP32_MASK                  0xF
#define PMIC_RG_AUDHPLTRIM_VAUDP32_SHIFT                 0
#define PMIC_RG_AUDHPRTRIM_VAUDP32_ADDR                  MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_AUDHPRTRIM_VAUDP32_MASK                  0xF
#define PMIC_RG_AUDHPRTRIM_VAUDP32_SHIFT                 4
#define PMIC_RG_AUDHPLFINETRIM_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_AUDHPLFINETRIM_VAUDP32_MASK              0x3
#define PMIC_RG_AUDHPLFINETRIM_VAUDP32_SHIFT             8
#define PMIC_RG_AUDHPRFINETRIM_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_AUDHPRFINETRIM_VAUDP32_MASK              0x3
#define PMIC_RG_AUDHPRFINETRIM_VAUDP32_SHIFT             10
#define PMIC_RG_AUDHPTRIM_EN_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_AUDHPTRIM_EN_VAUDP32_MASK                0x1
#define PMIC_RG_AUDHPTRIM_EN_VAUDP32_SHIFT               12
#define PMIC_RG_HPINPUTSTBENH_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_HPINPUTSTBENH_VAUDP32_MASK               0x1
#define PMIC_RG_HPINPUTSTBENH_VAUDP32_SHIFT              13
#define PMIC_RG_HPINPUTRESET0_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_HPINPUTRESET0_VAUDP32_MASK               0x1
#define PMIC_RG_HPINPUTRESET0_VAUDP32_SHIFT              14
#define PMIC_RG_HPOUTPUTRESET0_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON3
#define PMIC_RG_HPOUTPUTRESET0_VAUDP32_MASK              0x1
#define PMIC_RG_HPOUTPUTRESET0_VAUDP32_SHIFT             15
#define PMIC_RG_AUDHPDIFFINPBIASADJ_VAUDP32_ADDR         MT6355_AUDDEC_ANA_CON4
#define PMIC_RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK         0x7
#define PMIC_RG_AUDHPDIFFINPBIASADJ_VAUDP32_SHIFT        0
#define PMIC_RG_AUDHPLFCOMPRESSEL_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON4
#define PMIC_RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK           0x7
#define PMIC_RG_AUDHPLFCOMPRESSEL_VAUDP32_SHIFT          4
#define PMIC_RG_AUDHPHFCOMPRESSEL_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON4
#define PMIC_RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK           0x7
#define PMIC_RG_AUDHPHFCOMPRESSEL_VAUDP32_SHIFT          8
#define PMIC_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_ADDR       MT6355_AUDDEC_ANA_CON4
#define PMIC_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK       0x3
#define PMIC_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SHIFT      12
#define PMIC_RG_AUDHPCOMP_EN_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON4
#define PMIC_RG_AUDHPCOMP_EN_VAUDP32_MASK                0x1
#define PMIC_RG_AUDHPCOMP_EN_VAUDP32_SHIFT               15
#define PMIC_RG_AUDHPDECMGAINADJ_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON5
#define PMIC_RG_AUDHPDECMGAINADJ_VAUDP32_MASK            0x7
#define PMIC_RG_AUDHPDECMGAINADJ_VAUDP32_SHIFT           0
#define PMIC_RG_AUDHPDEDMGAINADJ_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON5
#define PMIC_RG_AUDHPDEDMGAINADJ_VAUDP32_MASK            0x7
#define PMIC_RG_AUDHPDEDMGAINADJ_VAUDP32_SHIFT           4
#define PMIC_RG_AUDHSPWRUP_VAUDP32_ADDR                  MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSPWRUP_VAUDP32_MASK                  0x1
#define PMIC_RG_AUDHSPWRUP_VAUDP32_SHIFT                 0
#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK            0x1
#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP32_SHIFT           1
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP32_MASK            0x3
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP32_SHIFT           2
#define PMIC_RG_AUDHSSCDISABLE_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSSCDISABLE_VAUDP32_MASK              0x1
#define PMIC_RG_AUDHSSCDISABLE_VAUDP32_SHIFT             4
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP32_ADDR             MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP32_MASK             0x1
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP32_SHIFT            5
#define PMIC_RG_AUDHSSTARTUP_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSSTARTUP_VAUDP32_MASK                0x1
#define PMIC_RG_AUDHSSTARTUP_VAUDP32_SHIFT               6
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP32_MASK              0x1
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP32_SHIFT             7
#define PMIC_RG_HSINPUTSTBENH_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_HSINPUTSTBENH_VAUDP32_MASK               0x1
#define PMIC_RG_HSINPUTSTBENH_VAUDP32_SHIFT              8
#define PMIC_RG_HSINPUTRESET0_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_HSINPUTRESET0_VAUDP32_MASK               0x1
#define PMIC_RG_HSINPUTRESET0_VAUDP32_SHIFT              9
#define PMIC_RG_HSOUTPUTRESET0_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_HSOUTPUTRESET0_VAUDP32_MASK              0x1
#define PMIC_RG_HSOUTPUTRESET0_VAUDP32_SHIFT             10
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON6
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP32_MASK              0x1
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP32_SHIFT             11
#define PMIC_RG_AUDLOLPWRUP_VAUDP32_ADDR                 MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLPWRUP_VAUDP32_MASK                 0x1
#define PMIC_RG_AUDLOLPWRUP_VAUDP32_SHIFT                0
#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK           0x1
#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP32_SHIFT          1
#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP32_ADDR           MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK           0x3
#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP32_SHIFT          2
#define PMIC_RG_AUDLOLSCDISABLE_VAUDP32_ADDR             MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLSCDISABLE_VAUDP32_MASK             0x1
#define PMIC_RG_AUDLOLSCDISABLE_VAUDP32_SHIFT            4
#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP32_ADDR            MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP32_MASK            0x1
#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP32_SHIFT           5
#define PMIC_RG_AUDLOSTARTUP_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOSTARTUP_VAUDP32_MASK                0x1
#define PMIC_RG_AUDLOSTARTUP_VAUDP32_SHIFT               6
#define PMIC_RG_LOINPUTSTBENH_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_LOINPUTSTBENH_VAUDP32_MASK               0x1
#define PMIC_RG_LOINPUTSTBENH_VAUDP32_SHIFT              7
#define PMIC_RG_LOOUTPUTSTBENH_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_LOOUTPUTSTBENH_VAUDP32_MASK              0x1
#define PMIC_RG_LOOUTPUTSTBENH_VAUDP32_SHIFT             8
#define PMIC_RG_LOINPUTRESET0_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_LOINPUTRESET0_VAUDP32_MASK               0x1
#define PMIC_RG_LOINPUTRESET0_VAUDP32_SHIFT              9
#define PMIC_RG_LOOUTPUTRESET0_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_LOOUTPUTRESET0_VAUDP32_MASK              0x1
#define PMIC_RG_LOOUTPUTRESET0_VAUDP32_SHIFT             10
#define PMIC_RG_LOOUT_SHORTVCM_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON7
#define PMIC_RG_LOOUT_SHORTVCM_VAUDP32_MASK              0x1
#define PMIC_RG_LOOUT_SHORTVCM_VAUDP32_SHIFT             11
#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_ADDR      MT6355_AUDDEC_ANA_CON8
#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK      0xF
#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SHIFT     0
#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP32_ADDR          MT6355_AUDDEC_ANA_CON8
#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK          0x3
#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP32_SHIFT         4
#define PMIC_RG_AUDTRIMBUF_EN_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON8
#define PMIC_RG_AUDTRIMBUF_EN_VAUDP32_MASK               0x1
#define PMIC_RG_AUDTRIMBUF_EN_VAUDP32_SHIFT              6
#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_ADDR     MT6355_AUDDEC_ANA_CON8
#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK     0x3
#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_SHIFT    8
#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_ADDR    MT6355_AUDDEC_ANA_CON8
#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK    0x3
#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_SHIFT   10
#define PMIC_RG_AUDHPSPKDET_EN_VAUDP32_ADDR              MT6355_AUDDEC_ANA_CON8
#define PMIC_RG_AUDHPSPKDET_EN_VAUDP32_MASK              0x1
#define PMIC_RG_AUDHPSPKDET_EN_VAUDP32_SHIFT             12
#define PMIC_RG_ABIDEC_RSVD0_VA32_ADDR                   MT6355_AUDDEC_ANA_CON9
#define PMIC_RG_ABIDEC_RSVD0_VA32_MASK                   0xFF
#define PMIC_RG_ABIDEC_RSVD0_VA32_SHIFT                  0
#define PMIC_RG_ABIDEC_RSVD0_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON9
#define PMIC_RG_ABIDEC_RSVD0_VAUDP32_MASK                0xFF
#define PMIC_RG_ABIDEC_RSVD0_VAUDP32_SHIFT               8
#define PMIC_RG_ABIDEC_RSVD1_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON10
#define PMIC_RG_ABIDEC_RSVD1_VAUDP32_MASK                0xFF
#define PMIC_RG_ABIDEC_RSVD1_VAUDP32_SHIFT               0
#define PMIC_RG_ABIDEC_RSVD2_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON10
#define PMIC_RG_ABIDEC_RSVD2_VAUDP32_MASK                0xFF
#define PMIC_RG_ABIDEC_RSVD2_VAUDP32_SHIFT               8
#define PMIC_RG_AUDZCDMUXSEL_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON11
#define PMIC_RG_AUDZCDMUXSEL_VAUDP32_MASK                0x7
#define PMIC_RG_AUDZCDMUXSEL_VAUDP32_SHIFT               0
#define PMIC_RG_AUDZCDCLKSEL_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON11
#define PMIC_RG_AUDZCDCLKSEL_VAUDP32_MASK                0x1
#define PMIC_RG_AUDZCDCLKSEL_VAUDP32_SHIFT               3
#define PMIC_RG_AUDBIASADJ_0_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON11
#define PMIC_RG_AUDBIASADJ_0_VAUDP32_MASK                0x1FF
#define PMIC_RG_AUDBIASADJ_0_VAUDP32_SHIFT               7
#define PMIC_RG_AUDBIASADJ_1_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON12
#define PMIC_RG_AUDBIASADJ_1_VAUDP32_MASK                0xFF
#define PMIC_RG_AUDBIASADJ_1_VAUDP32_SHIFT               0
#define PMIC_RG_AUDIBIASPWRDN_VAUDP32_ADDR               MT6355_AUDDEC_ANA_CON12
#define PMIC_RG_AUDIBIASPWRDN_VAUDP32_MASK               0x1
#define PMIC_RG_AUDIBIASPWRDN_VAUDP32_SHIFT              8
#define PMIC_RG_RSTB_DECODER_VA32_ADDR                   MT6355_AUDDEC_ANA_CON13
#define PMIC_RG_RSTB_DECODER_VA32_MASK                   0x1
#define PMIC_RG_RSTB_DECODER_VA32_SHIFT                  0
#define PMIC_RG_SEL_DECODER_96K_VA32_ADDR                MT6355_AUDDEC_ANA_CON13
#define PMIC_RG_SEL_DECODER_96K_VA32_MASK                0x1
#define PMIC_RG_SEL_DECODER_96K_VA32_SHIFT               1
#define PMIC_RG_SEL_DELAY_VCORE_ADDR                     MT6355_AUDDEC_ANA_CON13
#define PMIC_RG_SEL_DELAY_VCORE_MASK                     0x1
#define PMIC_RG_SEL_DELAY_VCORE_SHIFT                    2
#define PMIC_RG_AUDGLB_PWRDN_VA32_ADDR                   MT6355_AUDDEC_ANA_CON13
#define PMIC_RG_AUDGLB_PWRDN_VA32_MASK                   0x1
#define PMIC_RG_AUDGLB_PWRDN_VA32_SHIFT                  4
#define PMIC_RG_AUDGLB_LP_VOW_EN_VA32_ADDR               MT6355_AUDDEC_ANA_CON13
#define PMIC_RG_AUDGLB_LP_VOW_EN_VA32_MASK               0x1
#define PMIC_RG_AUDGLB_LP_VOW_EN_VA32_SHIFT              5
#define PMIC_RG_AUDGLB_LP2_VOW_EN_VA32_ADDR              MT6355_AUDDEC_ANA_CON13
#define PMIC_RG_AUDGLB_LP2_VOW_EN_VA32_MASK              0x1
#define PMIC_RG_AUDGLB_LP2_VOW_EN_VA32_SHIFT             6
#define PMIC_RG_LCLDO_DEC_EN_VA32_ADDR                   MT6355_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_DEC_EN_VA32_MASK                   0x1
#define PMIC_RG_LCLDO_DEC_EN_VA32_SHIFT                  0
#define PMIC_RG_LCLDO_DEC_PDDIS_EN_VA18_ADDR             MT6355_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_DEC_PDDIS_EN_VA18_MASK             0x1
#define PMIC_RG_LCLDO_DEC_PDDIS_EN_VA18_SHIFT            1
#define PMIC_RG_LCLDO_DEC_REMOTE_SENSE_VA18_ADDR         MT6355_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK         0x1
#define PMIC_RG_LCLDO_DEC_REMOTE_SENSE_VA18_SHIFT        2
#define PMIC_RG_NVREG_EN_VAUDP32_ADDR                    MT6355_AUDDEC_ANA_CON14
#define PMIC_RG_NVREG_EN_VAUDP32_MASK                    0x1
#define PMIC_RG_NVREG_EN_VAUDP32_SHIFT                   4
#define PMIC_RG_NVREG_PULL0V_VAUDP32_ADDR                MT6355_AUDDEC_ANA_CON14
#define PMIC_RG_NVREG_PULL0V_VAUDP32_MASK                0x1
#define PMIC_RG_NVREG_PULL0V_VAUDP32_SHIFT               5
#define PMIC_RG_AUDPMU_RSVD_VA18_ADDR                    MT6355_AUDDEC_ANA_CON14
#define PMIC_RG_AUDPMU_RSVD_VA18_MASK                    0xFF
#define PMIC_RG_AUDPMU_RSVD_VA18_SHIFT                   8
#define PMIC_RG_AUDPREAMPLON_ADDR                        MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLON_MASK                        0x1
#define PMIC_RG_AUDPREAMPLON_SHIFT                       0
#define PMIC_RG_AUDPREAMPLDCCEN_ADDR                     MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLDCCEN_MASK                     0x1
#define PMIC_RG_AUDPREAMPLDCCEN_SHIFT                    1
#define PMIC_RG_AUDPREAMPLDCPRECHARGE_ADDR               MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLDCPRECHARGE_MASK               0x1
#define PMIC_RG_AUDPREAMPLDCPRECHARGE_SHIFT              2
#define PMIC_RG_AUDPREAMPLPGATEST_ADDR                   MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLPGATEST_MASK                   0x1
#define PMIC_RG_AUDPREAMPLPGATEST_SHIFT                  3
#define PMIC_RG_AUDPREAMPLVSCALE_ADDR                    MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLVSCALE_MASK                    0x3
#define PMIC_RG_AUDPREAMPLVSCALE_SHIFT                   4
#define PMIC_RG_AUDPREAMPLINPUTSEL_ADDR                  MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLINPUTSEL_MASK                  0x3
#define PMIC_RG_AUDPREAMPLINPUTSEL_SHIFT                 6
#define PMIC_RG_AUDPREAMPLGAIN_ADDR                      MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLGAIN_MASK                      0x7
#define PMIC_RG_AUDPREAMPLGAIN_SHIFT                     8
#define PMIC_RG_BULKL_VCM_EN_ADDR                        MT6355_AUDENC_ANA_CON0
#define PMIC_RG_BULKL_VCM_EN_MASK                        0x1
#define PMIC_RG_BULKL_VCM_EN_SHIFT                       11
#define PMIC_RG_AUDADCLPWRUP_ADDR                        MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDADCLPWRUP_MASK                        0x1
#define PMIC_RG_AUDADCLPWRUP_SHIFT                       12
#define PMIC_RG_AUDADCLINPUTSEL_ADDR                     MT6355_AUDENC_ANA_CON0
#define PMIC_RG_AUDADCLINPUTSEL_MASK                     0x3
#define PMIC_RG_AUDADCLINPUTSEL_SHIFT                    13
#define PMIC_RG_AUDPREAMPRON_ADDR                        MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRON_MASK                        0x1
#define PMIC_RG_AUDPREAMPRON_SHIFT                       0
#define PMIC_RG_AUDPREAMPRDCCEN_ADDR                     MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRDCCEN_MASK                     0x1
#define PMIC_RG_AUDPREAMPRDCCEN_SHIFT                    1
#define PMIC_RG_AUDPREAMPRDCPRECHARGE_ADDR               MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRDCPRECHARGE_MASK               0x1
#define PMIC_RG_AUDPREAMPRDCPRECHARGE_SHIFT              2
#define PMIC_RG_AUDPREAMPRPGATEST_ADDR                   MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRPGATEST_MASK                   0x1
#define PMIC_RG_AUDPREAMPRPGATEST_SHIFT                  3
#define PMIC_RG_AUDPREAMPRVSCALE_ADDR                    MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRVSCALE_MASK                    0x3
#define PMIC_RG_AUDPREAMPRVSCALE_SHIFT                   4
#define PMIC_RG_AUDPREAMPRINPUTSEL_ADDR                  MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRINPUTSEL_MASK                  0x3
#define PMIC_RG_AUDPREAMPRINPUTSEL_SHIFT                 6
#define PMIC_RG_AUDPREAMPRGAIN_ADDR                      MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRGAIN_MASK                      0x7
#define PMIC_RG_AUDPREAMPRGAIN_SHIFT                     8
#define PMIC_RG_BULKR_VCM_EN_ADDR                        MT6355_AUDENC_ANA_CON1
#define PMIC_RG_BULKR_VCM_EN_MASK                        0x1
#define PMIC_RG_BULKR_VCM_EN_SHIFT                       11
#define PMIC_RG_AUDADCRPWRUP_ADDR                        MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDADCRPWRUP_MASK                        0x1
#define PMIC_RG_AUDADCRPWRUP_SHIFT                       12
#define PMIC_RG_AUDADCRINPUTSEL_ADDR                     MT6355_AUDENC_ANA_CON1
#define PMIC_RG_AUDADCRINPUTSEL_MASK                     0x3
#define PMIC_RG_AUDADCRINPUTSEL_SHIFT                    13
#define PMIC_RG_AUDULHALFBIAS_ADDR                       MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDULHALFBIAS_MASK                       0x1
#define PMIC_RG_AUDULHALFBIAS_SHIFT                      0
#define PMIC_RG_AUDGLBVOWLPWEN_ADDR                      MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDGLBVOWLPWEN_MASK                      0x1
#define PMIC_RG_AUDGLBVOWLPWEN_SHIFT                     1
#define PMIC_RG_AUDPREAMPLPEN_ADDR                       MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDPREAMPLPEN_MASK                       0x1
#define PMIC_RG_AUDPREAMPLPEN_SHIFT                      2
#define PMIC_RG_AUDADC1STSTAGELPEN_ADDR                  MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC1STSTAGELPEN_MASK                  0x1
#define PMIC_RG_AUDADC1STSTAGELPEN_SHIFT                 3
#define PMIC_RG_AUDADC2NDSTAGELPEN_ADDR                  MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC2NDSTAGELPEN_MASK                  0x1
#define PMIC_RG_AUDADC2NDSTAGELPEN_SHIFT                 4
#define PMIC_RG_AUDADCFLASHLPEN_ADDR                     MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADCFLASHLPEN_MASK                     0x1
#define PMIC_RG_AUDADCFLASHLPEN_SHIFT                    5
#define PMIC_RG_AUDPREAMPIDDTEST_ADDR                    MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDPREAMPIDDTEST_MASK                    0x3
#define PMIC_RG_AUDPREAMPIDDTEST_SHIFT                   6
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_ADDR               MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_MASK               0x3
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_SHIFT              8
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_ADDR               MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_MASK               0x3
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_SHIFT              10
#define PMIC_RG_AUDADCREFBUFIDDTEST_ADDR                 MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADCREFBUFIDDTEST_MASK                 0x3
#define PMIC_RG_AUDADCREFBUFIDDTEST_SHIFT                12
#define PMIC_RG_AUDADCFLASHIDDTEST_ADDR                  MT6355_AUDENC_ANA_CON2
#define PMIC_RG_AUDADCFLASHIDDTEST_MASK                  0x3
#define PMIC_RG_AUDADCFLASHIDDTEST_SHIFT                 14
#define PMIC_RG_AUDADCCLKRSTB_ADDR                       MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCCLKRSTB_MASK                       0x1
#define PMIC_RG_AUDADCCLKRSTB_SHIFT                      0
#define PMIC_RG_AUDADCCLKSEL_ADDR                        MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCCLKSEL_MASK                        0x3
#define PMIC_RG_AUDADCCLKSEL_SHIFT                       1
#define PMIC_RG_AUDADCCLKSOURCE_ADDR                     MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCCLKSOURCE_MASK                     0x3
#define PMIC_RG_AUDADCCLKSOURCE_SHIFT                    3
#define PMIC_RG_AUDADCCLKGENMODE_ADDR                    MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCCLKGENMODE_MASK                    0x3
#define PMIC_RG_AUDADCCLKGENMODE_SHIFT                   5
#define PMIC_RG_AUDADCDAC0P25FS_ADDR                     MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCDAC0P25FS_MASK                     0x1
#define PMIC_RG_AUDADCDAC0P25FS_SHIFT                    7
#define PMIC_RG_AUDPREAMPAAFEN_ADDR                      MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDPREAMPAAFEN_MASK                      0x1
#define PMIC_RG_AUDPREAMPAAFEN_SHIFT                     8
#define PMIC_RG_DCCVCMBUFLPMODSEL_ADDR                   MT6355_AUDENC_ANA_CON3
#define PMIC_RG_DCCVCMBUFLPMODSEL_MASK                   0x1
#define PMIC_RG_DCCVCMBUFLPMODSEL_SHIFT                  9
#define PMIC_RG_DCCVCMBUFLPSWEN_ADDR                     MT6355_AUDENC_ANA_CON3
#define PMIC_RG_DCCVCMBUFLPSWEN_MASK                     0x1
#define PMIC_RG_DCCVCMBUFLPSWEN_SHIFT                    10
#define PMIC_RG_AUDSPAREPGA_ADDR                         MT6355_AUDENC_ANA_CON3
#define PMIC_RG_AUDSPAREPGA_MASK                         0x1F
#define PMIC_RG_AUDSPAREPGA_SHIFT                        11
#define PMIC_RG_AUDADC1STSTAGESDENB_ADDR                 MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADC1STSTAGESDENB_MASK                 0x1
#define PMIC_RG_AUDADC1STSTAGESDENB_SHIFT                0
#define PMIC_RG_AUDADC2NDSTAGERESET_ADDR                 MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADC2NDSTAGERESET_MASK                 0x1
#define PMIC_RG_AUDADC2NDSTAGERESET_SHIFT                1
#define PMIC_RG_AUDADC3RDSTAGERESET_ADDR                 MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADC3RDSTAGERESET_MASK                 0x1
#define PMIC_RG_AUDADC3RDSTAGERESET_SHIFT                2
#define PMIC_RG_AUDADCFSRESET_ADDR                       MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCFSRESET_MASK                       0x1
#define PMIC_RG_AUDADCFSRESET_SHIFT                      3
#define PMIC_RG_AUDADCWIDECM_ADDR                        MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCWIDECM_MASK                        0x1
#define PMIC_RG_AUDADCWIDECM_SHIFT                       4
#define PMIC_RG_AUDADCNOPATEST_ADDR                      MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCNOPATEST_MASK                      0x1
#define PMIC_RG_AUDADCNOPATEST_SHIFT                     5
#define PMIC_RG_AUDADCBYPASS_ADDR                        MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCBYPASS_MASK                        0x1
#define PMIC_RG_AUDADCBYPASS_SHIFT                       6
#define PMIC_RG_AUDADCFFBYPASS_ADDR                      MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCFFBYPASS_MASK                      0x1
#define PMIC_RG_AUDADCFFBYPASS_SHIFT                     7
#define PMIC_RG_AUDADCDACFBCURRENT_ADDR                  MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACFBCURRENT_MASK                  0x1
#define PMIC_RG_AUDADCDACFBCURRENT_SHIFT                 8
#define PMIC_RG_AUDADCDACIDDTEST_ADDR                    MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACIDDTEST_MASK                    0x3
#define PMIC_RG_AUDADCDACIDDTEST_SHIFT                   9
#define PMIC_RG_AUDADCDACNRZ_ADDR                        MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACNRZ_MASK                        0x1
#define PMIC_RG_AUDADCDACNRZ_SHIFT                       11
#define PMIC_RG_AUDADCNODEM_ADDR                         MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCNODEM_MASK                         0x1
#define PMIC_RG_AUDADCNODEM_SHIFT                        12
#define PMIC_RG_AUDADCDACTEST_ADDR                       MT6355_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACTEST_MASK                       0x1
#define PMIC_RG_AUDADCDACTEST_SHIFT                      13
#define PMIC_RG_AUDADCTESTDATA_ADDR                      MT6355_AUDENC_ANA_CON5
#define PMIC_RG_AUDADCTESTDATA_MASK                      0xFFFF
#define PMIC_RG_AUDADCTESTDATA_SHIFT                     0
#define PMIC_RG_AUDRCTUNEL_ADDR                          MT6355_AUDENC_ANA_CON6
#define PMIC_RG_AUDRCTUNEL_MASK                          0x1F
#define PMIC_RG_AUDRCTUNEL_SHIFT                         0
#define PMIC_RG_AUDRCTUNELSEL_ADDR                       MT6355_AUDENC_ANA_CON6
#define PMIC_RG_AUDRCTUNELSEL_MASK                       0x1
#define PMIC_RG_AUDRCTUNELSEL_SHIFT                      5
#define PMIC_RG_AUDRCTUNER_ADDR                          MT6355_AUDENC_ANA_CON6
#define PMIC_RG_AUDRCTUNER_MASK                          0x1F
#define PMIC_RG_AUDRCTUNER_SHIFT                         8
#define PMIC_RG_AUDRCTUNERSEL_ADDR                       MT6355_AUDENC_ANA_CON6
#define PMIC_RG_AUDRCTUNERSEL_MASK                       0x1
#define PMIC_RG_AUDRCTUNERSEL_SHIFT                      13
#define PMIC_RGS_AUDRCTUNELREAD_ADDR                     MT6355_AUDENC_ANA_CON7
#define PMIC_RGS_AUDRCTUNELREAD_MASK                     0x1F
#define PMIC_RGS_AUDRCTUNELREAD_SHIFT                    0
#define PMIC_RGS_AUDRCTUNERREAD_ADDR                     MT6355_AUDENC_ANA_CON7
#define PMIC_RGS_AUDRCTUNERREAD_MASK                     0x1F
#define PMIC_RGS_AUDRCTUNERREAD_SHIFT                    8
#define PMIC_RG_AUDSPAREVA30_ADDR                        MT6355_AUDENC_ANA_CON8
#define PMIC_RG_AUDSPAREVA30_MASK                        0xFF
#define PMIC_RG_AUDSPAREVA30_SHIFT                       0
#define PMIC_RG_AUDSPAREVA18_ADDR                        MT6355_AUDENC_ANA_CON8
#define PMIC_RG_AUDSPAREVA18_MASK                        0xFF
#define PMIC_RG_AUDSPAREVA18_SHIFT                       8
#define PMIC_RG_AUDDIGMICEN_ADDR                         MT6355_AUDENC_ANA_CON9
#define PMIC_RG_AUDDIGMICEN_MASK                         0x1
#define PMIC_RG_AUDDIGMICEN_SHIFT                        0
#define PMIC_RG_AUDDIGMICBIAS_ADDR                       MT6355_AUDENC_ANA_CON9
#define PMIC_RG_AUDDIGMICBIAS_MASK                       0x3
#define PMIC_RG_AUDDIGMICBIAS_SHIFT                      1
#define PMIC_RG_DMICHPCLKEN_ADDR                         MT6355_AUDENC_ANA_CON9
#define PMIC_RG_DMICHPCLKEN_MASK                         0x1
#define PMIC_RG_DMICHPCLKEN_SHIFT                        3
#define PMIC_RG_AUDDIGMICPDUTY_ADDR                      MT6355_AUDENC_ANA_CON9
#define PMIC_RG_AUDDIGMICPDUTY_MASK                      0x3
#define PMIC_RG_AUDDIGMICPDUTY_SHIFT                     4
#define PMIC_RG_AUDDIGMICNDUTY_ADDR                      MT6355_AUDENC_ANA_CON9
#define PMIC_RG_AUDDIGMICNDUTY_MASK                      0x3
#define PMIC_RG_AUDDIGMICNDUTY_SHIFT                     6
#define PMIC_RG_DMICMONEN_ADDR                           MT6355_AUDENC_ANA_CON9
#define PMIC_RG_DMICMONEN_MASK                           0x1
#define PMIC_RG_DMICMONEN_SHIFT                          8
#define PMIC_RG_DMICMONSEL_ADDR                          MT6355_AUDENC_ANA_CON9
#define PMIC_RG_DMICMONSEL_MASK                          0x7
#define PMIC_RG_DMICMONSEL_SHIFT                         9
#define PMIC_RG_AUDSPAREVMIC_ADDR                        MT6355_AUDENC_ANA_CON9
#define PMIC_RG_AUDSPAREVMIC_MASK                        0xF
#define PMIC_RG_AUDSPAREVMIC_SHIFT                       12
#define PMIC_RG_AUDPWDBMICBIAS0_ADDR                     MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDPWDBMICBIAS0_MASK                     0x1
#define PMIC_RG_AUDPWDBMICBIAS0_SHIFT                    0
#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_ADDR                MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_MASK                0x1
#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_SHIFT               1
#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_ADDR                MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_MASK                0x1
#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_SHIFT               2
#define PMIC_RG_AUDMICBIAS0DCSW0NEN_ADDR                 MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0DCSW0NEN_MASK                 0x1
#define PMIC_RG_AUDMICBIAS0DCSW0NEN_SHIFT                3
#define PMIC_RG_AUDMICBIAS0VREF_ADDR                     MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0VREF_MASK                     0x7
#define PMIC_RG_AUDMICBIAS0VREF_SHIFT                    4
#define PMIC_RG_AUDMICBIAS0LOWPEN_ADDR                   MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0LOWPEN_MASK                   0x1
#define PMIC_RG_AUDMICBIAS0LOWPEN_SHIFT                  7
#define PMIC_RG_AUDPWDBMICBIAS2_ADDR                     MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDPWDBMICBIAS2_MASK                     0x1
#define PMIC_RG_AUDPWDBMICBIAS2_SHIFT                    8
#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_ADDR                MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_MASK                0x1
#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_SHIFT               9
#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_ADDR                MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_MASK                0x1
#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_SHIFT               10
#define PMIC_RG_AUDMICBIAS0DCSW2NEN_ADDR                 MT6355_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS0DCSW2NEN_MASK                 0x1
#define PMIC_RG_AUDMICBIAS0DCSW2NEN_SHIFT                11
#define PMIC_RG_AUDPWDBMICBIAS1_ADDR                     MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDPWDBMICBIAS1_MASK                     0x1
#define PMIC_RG_AUDPWDBMICBIAS1_SHIFT                    0
#define PMIC_RG_AUDMICBIAS1DCSW1PEN_ADDR                 MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDMICBIAS1DCSW1PEN_MASK                 0x1
#define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT                1
#define PMIC_RG_AUDMICBIAS1DCSW1NEN_ADDR                 MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDMICBIAS1DCSW1NEN_MASK                 0x1
#define PMIC_RG_AUDMICBIAS1DCSW1NEN_SHIFT                2
#define PMIC_RG_AUDMICBIAS1VREF_ADDR                     MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDMICBIAS1VREF_MASK                     0x7
#define PMIC_RG_AUDMICBIAS1VREF_SHIFT                    4
#define PMIC_RG_AUDMICBIAS1LOWPEN_ADDR                   MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDMICBIAS1LOWPEN_MASK                   0x1
#define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT                  7
#define PMIC_RG_AUDMICBIAS1HVEN_ADDR                     MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDMICBIAS1HVEN_MASK                     0x1
#define PMIC_RG_AUDMICBIAS1HVEN_SHIFT                    8
#define PMIC_RG_AUDMICBIAS1HVVREF_ADDR                   MT6355_AUDENC_ANA_CON11
#define PMIC_RG_AUDMICBIAS1HVVREF_MASK                   0x1
#define PMIC_RG_AUDMICBIAS1HVVREF_SHIFT                  9
#define PMIC_RG_BANDGAPGEN_ADDR                          MT6355_AUDENC_ANA_CON11
#define PMIC_RG_BANDGAPGEN_MASK                          0x1
#define PMIC_RG_BANDGAPGEN_SHIFT                         10
#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_ADDR            MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_MASK            0x1
#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT           0
#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_ADDR            MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_MASK            0x1
#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT           1
#define PMIC_RG_AUDACCDETMICBIAS2PULLLOW_ADDR            MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETMICBIAS2PULLLOW_MASK            0x1
#define PMIC_RG_AUDACCDETMICBIAS2PULLLOW_SHIFT           2
#define PMIC_RG_AUDACCDETVIN1PULLLOW_ADDR                MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETVIN1PULLLOW_MASK                0x1
#define PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT               3
#define PMIC_RG_EINTHIRENB_ADDR                          MT6355_AUDENC_ANA_CON12
#define PMIC_RG_EINTHIRENB_MASK                          0x1
#define PMIC_RG_EINTHIRENB_SHIFT                         4
#define PMIC_RG_AUDACCDETVTHACAL_ADDR                    MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETVTHACAL_MASK                    0x1
#define PMIC_RG_AUDACCDETVTHACAL_SHIFT                   5
#define PMIC_RG_AUDACCDETVTHBCAL_ADDR                    MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETVTHBCAL_MASK                    0x1
#define PMIC_RG_AUDACCDETVTHBCAL_SHIFT                   6
#define PMIC_RG_AUDACCDETTVDET_ADDR                      MT6355_AUDENC_ANA_CON12
#define PMIC_RG_AUDACCDETTVDET_MASK                      0x1
#define PMIC_RG_AUDACCDETTVDET_SHIFT                     7
#define PMIC_RG_ACCDETSEL_ADDR                           MT6355_AUDENC_ANA_CON12
#define PMIC_RG_ACCDETSEL_MASK                           0x1
#define PMIC_RG_ACCDETSEL_SHIFT                          8
#define PMIC_RG_SWBUFMODSEL_ADDR                         MT6355_AUDENC_ANA_CON12
#define PMIC_RG_SWBUFMODSEL_MASK                         0x1
#define PMIC_RG_SWBUFMODSEL_SHIFT                        9
#define PMIC_RG_SWBUFSWEN_ADDR                           MT6355_AUDENC_ANA_CON12
#define PMIC_RG_SWBUFSWEN_MASK                           0x1
#define PMIC_RG_SWBUFSWEN_SHIFT                          10
#define PMIC_RG_EINTCOMPVTH_ADDR                         MT6355_AUDENC_ANA_CON12
#define PMIC_RG_EINTCOMPVTH_MASK                         0x1
#define PMIC_RG_EINTCOMPVTH_SHIFT                        11
#define PMIC_RG_EINTCONFIGACCDET_ADDR                    MT6355_AUDENC_ANA_CON12
#define PMIC_RG_EINTCONFIGACCDET_MASK                    0x1
#define PMIC_RG_EINTCONFIGACCDET_SHIFT                   12
#define PMIC_RG_ACCDETSPAREVA30_ADDR                     MT6355_AUDENC_ANA_CON12
#define PMIC_RG_ACCDETSPAREVA30_MASK                     0x7
#define PMIC_RG_ACCDETSPAREVA30_SHIFT                    13
#define PMIC_RG_AUDENCSPAREVA30_ADDR                     MT6355_AUDENC_ANA_CON13
#define PMIC_RG_AUDENCSPAREVA30_MASK                     0xFF
#define PMIC_RG_AUDENCSPAREVA30_SHIFT                    0
#define PMIC_RG_AUDENCSPAREVA18_ADDR                     MT6355_AUDENC_ANA_CON13
#define PMIC_RG_AUDENCSPAREVA18_MASK                     0xFF
#define PMIC_RG_AUDENCSPAREVA18_SHIFT                    8
#define PMIC_RG_PLL_EN_ADDR                              MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLL_EN_MASK                              0x1
#define PMIC_RG_PLL_EN_SHIFT                             0
#define PMIC_RG_PLLBS_RST_ADDR                           MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLLBS_RST_MASK                           0x1
#define PMIC_RG_PLLBS_RST_SHIFT                          1
#define PMIC_RG_PLL_DCKO_SEL_ADDR                        MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLL_DCKO_SEL_MASK                        0x3
#define PMIC_RG_PLL_DCKO_SEL_SHIFT                       2
#define PMIC_RG_PLL_DIV1_ADDR                            MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLL_DIV1_MASK                            0x3F
#define PMIC_RG_PLL_DIV1_SHIFT                           4
#define PMIC_RG_PLL_RLATCH_EN_ADDR                       MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLL_RLATCH_EN_MASK                       0x1
#define PMIC_RG_PLL_RLATCH_EN_SHIFT                      10
#define PMIC_RG_PLL_PDIV1_EN_ADDR                        MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLL_PDIV1_EN_MASK                        0x1
#define PMIC_RG_PLL_PDIV1_EN_SHIFT                       11
#define PMIC_RG_PLL_PDIV1_ADDR                           MT6355_AUDENC_ANA_CON14
#define PMIC_RG_PLL_PDIV1_MASK                           0xF
#define PMIC_RG_PLL_PDIV1_SHIFT                          12
#define PMIC_RG_PLL_BC_ADDR                              MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_BC_MASK                              0x3
#define PMIC_RG_PLL_BC_SHIFT                             0
#define PMIC_RG_PLL_BP_ADDR                              MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_BP_MASK                              0x3
#define PMIC_RG_PLL_BP_SHIFT                             2
#define PMIC_RG_PLL_BR_ADDR                              MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_BR_MASK                              0x3
#define PMIC_RG_PLL_BR_SHIFT                             4
#define PMIC_RG_CKO_SEL_ADDR                             MT6355_AUDENC_ANA_CON15
#define PMIC_RG_CKO_SEL_MASK                             0x3
#define PMIC_RG_CKO_SEL_SHIFT                            6
#define PMIC_RG_PLL_IBSEL_ADDR                           MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_IBSEL_MASK                           0x3
#define PMIC_RG_PLL_IBSEL_SHIFT                          8
#define PMIC_RG_PLL_CKT_SEL_ADDR                         MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_CKT_SEL_MASK                         0x3
#define PMIC_RG_PLL_CKT_SEL_SHIFT                        10
#define PMIC_RG_PLL_VCT_EN_ADDR                          MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_VCT_EN_MASK                          0x1
#define PMIC_RG_PLL_VCT_EN_SHIFT                         12
#define PMIC_RG_PLL_CKT_EN_ADDR                          MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_CKT_EN_MASK                          0x1
#define PMIC_RG_PLL_CKT_EN_SHIFT                         13
#define PMIC_RG_PLL_HPM_EN_ADDR                          MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_HPM_EN_MASK                          0x1
#define PMIC_RG_PLL_HPM_EN_SHIFT                         14
#define PMIC_RG_PLL_DCHP_EN_ADDR                         MT6355_AUDENC_ANA_CON15
#define PMIC_RG_PLL_DCHP_EN_MASK                         0x1
#define PMIC_RG_PLL_DCHP_EN_SHIFT                        15
#define PMIC_RG_PLL_CDIV_ADDR                            MT6355_AUDENC_ANA_CON16
#define PMIC_RG_PLL_CDIV_MASK                            0x7
#define PMIC_RG_PLL_CDIV_SHIFT                           0
#define PMIC_RG_VCOBAND_ADDR                             MT6355_AUDENC_ANA_CON16
#define PMIC_RG_VCOBAND_MASK                             0x7
#define PMIC_RG_VCOBAND_SHIFT                            3
#define PMIC_RG_CKDRV_EN_ADDR                            MT6355_AUDENC_ANA_CON16
#define PMIC_RG_CKDRV_EN_MASK                            0x1
#define PMIC_RG_CKDRV_EN_SHIFT                           6
#define PMIC_RG_PLL_DCHP_AEN_ADDR                        MT6355_AUDENC_ANA_CON16
#define PMIC_RG_PLL_DCHP_AEN_MASK                        0x1
#define PMIC_RG_PLL_DCHP_AEN_SHIFT                       7
#define PMIC_RG_PLL_RSVA_ADDR                            MT6355_AUDENC_ANA_CON16
#define PMIC_RG_PLL_RSVA_MASK                            0xFF
#define PMIC_RG_PLL_RSVA_SHIFT                           8
#define PMIC_RG_AUDZCDENABLE_ADDR                        MT6355_ZCD_CON0
#define PMIC_RG_AUDZCDENABLE_MASK                        0x1
#define PMIC_RG_AUDZCDENABLE_SHIFT                       0
#define PMIC_RG_AUDZCDGAINSTEPTIME_ADDR                  MT6355_ZCD_CON0
#define PMIC_RG_AUDZCDGAINSTEPTIME_MASK                  0x7
#define PMIC_RG_AUDZCDGAINSTEPTIME_SHIFT                 1
#define PMIC_RG_AUDZCDGAINSTEPSIZE_ADDR                  MT6355_ZCD_CON0
#define PMIC_RG_AUDZCDGAINSTEPSIZE_MASK                  0x3
#define PMIC_RG_AUDZCDGAINSTEPSIZE_SHIFT                 4
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_ADDR                MT6355_ZCD_CON0
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_MASK                0x1
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_SHIFT               6
#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_ADDR                MT6355_ZCD_CON0
#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_MASK                0x1
#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_SHIFT               7
#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_ADDR                MT6355_ZCD_CON0
#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_MASK                0x7
#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_SHIFT               8
#define PMIC_RG_AUDLOLGAIN_ADDR                          MT6355_ZCD_CON1
#define PMIC_RG_AUDLOLGAIN_MASK                          0x1F
#define PMIC_RG_AUDLOLGAIN_SHIFT                         0
#define PMIC_RG_AUDLORGAIN_ADDR                          MT6355_ZCD_CON1
#define PMIC_RG_AUDLORGAIN_MASK                          0x1F
#define PMIC_RG_AUDLORGAIN_SHIFT                         7
#define PMIC_RG_AUDHPLGAIN_ADDR                          MT6355_ZCD_CON2
#define PMIC_RG_AUDHPLGAIN_MASK                          0x1F
#define PMIC_RG_AUDHPLGAIN_SHIFT                         0
#define PMIC_RG_AUDHPRGAIN_ADDR                          MT6355_ZCD_CON2
#define PMIC_RG_AUDHPRGAIN_MASK                          0x1F
#define PMIC_RG_AUDHPRGAIN_SHIFT                         7
#define PMIC_RG_AUDHSGAIN_ADDR                           MT6355_ZCD_CON3
#define PMIC_RG_AUDHSGAIN_MASK                           0x1F
#define PMIC_RG_AUDHSGAIN_SHIFT                          0
#define PMIC_RG_AUDIVLGAIN_ADDR                          MT6355_ZCD_CON4
#define PMIC_RG_AUDIVLGAIN_MASK                          0x7
#define PMIC_RG_AUDIVLGAIN_SHIFT                         0
#define PMIC_RG_AUDIVRGAIN_ADDR                          MT6355_ZCD_CON4
#define PMIC_RG_AUDIVRGAIN_MASK                          0x7
#define PMIC_RG_AUDIVRGAIN_SHIFT                         8
#define PMIC_RG_AUDINTGAIN1_ADDR                         MT6355_ZCD_CON5
#define PMIC_RG_AUDINTGAIN1_MASK                         0x3F
#define PMIC_RG_AUDINTGAIN1_SHIFT                        0
#define PMIC_RG_AUDINTGAIN2_ADDR                         MT6355_ZCD_CON5
#define PMIC_RG_AUDINTGAIN2_MASK                         0x3F
#define PMIC_RG_AUDINTGAIN2_SHIFT                        8
#define PMIC_RSV_CON0_RSV_ADDR                           MT6355_RSV_CON0
#define PMIC_RSV_CON0_RSV_MASK                           0x1
#define PMIC_RSV_CON0_RSV_SHIFT                          0

typedef enum {
	PMIC_HWCID,
	PMIC_SWCID,
	PMIC_RG_SRCLKEN_IN0_EN,
	PMIC_RG_SRCLKEN_IN1_EN,
	PMIC_RG_OSC_SEL,
	PMIC_RG_SRCLKEN_IN0_HW_MODE,
	PMIC_RG_SRCLKEN_IN1_HW_MODE,
	PMIC_RG_OSC_SEL_HW_MODE,
	PMIC_RG_SRCLKEN_IN_SYNC_EN,
	PMIC_RG_OSC_EN_AUTO_OFF,
	PMIC_TEST_OUT,
	PMIC_RG_MON_FLAG_SEL,
	PMIC_RG_MON_GRP_SEL,
	PMIC_RG_NANDTREE_MODE,
	PMIC_RG_TEST_AUXADC,
	PMIC_RG_EFUSE_MODE,
	PMIC_RG_TEST_STRUP,
	PMIC_TESTMODE_SW,
	PMIC_VA12_PG_DEB,
	PMIC_VA10_PG_DEB,
	PMIC_VSRAM_GPU_PG_DEB,
	PMIC_VSRAM_MD_PG_DEB,
	PMIC_VSRAM_CORE_PG_DEB,
	PMIC_VA18_PG_DEB,
	PMIC_BUCK_RSV_PG_DEB,
	PMIC_VDRAM2_PG_DEB,
	PMIC_VDRAM1_PG_DEB,
	PMIC_VPROC12_PG_DEB,
	PMIC_VPROC11_PG_DEB,
	PMIC_VS1_PG_DEB,
	PMIC_VMODEM_PG_DEB,
	PMIC_VGPU_PG_DEB,
	PMIC_VCORE_PG_DEB,
	PMIC_VS2_PG_DEB,
	PMIC_EXT_PMIC_PG_DEB,
	PMIC_VXO18_PG_DEB,
	PMIC_VXO22_PG_DEB,
	PMIC_VUSB33_PG_DEB,
	PMIC_VSRAM_PROC_PG_DEB,
	PMIC_VIO28_PG_DEB,
	PMIC_VUFS18_PG_DEB,
	PMIC_VEMC_PG_DEB,
	PMIC_VIO18_PG_DEB,
	PMIC_STRUP_VA12_PG_STATUS,
	PMIC_STRUP_VA10_PG_STATUS,
	PMIC_STRUP_VSRAM_GPU_PG_STATUS,
	PMIC_STRUP_VSRAM_MD_PG_STATUS,
	PMIC_STRUP_VSRAM_CORE_PG_STATUS,
	PMIC_STRUP_VA18_PG_STATUS,
	PMIC_STRUP_BUCK_RSV_PG_STATUS,
	PMIC_STRUP_VDRAM2_PG_STATUS,
	PMIC_STRUP_VDRAM1_PG_STATUS,
	PMIC_STRUP_VPROC12_PG_STATUS,
	PMIC_STRUP_VPROC11_PG_STATUS,
	PMIC_STRUP_VS1_PG_STATUS,
	PMIC_STRUP_VMODEM_PG_STATUS,
	PMIC_STRUP_VGPU_PG_STATUS,
	PMIC_STRUP_VCORE_PG_STATUS,
	PMIC_STRUP_VS2_PG_STATUS,
	PMIC_STRUP_EXT_PMIC_PG_STATUS,
	PMIC_STRUP_VXO18_PG_STATUS,
	PMIC_STRUP_VXO22_PG_STATUS,
	PMIC_STRUP_VUSB33_PG_STATUS,
	PMIC_STRUP_VSRAM_PROC_PG_STATUS,
	PMIC_STRUP_VIO28_PG_STATUS,
	PMIC_STRUP_VUFS18_PG_STATUS,
	PMIC_STRUP_VEMC_PG_STATUS,
	PMIC_STRUP_VIO18_PG_STATUS,
	PMIC_STRUP_BUCK_RSV_OC_STATUS,
	PMIC_STRUP_VDRAM2_OC_STATUS,
	PMIC_STRUP_VDRAM1_OC_STATUS,
	PMIC_STRUP_VPROC12_OC_STATUS,
	PMIC_STRUP_VPROC11_OC_STATUS,
	PMIC_STRUP_VS1_OC_STATUS,
	PMIC_STRUP_VMODEM_OC_STATUS,
	PMIC_STRUP_VGPU_OC_STATUS,
	PMIC_STRUP_VCORE_OC_STATUS,
	PMIC_STRUP_VS2_OC_STATUS,
	PMIC_PMU_THERMAL_DEB,
	PMIC_STRUP_THERMAL_STATUS,
	PMIC_PMU_TEST_MODE_SCAN,
	PMIC_PWRKEY_DEB,
	PMIC_HOMEKEY_DEB,
	PMIC_RTC_XTAL_DET_DONE,
	PMIC_XOSC32_ENB_DET,
	PMIC_RTC_XTAL_DET_RSV,
	PMIC_RG_PMU_TDSEL,
	PMIC_RG_SPI_TDSEL,
	PMIC_RG_AUD_TDSEL,
	PMIC_RG_E32CAL_TDSEL,
	PMIC_RG_PMU_RDSEL,
	PMIC_RG_SPI_RDSEL,
	PMIC_RG_AUD_RDSEL,
	PMIC_RG_E32CAL_RDSEL,
	PMIC_RG_SMT_WDTRSTB_IN,
	PMIC_RG_SMT_HOMEKEY,
	PMIC_RG_SMT_SRCLKEN_IN0,
	PMIC_RG_SMT_SRCLKEN_IN1,
	PMIC_RG_SMT_RTC_32K1V8_0,
	PMIC_RG_SMT_RTC_32K1V8_1,
	PMIC_RG_SMT_SCP_VREQ_VAO,
	PMIC_RG_SMT_SPI_CLK,
	PMIC_RG_SMT_SPI_CSN,
	PMIC_RG_SMT_SPI_MOSI,
	PMIC_RG_SMT_SPI_MISO,
	PMIC_RG_SMT_AUD_CLK,
	PMIC_RG_SMT_AUD_DAT_MOSI,
	PMIC_RG_SMT_AUD_DAT_MISO,
	PMIC_RG_SMT_VOW_CLK_MISO,
	PMIC_RG_OCTL_SRCLKEN_IN0,
	PMIC_RG_OCTL_SRCLKEN_IN1,
	PMIC_RG_OCTL_RTC_32K1V8_0,
	PMIC_RG_OCTL_RTC_32K1V8_1,
	PMIC_RG_OCTL_SPI_CLK,
	PMIC_RG_OCTL_SPI_CSN,
	PMIC_RG_OCTL_SPI_MOSI,
	PMIC_RG_OCTL_SPI_MISO,
	PMIC_RG_OCTL_AUD_CLK,
	PMIC_RG_OCTL_AUD_DAT_MOSI,
	PMIC_RG_OCTL_AUD_DAT_MISO,
	PMIC_RG_OCTL_VOW_CLK_MISO,
	PMIC_RG_OCTL_HOMEKEY,
	PMIC_RG_OCTL_SCP_VREQ_VAO,
	PMIC_RG_SPI_CLK_FILTER_EN,
	PMIC_RG_SPI_CSN_FILTER_EN,
	PMIC_RG_SPI_MOSI_FILTER_EN,
	PMIC_RG_SPI_MISO_FILTER_EN,
	PMIC_RG_AUD_CLK_FILTER_EN,
	PMIC_RG_AUD_DAT_MOSI_FILTER_EN,
	PMIC_RG_AUD_DAT_MISO_FILTER_EN,
	PMIC_RG_VOW_CLK_MISO_FILTER_EN,
	PMIC_RG_WDTRSTB_IN_FILTER_EN,
	PMIC_RG_HOMEKEY_FILTER_EN,
	PMIC_RG_SRCLKEN_IN0_FILTER_EN,
	PMIC_RG_SRCLKEN_IN1_FILTER_EN,
	PMIC_RG_RTC32K_1V8_0_FILTER_EN,
	PMIC_RG_RTC32K_1V8_1_FILTER_EN,
	PMIC_RG_SCP_VREQ_VAO_FILTER_EN,
	PMIC_RG_SPI_CLK_RCSEL,
	PMIC_RG_SPI_CSN_RCSEL,
	PMIC_RG_SPI_MOSI_RCSEL,
	PMIC_RG_SPI_MISO_RCSEL,
	PMIC_RG_AUD_CLK_RCSEL,
	PMIC_RG_AUD_DAT_MOSI_RCSEL,
	PMIC_RG_AUD_DAT_MISO_RCSEL,
	PMIC_RG_VOW_CLK_MISO_RCSEL,
	PMIC_RG_WDTRSTB_IN_RCSEL,
	PMIC_RG_HOMEKEY_RCSEL,
	PMIC_RG_SRCLKEN_IN0_RCSEL,
	PMIC_RG_SRCLKEN_IN1_RCSEL,
	PMIC_RG_RTC32K_1V8_0_RCSEL,
	PMIC_RG_RTC32K_1V8_1_RCSEL,
	PMIC_RG_SCP_VREQ_VAO_RCSEL,
	PMIC_TOP_STATUS,
	PMIC_TOP_STATUS_SET,
	PMIC_TOP_STATUS_CLR,
	PMIC_RG_SRCLKEN_IN2_EN,
	PMIC_RG_SRCLKEN_IN3_EN,
	PMIC_VM_MODE,
	PMIC_RG_G_SMPS_CK_PDN,
	PMIC_RG_G_SMPS_TEST_CK_PDN,
	PMIC_RG_INTRP_CK_PDN,
	PMIC_RG_INTRP_PRE_OC_CK_PDN,
	PMIC_RG_G_BIF_1M_CK_PDN,
	PMIC_RG_BIF_X1_CK_PDN,
	PMIC_RG_BIF_X4_CK_PDN,
	PMIC_RG_BIF_X72_CK_PDN,
	PMIC_RG_AUXADC_AO_1M_CK_PDN,
	PMIC_RG_AUXADC_CK_PDN,
	PMIC_RG_AUXADC_RNG_CK_PDN,
	PMIC_RG_AUXADC_1M_CK_PDN,
	PMIC_RG_DRV_32K_CK_PDN,
	PMIC_RG_TOP_CKPDN_CON0_RSV,
	PMIC_TOP_CKPDN_CON0_SET,
	PMIC_TOP_CKPDN_CON0_CLR,
	PMIC_RG_BUCK_9M_CK_PDN,
	PMIC_RG_BUCK_1M_CK_PDN,
	PMIC_RG_BUCK_18M_CK_PDN,
	PMIC_RG_BUCK_32K_CK_PDN,
	PMIC_RG_LDO_9M_CK_PDN,
	PMIC_RG_LDO_1M_CK_PDN,
	PMIC_RG_RSV0_CK_PDN,
	PMIC_RG_BUCK_ANA_CLK_PDN,
	PMIC_RG_TRIM_75K_CK_PDN,
	PMIC_RG_CHDET_75K_CK_PDN,
	PMIC_RG_SPI_CK_PDN,
	PMIC_RG_REG_CK_PDN,
	PMIC_RG_BGR_TEST_CK_PDN,
	PMIC_RG_FQMTR_32K_CK_PDN,
	PMIC_RG_FQMTR_CK_PDN,
	PMIC_RG_BUCK_ANA_CK_PDN,
	PMIC_TOP_CKPDN_CON1_SET,
	PMIC_TOP_CKPDN_CON1_CLR,
	PMIC_RG_EOSC_CALI_TEST_CK_PDN,
	PMIC_RG_RTC_EOSC32_CK_PDN,
	PMIC_RG_RTC_SEC_32K_CK_PDN,
	PMIC_RG_RTC_MCLK_PDN,
	PMIC_RG_RTC_32K_CK_PDN,
	PMIC_RG_RTC_26M_CK_PDN,
	PMIC_RG_FGADC_FT_CK_PDN,
	PMIC_RG_FGADC_DIG_CK_PDN,
	PMIC_RG_FGADC_ANA_CK_PDN,
	PMIC_RG_STRUP_32K_CK_PDN,
	PMIC_RG_STRUP_75K_CK_PDN,
	PMIC_RG_RTC32K_1V8_0_O_PDN,
	PMIC_RG_RTC32K_1V8_1_O_PDN,
	PMIC_RG_RTC_2SEC_OFF_DET_PDN,
	PMIC_RG_SMPS_CK_DIV_PDN,
	PMIC_TOP_CKPDN_CON2_SET,
	PMIC_TOP_CKPDN_CON2_CLR,
	PMIC_RG_BATON_75K_CK_PDN,
	PMIC_RG_EFUSE_CK_PDN,
	PMIC_RG_ACCDET_CK_PDN,
	PMIC_RG_AUD_CK_PDN,
	PMIC_RG_AUDIF_CK_PDN,
	PMIC_RG_VOW32K_CK_PDN,
	PMIC_RG_VOW12M_CK_PDN,
	PMIC_RG_ZCD13M_CK_PDN,
	PMIC_RG_RTC_SEC_MCLK_PDN,
	PMIC_RG_AUXADC_32K_CK_PDN,
	PMIC_RG_EINT_32K_CK_PDN,
	PMIC_RG_TOP_CKPDN_CON3_RSV,
	PMIC_TOP_CKPDN_CON3_SET,
	PMIC_TOP_CKPDN_CON3_CLR,
	PMIC_RG_RTCDET_CK_PDN,
	PMIC_RG_RTC_75K_CK_PDN,
	PMIC_TOP_CKPDN_CON4_SET,
	PMIC_TOP_CKPDN_CON4_CLR,
	PMIC_RG_FQMTR_CK_CKSEL,
	PMIC_RG_75K_32K_SEL,
	PMIC_RG_FGADC_ANA_CK_CKSEL,
	PMIC_RG_BGR_TEST_CK_CKSEL,
	PMIC_RG_AUD_CK_CKSEL,
	PMIC_RG_AUDIF_CK_CKSEL,
	PMIC_RG_TOP_CKSEL_CON0_RSV,
	PMIC_TOP_CKSEL_CON0_SET,
	PMIC_TOP_CKSEL_CON0_CLR,
	PMIC_RG_SRCVOLTEN_SW,
	PMIC_RG_BUCK_OSC_SEL_SW,
	PMIC_RG_VOWEN_SW,
	PMIC_RG_SRCVOLTEN_MODE,
	PMIC_RG_BUCK_OSC_SEL_MODE,
	PMIC_RG_VOWEN_MODE,
	PMIC_RG_TOP_CKSEL_CON2_RSV,
	PMIC_TOP_CKSEL_CON2_SET,
	PMIC_TOP_CKSEL_CON2_CLR,
	PMIC_RG_AUXADC_CK_DIVSEL,
	PMIC_RG_LDO_9M_CK_DIVSEL,
	PMIC_RG_BUCK_9M_CK_DIVSEL,
	PMIC_RG_BIF_X4_CK_DIVSEL,
	PMIC_RG_REG_CK_DIVSEL,
	PMIC_TOP_CKDIVSEL_CON0_RSV,
	PMIC_TOP_CKDIVSEL_CON0_SET,
	PMIC_TOP_CKDIVSEL_CON0_CLR,
	PMIC_RG_G_SMPS_CK_PDN_HWEN,
	PMIC_RG_SMPS_PD_1M_CK_PDN_HWEN,
	PMIC_RG_AUXADC_CK_PDN_HWEN,
	PMIC_RG_AUXADC_RNG_CK_PDN_HWEN,
	PMIC_RG_BIF_X4_CK_PDN_HWEN,
	PMIC_RG_BIF_X72_CK_PDN_HWEN,
	PMIC_RG_RTC_26M_CK_PDN_HWEN,
	PMIC_RG_REG_CK_PDN_HWEN,
	PMIC_RG_RTC_MCLK_PDN_HWEN,
	PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN,
	PMIC_RG_EFUSE_CK_PDN_HWEN,
	PMIC_RG_RTC_SEC_MCLK_PDN_HWEN,
	PMIC_RG_AUXADC_32K_CK_PDN_HWEN,
	PMIC_RG_EINT_32K_CK_PDN_HWEN,
	PMIC_TOP_CKHWEN_CON0_RSV,
	PMIC_TOP_CKHWEN_CON0_SET,
	PMIC_TOP_CKHWEN_CON0_CLR,
	PMIC_RG_BUCK_9M_CK_PDN_HWEN,
	PMIC_RG_BUCK_1M_CK_PDN_HWEN,
	PMIC_RG_BUCK_18M_CK_PDN_HWEN,
	PMIC_RG_LDO_1M_CK_PDN_HWEN,
	PMIC_RG_LDO_9M_CK_PDN_HWEN,
	PMIC_RG_BUCK_VMODEM_1M_CK_PDN_HWEN,
	PMIC_RG_AUXADC_1M_CK_PDN_HWEN,
	PMIC_TOP_CKHWEN_RSV,
	PMIC_TOP_CKHWEN_CON1_SET,
	PMIC_TOP_CKHWEN_CON1_CLR,
	PMIC_RG_VPROC11_FREQ_SEL,
	PMIC_RG_VPROC12_FREQ_SEL,
	PMIC_RG_VCORE_FREQ_SEL,
	PMIC_RG_VGPU_FREQ_SEL,
	PMIC_RG_VDRAM1_FREQ_SEL,
	PMIC_RG_VDRAM2_FREQ_SEL,
	PMIC_RG_VMODEM_FREQ_SEL,
	PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_RSV,
	PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_SET,
	PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON0_CLR,
	PMIC_RG_VS1_FREQ_SEL,
	PMIC_RG_VS2_FREQ_SEL,
	PMIC_RG_VPA_PHS_SEL,
	PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_RSV,
	PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_SET,
	PMIC_TOP_BUCK_ANACK_FREQ_SEL_CON1_CLR,
	PMIC_RG_PMU75K_CK_TST_DIS,
	PMIC_RG_SMPS_CK_TST_DIS,
	PMIC_RG_RTC32K_CK_TST_DIS,
	PMIC_RG_FG_CK_TST_DIS,
	PMIC_RG_RTC26M_CK_TST_DIS,
	PMIC_RG_AUD26M_CK_TST_DIS,
	PMIC_RG_VOW12M_CK_TST_DIS,
	PMIC_TOP_CKTST_CON0_RSV,
	PMIC_RG_BUCK_ANA_AUTO_OFF_DIS,
	PMIC_RG_AUXADC_CK_TSTSEL,
	PMIC_RG_FQMTR_CK_TSTSEL,
	PMIC_RG_RTCDET_CK_TSTSEL,
	PMIC_RG_RTC_EOSC32_CK_TSTSEL,
	PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL,
	PMIC_RG_RTC26M_CK_TSTSEL,
	PMIC_RG_RTC32K_CK_TSTSEL,
	PMIC_RG_FG_CK_TSTSEL,
	PMIC_RG_FGADC_ANA_CK_TSTSEL,
	PMIC_RG_BGR_TEST_CK_TSTSEL,
	PMIC_RG_PMU75K_CK_TSTSEL,
	PMIC_RG_SMPS_CK_TSTSEL,
	PMIC_RG_AUD_CK_TSTSEL,
	PMIC_RG_AUDIF_CK_TSTSEL,
	PMIC_RG_AUD26M_CK_TSTSEL,
	PMIC_RG_VOW12M_CK_TSTSEL,
	PMIC_RG_CLKSQ_EN_AUD,
	PMIC_RG_CLKSQ_EN_FQR,
	PMIC_RG_CLKSQ_EN_AUX_AP,
	PMIC_RG_CLKSQ_EN_AUX_MD,
	PMIC_RG_CLKSQ_EN_AUX_GPS,
	PMIC_RG_CLKSQ_EN_AUX_RSV,
	PMIC_RG_CLKSQ_EN_AUX_AP_MODE,
	PMIC_RG_CLKSQ_EN_AUX_MD_MODE,
	PMIC_RG_CLKSQ_IN_SEL_VA18,
	PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL,
	PMIC_TOP_CLKSQ_RSV,
	PMIC_DA_CLKSQ_EN_VA18,
	PMIC_TOP_CLKSQ_SET,
	PMIC_TOP_CLKSQ_CLR,
	PMIC_RG_CLKSQ_RTC_EN,
	PMIC_RG_CLKSQ_RTC_EN_HW_MODE,
	PMIC_TOP_CLKSQ_RTC_RSV0,
	PMIC_RG_ENBB_SEL,
	PMIC_RG_XOSC_EN_SEL,
	PMIC_TOP_CLKSQ_RTC_RSV1,
	PMIC_DA_CLKSQ_EN_VDIG18,
	PMIC_TOP_CLKSQ_RTC_SET,
	PMIC_TOP_CLKSQ_RTC_CLR,
	PMIC_RG_OSC_75K_TRIM,
	PMIC_RG_OSC_75K_TRIM_EN,
	PMIC_RG_OSC_75K_TRIM_RATE,
	PMIC_DA_OSC_75K_TRIM,
	PMIC_RG_G_SMPS_CK_PDN_SRCLKEN0_EN,
	PMIC_RG_G_SMPS_CK_PDN_SRCLKEN1_EN,
	PMIC_RG_G_SMPS_CK_PDN_SRCLKEN2_EN,
	PMIC_RG_G_SMPS_CK_PDN_BUCK_OSC_SEL_EN,
	PMIC_RG_G_SMPS_CK_PDN_VOWEN_EN,
	PMIC_RG_OSC_SEL_SRCLKEN0_EN,
	PMIC_RG_OSC_SEL_SRCLKEN1_EN,
	PMIC_RG_OSC_SEL_SRCLKEN2_EN,
	PMIC_RG_OSC_SEL_BUCK_LDO_EN,
	PMIC_RG_OSC_SEL_VOWEN_EN,
	PMIC_RG_CLK_RSV,
	PMIC_TOP_CLK_CON0_SET,
	PMIC_TOP_CLK_CON0_CLR,
	PMIC_RG_VPROC2_CKMUX_EN,
	PMIC_RG_VPA_SW_PDN_EN,
	PMIC_RG_LDO_1M_PDN_W_OSC_SEL,
	PMIC_RG_BUCK_1M_PDN_W_OSC_SEL,
	PMIC_RG_CLKCTL_RSV0,
	PMIC_TOP_CLK_CON1_SET,
	PMIC_TOP_CLK_CON1_CLR,
	PMIC_RG_DCXO_PWRKEY_RSTB_SEL,
	PMIC_RG_EFUSE_MAN_RST,
	PMIC_RG_AUXADC_RST,
	PMIC_RG_AUXADC_REG_RST,
	PMIC_RG_AUDIO_RST,
	PMIC_RG_ACCDET_RST,
	PMIC_RG_BIF_RST,
	PMIC_RG_DRIVER_RST,
	PMIC_RG_FGADC_RST,
	PMIC_RG_FQMTR_RST,
	PMIC_RG_RTC_RST,
	PMIC_RG_TYPE_C_CC_RST,
	PMIC_RG_CHRWDT_RST,
	PMIC_RG_ZCD_RST,
	PMIC_RG_AUDNCP_RST,
	PMIC_RG_CLK_TRIM_RST,
	PMIC_RG_BUCK_SRCLKEN_RST,
	PMIC_TOP_RST_CON0_SET,
	PMIC_TOP_RST_CON0_CLR,
	PMIC_RG_STRUP_LONG_PRESS_RST,
	PMIC_RG_BUCK_PROT_PMPP_RST,
	PMIC_RG_SPK_RST,
	PMIC_RG_CHRDET_RST,
	PMIC_RG_BUCK_LDO_FT_TESTMODE_RST,
	PMIC_RG_BATON_RST,
	PMIC_RG_FGADC_RST_SRC_SEL,
	PMIC_RG_LDO_CALI_RST,
	PMIC_RG_PSEQ_PWRMSK_RST_SEL,
	PMIC_TOP_RST_CON1_RSV,
	PMIC_TOP_RST_CON1_SET,
	PMIC_TOP_RST_CON1_CLR,
	PMIC_RG_CHR_LDO_DET_MODE,
	PMIC_RG_CHR_LDO_DET_SW,
	PMIC_RG_CHRWDT_FLAG_MODE,
	PMIC_RG_CHRWDT_FLAG_SW,
	PMIC_TOP_RST_CON2_RSV,
	PMIC_RG_WDTRSTB_EN,
	PMIC_RG_WDTRSTB_MODE,
	PMIC_WDTRSTB_STATUS,
	PMIC_WDTRSTB_STATUS_CLR,
	PMIC_RG_WDTRSTB_FB_EN,
	PMIC_RG_WDTRSTB_DEB,
	PMIC_RG_HOMEKEY_RST_EN,
	PMIC_RG_PWRKEY_RST_EN,
	PMIC_RG_PWRRST_TMR_DIS,
	PMIC_RG_PWRKEY_RST_TD,
	PMIC_TOP_RST_MISC_RSV,
	PMIC_TOP_RST_MISC_SET,
	PMIC_TOP_RST_MISC_CLR,
	PMIC_VPWRIN_RSTB_STATUS,
	PMIC_DDLO_RSTB_STATUS,
	PMIC_UVLO_RSTB_STATUS,
	PMIC_RTC_DDLO_RSTB_STATUS,
	PMIC_CHRWDT_REG_RSTB_STATUS,
	PMIC_CHRDET_REG_RSTB_STATUS,
	PMIC_BWDT_DDLO_RSTB_STATUS,
	PMIC_TOP_RST_STATUS_RSV,
	PMIC_TOP_RST_STATUS_SET,
	PMIC_TOP_RST_STATUS_CLR,
	PMIC_TOP_RST_RSV_CON0,
	PMIC_TOP_RST_RSV_CON1,
	PMIC_BANK_FQMTR_SWRST,
	PMIC_BANK_SPI_SWRST,
	PMIC_BANK_STRUP_SWRST,
	PMIC_BANK_BUCK_SWRST,
	PMIC_BANK_BUCK_ANA_SWRST,
	PMIC_BANK_WDTDBG_SWRST,
	PMIC_BANK_LDO_0_SWRST,
	PMIC_BANK_LDO_1_SWRST,
	PMIC_BANK_LDO_ANA_SWRST,
	PMIC_BANK_ACCDET_SWRST,
	PMIC_BANK_EFUSE_SWRST,
	PMIC_BANK_DCXO_SWRST,
	PMIC_BANK_PCHR_SWRST,
	PMIC_BANK_GPIO_SWRST,
	PMIC_BANK_EOSC_CALI_SWRST,
	PMIC_BANK_VRTC_PWM_SWRST,
	PMIC_TOP_RST_BANK_CON0_SET,
	PMIC_TOP_RST_BANK_CON0_CLR,
	PMIC_BANK_RTC_SWRST,
	PMIC_BANK_RTC_SEC_SWRST,
	PMIC_BANK_BIF_SWRST,
	PMIC_BANK_FGADC_SWRST,
	PMIC_BANK_AUXADC_SWRST,
	PMIC_BANK_DRIVER_SWRST,
	PMIC_BANK_AUDIO_SWRST,
	PMIC_BANK_AUDZCD_SWRST,
	PMIC_TOP_RST_BANK_CON1_RSV,
	PMIC_TOP_RST_BANK_CON1_SET,
	PMIC_TOP_RST_BANK_CON1_CLR,
	PMIC_RG_INT_EN_PWRKEY,
	PMIC_RG_INT_EN_HOMEKEY,
	PMIC_RG_INT_EN_PWRKEY_R,
	PMIC_RG_INT_EN_HOMEKEY_R,
	PMIC_RG_INT_EN_NI_LBAT_INT,
	PMIC_RG_INT_EN_CHRDET,
	PMIC_RG_INT_EN_CHRDET_EDGE,
	PMIC_RG_INT_EN_BATON_LV,
	PMIC_RG_INT_EN_BATON_HV,
	PMIC_RG_INT_EN_BATON_BAT_IN,
	PMIC_RG_INT_EN_BATON_BAT_OUT,
	PMIC_RG_INT_EN_RTC,
	PMIC_RG_INT_EN_RTC_NSEC,
	PMIC_RG_INT_EN_BIF,
	PMIC_RG_INT_EN_VCDT_HV_DET,
	PMIC_INT_CON0_SET,
	PMIC_INT_CON0_CLR,
	PMIC_RG_INT_EN_THR_H,
	PMIC_RG_INT_EN_THR_L,
	PMIC_RG_INT_EN_BAT_H,
	PMIC_RG_INT_EN_BAT_L,
	PMIC_RG_INT_EN_BAT2_H,
	PMIC_RG_INT_EN_BAT2_L,
	PMIC_RG_INT_EN_BAT_TEMP_H,
	PMIC_RG_INT_EN_BAT_TEMP_L,
	PMIC_RG_INT_EN_AUXADC_IMP,
	PMIC_RG_INT_EN_NAG_C_DLTV,
	PMIC_RG_INT_EN_JEITA_HOT,
	PMIC_RG_INT_EN_JEITA_WARM,
	PMIC_RG_INT_EN_JEITA_COOL,
	PMIC_RG_INT_EN_JEITA_COLD,
	PMIC_INT_CON1_SET,
	PMIC_INT_CON1_CLR,
	PMIC_RG_INT_EN_VPROC11_OC,
	PMIC_RG_INT_EN_VPROC12_OC,
	PMIC_RG_INT_EN_VCORE_OC,
	PMIC_RG_INT_EN_VGPU_OC,
	PMIC_RG_INT_EN_VDRAM1_OC,
	PMIC_RG_INT_EN_VDRAM2_OC,
	PMIC_RG_INT_EN_VMODEM_OC,
	PMIC_RG_INT_EN_VS1_OC,
	PMIC_RG_INT_EN_VS2_OC,
	PMIC_RG_INT_EN_VPA_OC,
	PMIC_RG_INT_EN_VCORE_PREOC,
	PMIC_RG_INT_EN_VA10_OC,
	PMIC_RG_INT_EN_VA12_OC,
	PMIC_RG_INT_EN_VA18_OC,
	PMIC_RG_INT_EN_VBIF28_OC,
	PMIC_RG_INT_EN_VCAMA1_OC,
	PMIC_INT_CON2_SET,
	PMIC_INT_CON2_CLR,
	PMIC_RG_INT_EN_VCAMA2_OC,
	PMIC_RG_INT_EN_VXO18_OC,
	PMIC_RG_INT_EN_VCAMD1_OC,
	PMIC_RG_INT_EN_VCAMD2_OC,
	PMIC_RG_INT_EN_VCAMIO_OC,
	PMIC_RG_INT_EN_VCN18_OC,
	PMIC_RG_INT_EN_VCN28_OC,
	PMIC_RG_INT_EN_VCN33_OC,
	PMIC_RG_INT_EN_VTCXO24_OC,
	PMIC_RG_INT_EN_VEMC_OC,
	PMIC_RG_INT_EN_VFE28_OC,
	PMIC_RG_INT_EN_VGP_OC,
	PMIC_RG_INT_EN_VLDO28_OC,
	PMIC_RG_INT_EN_VIO18_OC,
	PMIC_RG_INT_EN_VIO28_OC,
	PMIC_RG_INT_EN_VMC_OC,
	PMIC_INT_CON3_SET,
	PMIC_INT_CON3_CLR,
	PMIC_RG_INT_EN_VMCH_OC,
	PMIC_RG_INT_EN_VMIPI_OC,
	PMIC_RG_INT_EN_VRF12_OC,
	PMIC_RG_INT_EN_VRF18_1_OC,
	PMIC_RG_INT_EN_VRF18_2_OC,
	PMIC_RG_INT_EN_VSIM1_OC,
	PMIC_RG_INT_EN_VSIM2_OC,
	PMIC_RG_INT_EN_VGP2_OC,
	PMIC_RG_INT_EN_VSRAM_CORE_OC,
	PMIC_RG_INT_EN_VSRAM_PROC_OC,
	PMIC_RG_INT_EN_VSRAM_GPU_OC,
	PMIC_RG_INT_EN_VSRAM_MD_OC,
	PMIC_RG_INT_EN_VUFS18_OC,
	PMIC_RG_INT_EN_VUSB33_OC,
	PMIC_RG_INT_EN_VXO22_OC,
	PMIC_INT_CON4_SET,
	PMIC_INT_CON4_CLR,
	PMIC_RG_INT_EN_FG_BAT0_H,
	PMIC_RG_INT_EN_FG_BAT0_L,
	PMIC_RG_INT_EN_FG_CUR_H,
	PMIC_RG_INT_EN_FG_CUR_L,
	PMIC_RG_INT_EN_FG_ZCV,
	PMIC_RG_INT_EN_FG_BAT1_H,
	PMIC_RG_INT_EN_FG_BAT1_L,
	PMIC_RG_INT_EN_FG_N_CHARGE_L,
	PMIC_RG_INT_EN_FG_IAVG_H,
	PMIC_RG_INT_EN_FG_IAVG_L,
	PMIC_RG_INT_EN_FG_TIME_H,
	PMIC_RG_INT_EN_FG_DISCHARGE,
	PMIC_RG_INT_EN_FG_CHARGE,
	PMIC_RG_INT_EN_CON5,
	PMIC_INT_CON5_SET,
	PMIC_INT_CON5_CLR,
	PMIC_RG_INT_EN_AUDIO,
	PMIC_RG_INT_EN_MAD,
	PMIC_RG_INT_EN_EINT_RTC32K_1V8_1,
	PMIC_RG_INT_EN_EINT_AUD_CLK,
	PMIC_RG_INT_EN_EINT_AUD_DAT_MOSI,
	PMIC_RG_INT_EN_EINT_AUD_DAT_MISO,
	PMIC_RG_INT_EN_EINT_VOW_CLK_MISO,
	PMIC_RG_INT_EN_ACCDET,
	PMIC_RG_INT_EN_ACCDET_EINT,
	PMIC_RG_INT_EN_SPI_CMD_ALERT,
	PMIC_INT_CON6_SET,
	PMIC_INT_CON6_CLR,
	PMIC_RG_INT_MASK_PWRKEY,
	PMIC_RG_INT_MASK_HOMEKEY,
	PMIC_RG_INT_MASK_PWRKEY_R,
	PMIC_RG_INT_MASK_HOMEKEY_R,
	PMIC_RG_INT_MASK_NI_LBAT_INT,
	PMIC_RG_INT_MASK_CHRDET,
	PMIC_RG_INT_MASK_CHRDET_EDGE,
	PMIC_RG_INT_MASK_BATON_LV,
	PMIC_RG_INT_MASK_BATON_HV,
	PMIC_RG_INT_MASK_BATON_BAT_IN,
	PMIC_RG_INT_MASK_BATON_BAT_OUT,
	PMIC_RG_INT_MASK_RTC,
	PMIC_RG_INT_MASK_RTC_NSEC,
	PMIC_RG_INT_MASK_BIF,
	PMIC_RG_INT_MASK_VCDT_HV_DET,
	PMIC_INT_MASK_CON0_SET,
	PMIC_INT_MASK_CON0_CLR,
	PMIC_RG_INT_MASK_THR_H,
	PMIC_RG_INT_MASK_THR_L,
	PMIC_RG_INT_MASK_BAT_H,
	PMIC_RG_INT_MASK_BAT_L,
	PMIC_RG_INT_MASK_BAT2_H,
	PMIC_RG_INT_MASK_BAT2_L,
	PMIC_RG_INT_MASK_BAT_TEMP_H,
	PMIC_RG_INT_MASK_BAT_TEMP_L,
	PMIC_RG_INT_MASK_AUXADC_IMP,
	PMIC_RG_INT_MASK_NAG_C_DLTV,
	PMIC_RG_INT_MASK_JEITA_HOT,
	PMIC_RG_INT_MASK_JEITA_WARM,
	PMIC_RG_INT_MASK_JEITA_COOL,
	PMIC_RG_INT_MASK_JEITA_COLD,
	PMIC_INT_MASK_CON1_SET,
	PMIC_INT_MASK_CON1_CLR,
	PMIC_RG_INT_MASK_VPROC11_OC,
	PMIC_RG_INT_MASK_VPROC12_OC,
	PMIC_RG_INT_MASK_VCORE_OC,
	PMIC_RG_INT_MASK_VGPU_OC,
	PMIC_RG_INT_MASK_VDRAM1_OC,
	PMIC_RG_INT_MASK_VDRAM2_OC,
	PMIC_RG_INT_MASK_VMODEM_OC,
	PMIC_RG_INT_MASK_VS1_OC,
	PMIC_RG_INT_MASK_VS2_OC,
	PMIC_RG_INT_MASK_VPA_OC,
	PMIC_RG_INT_MASK_VCORE_PREOC,
	PMIC_RG_INT_MASK_VA10_OC,
	PMIC_RG_INT_MASK_VA12_OC,
	PMIC_RG_INT_MASK_VA18_OC,
	PMIC_RG_INT_MASK_VBIF28_OC,
	PMIC_RG_INT_MASK_VCAMA1_OC,
	PMIC_INT_MASK_CON2_SET,
	PMIC_INT_MASK_CON2_CLR,
	PMIC_RG_INT_MASK_VCAMA2_OC,
	PMIC_RG_INT_MASK_VXO18_OC,
	PMIC_RG_INT_MASK_VCAMD1_OC,
	PMIC_RG_INT_MASK_VCAMD2_OC,
	PMIC_RG_INT_MASK_VCAMIO_OC,
	PMIC_RG_INT_MASK_VCN18_OC,
	PMIC_RG_INT_MASK_VCN28_OC,
	PMIC_RG_INT_MASK_VCN33_OC,
	PMIC_RG_INT_MASK_VTCXO24_OC,
	PMIC_RG_INT_MASK_VEMC_OC,
	PMIC_RG_INT_MASK_VFE28_OC,
	PMIC_RG_INT_MASK_VGP_OC,
	PMIC_RG_INT_MASK_VLDO28_OC,
	PMIC_RG_INT_MASK_VIO18_OC,
	PMIC_RG_INT_MASK_VIO28_OC,
	PMIC_RG_INT_MASK_VMC_OC,
	PMIC_INT_MASK_CON3_SET,
	PMIC_INT_MASK_CON3_CLR,
	PMIC_RG_INT_MASK_VMCH_OC,
	PMIC_RG_INT_MASK_VMIPI_OC,
	PMIC_RG_INT_MASK_VRF12_OC,
	PMIC_RG_INT_MASK_VRF18_1_OC,
	PMIC_RG_INT_MASK_VRF18_2_OC,
	PMIC_RG_INT_MASK_VSIM1_OC,
	PMIC_RG_INT_MASK_VSIM2_OC,
	PMIC_RG_INT_MASK_VGP2_OC,
	PMIC_RG_INT_MASK_VSRAM_CORE_OC,
	PMIC_RG_INT_MASK_VSRAM_PROC_OC,
	PMIC_RG_INT_MASK_VSRAM_GPU_OC,
	PMIC_RG_INT_MASK_VSRAM_MD_OC,
	PMIC_RG_INT_MASK_VUFS18_OC,
	PMIC_RG_INT_MASK_VUSB33_OC,
	PMIC_RG_INT_MASK_VXO22_OC,
	PMIC_INT_MASK_CON4_SET,
	PMIC_INT_MASK_CON4_CLR,
	PMIC_RG_INT_MASK_FG_BAT0_H,
	PMIC_RG_INT_MASK_FG_BAT0_L,
	PMIC_RG_INT_MASK_FG_CUR_H,
	PMIC_RG_INT_MASK_FG_CUR_L,
	PMIC_RG_INT_MASK_FG_ZCV,
	PMIC_RG_INT_MASK_FG_BAT1_H,
	PMIC_RG_INT_MASK_FG_BAT1_L,
	PMIC_RG_INT_MASK_FG_N_CHARGE_L,
	PMIC_RG_INT_MASK_FG_IAVG_H,
	PMIC_RG_INT_MASK_FG_IAVG_L,
	PMIC_RG_INT_MASK_FG_TIME_H,
	PMIC_RG_INT_MASK_FG_DISCHARGE,
	PMIC_RG_INT_MASK_FG_CHARGE,
	PMIC_RG_INT_MASK_CON5,
	PMIC_INT_MASK_CON5_SET,
	PMIC_INT_MASK_CON5_CLR,
	PMIC_RG_INT_MASK_AUDIO,
	PMIC_RG_INT_MASK_MAD,
	PMIC_RG_INT_MASK_EINT_RTC32K_1V8_1,
	PMIC_RG_INT_MASK_EINT_AUD_CLK,
	PMIC_RG_INT_MASK_EINT_AUD_DAT_MOSI,
	PMIC_RG_INT_MASK_EINT_AUD_DAT_MISO,
	PMIC_RG_INT_MASK_EINT_VOW_CLK_MISO,
	PMIC_RG_INT_MASK_ACCDET,
	PMIC_RG_INT_MASK_ACCDET_EINT,
	PMIC_RG_INT_MASK_SPI_CMD_ALERT,
	PMIC_INT_MASK_CON6_SET,
	PMIC_INT_MASK_CON6_CLR,
	PMIC_RG_INT_STATUS_PWRKEY,
	PMIC_RG_INT_STATUS_HOMEKEY,
	PMIC_RG_INT_STATUS_PWRKEY_R,
	PMIC_RG_INT_STATUS_HOMEKEY_R,
	PMIC_RG_INT_STATUS_NI_LBAT_INT,
	PMIC_RG_INT_STATUS_CHRDET,
	PMIC_RG_INT_STATUS_CHRDET_EDGE,
	PMIC_RG_INT_STATUS_BATON_LV,
	PMIC_RG_INT_STATUS_BATON_HV,
	PMIC_RG_INT_STATUS_BATON_BAT_IN,
	PMIC_RG_INT_STATUS_BATON_BAT_OUT,
	PMIC_RG_INT_STATUS_RTC,
	PMIC_RG_INT_STATUS_RTC_NSEC,
	PMIC_RG_INT_STATUS_BIF,
	PMIC_RG_INT_STATUS_VCDT_HV_DET,
	PMIC_RG_INT_STATUS_THR_H,
	PMIC_RG_INT_STATUS_THR_L,
	PMIC_RG_INT_STATUS_BAT_H,
	PMIC_RG_INT_STATUS_BAT_L,
	PMIC_RG_INT_STATUS_BAT2_H,
	PMIC_RG_INT_STATUS_BAT2_L,
	PMIC_RG_INT_STATUS_BAT_TEMP_H,
	PMIC_RG_INT_STATUS_BAT_TEMP_L,
	PMIC_RG_INT_STATUS_AUXADC_IMP,
	PMIC_RG_INT_STATUS_NAG_C_DLTV,
	PMIC_RG_INT_STATUS_JEITA_HOT,
	PMIC_RG_INT_STATUS_JEITA_WARM,
	PMIC_RG_INT_STATUS_JEITA_COOL,
	PMIC_RG_INT_STATUS_JEITA_COLD,
	PMIC_RG_INT_STATUS_VPROC11_OC,
	PMIC_RG_INT_STATUS_VPROC12_OC,
	PMIC_RG_INT_STATUS_VCORE_OC,
	PMIC_RG_INT_STATUS_VGPU_OC,
	PMIC_RG_INT_STATUS_VDRAM1_OC,
	PMIC_RG_INT_STATUS_VDRAM2_OC,
	PMIC_RG_INT_STATUS_VMODEM_OC,
	PMIC_RG_INT_STATUS_VS1_OC,
	PMIC_RG_INT_STATUS_VS2_OC,
	PMIC_RG_INT_STATUS_VPA_OC,
	PMIC_RG_INT_STATUS_VCORE_PREOC,
	PMIC_RG_INT_STATUS_VA10_OC,
	PMIC_RG_INT_STATUS_VA12_OC,
	PMIC_RG_INT_STATUS_VA18_OC,
	PMIC_RG_INT_STATUS_VBIF28_OC,
	PMIC_RG_INT_STATUS_VCAMA1_OC,
	PMIC_RG_INT_STATUS_VCAMA2_OC,
	PMIC_RG_INT_STATUS_VXO18_OC,
	PMIC_RG_INT_STATUS_VCAMD1_OC,
	PMIC_RG_INT_STATUS_VCAMD2_OC,
	PMIC_RG_INT_STATUS_VCAMIO_OC,
	PMIC_RG_INT_STATUS_VCN18_OC,
	PMIC_RG_INT_STATUS_VCN28_OC,
	PMIC_RG_INT_STATUS_VCN33_OC,
	PMIC_RG_INT_STATUS_VTCXO24_OC,
	PMIC_RG_INT_STATUS_VEMC_OC,
	PMIC_RG_INT_STATUS_VFE28_OC,
	PMIC_RG_INT_STATUS_VGP_OC,
	PMIC_RG_INT_STATUS_VLDO28_OC,
	PMIC_RG_INT_STATUS_VIO18_OC,
	PMIC_RG_INT_STATUS_VIO28_OC,
	PMIC_RG_INT_STATUS_VMC_OC,
	PMIC_RG_INT_STATUS_VMCH_OC,
	PMIC_RG_INT_STATUS_VMIPI_OC,
	PMIC_RG_INT_STATUS_VRF12_OC,
	PMIC_RG_INT_STATUS_VRF18_1_OC,
	PMIC_RG_INT_STATUS_VRF18_2_OC,
	PMIC_RG_INT_STATUS_VSIM1_OC,
	PMIC_RG_INT_STATUS_VSIM2_OC,
	PMIC_RG_INT_STATUS_VGP2_OC,
	PMIC_RG_INT_STATUS_VSRAM_CORE_OC,
	PMIC_RG_INT_STATUS_VSRAM_PROC_OC,
	PMIC_RG_INT_STATUS_VSRAM_GPU_OC,
	PMIC_RG_INT_STATUS_VSRAM_MD_OC,
	PMIC_RG_INT_STATUS_VUFS18_OC,
	PMIC_RG_INT_STATUS_VUSB33_OC,
	PMIC_RG_INT_STATUS_VXO22_OC,
	PMIC_RG_INT_STATUS_FG_BAT0_H,
	PMIC_RG_INT_STATUS_FG_BAT0_L,
	PMIC_RG_INT_STATUS_FG_CUR_H,
	PMIC_RG_INT_STATUS_FG_CUR_L,
	PMIC_RG_INT_STATUS_FG_ZCV,
	PMIC_RG_INT_STATUS_FG_BAT1_H,
	PMIC_RG_INT_STATUS_FG_BAT1_L,
	PMIC_RG_INT_STATUS_FG_N_CHARGE_L,
	PMIC_RG_INT_STATUS_FG_IAVG_H,
	PMIC_RG_INT_STATUS_FG_IAVG_L,
	PMIC_RG_INT_STATUS_FG_TIME_H,
	PMIC_RG_INT_STATUS_FG_DISCHARGE,
	PMIC_RG_INT_STATUS_FG_CHARGE,
	PMIC_RG_INT_STATUS_CON5,
	PMIC_RG_INT_STATUS_AUDIO,
	PMIC_RG_INT_STATUS_MAD,
	PMIC_RG_INT_STATUS_EINT_RTC32K_1V8_1,
	PMIC_RG_INT_STATUS_EINT_AUD_CLK,
	PMIC_RG_INT_STATUS_EINT_AUD_DAT_MOSI,
	PMIC_RG_INT_STATUS_EINT_AUD_DAT_MISO,
	PMIC_RG_INT_STATUS_EINT_VOW_CLK_MISO,
	PMIC_RG_INT_STATUS_ACCDET,
	PMIC_RG_INT_STATUS_ACCDET_EINT,
	PMIC_RG_INT_STATUS_SPI_CMD_ALERT,
	PMIC_RG_INT_RAW_STATUS_PWRKEY,
	PMIC_RG_INT_RAW_STATUS_HOMEKEY,
	PMIC_RG_INT_RAW_STATUS_PWRKEY_R,
	PMIC_RG_INT_RAW_STATUS_HOMEKEY_R,
	PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT,
	PMIC_RG_INT_RAW_STATUS_CHRDET,
	PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE,
	PMIC_RG_INT_RAW_STATUS_BATON_LV,
	PMIC_RG_INT_RAW_STATUS_BATON_HV,
	PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN,
	PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT,
	PMIC_RG_INT_RAW_STATUS_RTC,
	PMIC_RG_INT_RAW_STATUS_RTC_NSEC,
	PMIC_RG_INT_RAW_STATUS_BIF,
	PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET,
	PMIC_RG_INT_RAW_STATUS_THR_H,
	PMIC_RG_INT_RAW_STATUS_THR_L,
	PMIC_RG_INT_RAW_STATUS_BAT_H,
	PMIC_RG_INT_RAW_STATUS_BAT_L,
	PMIC_RG_INT_RAW_STATUS_BAT2_H,
	PMIC_RG_INT_RAW_STATUS_BAT2_L,
	PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H,
	PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L,
	PMIC_RG_INT_RAW_STATUS_AUXADC_IMP,
	PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV,
	PMIC_RG_INT_RAW_STATUS_JEITA_HOT,
	PMIC_RG_INT_RAW_STATUS_JEITA_WARM,
	PMIC_RG_INT_RAW_STATUS_JEITA_COOL,
	PMIC_RG_INT_RAW_STATUS_JEITA_COLD,
	PMIC_RG_INT_RAW_STATUS_VPROC11_OC,
	PMIC_RG_INT_RAW_STATUS_VPROC12_OC,
	PMIC_RG_INT_RAW_STATUS_VCORE_OC,
	PMIC_RG_INT_RAW_STATUS_VGPU_OC,
	PMIC_RG_INT_RAW_STATUS_VDRAM1_OC,
	PMIC_RG_INT_RAW_STATUS_VDRAM2_OC,
	PMIC_RG_INT_RAW_STATUS_VMODEM_OC,
	PMIC_RG_INT_RAW_STATUS_VS1_OC,
	PMIC_RG_INT_RAW_STATUS_VS2_OC,
	PMIC_RG_INT_RAW_STATUS_VPA_OC,
	PMIC_RG_INT_RAW_STATUS_VCORE_PREOC,
	PMIC_RG_INT_RAW_STATUS_VA10_OC,
	PMIC_RG_INT_RAW_STATUS_VA12_OC,
	PMIC_RG_INT_RAW_STATUS_VA18_OC,
	PMIC_RG_INT_RAW_STATUS_VBIF28_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMA1_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMA2_OC,
	PMIC_RG_INT_RAW_STATUS_VXO18_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMD1_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMD2_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMIO_OC,
	PMIC_RG_INT_RAW_STATUS_VCN18_OC,
	PMIC_RG_INT_RAW_STATUS_VCN28_OC,
	PMIC_RG_INT_RAW_STATUS_VCN33_OC,
	PMIC_RG_INT_RAW_STATUS_VTCXO24_OC,
	PMIC_RG_INT_RAW_STATUS_VEMC_OC,
	PMIC_RG_INT_RAW_STATUS_VFE28_OC,
	PMIC_RG_INT_RAW_STATUS_VGP_OC,
	PMIC_RG_INT_RAW_STATUS_VLDO28_OC,
	PMIC_RG_INT_RAW_STATUS_VIO18_OC,
	PMIC_RG_INT_RAW_STATUS_VIO28_OC,
	PMIC_RG_INT_RAW_STATUS_VMC_OC,
	PMIC_RG_INT_RAW_STATUS_VMCH_OC,
	PMIC_RG_INT_RAW_STATUS_VMIPI_OC,
	PMIC_RG_INT_RAW_STATUS_VRF12_OC,
	PMIC_RG_INT_RAW_STATUS_VRF18_1_OC,
	PMIC_RG_INT_RAW_STATUS_VRF18_2_OC,
	PMIC_RG_INT_RAW_STATUS_VSIM1_OC,
	PMIC_RG_INT_RAW_STATUS_VSIM2_OC,
	PMIC_RG_INT_RAW_STATUS_VGP2_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_CORE_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_PROC_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_MD_OC,
	PMIC_RG_INT_RAW_STATUS_VUFS18_OC,
	PMIC_RG_INT_RAW_STATUS_VUSB33_OC,
	PMIC_RG_INT_RAW_STATUS_VXO22_OC,
	PMIC_RG_INT_RAW_STATUS_FG_BAT0_H,
	PMIC_RG_INT_RAW_STATUS_FG_BAT0_L,
	PMIC_RG_INT_RAW_STATUS_FG_CUR_H,
	PMIC_RG_INT_RAW_STATUS_FG_CUR_L,
	PMIC_RG_INT_RAW_STATUS_FG_ZCV,
	PMIC_RG_INT_RAW_STATUS_FG_BAT1_H,
	PMIC_RG_INT_RAW_STATUS_FG_BAT1_L,
	PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L,
	PMIC_RG_INT_RAW_STATUS_FG_IAVG_H,
	PMIC_RG_INT_RAW_STATUS_FG_IAVG_L,
	PMIC_RG_INT_RAW_STATUS_FG_TIME_H,
	PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE,
	PMIC_RG_INT_RAW_STATUS_FG_CHARGE,
	PMIC_RG_INT_RAW_STATUS_CON5,
	PMIC_RG_INT_RAW_STATUS_AUDIO,
	PMIC_RG_INT_RAW_STATUS_MAD,
	PMIC_RG_INT_RAW_STATUS_EINT_RTC32K_1V8_1,
	PMIC_RG_INT_RAW_STATUS_EINT_AUD_CLK,
	PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MOSI,
	PMIC_RG_INT_RAW_STATUS_EINT_AUD_DAT_MISO,
	PMIC_RG_INT_RAW_STATUS_EINT_VOW_CLK_MISO,
	PMIC_RG_INT_RAW_STATUS_ACCDET,
	PMIC_RG_INT_RAW_STATUS_ACCDET_EINT,
	PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT,
	PMIC_POLARITY,
	PMIC_RG_HOMEKEY_INT_SEL,
	PMIC_RG_PWRKEY_INT_SEL,
	PMIC_RG_CHRDET_INT_SEL,
	PMIC_RG_PCHR_CM_VINC_POLARITY_RSV,
	PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV,
	PMIC_INT_MISC_CON_SET,
	PMIC_INT_MISC_CON_CLR,
	PMIC_RG_INT_SEN_EINT_RTC32K_1V8_1,
	PMIC_RG_INT_SEN_EINT_AUD_CLK,
	PMIC_RG_INT_SEN_EINT_AUD_DAT_MOSI,
	PMIC_RG_INT_SEN_EINT_AUD_DAT_MISO,
	PMIC_RG_INT_SEN_EINT_VOW_CLK_MISO,
	PMIC_INT_EINT_CON0_SET,
	PMIC_INT_EINT_CON0_CLR,
	PMIC_RG_INT_POL_EINT_RTC32K_1V8_1,
	PMIC_RG_INT_POL_EINT_AUD_CLK,
	PMIC_RG_INT_POL_EINT_AUD_DAT_MOSI,
	PMIC_RG_INT_POL_EINT_AUD_DAT_MISO,
	PMIC_RG_INT_POL_EINT_VOW_CLK_MISO,
	PMIC_INT_EINT_CON1_SET,
	PMIC_INT_EINT_CON1_CLR,
	PMIC_RG_SW_SEL_EINT_RTC32K_1V8_1,
	PMIC_RG_SW_SEL_EINT_AUD_CLK,
	PMIC_RG_SW_SEL_EINT_AUD_DAT_MOSI,
	PMIC_RG_SW_SEL_EINT_AUD_DAT_MISO,
	PMIC_RG_SW_SEL_EINT_VOW_CLK_MISO,
	PMIC_INT_EINT_CON2_SET,
	PMIC_INT_EINT_CON2_CLR,
	PMIC_RG_SW_EINT_RTC32K_1V8_1,
	PMIC_RG_SW_EINT_AUD_CLK,
	PMIC_RG_SW_EINT_AUD_DAT_MOSI,
	PMIC_RG_SW_EINT_AUD_DAT_MISO,
	PMIC_RG_SW_EINT_VOW_CLK_MISO,
	PMIC_INT_EINT_CON3_SET,
	PMIC_INT_EINT_CON3_CLR,
	PMIC_RG_DEB_EINT_RTC32K_1V8_1,
	PMIC_RG_DEB_EINT_AUD_CLK,
	PMIC_RG_DEB_EINT_AUD_DAT_MOSI,
	PMIC_RG_DEB_EINT_AUD_DAT_MISO,
	PMIC_RG_DEB_EINT_VOW_CLK_MISO,
	PMIC_INT_EINT_CON4_SET,
	PMIC_INT_EINT_CON4_CLR,
	PMIC_FQMTR_TCKSEL,
	PMIC_FQMTR_BUSY,
	PMIC_FQMTR_DCXO26M_EN,
	PMIC_FQMTR_EN,
	PMIC_FQMTR_WINSET,
	PMIC_FQMTR_DATA,
	PMIC_RG_SLP_RW_EN,
	PMIC_RG_SPI_RSV,
	PMIC_DEW_DIO_EN,
	PMIC_DEW_READ_TEST,
	PMIC_DEW_WRITE_TEST,
	PMIC_DEW_CRC_SWRST,
	PMIC_DEW_CRC_EN,
	PMIC_DEW_CRC_VAL,
	PMIC_DEW_DBG_MON_SEL,
	PMIC_DEW_CIPHER_KEY_SEL,
	PMIC_DEW_CIPHER_IV_SEL,
	PMIC_DEW_CIPHER_EN,
	PMIC_DEW_CIPHER_RDY,
	PMIC_DEW_CIPHER_MODE,
	PMIC_DEW_CIPHER_SWRST,
	PMIC_DEW_RDDMY_NO,
	PMIC_INT_TYPE_CON0,
	PMIC_INT_TYPE_CON0_SET,
	PMIC_INT_TYPE_CON0_CLR,
	PMIC_INT_TYPE_CON1,
	PMIC_INT_TYPE_CON1_SET,
	PMIC_INT_TYPE_CON1_CLR,
	PMIC_INT_TYPE_CON2,
	PMIC_INT_TYPE_CON2_SET,
	PMIC_INT_TYPE_CON2_CLR,
	PMIC_INT_TYPE_CON3,
	PMIC_INT_TYPE_CON3_SET,
	PMIC_INT_TYPE_CON3_CLR,
	PMIC_INT_TYPE_CON4,
	PMIC_INT_TYPE_CON4_SET,
	PMIC_INT_TYPE_CON4_CLR,
	PMIC_INT_TYPE_CON5,
	PMIC_INT_TYPE_CON5_SET,
	PMIC_INT_TYPE_CON5_CLR,
	PMIC_INT_TYPE_CON6,
	PMIC_INT_TYPE_CON6_SET,
	PMIC_INT_TYPE_CON6_CLR,
	PMIC_CPU_INT_STA,
	PMIC_MD32_INT_STA,
	PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE,
	PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST,
	PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE,
	PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST,
	PMIC_RG_SPI_DLY_SEL,
	PMIC_RECORD_CMD0,
	PMIC_RECORD_CMD1,
	PMIC_RECORD_CMD2,
	PMIC_RECORD_WDATA0,
	PMIC_RECORD_WDATA1,
	PMIC_RECORD_WDATA2,
	PMIC_RG_ADDR_TARGET,
	PMIC_RG_ADDR_MASK,
	PMIC_RG_WDATA_TARGET,
	PMIC_RG_WDATA_MASK,
	PMIC_RG_SPI_RECORD_CLR,
	PMIC_RG_CMD_ALERT_CLR,
	PMIC_RG_THR_DET_DIS,
	PMIC_RG_THR_TEST,
	PMIC_RG_STRUP_THER_DEB_RMAX,
	PMIC_RG_STRUP_THER_DEB_FMAX,
	PMIC_DDUVLO_DEB_EN,
	PMIC_RG_STRUP_OSC_EN,
	PMIC_RG_STRUP_OSC_EN_SEL,
	PMIC_RG_STRUP_FT_CTRL,
	PMIC_RG_STRUP_PWRON_FORCE,
	PMIC_RG_BIASGEN_FORCE,
	PMIC_RG_STRUP_PWRON,
	PMIC_RG_STRUP_PWRON_SEL,
	PMIC_RG_BIASGEN,
	PMIC_RG_BIASGEN_SEL,
	PMIC_RG_RTC_XOSC32_ENB,
	PMIC_RG_RTC_XOSC32_ENB_SEL,
	PMIC_STRUP_DIG_IO_PG_FORCE,
	PMIC_RG_CLR_JUST_SMART_RST,
	PMIC_CLR_JUST_RST,
	PMIC_UVLO_L2H_DEB_EN,
	PMIC_JUST_SMART_RST,
	PMIC_JUST_PWRKEY_RST,
	PMIC_DA_QI_OSC_EN,
	PMIC_RG_STRUP_EXT_PMIC_EN,
	PMIC_RG_STRUP_EXT_PMIC_SEL,
	PMIC_STRUP_CON8_RSV0,
	PMIC_DA_QI_EXT_PMIC_EN,
	PMIC_RG_STRUP_AUXADC_START_SW,
	PMIC_RG_STRUP_AUXADC_RSTB_SW,
	PMIC_RG_STRUP_AUXADC_START_SEL,
	PMIC_RG_STRUP_AUXADC_RSTB_SEL,
	PMIC_RG_STRUP_AUXADC_RPCNT_MAX,
	PMIC_STRUP_PWROFF_SEQ_EN,
	PMIC_STRUP_PWROFF_PREOFF_EN,
	PMIC_STRUP_DIG0_RSV0,
	PMIC_STRUP_DIG1_RSV0,
	PMIC_RG_RSV_SWREG,
	PMIC_RG_STRUP_UVLO_U1U2_SEL,
	PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL,
	PMIC_RG_STRUP_THR_CLR,
	PMIC_RG_STRUP_LONG_PRESS_EXT_SEL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_TD,
	PMIC_RG_STRUP_LONG_PRESS_EXT_EN,
	PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL,
	PMIC_RG_SMART_RST_MODE,
	PMIC_RG_STRUP_ENVTEM,
	PMIC_RG_STRUP_ENVTEM_CTRL,
	PMIC_RG_STRUP_PWRKEY_COUNT_RESET,
	PMIC_RG_STRUP_VA12_PG_H2L_EN,
	PMIC_RG_STRUP_VA10_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_MD_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_CORE_PG_H2L_EN,
	PMIC_RG_STRUP_VA18_PG_H2L_EN,
	PMIC_RG_STRUP_BUCK_RSV_PG_H2L_EN,
	PMIC_RG_STRUP_VDRAM2_PG_H2L_EN,
	PMIC_RG_STRUP_VDRAM1_PG_H2L_EN,
	PMIC_RG_STRUP_VPROC12_PG_H2L_EN,
	PMIC_RG_STRUP_VPROC11_PG_H2L_EN,
	PMIC_RG_STRUP_VS1_PG_H2L_EN,
	PMIC_RG_STRUP_VMODEM_PG_H2L_EN,
	PMIC_RG_STRUP_VGPU_PG_H2L_EN,
	PMIC_RG_STRUP_VCORE_PG_H2L_EN,
	PMIC_RG_STRUP_VS2_PG_H2L_EN,
	PMIC_RG_STRUP_EXT_PMIC_PG_H2L_EN,
	PMIC_RG_STRUP_VUSB33_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN,
	PMIC_RG_STRUP_VUFS18_PG_H2L_EN,
	PMIC_RG_STRUP_VEMC_PG_H2L_EN,
	PMIC_RG_STRUP_VA12_PG_ENB,
	PMIC_RG_STRUP_VA10_PG_ENB,
	PMIC_RG_STRUP_VSRAM_GPU_PG_ENB,
	PMIC_RG_STRUP_VSRAM_MD_PG_ENB,
	PMIC_RG_STRUP_VSRAM_CORE_PG_ENB,
	PMIC_RG_STRUP_VA18_PG_ENB,
	PMIC_RG_STRUP_BUCK_RSV_PG_ENB,
	PMIC_RG_STRUP_VDRAM2_PG_ENB,
	PMIC_RG_STRUP_VDRAM1_PG_ENB,
	PMIC_RG_STRUP_VPROC12_PG_ENB,
	PMIC_RG_STRUP_VPROC11_PG_ENB,
	PMIC_RG_STRUP_VS1_PG_ENB,
	PMIC_RG_STRUP_VMODEM_PG_ENB,
	PMIC_RG_STRUP_VGPU_PG_ENB,
	PMIC_RG_STRUP_VCORE_PG_ENB,
	PMIC_RG_STRUP_VS2_PG_ENB,
	PMIC_RG_STRUP_EXT_PMIC_PG_ENB,
	PMIC_RG_STRUP_VXO18_PG_ENB,
	PMIC_RG_STRUP_VXO22_PG_ENB,
	PMIC_RG_STRUP_VUSB33_PG_ENB,
	PMIC_RG_STRUP_VSRAM_PROC_PG_ENB,
	PMIC_RG_STRUP_VIO28_PG_ENB,
	PMIC_RG_STRUP_VUFS18_PG_ENB,
	PMIC_RG_STRUP_VEMC_PG_ENB,
	PMIC_RG_STRUP_VIO18_PG_ENB,
	PMIC_RG_STRUP_BUCK_RSV_OC_ENB,
	PMIC_RG_STRUP_VDRAM2_OC_ENB,
	PMIC_RG_STRUP_VDRAM1_OC_ENB,
	PMIC_RG_STRUP_VPROC12_OC_ENB,
	PMIC_RG_STRUP_VPROC11_OC_ENB,
	PMIC_RG_STRUP_VS1_OC_ENB,
	PMIC_RG_STRUP_VMODEM_OC_ENB,
	PMIC_RG_STRUP_VGPU_OC_ENB,
	PMIC_RG_STRUP_VCORE_OC_ENB,
	PMIC_RG_STRUP_VS2_OC_ENB,
	PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND,
	PMIC_RG_EXT_PMIC_PG_DEBTD,
	PMIC_RG_RTC_SPAR_DEB_EN,
	PMIC_RG_RTC_ALARM_DEB_EN,
	PMIC_RG_TM_OUT,
	PMIC_RG_THR_LOC_SEL,
	PMIC_RG_THRDET_SEL,
	PMIC_RG_STRUP_THR_SEL,
	PMIC_RG_THR_TMODE,
	PMIC_RG_VREF_BG,
	PMIC_RG_STRUP_IREF_TRIM,
	PMIC_RG_RST_DRVSEL,
	PMIC_RG_EN_DRVSEL,
	PMIC_RG_PMU_RSV,
	PMIC_RGS_ANA_CHIP_ID,
	PMIC_RG_PWRHOLD,
	PMIC_RG_USBDL_MODE,
	PMIC_RG_CRST,
	PMIC_RG_WRST,
	PMIC_RG_RSTB_ONINTV,
	PMIC_RG_CRST_INTV,
	PMIC_RG_WRST_INTV,
	PMIC_RG_PSEQ_IVGEN_SEL,
	PMIC_RG_PSEQ_FSM_RST_SEL,
	PMIC_RG_PSEQ_PG_CK_SEL,
	PMIC_RG_PSEQ_1MS_TK_EXT,
	PMIC_RG_PSEQ_SPAR_XCPT_MASK,
	PMIC_RG_PSEQ_RTCA_XCPT_MASK,
	PMIC_RG_WDTRST_EN,
	PMIC_RG_WDTRST_ACT,
	PMIC_RG_PSPG_SHDN_EN,
	PMIC_RG_THM_SHDN_EN,
	PMIC_RG_KEYPWR_VCORE_OPT,
	PMIC_RG_PSEQ_FORCE_ON,
	PMIC_RG_PSEQ_FORCE_ALL_DOFF,
	PMIC_RG_PSEQ_F75K_FORCE,
	PMIC_RG_PSEQ_RSV0,
	PMIC_RG_PSEQ_RSV1,
	PMIC_RG_PSEQ_RSV2,
	PMIC_RG_BWDT_EN,
	PMIC_RG_BWDT_TSEL,
	PMIC_RG_BWDT_CSEL,
	PMIC_RG_BWDT_TD,
	PMIC_RG_BWDT_CHRTD,
	PMIC_RG_BWDT_DDLO_TD,
	PMIC_RG_BWDT_SRCSEL,
	PMIC_RG_CPS_W_KEY,
	PMIC_RG_SLOT_INTV_UP,
	PMIC_RG_SEQ_LEN,
	PMIC_RG_SLOT_INTV_DOWN,
	PMIC_RG_DSEQ_LEN,
	PMIC_RG_VS2_USA,
	PMIC_RG_VSRAM_CORE_USA,
	PMIC_RG_VSRAM_MD_USA,
	PMIC_RG_VSRAM_GPU_USA,
	PMIC_RG_VCORE_USA,
	PMIC_RG_VGPU_USA,
	PMIC_RG_VMODEM_USA,
	PMIC_RG_VS1_USA,
	PMIC_RG_VA10_USA,
	PMIC_RG_VA12_USA,
	PMIC_RG_VIO18_USA,
	PMIC_RG_VEMC_USA,
	PMIC_RG_VUFS18_USA,
	PMIC_RG_VIO28_USA,
	PMIC_RG_VSRAM_PROC_USA,
	PMIC_RG_VPROC11_USA,
	PMIC_RG_VPROC12_USA,
	PMIC_RG_EXT_PMIC_USA,
	PMIC_RG_VDRAM1_USA,
	PMIC_RG_VDRAM2_USA,
	PMIC_RG_VUSB33_USA,
	PMIC_RG_VXO22_USA,
	PMIC_RG_VXO18_USA,
	PMIC_RG_BUCK_RSV_USA,
	PMIC_RG_VS2_DSA,
	PMIC_RG_VSRAM_CORE_DSA,
	PMIC_RG_VSRAM_MD_DSA,
	PMIC_RG_VSRAM_GPU_DSA,
	PMIC_RG_VCORE_DSA,
	PMIC_RG_VGPU_DSA,
	PMIC_RG_VMODEM_DSA,
	PMIC_RG_VS1_DSA,
	PMIC_RG_VA10_DSA,
	PMIC_RG_VA12_DSA,
	PMIC_RG_VIO18_DSA,
	PMIC_RG_VEMC_DSA,
	PMIC_RG_VUFS18_DSA,
	PMIC_RG_VIO28_DSA,
	PMIC_RG_VSRAM_PROC_DSA,
	PMIC_RG_VPROC11_DSA,
	PMIC_RG_VPROC12_DSA,
	PMIC_RG_EXT_PMIC_DSA,
	PMIC_RG_VDRAM1_DSA,
	PMIC_RG_VDRAM2_DSA,
	PMIC_RG_VUSB33_DSA,
	PMIC_RG_VXO22_DSA,
	PMIC_RG_VXO18_DSA,
	PMIC_RG_BUCK_RSV_DSA,
	PMIC_RG_POR_FLAG,
	PMIC_STS_PWRKEY,
	PMIC_STS_RTCA,
	PMIC_STS_CHRIN,
	PMIC_STS_SPAR,
	PMIC_STS_RBOOT,
	PMIC_STS_UVLO,
	PMIC_STS_PGFAIL,
	PMIC_STS_PSOC,
	PMIC_STS_THRDN,
	PMIC_STS_WRST,
	PMIC_STS_CRST,
	PMIC_STS_PKEYLP,
	PMIC_STS_NORMOFF,
	PMIC_STS_BWDT,
	PMIC_STS_DDLO,
	PMIC_STS_WDT,
	PMIC_STS_PUPSRC,
	PMIC_STS_KEYPWR,
	PMIC_RG_POFFSTS_CLR,
	PMIC_RG_PONSTS_CLR,
	PMIC_RG_BUCK_LDO_FT_EN,
	PMIC_RG_BUCK_DCM_MODE,
	PMIC_RG_BUCK_ALL_CON0_RSV,
	PMIC_RG_BUCK_STB_MAX,
	PMIC_RG_BUCK_LP_PROT_DISABLE,
	PMIC_RG_BUCK_VSLEEP_SRC0,
	PMIC_RG_BUCK_VSLEEP_SRC1,
	PMIC_RG_BUCK_R2R_SRC0,
	PMIC_RG_BUCK_R2R_SRC1,
	PMIC_RG_BUCK_LP_SEQ_COUNT,
	PMIC_RG_BUCK_ON_SEQ_COUNT,
	PMIC_RG_BUCK_MINFREQ_LATENCY_MAX,
	PMIC_RG_BUCK_MINFREQ_DURATION_MAX,
	PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS,
	PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS,
	PMIC_RG_BUCK_VCORE_OC_SDN_STATUS,
	PMIC_RG_BUCK_VGPU_OC_SDN_STATUS,
	PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS,
	PMIC_RG_BUCK_VDRAM2_OC_SDN_STATUS,
	PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS,
	PMIC_RG_BUCK_VS1_OC_SDN_STATUS,
	PMIC_RG_BUCK_VS2_OC_SDN_STATUS,
	PMIC_RG_BUCK_VPA_OC_SDN_STATUS,
	PMIC_RG_BUCK_VPROC11_OC_SDN_EN,
	PMIC_RG_BUCK_VPROC12_OC_SDN_EN,
	PMIC_RG_BUCK_VCORE_OC_SDN_EN,
	PMIC_RG_BUCK_VGPU_OC_SDN_EN,
	PMIC_RG_BUCK_VDRAM1_OC_SDN_EN,
	PMIC_RG_BUCK_VDRAM2_OC_SDN_EN,
	PMIC_RG_BUCK_VMODEM_OC_SDN_EN,
	PMIC_RG_BUCK_VS1_OC_SDN_EN,
	PMIC_RG_BUCK_VS2_OC_SDN_EN,
	PMIC_RG_BUCK_VPA_OC_SDN_EN,
	PMIC_RG_BUCK_K_RST_DONE,
	PMIC_RG_BUCK_K_MAP_SEL,
	PMIC_RG_BUCK_K_ONCE_EN,
	PMIC_RG_BUCK_K_ONCE,
	PMIC_RG_BUCK_K_START_MANUAL,
	PMIC_RG_BUCK_K_SRC_SEL,
	PMIC_RG_BUCK_K_AUTO_EN,
	PMIC_RG_BUCK_K_INV,
	PMIC_RG_BUCK_K_CK_EN,
	PMIC_RG_BUCK_K_CONTROL_SMPS,
	PMIC_BUCK_K_RESULT,
	PMIC_BUCK_K_DONE,
	PMIC_BUCK_K_CONTROL,
	PMIC_DA_QI_SMPS_OSC_CAL,
	PMIC_RG_BUCK_K_BUCK_CK_CNT,
	PMIC_RG_VOW_BUCK_VCORE_DVS_DONE,
	PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE,
	PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE,
	PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE,
	PMIC_VOW_BUCK_VCORE_DVS_DONE,
	PMIC_VOW_LDO_VSRAM_CORE_DVS_DONE,
	PMIC_VOW_DVS_DONE,
	PMIC_RG_BUCK_VPROC11_EN,
	PMIC_RG_BUCK_VPROC11_LP,
	PMIC_RG_BUCK_VPROC11_VOSEL,
	PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP,
	PMIC_RG_BUCK_VPROC11_SFCHG_FRATE,
	PMIC_RG_BUCK_VPROC11_SFCHG_FEN,
	PMIC_RG_BUCK_VPROC11_SFCHG_RRATE,
	PMIC_RG_BUCK_VPROC11_SFCHG_REN,
	PMIC_RG_BUCK_VPROC11_DVS_EN_TD,
	PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL,
	PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE,
	PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD,
	PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VPROC11_SW_OP_EN,
	PMIC_RG_BUCK_VPROC11_HW0_OP_EN,
	PMIC_RG_BUCK_VPROC11_HW1_OP_EN,
	PMIC_RG_BUCK_VPROC11_HW2_OP_EN,
	PMIC_RG_BUCK_VPROC11_OP_EN_SET,
	PMIC_RG_BUCK_VPROC11_OP_EN_CLR,
	PMIC_RG_BUCK_VPROC11_HW0_OP_CFG,
	PMIC_RG_BUCK_VPROC11_HW1_OP_CFG,
	PMIC_RG_BUCK_VPROC11_HW2_OP_CFG,
	PMIC_RG_BUCK_VPROC11_ON_OP,
	PMIC_RG_BUCK_VPROC11_LP_OP,
	PMIC_RG_BUCK_VPROC11_OP_CFG_SET,
	PMIC_RG_BUCK_VPROC11_OP_CFG_CLR,
	PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL,
	PMIC_RG_BUCK_VPROC11_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VPROC11_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VPROC11_OC_DEG_EN,
	PMIC_RG_BUCK_VPROC11_OC_WND,
	PMIC_RG_BUCK_VPROC11_OC_THD,
	PMIC_DA_VPROC11_VOSEL,
	PMIC_DA_VPROC11_VOSEL_GRAY,
	PMIC_DA_VPROC11_EN,
	PMIC_DA_VPROC11_STB,
	PMIC_DA_VPROC11_VSLEEP_SEL,
	PMIC_DA_VPROC11_R2R_PDN,
	PMIC_DA_VPROC11_DVS_EN,
	PMIC_DA_VPROC11_DVS_DOWN,
	PMIC_DA_VPROC11_SSH,
	PMIC_DA_VPROC11_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS,
	PMIC_RG_BUCK_VPROC11_CK_SW_MODE,
	PMIC_RG_BUCK_VPROC11_CK_SW_EN,
	PMIC_RG_BUCK_VPROC12_EN,
	PMIC_RG_BUCK_VPROC12_LP,
	PMIC_RG_BUCK_VPROC12_VOSEL,
	PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP,
	PMIC_RG_BUCK_VPROC12_SFCHG_FRATE,
	PMIC_RG_BUCK_VPROC12_SFCHG_FEN,
	PMIC_RG_BUCK_VPROC12_SFCHG_RRATE,
	PMIC_RG_BUCK_VPROC12_SFCHG_REN,
	PMIC_RG_BUCK_VPROC12_DVS_EN_TD,
	PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL,
	PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE,
	PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD,
	PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VPROC12_SW_OP_EN,
	PMIC_RG_BUCK_VPROC12_HW0_OP_EN,
	PMIC_RG_BUCK_VPROC12_HW1_OP_EN,
	PMIC_RG_BUCK_VPROC12_HW2_OP_EN,
	PMIC_RG_BUCK_VPROC12_OP_EN_SET,
	PMIC_RG_BUCK_VPROC12_OP_EN_CLR,
	PMIC_RG_BUCK_VPROC12_HW0_OP_CFG,
	PMIC_RG_BUCK_VPROC12_HW1_OP_CFG,
	PMIC_RG_BUCK_VPROC12_HW2_OP_CFG,
	PMIC_RG_BUCK_VPROC12_ON_OP,
	PMIC_RG_BUCK_VPROC12_LP_OP,
	PMIC_RG_BUCK_VPROC12_OP_CFG_SET,
	PMIC_RG_BUCK_VPROC12_OP_CFG_CLR,
	PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL,
	PMIC_RG_BUCK_VPROC12_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VPROC12_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VPROC12_OC_DEG_EN,
	PMIC_RG_BUCK_VPROC12_OC_WND,
	PMIC_RG_BUCK_VPROC12_OC_THD,
	PMIC_DA_VPROC12_VOSEL,
	PMIC_DA_VPROC12_VOSEL_GRAY,
	PMIC_DA_VPROC12_EN,
	PMIC_DA_VPROC12_STB,
	PMIC_DA_VPROC12_VSLEEP_SEL,
	PMIC_DA_VPROC12_R2R_PDN,
	PMIC_DA_VPROC12_DVS_EN,
	PMIC_DA_VPROC12_DVS_DOWN,
	PMIC_DA_VPROC12_SSH,
	PMIC_DA_VPROC12_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS,
	PMIC_RG_BUCK_VPROC12_CK_SW_MODE,
	PMIC_RG_BUCK_VPROC12_CK_SW_EN,
	PMIC_RG_BUCK_VCORE_EN,
	PMIC_RG_BUCK_VCORE_LP,
	PMIC_RG_BUCK_VCORE_VOSEL,
	PMIC_RG_BUCK_VCORE_VOSEL_SLEEP,
	PMIC_RG_BUCK_VCORE_SFCHG_FRATE,
	PMIC_RG_BUCK_VCORE_SFCHG_FEN,
	PMIC_RG_BUCK_VCORE_SFCHG_RRATE,
	PMIC_RG_BUCK_VCORE_SFCHG_REN,
	PMIC_RG_BUCK_VCORE_DVS_EN_TD,
	PMIC_RG_BUCK_VCORE_DVS_EN_CTRL,
	PMIC_RG_BUCK_VCORE_DVS_EN_ONCE,
	PMIC_RG_BUCK_VCORE_DVS_DOWN_TD,
	PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VCORE_SW_OP_EN,
	PMIC_RG_BUCK_VCORE_HW0_OP_EN,
	PMIC_RG_BUCK_VCORE_HW1_OP_EN,
	PMIC_RG_BUCK_VCORE_HW2_OP_EN,
	PMIC_RG_BUCK_VCORE_OP_EN_SET,
	PMIC_RG_BUCK_VCORE_OP_EN_CLR,
	PMIC_RG_BUCK_VCORE_HW0_OP_CFG,
	PMIC_RG_BUCK_VCORE_HW1_OP_CFG,
	PMIC_RG_BUCK_VCORE_HW2_OP_CFG,
	PMIC_RG_BUCK_VCORE_ON_OP,
	PMIC_RG_BUCK_VCORE_LP_OP,
	PMIC_RG_BUCK_VCORE_OP_CFG_SET,
	PMIC_RG_BUCK_VCORE_OP_CFG_CLR,
	PMIC_RG_BUCK_VCORE_SP_SW_VOSEL,
	PMIC_RG_BUCK_VCORE_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VCORE_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VCORE_OC_DEG_EN,
	PMIC_RG_BUCK_VCORE_OC_WND,
	PMIC_RG_BUCK_VCORE_OC_THD,
	PMIC_DA_VCORE_VOSEL,
	PMIC_DA_VCORE_VOSEL_GRAY,
	PMIC_DA_VCORE_EN,
	PMIC_DA_VCORE_STB,
	PMIC_DA_VCORE_VSLEEP_SEL,
	PMIC_DA_VCORE_R2R_PDN,
	PMIC_DA_VCORE_DVS_EN,
	PMIC_DA_VCORE_DVS_DOWN,
	PMIC_DA_VCORE_SSH,
	PMIC_DA_VCORE_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VCORE_OSC_SEL_DIS,
	PMIC_RG_BUCK_VCORE_CK_SW_MODE,
	PMIC_RG_BUCK_VCORE_CK_SW_EN,
	PMIC_RG_BUCK_VCORE_SSHUB_MODE,
	PMIC_RG_BUCK_VCORE_SSHUB_ON,
	PMIC_RG_BUCK_VCORE_SSHUB_VOSEL,
	PMIC_RG_BUCK_VGPU_EN,
	PMIC_RG_BUCK_VGPU_LP,
	PMIC_RG_BUCK_VGPU_VOSEL,
	PMIC_RG_BUCK_VGPU_VOSEL_SLEEP,
	PMIC_RG_BUCK_VGPU_SFCHG_FRATE,
	PMIC_RG_BUCK_VGPU_SFCHG_FEN,
	PMIC_RG_BUCK_VGPU_SFCHG_RRATE,
	PMIC_RG_BUCK_VGPU_SFCHG_REN,
	PMIC_RG_BUCK_VGPU_DVS_EN_TD,
	PMIC_RG_BUCK_VGPU_DVS_EN_CTRL,
	PMIC_RG_BUCK_VGPU_DVS_EN_ONCE,
	PMIC_RG_BUCK_VGPU_DVS_DOWN_TD,
	PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VGPU_SW_OP_EN,
	PMIC_RG_BUCK_VGPU_HW0_OP_EN,
	PMIC_RG_BUCK_VGPU_HW1_OP_EN,
	PMIC_RG_BUCK_VGPU_HW2_OP_EN,
	PMIC_RG_BUCK_VGPU_OP_EN_SET,
	PMIC_RG_BUCK_VGPU_OP_EN_CLR,
	PMIC_RG_BUCK_VGPU_HW0_OP_CFG,
	PMIC_RG_BUCK_VGPU_HW1_OP_CFG,
	PMIC_RG_BUCK_VGPU_HW2_OP_CFG,
	PMIC_RG_BUCK_VGPU_ON_OP,
	PMIC_RG_BUCK_VGPU_LP_OP,
	PMIC_RG_BUCK_VGPU_OP_CFG_SET,
	PMIC_RG_BUCK_VGPU_OP_CFG_CLR,
	PMIC_RG_BUCK_VGPU_SP_SW_VOSEL,
	PMIC_RG_BUCK_VGPU_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VGPU_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VGPU_OC_DEG_EN,
	PMIC_RG_BUCK_VGPU_OC_WND,
	PMIC_RG_BUCK_VGPU_OC_THD,
	PMIC_DA_VGPU_VOSEL,
	PMIC_DA_VGPU_VOSEL_GRAY,
	PMIC_DA_VGPU_EN,
	PMIC_DA_VGPU_STB,
	PMIC_DA_VGPU_VSLEEP_SEL,
	PMIC_DA_VGPU_R2R_PDN,
	PMIC_DA_VGPU_DVS_EN,
	PMIC_DA_VGPU_DVS_DOWN,
	PMIC_DA_VGPU_SSH,
	PMIC_DA_VGPU_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VGPU_OSC_SEL_DIS,
	PMIC_RG_BUCK_VGPU_CK_SW_MODE,
	PMIC_RG_BUCK_VGPU_CK_SW_EN,
	PMIC_RG_BUCK_VDRAM1_EN,
	PMIC_RG_BUCK_VDRAM1_LP,
	PMIC_RG_BUCK_VDRAM1_VOSEL,
	PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP,
	PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE,
	PMIC_RG_BUCK_VDRAM1_SFCHG_FEN,
	PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE,
	PMIC_RG_BUCK_VDRAM1_SFCHG_REN,
	PMIC_RG_BUCK_VDRAM1_DVS_EN_TD,
	PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL,
	PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE,
	PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD,
	PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VDRAM1_SW_OP_EN,
	PMIC_RG_BUCK_VDRAM1_HW0_OP_EN,
	PMIC_RG_BUCK_VDRAM1_HW1_OP_EN,
	PMIC_RG_BUCK_VDRAM1_HW2_OP_EN,
	PMIC_RG_BUCK_VDRAM1_OP_EN_SET,
	PMIC_RG_BUCK_VDRAM1_OP_EN_CLR,
	PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG,
	PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG,
	PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG,
	PMIC_RG_BUCK_VDRAM1_ON_OP,
	PMIC_RG_BUCK_VDRAM1_LP_OP,
	PMIC_RG_BUCK_VDRAM1_OP_CFG_SET,
	PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR,
	PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL,
	PMIC_RG_BUCK_VDRAM1_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VDRAM1_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VDRAM1_OC_DEG_EN,
	PMIC_RG_BUCK_VDRAM1_OC_WND,
	PMIC_RG_BUCK_VDRAM1_OC_THD,
	PMIC_DA_VDRAM1_VOSEL,
	PMIC_DA_VDRAM1_VOSEL_GRAY,
	PMIC_DA_VDRAM1_EN,
	PMIC_DA_VDRAM1_STB,
	PMIC_DA_VDRAM1_VSLEEP_SEL,
	PMIC_DA_VDRAM1_R2R_PDN,
	PMIC_DA_VDRAM1_DVS_EN,
	PMIC_DA_VDRAM1_DVS_DOWN,
	PMIC_DA_VDRAM1_SSH,
	PMIC_DA_VDRAM1_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS,
	PMIC_RG_BUCK_VDRAM1_CK_SW_MODE,
	PMIC_RG_BUCK_VDRAM1_CK_SW_EN,
	PMIC_RG_BUCK_VDRAM2_EN,
	PMIC_RG_BUCK_VDRAM2_LP,
	PMIC_RG_BUCK_VDRAM2_VOSEL,
	PMIC_RG_BUCK_VDRAM2_VOSEL_SLEEP,
	PMIC_RG_BUCK_VDRAM2_SFCHG_FRATE,
	PMIC_RG_BUCK_VDRAM2_SFCHG_FEN,
	PMIC_RG_BUCK_VDRAM2_SFCHG_RRATE,
	PMIC_RG_BUCK_VDRAM2_SFCHG_REN,
	PMIC_RG_BUCK_VDRAM2_DVS_EN_TD,
	PMIC_RG_BUCK_VDRAM2_DVS_EN_CTRL,
	PMIC_RG_BUCK_VDRAM2_DVS_EN_ONCE,
	PMIC_RG_BUCK_VDRAM2_DVS_DOWN_TD,
	PMIC_RG_BUCK_VDRAM2_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VDRAM2_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VDRAM2_SW_OP_EN,
	PMIC_RG_BUCK_VDRAM2_HW0_OP_EN,
	PMIC_RG_BUCK_VDRAM2_HW1_OP_EN,
	PMIC_RG_BUCK_VDRAM2_HW2_OP_EN,
	PMIC_RG_BUCK_VDRAM2_OP_EN_SET,
	PMIC_RG_BUCK_VDRAM2_OP_EN_CLR,
	PMIC_RG_BUCK_VDRAM2_HW0_OP_CFG,
	PMIC_RG_BUCK_VDRAM2_HW1_OP_CFG,
	PMIC_RG_BUCK_VDRAM2_HW2_OP_CFG,
	PMIC_RG_BUCK_VDRAM2_ON_OP,
	PMIC_RG_BUCK_VDRAM2_LP_OP,
	PMIC_RG_BUCK_VDRAM2_OP_CFG_SET,
	PMIC_RG_BUCK_VDRAM2_OP_CFG_CLR,
	PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL,
	PMIC_RG_BUCK_VDRAM2_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VDRAM2_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VDRAM2_OC_DEG_EN,
	PMIC_RG_BUCK_VDRAM2_OC_WND,
	PMIC_RG_BUCK_VDRAM2_OC_THD,
	PMIC_DA_VDRAM2_VOSEL,
	PMIC_DA_VDRAM2_VOSEL_GRAY,
	PMIC_DA_VDRAM2_EN,
	PMIC_DA_VDRAM2_STB,
	PMIC_DA_VDRAM2_VSLEEP_SEL,
	PMIC_DA_VDRAM2_R2R_PDN,
	PMIC_DA_VDRAM2_DVS_EN,
	PMIC_DA_VDRAM2_DVS_DOWN,
	PMIC_DA_VDRAM2_SSH,
	PMIC_DA_VDRAM2_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VDRAM2_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VDRAM2_OSC_SEL_DIS,
	PMIC_RG_BUCK_VDRAM2_CK_SW_MODE,
	PMIC_RG_BUCK_VDRAM2_CK_SW_EN,
	PMIC_RG_BUCK_VMODEM_EN,
	PMIC_RG_BUCK_VMODEM_LP,
	PMIC_RG_BUCK_VMODEM_VOSEL,
	PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP,
	PMIC_RG_BUCK_VMODEM_SFCHG_FRATE,
	PMIC_RG_BUCK_VMODEM_SFCHG_FEN,
	PMIC_RG_BUCK_VMODEM_SFCHG_RRATE,
	PMIC_RG_BUCK_VMODEM_SFCHG_REN,
	PMIC_RG_BUCK_VMODEM_DVS_EN_TD,
	PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL,
	PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE,
	PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD,
	PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VMODEM_SW_OP_EN,
	PMIC_RG_BUCK_VMODEM_HW0_OP_EN,
	PMIC_RG_BUCK_VMODEM_HW1_OP_EN,
	PMIC_RG_BUCK_VMODEM_HW2_OP_EN,
	PMIC_RG_BUCK_VMODEM_OP_EN_SET,
	PMIC_RG_BUCK_VMODEM_OP_EN_CLR,
	PMIC_RG_BUCK_VMODEM_HW0_OP_CFG,
	PMIC_RG_BUCK_VMODEM_HW1_OP_CFG,
	PMIC_RG_BUCK_VMODEM_HW2_OP_CFG,
	PMIC_RG_BUCK_VMODEM_ON_OP,
	PMIC_RG_BUCK_VMODEM_LP_OP,
	PMIC_RG_BUCK_VMODEM_OP_CFG_SET,
	PMIC_RG_BUCK_VMODEM_OP_CFG_CLR,
	PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL,
	PMIC_RG_BUCK_VMODEM_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VMODEM_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VMODEM_OC_DEG_EN,
	PMIC_RG_BUCK_VMODEM_OC_WND,
	PMIC_RG_BUCK_VMODEM_OC_THD,
	PMIC_DA_VMODEM_VOSEL,
	PMIC_DA_VMODEM_VOSEL_GRAY,
	PMIC_DA_VMODEM_EN,
	PMIC_DA_VMODEM_STB,
	PMIC_DA_VMODEM_VSLEEP_SEL,
	PMIC_DA_VMODEM_R2R_PDN,
	PMIC_DA_VMODEM_DVS_EN,
	PMIC_DA_VMODEM_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS,
	PMIC_RG_BUCK_VMODEM_CK_SW_MODE,
	PMIC_RG_BUCK_VMODEM_CK_SW_EN,
	PMIC_RG_BUCK_VMODEM_VOSEL_DLC0,
	PMIC_RG_BUCK_VMODEM_VOSEL_DLC1,
	PMIC_RG_BUCK_VMODEM_VOSEL_DLC2,
	PMIC_RG_BUCK_VMODEM_DLC0,
	PMIC_RG_BUCK_VMODEM_DLC1,
	PMIC_RG_BUCK_VMODEM_DLC2,
	PMIC_RG_BUCK_VMODEM_DLC3,
	PMIC_RG_BUCK_VMODEM_DLC_MAP_EN,
	PMIC_RG_BUCK_VMODEM_DLC,
	PMIC_DA_VMODEM_DLC,
	PMIC_RG_BUCK_VS1_EN,
	PMIC_RG_BUCK_VS1_LP,
	PMIC_RG_BUCK_VS1_VOSEL,
	PMIC_RG_BUCK_VS1_VOSEL_SLEEP,
	PMIC_RG_BUCK_VS1_SFCHG_FRATE,
	PMIC_RG_BUCK_VS1_SFCHG_FEN,
	PMIC_RG_BUCK_VS1_SFCHG_RRATE,
	PMIC_RG_BUCK_VS1_SFCHG_REN,
	PMIC_RG_BUCK_VS1_DVS_EN_TD,
	PMIC_RG_BUCK_VS1_DVS_EN_CTRL,
	PMIC_RG_BUCK_VS1_DVS_EN_ONCE,
	PMIC_RG_BUCK_VS1_DVS_DOWN_TD,
	PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VS1_SW_OP_EN,
	PMIC_RG_BUCK_VS1_HW0_OP_EN,
	PMIC_RG_BUCK_VS1_HW1_OP_EN,
	PMIC_RG_BUCK_VS1_HW2_OP_EN,
	PMIC_RG_BUCK_VS1_OP_EN_SET,
	PMIC_RG_BUCK_VS1_OP_EN_CLR,
	PMIC_RG_BUCK_VS1_HW0_OP_CFG,
	PMIC_RG_BUCK_VS1_HW1_OP_CFG,
	PMIC_RG_BUCK_VS1_HW2_OP_CFG,
	PMIC_RG_BUCK_VS1_ON_OP,
	PMIC_RG_BUCK_VS1_LP_OP,
	PMIC_RG_BUCK_VS1_OP_CFG_SET,
	PMIC_RG_BUCK_VS1_OP_CFG_CLR,
	PMIC_RG_BUCK_VS1_SP_SW_VOSEL,
	PMIC_RG_BUCK_VS1_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VS1_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VS1_OC_DEG_EN,
	PMIC_RG_BUCK_VS1_OC_WND,
	PMIC_RG_BUCK_VS1_OC_THD,
	PMIC_DA_VS1_VOSEL,
	PMIC_DA_VS1_VOSEL_GRAY,
	PMIC_DA_VS1_EN,
	PMIC_DA_VS1_STB,
	PMIC_DA_VS1_VSLEEP_SEL,
	PMIC_DA_VS1_R2R_PDN,
	PMIC_DA_VS1_DVS_EN,
	PMIC_DA_VS1_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VS1_OSC_SEL_DIS,
	PMIC_RG_BUCK_VS1_CK_SW_MODE,
	PMIC_RG_BUCK_VS1_CK_SW_EN,
	PMIC_RG_BUCK_VS1_VOTER_EN,
	PMIC_RG_BUCK_VS1_VOTER_EN_SET,
	PMIC_RG_BUCK_VS1_VOTER_EN_CLR,
	PMIC_RG_BUCK_VS1_VOTER_VOSEL,
	PMIC_RG_BUCK_VS2_EN,
	PMIC_RG_BUCK_VS2_LP,
	PMIC_RG_BUCK_VS2_VOSEL,
	PMIC_RG_BUCK_VS2_VOSEL_SLEEP,
	PMIC_RG_BUCK_VS2_SFCHG_FRATE,
	PMIC_RG_BUCK_VS2_SFCHG_FEN,
	PMIC_RG_BUCK_VS2_SFCHG_RRATE,
	PMIC_RG_BUCK_VS2_SFCHG_REN,
	PMIC_RG_BUCK_VS2_DVS_EN_TD,
	PMIC_RG_BUCK_VS2_DVS_EN_CTRL,
	PMIC_RG_BUCK_VS2_DVS_EN_ONCE,
	PMIC_RG_BUCK_VS2_DVS_DOWN_TD,
	PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VS2_SW_OP_EN,
	PMIC_RG_BUCK_VS2_HW0_OP_EN,
	PMIC_RG_BUCK_VS2_HW1_OP_EN,
	PMIC_RG_BUCK_VS2_HW2_OP_EN,
	PMIC_RG_BUCK_VS2_OP_EN_SET,
	PMIC_RG_BUCK_VS2_OP_EN_CLR,
	PMIC_RG_BUCK_VS2_HW0_OP_CFG,
	PMIC_RG_BUCK_VS2_HW1_OP_CFG,
	PMIC_RG_BUCK_VS2_HW2_OP_CFG,
	PMIC_RG_BUCK_VS2_ON_OP,
	PMIC_RG_BUCK_VS2_LP_OP,
	PMIC_RG_BUCK_VS2_OP_CFG_SET,
	PMIC_RG_BUCK_VS2_OP_CFG_CLR,
	PMIC_RG_BUCK_VS2_SP_SW_VOSEL,
	PMIC_RG_BUCK_VS2_SP_SW_VOSEL_EN,
	PMIC_RG_BUCK_VS2_SP_ON_VOSEL_MUX_SEL,
	PMIC_RG_BUCK_VS2_OC_DEG_EN,
	PMIC_RG_BUCK_VS2_OC_WND,
	PMIC_RG_BUCK_VS2_OC_THD,
	PMIC_DA_VS2_VOSEL,
	PMIC_DA_VS2_VOSEL_GRAY,
	PMIC_DA_VS2_EN,
	PMIC_DA_VS2_STB,
	PMIC_DA_VS2_VSLEEP_SEL,
	PMIC_DA_VS2_R2R_PDN,
	PMIC_DA_VS2_DVS_EN,
	PMIC_DA_VS2_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VS2_OSC_SEL_DIS,
	PMIC_RG_BUCK_VS2_CK_SW_MODE,
	PMIC_RG_BUCK_VS2_CK_SW_EN,
	PMIC_RG_BUCK_VS2_VOTER_EN,
	PMIC_RG_BUCK_VS2_VOTER_EN_SET,
	PMIC_RG_BUCK_VS2_VOTER_EN_CLR,
	PMIC_RG_BUCK_VS2_VOTER_VOSEL,
	PMIC_RG_BUCK_VPA_EN,
	PMIC_RG_BUCK_VPA_VOSEL,
	PMIC_RG_BUCK_VPA_SFCHG_FRATE,
	PMIC_RG_BUCK_VPA_SFCHG_FEN,
	PMIC_RG_BUCK_VPA_SFCHG_RRATE,
	PMIC_RG_BUCK_VPA_SFCHG_REN,
	PMIC_RG_BUCK_VPA_DVS_TRANST_TD,
	PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL,
	PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE,
	PMIC_RG_BUCK_VPA_DVS_BW_TD,
	PMIC_RG_BUCK_VPA_DVS_BW_CTRL,
	PMIC_RG_BUCK_VPA_DVS_BW_ONCE,
	PMIC_RG_BUCK_VPA_OC_DEG_EN,
	PMIC_RG_BUCK_VPA_OC_WND,
	PMIC_RG_BUCK_VPA_OC_THD,
	PMIC_DA_VPA_VOSEL,
	PMIC_DA_VPA_VOSEL_GRAY,
	PMIC_DA_VPA_EN,
	PMIC_DA_VPA_STB,
	PMIC_DA_VPA_DVS_TRANST,
	PMIC_DA_VPA_DVS_BW,
	PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VPA_OSC_SEL_DIS,
	PMIC_RG_BUCK_VPA_CK_SW_MODE,
	PMIC_RG_BUCK_VPA_CK_SW_EN,
	PMIC_RG_BUCK_VPA_VOSEL_DLC011,
	PMIC_RG_BUCK_VPA_VOSEL_DLC111,
	PMIC_RG_BUCK_VPA_VOSEL_DLC001,
	PMIC_RG_BUCK_VPA_DLC_MAP_EN,
	PMIC_RG_BUCK_VPA_DLC,
	PMIC_DA_VPA_DLC,
	PMIC_RG_BUCK_VPA_MSFG_EN,
	PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO,
	PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO,
	PMIC_RG_BUCK_VPA_MSFG_RRATE0,
	PMIC_RG_BUCK_VPA_MSFG_RRATE1,
	PMIC_RG_BUCK_VPA_MSFG_RRATE2,
	PMIC_RG_BUCK_VPA_MSFG_RRATE3,
	PMIC_RG_BUCK_VPA_MSFG_RRATE4,
	PMIC_RG_BUCK_VPA_MSFG_RRATE5,
	PMIC_RG_BUCK_VPA_MSFG_RTHD0,
	PMIC_RG_BUCK_VPA_MSFG_RTHD1,
	PMIC_RG_BUCK_VPA_MSFG_RTHD2,
	PMIC_RG_BUCK_VPA_MSFG_RTHD3,
	PMIC_RG_BUCK_VPA_MSFG_RTHD4,
	PMIC_RG_BUCK_VPA_MSFG_FRATE0,
	PMIC_RG_BUCK_VPA_MSFG_FRATE1,
	PMIC_RG_BUCK_VPA_MSFG_FRATE2,
	PMIC_RG_BUCK_VPA_MSFG_FRATE3,
	PMIC_RG_BUCK_VPA_MSFG_FRATE4,
	PMIC_RG_BUCK_VPA_MSFG_FRATE5,
	PMIC_RG_BUCK_VPA_MSFG_FTHD0,
	PMIC_RG_BUCK_VPA_MSFG_FTHD1,
	PMIC_RG_BUCK_VPA_MSFG_FTHD2,
	PMIC_RG_BUCK_VPA_MSFG_FTHD3,
	PMIC_RG_BUCK_VPA_MSFG_FTHD4,
	PMIC_RG_SMPS_TESTMODE_B,
	PMIC_RG_VPA_BURSTH,
	PMIC_RG_VPA_BURSTL,
	PMIC_RG_VPA_TRIMH,
	PMIC_RG_VPA_TRIML,
	PMIC_RG_VPA_TRIM_REF,
	PMIC_RG_VCORE_TRIMH,
	PMIC_RG_VCORE_TRIML,
	PMIC_RG_VCORE_VSLEEP_TRIM,
	PMIC_RG_VCORE_SLEEP_VOLTAGE,
	PMIC_RG_VDRAM1_TRIMH,
	PMIC_RG_VDRAM1_TRIML,
	PMIC_RG_VDRAM1_VSLEEP_TRIM,
	PMIC_RG_VDRAM1_SLEEP_VOLTAGE,
	PMIC_RG_VMODEM_TRIMH,
	PMIC_RG_VMODEM_TRIML,
	PMIC_RG_VMODEM_VSLEEP_TRIM,
	PMIC_RG_VMODEM_SLEEP_VOLTAGE,
	PMIC_RG_VGPU_TRIMH,
	PMIC_RG_VGPU_TRIML,
	PMIC_RG_VGPU_VSLEEP_TRIM,
	PMIC_RG_VGPU_SLEEP_VOLTAGE,
	PMIC_RG_VS1_TRIMH,
	PMIC_RG_VS1_TRIML,
	PMIC_RG_VS1_VSLEEP_TRIM,
	PMIC_RG_VS1_SLEEP_VOLTAGE,
	PMIC_RG_VS2_TRIMH,
	PMIC_RG_VS2_TRIML,
	PMIC_RG_VS2_VSLEEP_TRIM,
	PMIC_RG_VS2_SLEEP_VOLTAGE,
	PMIC_RG_VDRAM2_TRIMH,
	PMIC_RG_VDRAM2_TRIML,
	PMIC_RG_VDRAM2_VSLEEP_TRIM,
	PMIC_RG_VDRAM2_SLEEP_VOLTAGE,
	PMIC_RG_VPROC11_TRIMH,
	PMIC_RG_VPROC11_TRIML,
	PMIC_RG_VPROC11_VSLEEP_TRIM,
	PMIC_RG_VPROC11_SLEEP_VOLTAGE,
	PMIC_RG_VPROC12_TRIMH,
	PMIC_RG_VPROC12_TRIML,
	PMIC_RG_VPROC12_VSLEEP_TRIM,
	PMIC_RG_VPROC12_SLEEP_VOLTAGE,
	PMIC_RG_VSRAM_PROC_TRIMH,
	PMIC_RG_VSRAM_PROC_TRIML,
	PMIC_RG_VSRAM_PROC_VSLEEP_TRIM,
	PMIC_RG_VSRAM_PROC_SLEEP_VOLTAGE,
	PMIC_RG_VSRAM_CORE_TRIMH,
	PMIC_RG_VSRAM_CORE_TRIML,
	PMIC_RG_VSRAM_CORE_VSLEEP_TRIM,
	PMIC_RG_VSRAM_CORE_SLEEP_VOLTAGE,
	PMIC_RG_VSRAM_GPU_TRIMH,
	PMIC_RG_VSRAM_GPU_TRIML,
	PMIC_RG_VSRAM_GPU_VSLEEP_TRIM,
	PMIC_RG_VSRAM_GPU_SLEEP_VOLTAGE,
	PMIC_RG_VSRAM_MD_TRIMH,
	PMIC_RG_VSRAM_MD_TRIML,
	PMIC_RG_VSRAM_MD_VSLEEP_TRIM,
	PMIC_RG_VSRAM_MD_SLEEP_VOLTAGE,
	PMIC_RG_SMPS_IVGD_DET,
	PMIC_RG_VOUTDET_EN,
	PMIC_RG_AUTOK_RST,
	PMIC_RG_VPROC11_FPWM,
	PMIC_RG_VPROC12_FPWM,
	PMIC_RG_VPROC11_NDIS_EN,
	PMIC_RG_VPROC12_NDIS_EN,
	PMIC_RG_VPROC11_FCOT,
	PMIC_RG_VPROC12_FCOT,
	PMIC_RG_VPROC_TMDL,
	PMIC_RG_VPROC_DISCONFIG20,
	PMIC_RG_VPROC11_TBDIS,
	PMIC_RG_VPROC12_TBDIS,
	PMIC_RG_VPROC11_VDIFFOFF,
	PMIC_RG_VPROC12_VDIFFOFF,
	PMIC_RG_VPROC11_RCOMP0,
	PMIC_RG_VPROC11_RCOMP1,
	PMIC_RG_VPROC11_CCOMP0,
	PMIC_RG_VPROC11_CCOMP1,
	PMIC_RG_VPROC11_RAMP_SLP,
	PMIC_RG_VPROC12_RCOMP0,
	PMIC_RG_VPROC12_RCOMP1,
	PMIC_RG_VPROC12_CCOMP0,
	PMIC_RG_VPROC12_CCOMP1,
	PMIC_RG_VPROC12_RAMP_SLP,
	PMIC_RG_VPROC11_RCS,
	PMIC_RG_VPROC12_RCS,
	PMIC_RG_VPROC11_RCB,
	PMIC_RG_VPROC12_RCB,
	PMIC_RG_VPROC11_CSP_TRIM,
	PMIC_RG_VPROC12_CSP_TRIM,
	PMIC_RG_VPROC11_CSN_TRIM,
	PMIC_RG_VPROC12_CSN_TRIM,
	PMIC_RG_VPROC11_ZC_TRIM,
	PMIC_RG_VPROC12_ZC_TRIM,
	PMIC_RG_VPROC11_NLIM_TRIM,
	PMIC_RG_VPROC12_NLIM_TRIM,
	PMIC_RG_VPROC11_RPSI1_TRIM,
	PMIC_RG_VPROC12_RPSI1_TRIM,
	PMIC_RG_VPROC11_TB_WIDTH,
	PMIC_RG_VPROC12_TB_WIDTH,
	PMIC_RG_VPROC11_UG_SR,
	PMIC_RG_VPROC11_LG_SR,
	PMIC_RG_VPROC12_UG_SR,
	PMIC_RG_VPROC12_LG_SR,
	PMIC_RG_VPROC11_PFM_TON,
	PMIC_RG_VPROC12_PFM_TON,
	PMIC_RG_VPROC11_TON_TRIM,
	PMIC_RG_VPROC12_TON_TRIM,
	PMIC_RGS_VPROC11_OC_STATUS,
	PMIC_RGS_VPROC12_OC_STATUS,
	PMIC_RGS_VPROC_TRIMOK_STATUS,
	PMIC_RGS_VPROC_CONFIG20_STATUS,
	PMIC_RGS_VPROC11_PREOC_STATUS,
	PMIC_RGS_VPROC11_DIG_MON,
	PMIC_RGS_VPROC12_DIG_MON,
	PMIC_RG_VPROC11_TRAN_BST,
	PMIC_RG_VPROC12_TRAN_BST,
	PMIC_RG_VPROC11_COTRAMP_SLP,
	PMIC_RG_VPROC12_COTRAMP_SLP,
	PMIC_RG_VPROC11_SLEEP_TIME,
	PMIC_RG_VPROC12_SLEEP_TIME,
	PMIC_RG_VPROC11_VREFTB,
	PMIC_RG_VPROC12_VREFTB,
	PMIC_RG_VPROC11_CSNSLP_TRIM,
	PMIC_RG_VPROC12_CSNSLP_TRIM,
	PMIC_RG_VPROC11_CSPSLP_TRIM,
	PMIC_RG_VPROC12_CSPSLP_TRIM,
	PMIC_RG_VPROC11_FUGON,
	PMIC_RG_VPROC12_FUGON,
	PMIC_RG_VPROC11_FLGON,
	PMIC_RG_VPROC12_FLGON,
	PMIC_RG_VPROC11_PREOC_TRIM,
	PMIC_RG_VPROC11_RSV,
	PMIC_RG_VPROC12_RSV,
	PMIC_RG_VPROC11_NONAUDIBLE_EN,
	PMIC_RG_VPROC12_NONAUDIBLE_EN,
	PMIC_RG_VPROC_DISAUTOK,
	PMIC_RG_VCORE_FPWM,
	PMIC_RG_VGPU_FPWM,
	PMIC_RG_VCORE_NDIS_EN,
	PMIC_RG_VGPU_NDIS_EN,
	PMIC_RG_VCORE_FCOT,
	PMIC_RG_VGPU_FCOT,
	PMIC_RG_VCOREVGPU_TMDL,
	PMIC_RG_VCOREVGPU_DISCONFIG20,
	PMIC_RG_VCORE_TBDIS,
	PMIC_RG_VGPU_TBDIS,
	PMIC_RG_VCORE_VDIFFOFF,
	PMIC_RG_VGPU_VDIFFOFF,
	PMIC_RG_VCORE_RCOMP0,
	PMIC_RG_VCORE_RCOMP1,
	PMIC_RG_VCORE_CCOMP0,
	PMIC_RG_VCORE_CCOMP1,
	PMIC_RG_VCORE_RAMP_SLP,
	PMIC_RG_VGPU_RCOMP0,
	PMIC_RG_VGPU_RCOMP1,
	PMIC_RG_VGPU_CCOMP0,
	PMIC_RG_VGPU_CCOMP1,
	PMIC_RG_VGPU_RAMP_SLP,
	PMIC_RG_VCORE_RCS,
	PMIC_RG_VGPU_RCS,
	PMIC_RG_VCORE_RCB,
	PMIC_RG_VGPU_RCB,
	PMIC_RG_VCORE_CSP_TRIM,
	PMIC_RG_VGPU_CSP_TRIM,
	PMIC_RG_VCORE_CSN_TRIM,
	PMIC_RG_VGPU_CSN_TRIM,
	PMIC_RG_VCORE_ZC_TRIM,
	PMIC_RG_VGPU_ZC_TRIM,
	PMIC_RG_VCORE_NLIM_TRIM,
	PMIC_RG_VGPU_NLIM_TRIM,
	PMIC_RG_VCORE_RPSI1_TRIM,
	PMIC_RG_VGPU_RPSI1_TRIM,
	PMIC_RG_VCORE_TB_WIDTH,
	PMIC_RG_VGPU_TB_WIDTH,
	PMIC_RG_VCORE_UG_SR,
	PMIC_RG_VCORE_LG_SR,
	PMIC_RG_VGPU_UG_SR,
	PMIC_RG_VGPU_LG_SR,
	PMIC_RG_VCORE_PFM_TON,
	PMIC_RG_VGPU_PFM_TON,
	PMIC_RG_VCORE_TON_TRIM,
	PMIC_RG_VGPU_TON_TRIM,
	PMIC_RGS_VCORE_OC_STATUS,
	PMIC_RGS_VGPU_OC_STATUS,
	PMIC_RGS_VCOREVGPU_TRIMOK_STATUS,
	PMIC_RGS_VCOREVGPU_CONFIG20_STATUS,
	PMIC_RGS_VCORE_PREOC_STATUS,
	PMIC_RGS_VCORE_DIG_MON,
	PMIC_RGS_VGPU_DIG_MON,
	PMIC_RG_VCORE_TRAN_BST,
	PMIC_RG_VGPU_TRAN_BST,
	PMIC_RG_VCORE_COTRAMP_SLP,
	PMIC_RG_VGPU_COTRAMP_SLP,
	PMIC_RG_VCORE_SLEEP_TIME,
	PMIC_RG_VGPU_SLEEP_TIME,
	PMIC_RG_VCORE_VREFTB,
	PMIC_RG_VGPU_VREFTB,
	PMIC_RG_VCORE_CSNSLP_TRIM,
	PMIC_RG_VGPU_CSNSLP_TRIM,
	PMIC_RG_VCORE_CSPSLP_TRIM,
	PMIC_RG_VGPU_CSPSLP_TRIM,
	PMIC_RG_VCORE_FUGON,
	PMIC_RG_VGPU_FUGON,
	PMIC_RG_VCORE_FLGON,
	PMIC_RG_VGPU_FLGON,
	PMIC_RG_VCORE_PREOC_TRIM,
	PMIC_RG_VCORE_RSV,
	PMIC_RG_VGPU_RSV,
	PMIC_RG_VCORE_NONAUDIBLE_EN,
	PMIC_RG_VGPU_NONAUDIBLE_EN,
	PMIC_RG_VCOREVGPU_DISAUTOK,
	PMIC_RG_VDRAM1_FCOT,
	PMIC_RG_VDRAM1_RCOMP,
	PMIC_RG_VDRAM1_TB_DIS,
	PMIC_RG_VDRAM1_DISPG,
	PMIC_RG_VDRAM1_FPWM,
	PMIC_RG_VDRAM1_ZC_TRIM,
	PMIC_RG_VDRAM1_NLIM_TRIM,
	PMIC_RG_VDRAM1_PFM_TON,
	PMIC_RG_VDRAM1_PWMRAMP_SLP,
	PMIC_RG_VDRAM1_COTRAMP_SLP,
	PMIC_RG_VDRAM1_RCS,
	PMIC_RG_VDRAM1_CSN_TRIM,
	PMIC_RG_VDRAM1_CSP_TRIM,
	PMIC_RG_VDRAM1_RPSI_TRIM,
	PMIC_RG_VDRAM1_SLEEP_TIME,
	PMIC_RG_VDRAM1_NLIM_GATING,
	PMIC_RG_VDRAM1_TON_TRIM,
	PMIC_RG_VDRAM1_VDIFF_OFF,
	PMIC_RG_VDRAM1_VREFUP,
	PMIC_RG_VDRAM1_TB_WIDTH,
	PMIC_RG_VDRAM1_UG_SR,
	PMIC_RG_VDRAM1_LG_SR,
	PMIC_RG_VDRAM1_CCOMP,
	PMIC_RG_VDRAM1_NDIS_EN,
	PMIC_RG_VDRAM1_TMDL,
	PMIC_RG_VDRAM1_RSV,
	PMIC_RG_VDRAM1_CSNSLP_TRIM,
	PMIC_RG_VDRAM1_CSPSLP_TRIM,
	PMIC_RG_VDRAM1_FUGON,
	PMIC_RG_VDRAM1_FLGON,
	PMIC_RG_VDRAM1_NONAUDIBLE_EN,
	PMIC_RG_VDRAM1_VDIFFPFM_OFF,
	PMIC_RGS_VDRAM1_OC_STATUS,
	PMIC_RGS_VDRAM1_ENPWM_STATUS,
	PMIC_RG_VDRAM1_DISAUTOK,
	PMIC_RGS_VDRAM1_TRIMOK_STATUS,
	PMIC_RGS_VDRAM1_DIG_MON,
	PMIC_RG_VDRAM2_FCOT,
	PMIC_RG_VDRAM2_RCOMP,
	PMIC_RG_VDRAM2_TB_DIS,
	PMIC_RG_VDRAM2_DISPG,
	PMIC_RG_VDRAM2_FPWM,
	PMIC_RG_VDRAM2_ZC_TRIM,
	PMIC_RG_VDRAM2_NLIM_TRIM,
	PMIC_RG_VDRAM2_PFM_TON,
	PMIC_RG_VDRAM2_PWMRAMP_SLP,
	PMIC_RG_VDRAM2_COTRAMP_SLP,
	PMIC_RG_VDRAM2_RCS,
	PMIC_RG_VDRAM2_CSN_TRIM,
	PMIC_RG_VDRAM2_CSP_TRIM,
	PMIC_RG_VDRAM2_RPSI_TRIM,
	PMIC_RG_VDRAM2_SLEEP_TIME,
	PMIC_RG_VDRAM2_NLIM_GATING,
	PMIC_RG_VDRAM2_TON_TRIM,
	PMIC_RG_VDRAM2_VDIFF_OFF,
	PMIC_RG_VDRAM2_VREFUP,
	PMIC_RG_VDRAM2_TB_WIDTH,
	PMIC_RG_VDRAM2_UG_SR,
	PMIC_RG_VDRAM2_LG_SR,
	PMIC_RG_VDRAM2_CCOMP,
	PMIC_RG_VDRAM2_NDIS_EN,
	PMIC_RG_VDRAM2_TMDL,
	PMIC_RG_VDRAM2_RSV,
	PMIC_RG_VDRAM2_CSNSLP_TRIM,
	PMIC_RG_VDRAM2_CSPSLP_TRIM,
	PMIC_RG_VDRAM2_FUGON,
	PMIC_RG_VDRAM2_FLGON,
	PMIC_RG_VDRAM2_NONAUDIBLE_EN,
	PMIC_RG_VDRAM2_VDIFFPFM_OFF,
	PMIC_RGS_VDRAM2_OC_STATUS,
	PMIC_RGS_VDRAM2_ENPWM_STATUS,
	PMIC_RG_VDRAM2_DISAUTOK,
	PMIC_RGS_VDRAM2_TRIMOK_STATUS,
	PMIC_RGS_VDRAM2_DIG_MON,
	PMIC_RG_VMODEM_MODESET,
	PMIC_RG_VMODEM_NDIS_EN,
	PMIC_RG_VMODEM_VRF18_SSTART_EN,
	PMIC_RG_VMODEM_AUTO_MODE,
	PMIC_RG_VMODEM_RZSEL0,
	PMIC_RG_VMODEM_RZSEL1,
	PMIC_RG_VMODEM_CCSEL0,
	PMIC_RG_VMODEM_CCSEL1,
	PMIC_RG_VMODEM_CSL,
	PMIC_RG_VMODEM_SLP,
	PMIC_RG_VMODEM_ADRC_FEN,
	PMIC_RG_VMODEM_VC_CAP_CLAMP_FEN,
	PMIC_RG_VMODEM_VC_CLAMP_FEN,
	PMIC_RG_VMODEM_BURST,
	PMIC_RG_VMODEM_CSR,
	PMIC_RG_VMODEM_ZXOS_TRIM,
	PMIC_RG_VMODEM_PFMSR_EH,
	PMIC_RG_VMODEM_NLIM_GATING,
	PMIC_RG_VMODEM_PWMSR_EH,
	PMIC_RG_VMODEM_HS_VTHDET,
	PMIC_RG_VMODEM_PG_GATING,
	PMIC_RG_VMODEM_HS_ONSPEED_EH,
	PMIC_RG_VMODEM_NLIM_TRIMMING,
	PMIC_RG_VMODEM_SR_P,
	PMIC_RG_VMODEM_SR_N,
	PMIC_RG_VMODEM_PFM_RIP,
	PMIC_RG_VMODEM_TRAN_BST,
	PMIC_RG_VMODEM_DTS_ENB,
	PMIC_RG_VMODEM_MIN_OFF,
	PMIC_RG_VMODEM_1P35UP_SEL_EN,
	PMIC_RG_VMODEM_DLC_AUTO_MODE,
	PMIC_RG_VMODEM_SRC_AUTO_MODE,
	PMIC_RG_VMODEM_UGP_SR,
	PMIC_RG_VMODEM_LGP_SR,
	PMIC_RG_VMODEM_UGP_SR_PFM,
	PMIC_RG_VMODEM_LGP_SR_PFM,
	PMIC_RG_VMODEM_UGD_VTHSEL,
	PMIC_RG_VMODEM_FNLX,
	PMIC_RG_VMODEM_VDIFF_ENLOWIQ,
	PMIC_RG_VMODEM_PFMOC_FWUPOFF,
	PMIC_RG_VMODEM_PWMOC_FWUPOFF,
	PMIC_RG_VMODEM_CP_FWUPOFF,
	PMIC_RG_VMODEM_ZX_GATING,
	PMIC_RG_VMODEM_RSV,
	PMIC_RG_VMODEM_AZC_EN,
	PMIC_RG_VMODEM_AZC_DELAY,
	PMIC_RG_VMODEM_AZC_HOLD_ENB,
	PMIC_RGS_VMODEM_OC_STATUS,
	PMIC_RGS_VMODEM_DIG_MON,
	PMIC_RGS_VMODEM_ENPWM_STATUS,
	PMIC_RG_VMODEM_IODETECT_EN18,
	PMIC_RG_VMODEM_PREOC_SEL,
	PMIC_RG_VMODEM_NONAUDIBLE_EN,
	PMIC_RG_VS1_MIN_OFF,
	PMIC_RG_VS1_VRF18_SSTART_EN,
	PMIC_RG_VS1_1P35UP_SEL_EN,
	PMIC_RG_VS1_RZSEL,
	PMIC_RG_VS1_CSR,
	PMIC_RG_VS1_CSL,
	PMIC_RG_VS1_SLP,
	PMIC_RG_VS1_ZX_OS,
	PMIC_RG_VS1_NDIS_EN,
	PMIC_RG_VS1_CSM_N,
	PMIC_RG_VS1_CSM_P,
	PMIC_RG_VS1_RSV,
	PMIC_RG_VS1_ZXOS_TRIM,
	PMIC_RG_VS1_MODESET,
	PMIC_RG_VS1_PFM_RIP,
	PMIC_RG_VS1_TRAN_BST,
	PMIC_RG_VS1_DTS_ENB,
	PMIC_RG_VS1_AUTO_MODE,
	PMIC_RG_VS1_PWM_TRIG,
	PMIC_RG_VS1_RSV_H,
	PMIC_RG_VS1_RSV_L,
	PMIC_RG_VS1_NONAUDIBLE_EN,
	PMIC_RG_VS1_SR_P,
	PMIC_RG_VS1_SR_N,
	PMIC_RG_VS1_BURST,
	PMIC_RGS_VS1_ENPWM_STATUS,
	PMIC_RGS_VS1_OC_STATUS,
	PMIC_RGS_VS1_DIG_MON,
	PMIC_RG_VS2_MIN_OFF,
	PMIC_RG_VS2_VRF18_SSTART_EN,
	PMIC_RG_VS2_1P35UP_SEL_EN,
	PMIC_RG_VS2_RZSEL,
	PMIC_RG_VS2_CSR,
	PMIC_RG_VS2_CSL,
	PMIC_RG_VS2_SLP,
	PMIC_RG_VS2_ZX_OS,
	PMIC_RG_VS2_NDIS_EN,
	PMIC_RG_VS2_CSM_N,
	PMIC_RG_VS2_CSM_P,
	PMIC_RG_VS2_RSV,
	PMIC_RG_VS2_ZXOS_TRIM,
	PMIC_RG_VS2_MODESET,
	PMIC_RG_VS2_PFM_RIP,
	PMIC_RG_VS2_TRAN_BST,
	PMIC_RG_VS2_DTS_ENB,
	PMIC_RG_VS2_AUTO_MODE,
	PMIC_RG_VS2_PWM_TRIG,
	PMIC_RG_VS2_RSV_H,
	PMIC_RG_VS2_RSV_L,
	PMIC_RG_VS2_NONAUDIBLE_EN,
	PMIC_RG_VS2_SR_P,
	PMIC_RG_VS2_SR_N,
	PMIC_RG_VS2_BURST,
	PMIC_RGS_VS2_ENPWM_STATUS,
	PMIC_RGS_VS2_OC_STATUS,
	PMIC_RGS_VS2_DIG_MON,
	PMIC_RG_VPA_NDIS_EN,
	PMIC_RG_VPA_MODESET,
	PMIC_RG_VPA_CC,
	PMIC_RG_VPA_CSR,
	PMIC_RG_VPA_CSMIR,
	PMIC_RG_VPA_CSL,
	PMIC_RG_VPA_SLP,
	PMIC_RG_VPA_AZC_EN,
	PMIC_RG_VPA_CP_FWUPOFF,
	PMIC_RG_VPA_AZC_DELAY,
	PMIC_RG_VPA_RZSEL,
	PMIC_RG_VPA_ZXREF,
	PMIC_RG_VPA_NLIM_SEL,
	PMIC_RG_VPA_HZP,
	PMIC_RG_VPA_BWEX_GAT,
	PMIC_RG_VPA_SLEW,
	PMIC_RG_VPA_SLEW_NMOS,
	PMIC_RG_VPA_MIN_ON,
	PMIC_RG_VPA_VBAT_DEL,
	PMIC_RGS_VPA_AZC_VOS_SEL,
	PMIC_RG_VPA_MIN_PK,
	PMIC_RG_VPA_RSV1,
	PMIC_RG_VPA_RSV2,
	PMIC_RGS_VPA_OC_STATUS,
	PMIC_RGS_VPA_AZC_ZX,
	PMIC_WDTDBG_CLR,
	PMIC_WDTDBG_CON0_RSV0,
	PMIC_VPROC11_VOSEL_WDTDBG,
	PMIC_VPROC12_VOSEL_WDTDBG,
	PMIC_VCORE_VOSEL_WDTDBG,
	PMIC_VGPU_VOSEL_WDTDBG,
	PMIC_VDRAM1_VOSEL_WDTDBG,
	PMIC_VDRAM2_VOSEL_WDTDBG,
	PMIC_VMODEM_VOSEL_WDTDBG,
	PMIC_VS1_VOSEL_WDTDBG,
	PMIC_VS2_VOSEL_WDTDBG,
	PMIC_VPA_VOSEL_WDTDBG,
	PMIC_VSRAM_PROC_VOSEL_WDTDBG,
	PMIC_VSRAM_CORE_VOSEL_WDTDBG,
	PMIC_VSRAM_GPU_VOSEL_WDTDBG,
	PMIC_VSRAM_MD_VOSEL_WDTDBG,
	PMIC_RG_LDO_VIO28_EN,
	PMIC_RG_LDO_VIO28_LP,
	PMIC_RG_LDO_VIO28_SW_OP_EN,
	PMIC_RG_LDO_VIO28_HW0_OP_EN,
	PMIC_RG_LDO_VIO28_HW1_OP_EN,
	PMIC_RG_LDO_VIO28_HW2_OP_EN,
	PMIC_RG_LDO_VIO28_OP_EN_SET,
	PMIC_RG_LDO_VIO28_OP_EN_CLR,
	PMIC_RG_LDO_VIO28_HW0_OP_CFG,
	PMIC_RG_LDO_VIO28_HW1_OP_CFG,
	PMIC_RG_LDO_VIO28_HW2_OP_CFG,
	PMIC_RG_LDO_VIO28_ON_OP,
	PMIC_RG_LDO_VIO28_LP_OP,
	PMIC_RG_LDO_VIO28_OP_CFG_SET,
	PMIC_RG_LDO_VIO28_OP_CFG_CLR,
	PMIC_DA_QI_VIO28_MODE,
	PMIC_RG_LDO_VIO28_STBTD,
	PMIC_DA_QI_VIO28_STB,
	PMIC_DA_QI_VIO28_EN,
	PMIC_RG_LDO_VIO28_OCFB_EN,
	PMIC_DA_QI_VIO28_OCFB_EN,
	PMIC_RG_LDO_VIO28_DUMMY_LOAD,
	PMIC_DA_QI_VIO28_DUMMY_LOAD,
	PMIC_RG_LDO_VIO18_EN,
	PMIC_RG_LDO_VIO18_LP,
	PMIC_RG_LDO_VIO18_SW_OP_EN,
	PMIC_RG_LDO_VIO18_HW0_OP_EN,
	PMIC_RG_LDO_VIO18_HW1_OP_EN,
	PMIC_RG_LDO_VIO18_HW2_OP_EN,
	PMIC_RG_LDO_VIO18_OP_EN_SET,
	PMIC_RG_LDO_VIO18_OP_EN_CLR,
	PMIC_RG_LDO_VIO18_HW0_OP_CFG,
	PMIC_RG_LDO_VIO18_HW1_OP_CFG,
	PMIC_RG_LDO_VIO18_HW2_OP_CFG,
	PMIC_RG_LDO_VIO18_ON_OP,
	PMIC_RG_LDO_VIO18_LP_OP,
	PMIC_RG_LDO_VIO18_OP_CFG_SET,
	PMIC_RG_LDO_VIO18_OP_CFG_CLR,
	PMIC_DA_QI_VIO18_MODE,
	PMIC_RG_LDO_VIO18_STBTD,
	PMIC_DA_QI_VIO18_STB,
	PMIC_DA_QI_VIO18_EN,
	PMIC_RG_LDO_VIO18_OCFB_EN,
	PMIC_DA_QI_VIO18_OCFB_EN,
	PMIC_RG_LDO_VIO18_DUMMY_LOAD,
	PMIC_DA_QI_VIO18_DUMMY_LOAD,
	PMIC_RG_LDO_VUFS18_EN,
	PMIC_RG_LDO_VUFS18_LP,
	PMIC_RG_LDO_VUFS18_SW_OP_EN,
	PMIC_RG_LDO_VUFS18_HW0_OP_EN,
	PMIC_RG_LDO_VUFS18_HW1_OP_EN,
	PMIC_RG_LDO_VUFS18_HW2_OP_EN,
	PMIC_RG_LDO_VUFS18_OP_EN_SET,
	PMIC_RG_LDO_VUFS18_OP_EN_CLR,
	PMIC_RG_LDO_VUFS18_HW0_OP_CFG,
	PMIC_RG_LDO_VUFS18_HW1_OP_CFG,
	PMIC_RG_LDO_VUFS18_HW2_OP_CFG,
	PMIC_RG_LDO_VUFS18_ON_OP,
	PMIC_RG_LDO_VUFS18_LP_OP,
	PMIC_RG_LDO_VUFS18_OP_CFG_SET,
	PMIC_RG_LDO_VUFS18_OP_CFG_CLR,
	PMIC_DA_QI_VUFS18_MODE,
	PMIC_RG_LDO_VUFS18_STBTD,
	PMIC_DA_QI_VUFS18_STB,
	PMIC_DA_QI_VUFS18_EN,
	PMIC_RG_LDO_VUFS18_OCFB_EN,
	PMIC_DA_QI_VUFS18_OCFB_EN,
	PMIC_RG_LDO_VUFS18_DUMMY_LOAD,
	PMIC_DA_QI_VUFS18_DUMMY_LOAD,
	PMIC_RG_LDO_VA10_EN,
	PMIC_RG_LDO_VA10_LP,
	PMIC_RG_VA10_VOCAL,
	PMIC_RG_VA10_VOSEL,
	PMIC_RG_LDO_VA10_SW_OP_EN,
	PMIC_RG_LDO_VA10_HW0_OP_EN,
	PMIC_RG_LDO_VA10_HW1_OP_EN,
	PMIC_RG_LDO_VA10_HW2_OP_EN,
	PMIC_RG_LDO_VA10_OP_EN_SET,
	PMIC_RG_LDO_VA10_OP_EN_CLR,
	PMIC_RG_LDO_VA10_HW0_OP_CFG,
	PMIC_RG_LDO_VA10_HW1_OP_CFG,
	PMIC_RG_LDO_VA10_HW2_OP_CFG,
	PMIC_RG_LDO_VA10_ON_OP,
	PMIC_RG_LDO_VA10_LP_OP,
	PMIC_RG_LDO_VA10_OP_CFG_SET,
	PMIC_RG_LDO_VA10_OP_CFG_CLR,
	PMIC_DA_QI_VA10_MODE,
	PMIC_RG_LDO_VA10_STBTD,
	PMIC_DA_QI_VA10_STB,
	PMIC_DA_QI_VA10_EN,
	PMIC_RG_LDO_VA10_SLEEP_MODE,
	PMIC_RG_LDO_VA10_OCFB_EN,
	PMIC_DA_QI_VA10_OCFB_EN,
	PMIC_RG_LDO_VA10_DUMMY_LOAD,
	PMIC_DA_QI_VA10_DUMMY_LOAD,
	PMIC_RG_LDO_VA12_EN,
	PMIC_RG_LDO_VA12_LP,
	PMIC_RG_LDO_VA12_SW_OP_EN,
	PMIC_RG_LDO_VA12_HW0_OP_EN,
	PMIC_RG_LDO_VA12_HW1_OP_EN,
	PMIC_RG_LDO_VA12_HW2_OP_EN,
	PMIC_RG_LDO_VA12_OP_EN_SET,
	PMIC_RG_LDO_VA12_OP_EN_CLR,
	PMIC_RG_LDO_VA12_HW0_OP_CFG,
	PMIC_RG_LDO_VA12_HW1_OP_CFG,
	PMIC_RG_LDO_VA12_HW2_OP_CFG,
	PMIC_RG_LDO_VA12_ON_OP,
	PMIC_RG_LDO_VA12_LP_OP,
	PMIC_RG_LDO_VA12_OP_CFG_SET,
	PMIC_RG_LDO_VA12_OP_CFG_CLR,
	PMIC_DA_QI_VA12_MODE,
	PMIC_RG_LDO_VA12_STBTD,
	PMIC_DA_QI_VA12_STB,
	PMIC_DA_QI_VA12_EN,
	PMIC_RG_LDO_VA12_OCFB_EN,
	PMIC_DA_QI_VA12_OCFB_EN,
	PMIC_RG_LDO_VA12_DUMMY_LOAD,
	PMIC_DA_QI_VA12_DUMMY_LOAD,
	PMIC_RG_LDO_VA18_EN,
	PMIC_RG_LDO_VA18_LP,
	PMIC_RG_LDO_VA18_SW_OP_EN,
	PMIC_RG_LDO_VA18_HW0_OP_EN,
	PMIC_RG_LDO_VA18_HW1_OP_EN,
	PMIC_RG_LDO_VA18_HW2_OP_EN,
	PMIC_RG_LDO_VA18_OP_EN_SET,
	PMIC_RG_LDO_VA18_OP_EN_CLR,
	PMIC_RG_LDO_VA18_HW0_OP_CFG,
	PMIC_RG_LDO_VA18_HW1_OP_CFG,
	PMIC_RG_LDO_VA18_HW2_OP_CFG,
	PMIC_RG_LDO_VA18_ON_OP,
	PMIC_RG_LDO_VA18_LP_OP,
	PMIC_RG_LDO_VA18_OP_CFG_SET,
	PMIC_RG_LDO_VA18_OP_CFG_CLR,
	PMIC_DA_QI_VA18_MODE,
	PMIC_RG_LDO_VA18_STBTD,
	PMIC_DA_QI_VA18_STB,
	PMIC_DA_QI_VA18_EN,
	PMIC_RG_LDO_VA18_AUXADC_PWDB_EN,
	PMIC_RG_LDO_VA18_OCFB_EN,
	PMIC_DA_QI_VA18_OCFB_EN,
	PMIC_RG_LDO_VA18_DUMMY_LOAD,
	PMIC_DA_QI_VA18_DUMMY_LOAD,
	PMIC_RG_LDO_VUSB33_EN_0,
	PMIC_RG_LDO_VUSB33_LP,
	PMIC_RG_LDO_VUSB33_SW_OP_EN,
	PMIC_RG_LDO_VUSB33_HW0_OP_EN,
	PMIC_RG_LDO_VUSB33_HW1_OP_EN,
	PMIC_RG_LDO_VUSB33_HW2_OP_EN,
	PMIC_RG_LDO_VUSB33_OP_EN_SET,
	PMIC_RG_LDO_VUSB33_OP_EN_CLR,
	PMIC_RG_LDO_VUSB33_HW0_OP_CFG,
	PMIC_RG_LDO_VUSB33_HW1_OP_CFG,
	PMIC_RG_LDO_VUSB33_HW2_OP_CFG,
	PMIC_RG_LDO_VUSB33_ON_OP,
	PMIC_RG_LDO_VUSB33_LP_OP,
	PMIC_RG_LDO_VUSB33_OP_CFG_SET,
	PMIC_RG_LDO_VUSB33_OP_CFG_CLR,
	PMIC_RG_LDO_VUSB33_EN_1,
	PMIC_DA_QI_VUSB33_MODE,
	PMIC_RG_LDO_VUSB33_STBTD,
	PMIC_DA_QI_VUSB33_STB,
	PMIC_DA_QI_VUSB33_EN,
	PMIC_RG_LDO_VUSB33_OCFB_EN,
	PMIC_DA_QI_VUSB33_OCFB_EN,
	PMIC_RG_LDO_VUSB33_DUMMY_LOAD,
	PMIC_DA_QI_VUSB33_DUMMY_LOAD,
	PMIC_RG_LDO_VEMC_EN,
	PMIC_RG_LDO_VEMC_LP,
	PMIC_RG_LDO_VEMC_SW_OP_EN,
	PMIC_RG_LDO_VEMC_HW0_OP_EN,
	PMIC_RG_LDO_VEMC_HW1_OP_EN,
	PMIC_RG_LDO_VEMC_HW2_OP_EN,
	PMIC_RG_LDO_VEMC_OP_EN_SET,
	PMIC_RG_LDO_VEMC_OP_EN_CLR,
	PMIC_RG_LDO_VEMC_HW0_OP_CFG,
	PMIC_RG_LDO_VEMC_HW1_OP_CFG,
	PMIC_RG_LDO_VEMC_HW2_OP_CFG,
	PMIC_RG_LDO_VEMC_ON_OP,
	PMIC_RG_LDO_VEMC_LP_OP,
	PMIC_RG_LDO_VEMC_OP_CFG_SET,
	PMIC_RG_LDO_VEMC_OP_CFG_CLR,
	PMIC_DA_QI_VEMC_MODE,
	PMIC_RG_LDO_VEMC_STBTD,
	PMIC_DA_QI_VEMC_STB,
	PMIC_DA_QI_VEMC_EN,
	PMIC_RG_LDO_VEMC_OCFB_EN,
	PMIC_DA_QI_VEMC_OCFB_EN,
	PMIC_RG_LDO_VEMC_DUMMY_LOAD,
	PMIC_DA_QI_VEMC_DUMMY_LOAD,
	PMIC_RG_LDO_VXO22_EN,
	PMIC_RG_LDO_VXO22_LP,
	PMIC_RG_LDO_VXO22_SW_OP_EN,
	PMIC_RG_LDO_VXO22_HW0_OP_EN,
	PMIC_RG_LDO_VXO22_HW1_OP_EN,
	PMIC_RG_LDO_VXO22_HW2_OP_EN,
	PMIC_RG_LDO_VXO22_OP_EN_SET,
	PMIC_RG_LDO_VXO22_OP_EN_CLR,
	PMIC_RG_LDO_VXO22_HW0_OP_CFG,
	PMIC_RG_LDO_VXO22_HW1_OP_CFG,
	PMIC_RG_LDO_VXO22_HW2_OP_CFG,
	PMIC_RG_LDO_VXO22_ON_OP,
	PMIC_RG_LDO_VXO22_LP_OP,
	PMIC_RG_LDO_VXO22_OP_CFG_SET,
	PMIC_RG_LDO_VXO22_OP_CFG_CLR,
	PMIC_DA_QI_VXO22_MODE,
	PMIC_RG_LDO_VXO22_STBTD,
	PMIC_DA_QI_VXO22_STB,
	PMIC_DA_QI_VXO22_EN,
	PMIC_RG_LDO_VXO22_OCFB_EN,
	PMIC_DA_QI_VXO22_OCFB_EN,
	PMIC_RG_LDO_VXO22_DUMMY_LOAD,
	PMIC_DA_QI_VXO22_DUMMY_LOAD,
	PMIC_RG_LDO_VXO18_EN,
	PMIC_RG_LDO_VXO18_LP,
	PMIC_RG_LDO_VXO18_SW_OP_EN,
	PMIC_RG_LDO_VXO18_HW0_OP_EN,
	PMIC_RG_LDO_VXO18_HW1_OP_EN,
	PMIC_RG_LDO_VXO18_HW2_OP_EN,
	PMIC_RG_LDO_VXO18_OP_EN_SET,
	PMIC_RG_LDO_VXO18_OP_EN_CLR,
	PMIC_RG_LDO_VXO18_HW0_OP_CFG,
	PMIC_RG_LDO_VXO18_HW1_OP_CFG,
	PMIC_RG_LDO_VXO18_HW2_OP_CFG,
	PMIC_RG_LDO_VXO18_ON_OP,
	PMIC_RG_LDO_VXO18_LP_OP,
	PMIC_RG_LDO_VXO18_OP_CFG_SET,
	PMIC_RG_LDO_VXO18_OP_CFG_CLR,
	PMIC_DA_QI_VXO18_MODE,
	PMIC_RG_LDO_VXO18_STBTD,
	PMIC_DA_QI_VXO18_STB,
	PMIC_DA_QI_VXO18_EN,
	PMIC_RG_LDO_VXO18_OCFB_EN,
	PMIC_DA_QI_VXO18_OCFB_EN,
	PMIC_RG_LDO_VXO18_DUMMY_LOAD,
	PMIC_DA_QI_VXO18_DUMMY_LOAD,
	PMIC_RG_LDO_VSIM1_EN,
	PMIC_RG_LDO_VSIM1_LP,
	PMIC_RG_LDO_VSIM1_SW_OP_EN,
	PMIC_RG_LDO_VSIM1_HW0_OP_EN,
	PMIC_RG_LDO_VSIM1_HW1_OP_EN,
	PMIC_RG_LDO_VSIM1_HW2_OP_EN,
	PMIC_RG_LDO_VSIM1_OP_EN_SET,
	PMIC_RG_LDO_VSIM1_OP_EN_CLR,
	PMIC_RG_LDO_VSIM1_HW0_OP_CFG,
	PMIC_RG_LDO_VSIM1_HW1_OP_CFG,
	PMIC_RG_LDO_VSIM1_HW2_OP_CFG,
	PMIC_RG_LDO_VSIM1_ON_OP,
	PMIC_RG_LDO_VSIM1_LP_OP,
	PMIC_RG_LDO_VSIM1_OP_CFG_SET,
	PMIC_RG_LDO_VSIM1_OP_CFG_CLR,
	PMIC_DA_QI_VSIM1_MODE,
	PMIC_RG_LDO_VSIM1_STBTD,
	PMIC_DA_QI_VSIM1_STB,
	PMIC_DA_QI_VSIM1_EN,
	PMIC_RG_LDO_VSIM1_OCFB_EN,
	PMIC_DA_QI_VSIM1_OCFB_EN,
	PMIC_RG_LDO_VSIM1_DUMMY_LOAD,
	PMIC_DA_QI_VSIM1_DUMMY_LOAD,
	PMIC_RG_LDO_VSIM2_EN,
	PMIC_RG_LDO_VSIM2_LP,
	PMIC_RG_LDO_VSIM2_SW_OP_EN,
	PMIC_RG_LDO_VSIM2_HW0_OP_EN,
	PMIC_RG_LDO_VSIM2_HW1_OP_EN,
	PMIC_RG_LDO_VSIM2_HW2_OP_EN,
	PMIC_RG_LDO_VSIM2_OP_EN_SET,
	PMIC_RG_LDO_VSIM2_OP_EN_CLR,
	PMIC_RG_LDO_VSIM2_HW0_OP_CFG,
	PMIC_RG_LDO_VSIM2_HW1_OP_CFG,
	PMIC_RG_LDO_VSIM2_HW2_OP_CFG,
	PMIC_RG_LDO_VSIM2_ON_OP,
	PMIC_RG_LDO_VSIM2_LP_OP,
	PMIC_RG_LDO_VSIM2_OP_CFG_SET,
	PMIC_RG_LDO_VSIM2_OP_CFG_CLR,
	PMIC_DA_QI_VSIM2_MODE,
	PMIC_RG_LDO_VSIM2_STBTD,
	PMIC_DA_QI_VSIM2_STB,
	PMIC_DA_QI_VSIM2_EN,
	PMIC_RG_LDO_VSIM2_OCFB_EN,
	PMIC_DA_QI_VSIM2_OCFB_EN,
	PMIC_RG_LDO_VSIM2_DUMMY_LOAD,
	PMIC_DA_QI_VSIM2_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMD1_EN,
	PMIC_RG_LDO_VCAMD1_LP,
	PMIC_RG_LDO_VCAMD1_SW_OP_EN,
	PMIC_RG_LDO_VCAMD1_HW0_OP_EN,
	PMIC_RG_LDO_VCAMD1_HW1_OP_EN,
	PMIC_RG_LDO_VCAMD1_HW2_OP_EN,
	PMIC_RG_LDO_VCAMD1_OP_EN_SET,
	PMIC_RG_LDO_VCAMD1_OP_EN_CLR,
	PMIC_RG_LDO_VCAMD1_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMD1_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMD1_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMD1_ON_OP,
	PMIC_RG_LDO_VCAMD1_LP_OP,
	PMIC_RG_LDO_VCAMD1_OP_CFG_SET,
	PMIC_RG_LDO_VCAMD1_OP_CFG_CLR,
	PMIC_DA_QI_VCAMD1_MODE,
	PMIC_RG_LDO_VCAMD1_STBTD,
	PMIC_DA_QI_VCAMD1_STB,
	PMIC_DA_QI_VCAMD1_EN,
	PMIC_RG_LDO_VCAMD1_OCFB_EN,
	PMIC_DA_QI_VCAMD1_OCFB_EN,
	PMIC_RG_LDO_VCAMD1_DUMMY_LOAD,
	PMIC_DA_QI_VCAMD1_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMD2_EN,
	PMIC_RG_LDO_VCAMD2_LP,
	PMIC_RG_LDO_VCAMD2_SW_OP_EN,
	PMIC_RG_LDO_VCAMD2_HW0_OP_EN,
	PMIC_RG_LDO_VCAMD2_HW1_OP_EN,
	PMIC_RG_LDO_VCAMD2_HW2_OP_EN,
	PMIC_RG_LDO_VCAMD2_OP_EN_SET,
	PMIC_RG_LDO_VCAMD2_OP_EN_CLR,
	PMIC_RG_LDO_VCAMD2_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMD2_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMD2_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMD2_ON_OP,
	PMIC_RG_LDO_VCAMD2_LP_OP,
	PMIC_RG_LDO_VCAMD2_OP_CFG_SET,
	PMIC_RG_LDO_VCAMD2_OP_CFG_CLR,
	PMIC_DA_QI_VCAMD2_MODE,
	PMIC_RG_LDO_VCAMD2_STBTD,
	PMIC_DA_QI_VCAMD2_STB,
	PMIC_DA_QI_VCAMD2_EN,
	PMIC_RG_LDO_VCAMD2_OCFB_EN,
	PMIC_DA_QI_VCAMD2_OCFB_EN,
	PMIC_RG_LDO_VCAMD2_DUMMY_LOAD,
	PMIC_DA_QI_VCAMD2_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMIO_EN,
	PMIC_RG_LDO_VCAMIO_LP,
	PMIC_RG_LDO_VCAMIO_SW_OP_EN,
	PMIC_RG_LDO_VCAMIO_HW0_OP_EN,
	PMIC_RG_LDO_VCAMIO_HW1_OP_EN,
	PMIC_RG_LDO_VCAMIO_HW2_OP_EN,
	PMIC_RG_LDO_VCAMIO_OP_EN_SET,
	PMIC_RG_LDO_VCAMIO_OP_EN_CLR,
	PMIC_RG_LDO_VCAMIO_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMIO_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMIO_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMIO_ON_OP,
	PMIC_RG_LDO_VCAMIO_LP_OP,
	PMIC_RG_LDO_VCAMIO_OP_CFG_SET,
	PMIC_RG_LDO_VCAMIO_OP_CFG_CLR,
	PMIC_DA_QI_VCAMIO_MODE,
	PMIC_RG_LDO_VCAMIO_STBTD,
	PMIC_DA_QI_VCAMIO_STB,
	PMIC_DA_QI_VCAMIO_EN,
	PMIC_RG_LDO_VCAMIO_OCFB_EN,
	PMIC_DA_QI_VCAMIO_OCFB_EN,
	PMIC_RG_LDO_VCAMIO_DUMMY_LOAD,
	PMIC_DA_QI_VCAMIO_DUMMY_LOAD,
	PMIC_RG_LDO_VMIPI_EN,
	PMIC_RG_LDO_VMIPI_LP,
	PMIC_RG_LDO_VMIPI_SW_OP_EN,
	PMIC_RG_LDO_VMIPI_HW0_OP_EN,
	PMIC_RG_LDO_VMIPI_HW1_OP_EN,
	PMIC_RG_LDO_VMIPI_HW2_OP_EN,
	PMIC_RG_LDO_VMIPI_OP_EN_SET,
	PMIC_RG_LDO_VMIPI_OP_EN_CLR,
	PMIC_RG_LDO_VMIPI_HW0_OP_CFG,
	PMIC_RG_LDO_VMIPI_HW1_OP_CFG,
	PMIC_RG_LDO_VMIPI_HW2_OP_CFG,
	PMIC_RG_LDO_VMIPI_ON_OP,
	PMIC_RG_LDO_VMIPI_LP_OP,
	PMIC_RG_LDO_VMIPI_OP_CFG_SET,
	PMIC_RG_LDO_VMIPI_OP_CFG_CLR,
	PMIC_DA_QI_VMIPI_MODE,
	PMIC_RG_LDO_VMIPI_STBTD,
	PMIC_DA_QI_VMIPI_STB,
	PMIC_DA_QI_VMIPI_EN,
	PMIC_RG_LDO_VMIPI_OCFB_EN,
	PMIC_DA_QI_VMIPI_OCFB_EN,
	PMIC_RG_LDO_VMIPI_DUMMY_LOAD,
	PMIC_DA_QI_VMIPI_DUMMY_LOAD,
	PMIC_RG_LDO_VGP_EN,
	PMIC_RG_LDO_VGP_LP,
	PMIC_RG_LDO_VGP_SW_OP_EN,
	PMIC_RG_LDO_VGP_HW0_OP_EN,
	PMIC_RG_LDO_VGP_HW1_OP_EN,
	PMIC_RG_LDO_VGP_HW2_OP_EN,
	PMIC_RG_LDO_VGP_OP_EN_SET,
	PMIC_RG_LDO_VGP_OP_EN_CLR,
	PMIC_RG_LDO_VGP_HW0_OP_CFG,
	PMIC_RG_LDO_VGP_HW1_OP_CFG,
	PMIC_RG_LDO_VGP_HW2_OP_CFG,
	PMIC_RG_LDO_VGP_ON_OP,
	PMIC_RG_LDO_VGP_LP_OP,
	PMIC_RG_LDO_VGP_OP_CFG_SET,
	PMIC_RG_LDO_VGP_OP_CFG_CLR,
	PMIC_DA_QI_VGP_MODE,
	PMIC_RG_LDO_VGP_STBTD,
	PMIC_DA_QI_VGP_STB,
	PMIC_DA_QI_VGP_EN,
	PMIC_RG_LDO_VGP_OCFB_EN,
	PMIC_DA_QI_VGP_OCFB_EN,
	PMIC_RG_LDO_VGP_DUMMY_LOAD,
	PMIC_DA_QI_VGP_DUMMY_LOAD,
	PMIC_RG_LDO_VCN33_EN_BT,
	PMIC_RG_LDO_VCN33_LP,
	PMIC_RG_LDO_VCN33_SW_OP_EN,
	PMIC_RG_LDO_VCN33_HW0_OP_EN,
	PMIC_RG_LDO_VCN33_HW1_OP_EN,
	PMIC_RG_LDO_VCN33_HW2_OP_EN,
	PMIC_RG_LDO_VCN33_OP_EN_SET,
	PMIC_RG_LDO_VCN33_OP_EN_CLR,
	PMIC_RG_LDO_VCN33_HW0_OP_CFG,
	PMIC_RG_LDO_VCN33_HW1_OP_CFG,
	PMIC_RG_LDO_VCN33_HW2_OP_CFG,
	PMIC_RG_LDO_VCN33_ON_OP,
	PMIC_RG_LDO_VCN33_LP_OP,
	PMIC_RG_LDO_VCN33_OP_CFG_SET,
	PMIC_RG_LDO_VCN33_OP_CFG_CLR,
	PMIC_RG_LDO_VCN33_EN_WIFI,
	PMIC_DA_QI_VCN33_MODE,
	PMIC_RG_LDO_VCN33_STBTD,
	PMIC_DA_QI_VCN33_STB,
	PMIC_DA_QI_VCN33_EN,
	PMIC_RG_LDO_VCN33_OCFB_EN,
	PMIC_DA_QI_VCN33_OCFB_EN,
	PMIC_RG_LDO_VCN33_DUMMY_LOAD,
	PMIC_DA_QI_VCN33_DUMMY_LOAD,
	PMIC_RG_LDO_VCN18_EN,
	PMIC_RG_LDO_VCN18_LP,
	PMIC_RG_LDO_VCN18_SW_OP_EN,
	PMIC_RG_LDO_VCN18_HW0_OP_EN,
	PMIC_RG_LDO_VCN18_HW1_OP_EN,
	PMIC_RG_LDO_VCN18_HW2_OP_EN,
	PMIC_RG_LDO_VCN18_OP_EN_SET,
	PMIC_RG_LDO_VCN18_OP_EN_CLR,
	PMIC_RG_LDO_VCN18_HW0_OP_CFG,
	PMIC_RG_LDO_VCN18_HW1_OP_CFG,
	PMIC_RG_LDO_VCN18_HW2_OP_CFG,
	PMIC_RG_LDO_VCN18_ON_OP,
	PMIC_RG_LDO_VCN18_LP_OP,
	PMIC_RG_LDO_VCN18_OP_CFG_SET,
	PMIC_RG_LDO_VCN18_OP_CFG_CLR,
	PMIC_DA_QI_VCN18_MODE,
	PMIC_RG_LDO_VCN18_STBTD,
	PMIC_DA_QI_VCN18_STB,
	PMIC_DA_QI_VCN18_EN,
	PMIC_RG_LDO_VCN18_OCFB_EN,
	PMIC_DA_QI_VCN18_OCFB_EN,
	PMIC_RG_LDO_VCN18_DUMMY_LOAD,
	PMIC_DA_QI_VCN18_DUMMY_LOAD,
	PMIC_RG_LDO_VCN28_EN,
	PMIC_RG_LDO_VCN28_LP,
	PMIC_RG_LDO_VCN28_SW_OP_EN,
	PMIC_RG_LDO_VCN28_HW0_OP_EN,
	PMIC_RG_LDO_VCN28_HW1_OP_EN,
	PMIC_RG_LDO_VCN28_HW2_OP_EN,
	PMIC_RG_LDO_VCN28_HW3_OP_EN,
	PMIC_RG_LDO_VCN28_OP_EN_SET,
	PMIC_RG_LDO_VCN28_OP_EN_CLR,
	PMIC_RG_LDO_VCN28_HW0_OP_CFG,
	PMIC_RG_LDO_VCN28_HW1_OP_CFG,
	PMIC_RG_LDO_VCN28_HW2_OP_CFG,
	PMIC_RG_LDO_VCN28_HW3_OP_CFG,
	PMIC_RG_LDO_VCN28_ON_OP,
	PMIC_RG_LDO_VCN28_LP_OP,
	PMIC_RG_LDO_VCN28_OP_CFG_SET,
	PMIC_RG_LDO_VCN28_OP_CFG_CLR,
	PMIC_DA_QI_VCN28_MODE,
	PMIC_RG_LDO_VCN28_STBTD,
	PMIC_DA_QI_VCN28_STB,
	PMIC_DA_QI_VCN28_EN,
	PMIC_RG_LDO_VCN28_OCFB_EN,
	PMIC_DA_QI_VCN28_OCFB_EN,
	PMIC_RG_LDO_VCN28_DUMMY_LOAD,
	PMIC_DA_QI_VCN28_DUMMY_LOAD,
	PMIC_RG_LDO_VBIF28_EN,
	PMIC_RG_LDO_VBIF28_LP,
	PMIC_RG_LDO_VBIF28_SW_OP_EN,
	PMIC_RG_LDO_VBIF28_HW0_OP_EN,
	PMIC_RG_LDO_VBIF28_HW1_OP_EN,
	PMIC_RG_LDO_VBIF28_HW2_OP_EN,
	PMIC_RG_LDO_VBIF28_OP_EN_SET,
	PMIC_RG_LDO_VBIF28_OP_EN_CLR,
	PMIC_RG_LDO_VBIF28_HW0_OP_CFG,
	PMIC_RG_LDO_VBIF28_HW1_OP_CFG,
	PMIC_RG_LDO_VBIF28_HW2_OP_CFG,
	PMIC_RG_LDO_VBIF28_ON_OP,
	PMIC_RG_LDO_VBIF28_LP_OP,
	PMIC_RG_LDO_VBIF28_OP_CFG_SET,
	PMIC_RG_LDO_VBIF28_OP_CFG_CLR,
	PMIC_DA_QI_VBIF28_MODE,
	PMIC_RG_LDO_VBIF28_STBTD,
	PMIC_DA_QI_VBIF28_STB,
	PMIC_DA_QI_VBIF28_EN,
	PMIC_RG_LDO_VBIF28_OCFB_EN,
	PMIC_DA_QI_VBIF28_OCFB_EN,
	PMIC_RG_LDO_VBIF28_DUMMY_LOAD,
	PMIC_DA_QI_VBIF28_DUMMY_LOAD,
	PMIC_RG_LDO_VTCXO24_EN,
	PMIC_RG_LDO_VTCXO24_LP,
	PMIC_RG_LDO_VTCXO24_SW_OP_EN,
	PMIC_RG_LDO_VTCXO24_HW0_OP_EN,
	PMIC_RG_LDO_VTCXO24_HW1_OP_EN,
	PMIC_RG_LDO_VTCXO24_HW2_OP_EN,
	PMIC_RG_LDO_VTCXO24_OP_EN_SET,
	PMIC_RG_LDO_VTCXO24_OP_EN_CLR,
	PMIC_RG_LDO_VTCXO24_HW0_OP_CFG,
	PMIC_RG_LDO_VTCXO24_HW1_OP_CFG,
	PMIC_RG_LDO_VTCXO24_HW2_OP_CFG,
	PMIC_RG_LDO_VTCXO24_ON_OP,
	PMIC_RG_LDO_VTCXO24_LP_OP,
	PMIC_RG_LDO_VTCXO24_OP_CFG_SET,
	PMIC_RG_LDO_VTCXO24_OP_CFG_CLR,
	PMIC_DA_QI_VTCXO24_MODE,
	PMIC_RG_LDO_VTCXO24_STBTD,
	PMIC_DA_QI_VTCXO24_STB,
	PMIC_DA_QI_VTCXO24_EN,
	PMIC_RG_LDO_VTCXO24_OCFB_EN,
	PMIC_DA_QI_VTCXO24_OCFB_EN,
	PMIC_RG_LDO_VTCXO24_DUMMY_LOAD,
	PMIC_DA_QI_VTCXO24_DUMMY_LOAD,
	PMIC_RG_LDO_VLDO28_EN_AF,
	PMIC_RG_LDO_VLDO28_LP,
	PMIC_RG_LDO_VLDO28_SW_OP_EN,
	PMIC_RG_LDO_VLDO28_HW0_OP_EN,
	PMIC_RG_LDO_VLDO28_HW1_OP_EN,
	PMIC_RG_LDO_VLDO28_HW2_OP_EN,
	PMIC_RG_LDO_VLDO28_OP_EN_SET,
	PMIC_RG_LDO_VLDO28_OP_EN_CLR,
	PMIC_RG_LDO_VLDO28_HW0_OP_CFG,
	PMIC_RG_LDO_VLDO28_HW1_OP_CFG,
	PMIC_RG_LDO_VLDO28_HW2_OP_CFG,
	PMIC_RG_LDO_VLDO28_ON_OP,
	PMIC_RG_LDO_VLDO28_LP_OP,
	PMIC_RG_LDO_VLDO28_OP_CFG_SET,
	PMIC_RG_LDO_VLDO28_OP_CFG_CLR,
	PMIC_RG_LDO_VLDO28_EN_TP,
	PMIC_DA_QI_VLDO28_MODE,
	PMIC_RG_LDO_VLDO28_STBTD,
	PMIC_DA_QI_VLDO28_STB,
	PMIC_DA_QI_VLDO28_EN,
	PMIC_RG_LDO_VLDO28_OCFB_EN,
	PMIC_DA_QI_VLDO28_OCFB_EN,
	PMIC_RG_LDO_VLDO28_DUMMY_LOAD,
	PMIC_DA_QI_VLDO28_DUMMY_LOAD,
	PMIC_RG_LDO_VGP2_EN,
	PMIC_RG_LDO_VGP2_LP,
	PMIC_RG_LDO_VGP2_SW_OP_EN,
	PMIC_RG_LDO_VGP2_HW0_OP_EN,
	PMIC_RG_LDO_VGP2_HW1_OP_EN,
	PMIC_RG_LDO_VGP2_HW2_OP_EN,
	PMIC_RG_LDO_VGP2_OP_EN_SET,
	PMIC_RG_LDO_VGP2_OP_EN_CLR,
	PMIC_RG_LDO_VGP2_HW0_OP_CFG,
	PMIC_RG_LDO_VGP2_HW1_OP_CFG,
	PMIC_RG_LDO_VGP2_HW2_OP_CFG,
	PMIC_RG_LDO_VGP2_ON_OP,
	PMIC_RG_LDO_VGP2_LP_OP,
	PMIC_RG_LDO_VGP2_OP_CFG_SET,
	PMIC_RG_LDO_VGP2_OP_CFG_CLR,
	PMIC_DA_QI_VGP2_MODE,
	PMIC_RG_LDO_VGP2_STBTD,
	PMIC_DA_QI_VGP2_STB,
	PMIC_DA_QI_VGP2_EN,
	PMIC_RG_LDO_VGP2_THER_SDN_EN,
	PMIC_RG_LDO_VGP2_OCFB_EN,
	PMIC_DA_QI_VGP2_OCFB_EN,
	PMIC_RG_LDO_VGP2_DUMMY_LOAD,
	PMIC_DA_QI_VGP2_DUMMY_LOAD,
	PMIC_RG_LDO_VFE28_EN,
	PMIC_RG_LDO_VFE28_LP,
	PMIC_RG_LDO_VFE28_SW_OP_EN,
	PMIC_RG_LDO_VFE28_HW0_OP_EN,
	PMIC_RG_LDO_VFE28_HW1_OP_EN,
	PMIC_RG_LDO_VFE28_HW2_OP_EN,
	PMIC_RG_LDO_VFE28_OP_EN_SET,
	PMIC_RG_LDO_VFE28_OP_EN_CLR,
	PMIC_RG_LDO_VFE28_HW0_OP_CFG,
	PMIC_RG_LDO_VFE28_HW1_OP_CFG,
	PMIC_RG_LDO_VFE28_HW2_OP_CFG,
	PMIC_RG_LDO_VFE28_ON_OP,
	PMIC_RG_LDO_VFE28_LP_OP,
	PMIC_RG_LDO_VFE28_OP_CFG_SET,
	PMIC_RG_LDO_VFE28_OP_CFG_CLR,
	PMIC_DA_QI_VFE28_MODE,
	PMIC_RG_LDO_VFE28_STBTD,
	PMIC_DA_QI_VFE28_STB,
	PMIC_DA_QI_VFE28_EN,
	PMIC_RG_LDO_VFE28_OCFB_EN,
	PMIC_DA_QI_VFE28_OCFB_EN,
	PMIC_RG_LDO_VFE28_DUMMY_LOAD,
	PMIC_DA_QI_VFE28_DUMMY_LOAD,
	PMIC_RG_LDO_VMCH_EN,
	PMIC_RG_LDO_VMCH_LP,
	PMIC_RG_LDO_VMCH_SW_OP_EN,
	PMIC_RG_LDO_VMCH_HW0_OP_EN,
	PMIC_RG_LDO_VMCH_HW1_OP_EN,
	PMIC_RG_LDO_VMCH_HW2_OP_EN,
	PMIC_RG_LDO_VMCH_OP_EN_SET,
	PMIC_RG_LDO_VMCH_OP_EN_CLR,
	PMIC_RG_LDO_VMCH_HW0_OP_CFG,
	PMIC_RG_LDO_VMCH_HW1_OP_CFG,
	PMIC_RG_LDO_VMCH_HW2_OP_CFG,
	PMIC_RG_LDO_VMCH_ON_OP,
	PMIC_RG_LDO_VMCH_LP_OP,
	PMIC_RG_LDO_VMCH_OP_CFG_SET,
	PMIC_RG_LDO_VMCH_OP_CFG_CLR,
	PMIC_DA_QI_VMCH_MODE,
	PMIC_RG_LDO_VMCH_STBTD,
	PMIC_DA_QI_VMCH_STB,
	PMIC_DA_QI_VMCH_EN,
	PMIC_RG_LDO_VMCH_OCFB_EN,
	PMIC_DA_QI_VMCH_OCFB_EN,
	PMIC_RG_LDO_VMCH_DUMMY_LOAD,
	PMIC_DA_QI_VMCH_DUMMY_LOAD,
	PMIC_RG_LDO_VMC_EN,
	PMIC_RG_LDO_VMC_LP,
	PMIC_RG_LDO_VMC_SW_OP_EN,
	PMIC_RG_LDO_VMC_HW0_OP_EN,
	PMIC_RG_LDO_VMC_HW1_OP_EN,
	PMIC_RG_LDO_VMC_HW2_OP_EN,
	PMIC_RG_LDO_VMC_OP_EN_SET,
	PMIC_RG_LDO_VMC_OP_EN_CLR,
	PMIC_RG_LDO_VMC_HW0_OP_CFG,
	PMIC_RG_LDO_VMC_HW1_OP_CFG,
	PMIC_RG_LDO_VMC_HW2_OP_CFG,
	PMIC_RG_LDO_VMC_ON_OP,
	PMIC_RG_LDO_VMC_LP_OP,
	PMIC_RG_LDO_VMC_OP_CFG_SET,
	PMIC_RG_LDO_VMC_OP_CFG_CLR,
	PMIC_DA_QI_VMC_MODE,
	PMIC_RG_LDO_VMC_STBTD,
	PMIC_DA_QI_VMC_STB,
	PMIC_DA_QI_VMC_EN,
	PMIC_RG_LDO_VMC_OCFB_EN,
	PMIC_DA_QI_VMC_OCFB_EN,
	PMIC_RG_LDO_VMC_DUMMY_LOAD,
	PMIC_DA_QI_VMC_DUMMY_LOAD,
	PMIC_RG_LDO_VRF18_1_EN,
	PMIC_RG_LDO_VRF18_1_LP,
	PMIC_RG_LDO_VRF18_1_SW_OP_EN,
	PMIC_RG_LDO_VRF18_1_HW0_OP_EN,
	PMIC_RG_LDO_VRF18_1_HW1_OP_EN,
	PMIC_RG_LDO_VRF18_1_HW2_OP_EN,
	PMIC_RG_LDO_VRF18_1_OP_EN_SET,
	PMIC_RG_LDO_VRF18_1_OP_EN_CLR,
	PMIC_RG_LDO_VRF18_1_HW0_OP_CFG,
	PMIC_RG_LDO_VRF18_1_HW1_OP_CFG,
	PMIC_RG_LDO_VRF18_1_HW2_OP_CFG,
	PMIC_RG_LDO_VRF18_1_ON_OP,
	PMIC_RG_LDO_VRF18_1_LP_OP,
	PMIC_RG_LDO_VRF18_1_OP_CFG_SET,
	PMIC_RG_LDO_VRF18_1_OP_CFG_CLR,
	PMIC_DA_QI_VRF18_1_MODE,
	PMIC_RG_LDO_VRF18_1_STBTD,
	PMIC_DA_QI_VRF18_1_STB,
	PMIC_DA_QI_VRF18_1_EN,
	PMIC_RG_LDO_VRF18_1_OCFB_EN,
	PMIC_DA_QI_VRF18_1_OCFB_EN,
	PMIC_RG_LDO_VRF18_1_DUMMY_LOAD,
	PMIC_DA_QI_VRF18_1_DUMMY_LOAD,
	PMIC_RG_LDO_VRF18_2_EN,
	PMIC_RG_LDO_VRF18_2_LP,
	PMIC_RG_LDO_VRF18_2_SW_OP_EN,
	PMIC_RG_LDO_VRF18_2_HW0_OP_EN,
	PMIC_RG_LDO_VRF18_2_HW1_OP_EN,
	PMIC_RG_LDO_VRF18_2_HW2_OP_EN,
	PMIC_RG_LDO_VRF18_2_OP_EN_SET,
	PMIC_RG_LDO_VRF18_2_OP_EN_CLR,
	PMIC_RG_LDO_VRF18_2_HW0_OP_CFG,
	PMIC_RG_LDO_VRF18_2_HW1_OP_CFG,
	PMIC_RG_LDO_VRF18_2_HW2_OP_CFG,
	PMIC_RG_LDO_VRF18_2_ON_OP,
	PMIC_RG_LDO_VRF18_2_LP_OP,
	PMIC_RG_LDO_VRF18_2_OP_CFG_SET,
	PMIC_RG_LDO_VRF18_2_OP_CFG_CLR,
	PMIC_DA_QI_VRF18_2_MODE,
	PMIC_RG_LDO_VRF18_2_STBTD,
	PMIC_DA_QI_VRF18_2_STB,
	PMIC_DA_QI_VRF18_2_EN,
	PMIC_RG_LDO_VRF18_2_OCFB_EN,
	PMIC_DA_QI_VRF18_2_OCFB_EN,
	PMIC_RG_LDO_VRF18_2_DUMMY_LOAD,
	PMIC_DA_QI_VRF18_2_DUMMY_LOAD,
	PMIC_RG_LDO_VRF12_EN,
	PMIC_RG_LDO_VRF12_LP,
	PMIC_RG_LDO_VRF12_SW_OP_EN,
	PMIC_RG_LDO_VRF12_HW0_OP_EN,
	PMIC_RG_LDO_VRF12_HW1_OP_EN,
	PMIC_RG_LDO_VRF12_HW2_OP_EN,
	PMIC_RG_LDO_VRF12_OP_EN_SET,
	PMIC_RG_LDO_VRF12_OP_EN_CLR,
	PMIC_RG_LDO_VRF12_HW0_OP_CFG,
	PMIC_RG_LDO_VRF12_HW1_OP_CFG,
	PMIC_RG_LDO_VRF12_HW2_OP_CFG,
	PMIC_RG_LDO_VRF12_ON_OP,
	PMIC_RG_LDO_VRF12_LP_OP,
	PMIC_RG_LDO_VRF12_OP_CFG_SET,
	PMIC_RG_LDO_VRF12_OP_CFG_CLR,
	PMIC_DA_QI_VRF12_MODE,
	PMIC_RG_LDO_VRF12_STBTD,
	PMIC_DA_QI_VRF12_STB,
	PMIC_DA_QI_VRF12_EN,
	PMIC_RG_LDO_VRF12_OCFB_EN,
	PMIC_DA_QI_VRF12_OCFB_EN,
	PMIC_RG_LDO_VRF12_DUMMY_LOAD,
	PMIC_DA_QI_VRF12_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMA1_EN,
	PMIC_RG_LDO_VCAMA1_LP,
	PMIC_RG_LDO_VCAMA1_SW_OP_EN,
	PMIC_RG_LDO_VCAMA1_HW0_OP_EN,
	PMIC_RG_LDO_VCAMA1_HW1_OP_EN,
	PMIC_RG_LDO_VCAMA1_HW2_OP_EN,
	PMIC_RG_LDO_VCAMA1_OP_EN_SET,
	PMIC_RG_LDO_VCAMA1_OP_EN_CLR,
	PMIC_RG_LDO_VCAMA1_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMA1_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMA1_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMA1_ON_OP,
	PMIC_RG_LDO_VCAMA1_LP_OP,
	PMIC_RG_LDO_VCAMA1_OP_CFG_SET,
	PMIC_RG_LDO_VCAMA1_OP_CFG_CLR,
	PMIC_DA_QI_VCAMA1_MODE,
	PMIC_RG_LDO_VCAMA1_STBTD,
	PMIC_DA_QI_VCAMA1_STB,
	PMIC_DA_QI_VCAMA1_EN,
	PMIC_RG_LDO_VCAMA1_OCFB_EN,
	PMIC_DA_QI_VCAMA1_OCFB_EN,
	PMIC_RG_LDO_VCAMA1_DUMMY_LOAD,
	PMIC_DA_QI_VCAMA1_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMA2_EN,
	PMIC_RG_LDO_VCAMA2_LP,
	PMIC_RG_LDO_VCAMA2_SW_OP_EN,
	PMIC_RG_LDO_VCAMA2_HW0_OP_EN,
	PMIC_RG_LDO_VCAMA2_HW1_OP_EN,
	PMIC_RG_LDO_VCAMA2_HW2_OP_EN,
	PMIC_RG_LDO_VCAMA2_OP_EN_SET,
	PMIC_RG_LDO_VCAMA2_OP_EN_CLR,
	PMIC_RG_LDO_VCAMA2_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMA2_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMA2_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMA2_ON_OP,
	PMIC_RG_LDO_VCAMA2_LP_OP,
	PMIC_RG_LDO_VCAMA2_OP_CFG_SET,
	PMIC_RG_LDO_VCAMA2_OP_CFG_CLR,
	PMIC_DA_QI_VCAMA2_MODE,
	PMIC_RG_LDO_VCAMA2_STBTD,
	PMIC_DA_QI_VCAMA2_STB,
	PMIC_DA_QI_VCAMA2_EN,
	PMIC_RG_LDO_VCAMA2_OCFB_EN,
	PMIC_DA_QI_VCAMA2_OCFB_EN,
	PMIC_RG_LDO_VCAMA2_DUMMY_LOAD,
	PMIC_DA_QI_VCAMA2_DUMMY_LOAD,
	PMIC_LDO_DEGTD_SEL,
	PMIC_RG_VRTC_EN,
	PMIC_DA_QI_VRTC_EN,
	PMIC_RG_LDO_RSV1,
	PMIC_RG_LDO_RSV0,
	PMIC_RG_LDO_RSV2,
	PMIC_RG_LDO_VSRAM_PROC_EN,
	PMIC_RG_LDO_VSRAM_PROC_LP,
	PMIC_RG_LDO_VSRAM_PROC_VOSEL,
	PMIC_RG_LDO_VSRAM_PROC_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_PROC_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_PROC_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_PROC_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_PROC_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_PROC_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_PROC_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_PROC_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_PROC_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC_ON_OP,
	PMIC_RG_LDO_VSRAM_PROC_LP_OP,
	PMIC_RG_LDO_VSRAM_PROC_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_PROC_OP_CFG_CLR,
	PMIC_DA_QI_VSRAM_PROC_MODE,
	PMIC_RG_LDO_VSRAM_PROC_STBTD,
	PMIC_RG_LDO_VSRAM_PROC_OCFB_EN,
	PMIC_DA_QI_VSRAM_PROC_OCFB_EN,
	PMIC_RG_LDO_VSRAM_PROC_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_PROC_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_PROC_VOSEL_GRAY,
	PMIC_DA_QI_VSRAM_PROC_VOSEL,
	PMIC_DA_QI_VSRAM_PROC_EN,
	PMIC_DA_QI_VSRAM_PROC_STB,
	PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL,
	PMIC_DA_NI_VSRAM_PROC_R2R_PDN,
	PMIC_DA_NI_VSRAM_PROC_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_CORE_EN,
	PMIC_RG_LDO_VSRAM_CORE_LP,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_CORE_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_CORE_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_CORE_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_CORE_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_CORE_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_CORE_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_CORE_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_CORE_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_CORE_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_CORE_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_CORE_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_CORE_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_CORE_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_CORE_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_CORE_ON_OP,
	PMIC_RG_LDO_VSRAM_CORE_LP_OP,
	PMIC_RG_LDO_VSRAM_CORE_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_CORE_OP_CFG_CLR,
	PMIC_DA_QI_VSRAM_CORE_MODE,
	PMIC_RG_LDO_VSRAM_CORE_STBTD,
	PMIC_RG_LDO_VSRAM_CORE_OCFB_EN,
	PMIC_DA_QI_VSRAM_CORE_OCFB_EN,
	PMIC_RG_LDO_VSRAM_CORE_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_CORE_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_CORE_VOSEL_GRAY,
	PMIC_DA_QI_VSRAM_CORE_VOSEL,
	PMIC_DA_QI_VSRAM_CORE_EN,
	PMIC_DA_QI_VSRAM_CORE_STB,
	PMIC_DA_NI_VSRAM_CORE_VSLEEP_SEL,
	PMIC_DA_NI_VSRAM_CORE_R2R_PDN,
	PMIC_DA_NI_VSRAM_CORE_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_GPU_EN,
	PMIC_RG_LDO_VSRAM_GPU_LP,
	PMIC_RG_LDO_VSRAM_GPU_VOSEL,
	PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_GPU_ON_OP,
	PMIC_RG_LDO_VSRAM_GPU_LP_OP,
	PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR,
	PMIC_DA_QI_VSRAM_GPU_MODE,
	PMIC_RG_LDO_VSRAM_GPU_STBTD,
	PMIC_RG_LDO_VSRAM_GPU_OCFB_EN,
	PMIC_DA_QI_VSRAM_GPU_OCFB_EN,
	PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_GPU_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_GPU_VOSEL_GRAY,
	PMIC_DA_QI_VSRAM_GPU_VOSEL,
	PMIC_DA_QI_VSRAM_GPU_EN,
	PMIC_DA_QI_VSRAM_GPU_STB,
	PMIC_DA_NI_VSRAM_GPU_VSLEEP_SEL,
	PMIC_DA_NI_VSRAM_GPU_R2R_PDN,
	PMIC_DA_NI_VSRAM_GPU_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_MD_EN,
	PMIC_RG_LDO_VSRAM_MD_LP,
	PMIC_RG_LDO_VSRAM_MD_VOSEL,
	PMIC_RG_LDO_VSRAM_MD_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_MD_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_MD_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_MD_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_MD_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_MD_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_MD_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_MD_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_MD_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_MD_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_MD_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_MD_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_MD_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_MD_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_MD_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_MD_ON_OP,
	PMIC_RG_LDO_VSRAM_MD_LP_OP,
	PMIC_RG_LDO_VSRAM_MD_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_MD_OP_CFG_CLR,
	PMIC_DA_QI_VSRAM_MD_MODE,
	PMIC_RG_LDO_VSRAM_MD_STBTD,
	PMIC_RG_LDO_VSRAM_MD_OCFB_EN,
	PMIC_DA_QI_VSRAM_MD_OCFB_EN,
	PMIC_RG_LDO_VSRAM_MD_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_MD_DUMMY_LOAD,
	PMIC_DA_QI_VSRAM_MD_VOSEL_GRAY,
	PMIC_DA_QI_VSRAM_MD_VOSEL,
	PMIC_DA_QI_VSRAM_MD_EN,
	PMIC_DA_QI_VSRAM_MD_STB,
	PMIC_DA_NI_VSRAM_MD_VSLEEP_SEL,
	PMIC_DA_NI_VSRAM_MD_R2R_PDN,
	PMIC_DA_NI_VSRAM_MD_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_CORE_TRACK_SLEEP_CTRL,
	PMIC_RG_LDO_VSRAM_CORE_TRACK_ON_CTRL,
	PMIC_RG_LDO_VSRAM_CORE_TRACK_VBUCK_ON_CTRL,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL_DELTA,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL_OFFSET,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_LB,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL_ON_HB,
	PMIC_RG_LDO_VSRAM_CORE_VOSEL_SLEEP_LB,
	PMIC_RG_LDO_DCM_MODE,
	PMIC_RG_LDO_VIO28_CK_SW_MODE,
	PMIC_RG_LDO_VIO28_CK_SW_EN,
	PMIC_RG_LDO_VIO28_OSC_SEL_DIS,
	PMIC_RG_LDO_VIO18_CK_SW_MODE,
	PMIC_RG_LDO_VIO18_CK_SW_EN,
	PMIC_RG_LDO_VIO18_OSC_SEL_DIS,
	PMIC_RG_LDO_VUFS18_CK_SW_MODE,
	PMIC_RG_LDO_VUFS18_CK_SW_EN,
	PMIC_RG_LDO_VUFS18_OSC_SEL_DIS,
	PMIC_RG_LDO_VA10_CK_SW_MODE,
	PMIC_RG_LDO_VA10_CK_SW_EN,
	PMIC_RG_LDO_VA10_OSC_SEL_DIS,
	PMIC_RG_LDO_VA12_CK_SW_MODE,
	PMIC_RG_LDO_VA12_CK_SW_EN,
	PMIC_RG_LDO_VA12_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_PROC_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_PROC_CK_SW_EN,
	PMIC_RG_LDO_VSRAM_PROC_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_CORE_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_CORE_CK_SW_EN,
	PMIC_RG_LDO_VSRAM_CORE_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_GPU_CK_SW_EN,
	PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_MD_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_MD_CK_SW_EN,
	PMIC_RG_LDO_VSRAM_MD_OSC_SEL_DIS,
	PMIC_RG_LDO_VA18_CK_SW_MODE,
	PMIC_RG_LDO_VA18_CK_SW_EN,
	PMIC_RG_LDO_VA18_OSC_SEL_DIS,
	PMIC_RG_LDO_VUSB33_CK_SW_MODE,
	PMIC_RG_LDO_VUSB33_CK_SW_EN,
	PMIC_RG_LDO_VUSB33_OSC_SEL_DIS,
	PMIC_RG_LDO_VEMC_CK_SW_MODE,
	PMIC_RG_LDO_VEMC_CK_SW_EN,
	PMIC_RG_LDO_VEMC_OSC_SEL_DIS,
	PMIC_RG_LDO_VXO22_CK_SW_MODE,
	PMIC_RG_LDO_VXO22_CK_SW_EN,
	PMIC_RG_LDO_VXO22_OSC_SEL_DIS,
	PMIC_RG_LDO_VXO18_CK_SW_MODE,
	PMIC_RG_LDO_VXO18_CK_SW_EN,
	PMIC_RG_LDO_VXO18_OSC_SEL_DIS,
	PMIC_RG_LDO_VSIM1_CK_SW_MODE,
	PMIC_RG_LDO_VSIM1_CK_SW_EN,
	PMIC_RG_LDO_VSIM1_OSC_SEL_DIS,
	PMIC_RG_LDO_VSIM2_CK_SW_MODE,
	PMIC_RG_LDO_VSIM2_CK_SW_EN,
	PMIC_RG_LDO_VSIM2_OSC_SEL_DIS,
	PMIC_RG_LDO_VCAMD1_CK_SW_MODE,
	PMIC_RG_LDO_VCAMD1_CK_SW_EN,
	PMIC_RG_LDO_VCAMD1_OSC_SEL_DIS,
	PMIC_RG_LDO_VCAMD2_CK_SW_MODE,
	PMIC_RG_LDO_VCAMD2_CK_SW_EN,
	PMIC_RG_LDO_VCAMD2_OSC_SEL_DIS,
	PMIC_RG_LDO_VCAMIO_CK_SW_MODE,
	PMIC_RG_LDO_VCAMIO_CK_SW_EN,
	PMIC_RG_LDO_VCAMIO_OSC_SEL_DIS,
	PMIC_RG_LDO_VMIPI_CK_SW_MODE,
	PMIC_RG_LDO_VMIPI_CK_SW_EN,
	PMIC_RG_LDO_VMIPI_OSC_SEL_DIS,
	PMIC_RG_LDO_VGP_CK_SW_MODE,
	PMIC_RG_LDO_VGP_CK_SW_EN,
	PMIC_RG_LDO_VGP_OSC_SEL_DIS,
	PMIC_RG_LDO_VCN33_CK_SW_MODE,
	PMIC_RG_LDO_VCN33_CK_SW_EN,
	PMIC_RG_LDO_VCN33_OSC_SEL_DIS,
	PMIC_RG_LDO_VCN18_CK_SW_MODE,
	PMIC_RG_LDO_VCN18_CK_SW_EN,
	PMIC_RG_LDO_VCN18_OSC_SEL_DIS,
	PMIC_RG_LDO_VCN28_CK_SW_MODE,
	PMIC_RG_LDO_VCN28_CK_SW_EN,
	PMIC_RG_LDO_VCN28_OSC_SEL_DIS,
	PMIC_RG_LDO_VGP2_CK_SW_MODE,
	PMIC_RG_LDO_VGP2_CK_SW_EN,
	PMIC_RG_LDO_VGP2_OSC_SEL_DIS,
	PMIC_RG_LDO_VBIF28_CK_SW_MODE,
	PMIC_RG_LDO_VBIF28_CK_SW_EN,
	PMIC_RG_LDO_VBIF28_OSC_SEL_DIS,
	PMIC_RG_LDO_VFE28_CK_SW_MODE,
	PMIC_RG_LDO_VFE28_CK_SW_EN,
	PMIC_RG_LDO_VFE28_OSC_SEL_DIS,
	PMIC_RG_LDO_VMCH_CK_SW_MODE,
	PMIC_RG_LDO_VMCH_CK_SW_EN,
	PMIC_RG_LDO_VMCH_OSC_SEL_DIS,
	PMIC_RG_LDO_VMC_CK_SW_MODE,
	PMIC_RG_LDO_VMC_CK_SW_EN,
	PMIC_RG_LDO_VMC_OSC_SEL_DIS,
	PMIC_RG_LDO_VRF18_1_CK_SW_MODE,
	PMIC_RG_LDO_VRF18_1_CK_SW_EN,
	PMIC_RG_LDO_VRF18_1_OSC_SEL_DIS,
	PMIC_RG_LDO_VRF18_2_CK_SW_MODE,
	PMIC_RG_LDO_VRF18_2_CK_SW_EN,
	PMIC_RG_LDO_VRF18_2_OSC_SEL_DIS,
	PMIC_RG_LDO_VTCXO24_CK_SW_MODE,
	PMIC_RG_LDO_VTCXO24_CK_SW_EN,
	PMIC_RG_LDO_VTCXO24_OSC_SEL_DIS,
	PMIC_RG_LDO_VLDO28_CK_SW_MODE,
	PMIC_RG_LDO_VLDO28_CK_SW_EN,
	PMIC_RG_LDO_VLDO28_OSC_SEL_DIS,
	PMIC_RG_LDO_VRF12_CK_SW_MODE,
	PMIC_RG_LDO_VRF12_CK_SW_EN,
	PMIC_RG_LDO_VRF12_OSC_SEL_DIS,
	PMIC_RG_LDO_VCAMA1_CK_SW_MODE,
	PMIC_RG_LDO_VCAMA1_CK_SW_EN,
	PMIC_RG_LDO_VCAMA1_OSC_SEL_DIS,
	PMIC_RG_LDO_VCAMA2_CK_SW_MODE,
	PMIC_RG_LDO_VCAMA2_CK_SW_EN,
	PMIC_RG_LDO_VCAMA2_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL_EN,
	PMIC_RG_LDO_VSRAM_PROC_SP_SW_VOSEL,
	PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL_EN,
	PMIC_RG_LDO_VSRAM_GPU_SP_SW_VOSEL,
	PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL_EN,
	PMIC_RG_LDO_VSRAM_MD_SP_SW_VOSEL,
	PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL_EN,
	PMIC_RG_LDO_VSRAM_CORE_SP_SW_VOSEL,
	PMIC_RG_LDO_VSRAM_CORE_SSHUB_ON,
	PMIC_RG_LDO_VSRAM_CORE_SSHUB_MODE,
	PMIC_RG_LDO_VSRAM_CORE_SSHUB_VOSEL,
	PMIC_RG_LDO_LP_PROT_DISABLE,
	PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS,
	PMIC_RG_LDO_VSRAM_PROC_R2R_PDN_DIS,
	PMIC_RG_LDO_VSRAM_CORE_R2R_PDN_DIS,
	PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS,
	PMIC_RG_LDO_VSRAM_MD_R2R_PDN_DIS,
	PMIC_RG_VFE28_VOCAL,
	PMIC_RG_VFE28_VOSEL,
	PMIC_RG_VFE28_VOTRIM,
	PMIC_RGS_VFE28_CAL_INDI,
	PMIC_RG_VFE28_OC_TRIM,
	PMIC_RG_VFE28_NDIS_EN,
	PMIC_RG_VFE28_STB_SEL,
	PMIC_RG_VFE28_RSV,
	PMIC_RG_VFE28_VOS_CAL_EN,
	PMIC_RG_VTCXO24_VOCAL,
	PMIC_RG_VTCXO24_VOSEL,
	PMIC_RG_VTCXO24_VOTRIM,
	PMIC_RGS_VTCXO24_CAL_INDI,
	PMIC_RG_VTCXO24_OC_TRIM,
	PMIC_RG_VTCXO24_NDIS_EN,
	PMIC_RG_VTCXO24_STB_SEL,
	PMIC_RG_VTCXO24_RSV,
	PMIC_RG_VTCXO24_VOS_CAL_EN,
	PMIC_RG_VXO22_VOCAL,
	PMIC_RG_VXO22_VOSEL,
	PMIC_RG_VXO22_VOTRIM,
	PMIC_RGS_VXO22_CAL_INDI,
	PMIC_RG_VXO22_OC_TRIM,
	PMIC_RG_VXO22_NDIS_EN,
	PMIC_RG_VXO22_STB_SEL,
	PMIC_RG_VXO22_RSV,
	PMIC_RG_VXO22_VOS_CAL_EN,
	PMIC_RG_VCN28_VOCAL,
	PMIC_RG_VCN28_VOSEL,
	PMIC_RG_VCN28_VOTRIM,
	PMIC_RGS_VCN28_CAL_INDI,
	PMIC_RG_VCN28_OC_TRIM,
	PMIC_RG_VCN28_NDIS_EN,
	PMIC_RG_VCN28_STB_SEL,
	PMIC_RG_VCN28_RSV,
	PMIC_RG_VCN28_VOS_CAL_EN,
	PMIC_RG_VCAMA1_VOCAL,
	PMIC_RG_VCAMA1_VOSEL,
	PMIC_RG_VCAMA1_VOTRIM,
	PMIC_RGS_VCAMA1_CAL_INDI,
	PMIC_RG_VCAMA1_OC_TRIM,
	PMIC_RG_VCAMA1_NDIS_EN,
	PMIC_RG_VCAMA1_STB_SEL,
	PMIC_RG_VCAMA1_RSV,
	PMIC_RG_VCAMA1_VOS_CAL_EN,
	PMIC_RG_VCAMA2_VOCAL,
	PMIC_RG_VCAMA2_VOSEL,
	PMIC_RG_VCAMA2_VOTRIM,
	PMIC_RGS_VCAMA2_CAL_INDI,
	PMIC_RG_VCAMA2_OC_TRIM,
	PMIC_RG_VCAMA2_NDIS_EN,
	PMIC_RG_VCAMA2_STB_SEL,
	PMIC_RG_VCAMA2_RSV,
	PMIC_RG_VCAMA2_VOS_CAL_EN,
	PMIC_RG_VA18_VOCAL,
	PMIC_RG_VA18_VOSEL,
	PMIC_RG_VA18_VOTRIM,
	PMIC_RGS_VA18_CAL_INDI,
	PMIC_RG_VA18_OC_TRIM,
	PMIC_RG_VA18_NDIS_EN,
	PMIC_RG_VA18_STB_SEL,
	PMIC_RG_VA18_RSV,
	PMIC_RG_VA18_VOS_CAL_EN,
	PMIC_RG_VUSB33_VOCAL,
	PMIC_RG_VUSB33_VOSEL,
	PMIC_RG_VUSB33_VOTRIM,
	PMIC_RGS_VUSB33_CAL_INDI,
	PMIC_RG_VUSB33_OC_TRIM,
	PMIC_RG_VUSB33_NDIS_EN,
	PMIC_RG_VUSB33_STB_SEL,
	PMIC_RG_VUSB33_RSV,
	PMIC_RG_VUSB33_VOS_CAL_EN,
	PMIC_RG_VBIF28_VOCAL,
	PMIC_RG_VBIF28_VOSEL,
	PMIC_RG_VBIF28_VOTRIM,
	PMIC_RGS_VBIF28_CAL_INDI,
	PMIC_RG_VBIF28_OC_TRIM,
	PMIC_RG_VBIF28_NDIS_EN,
	PMIC_RG_VBIF28_STB_SEL,
	PMIC_RG_VBIF28_RSV,
	PMIC_RG_VBIF28_VOS_CAL_EN,
	PMIC_RG_VGP2_VOCAL,
	PMIC_RG_VGP2_VOSEL,
	PMIC_RG_VGP2_VOTRIM,
	PMIC_RGS_VGP2_CAL_INDI,
	PMIC_RG_VGP2_OC_TRIM,
	PMIC_RG_VGP2_NDIS_EN,
	PMIC_RG_VGP2_STB_SEL,
	PMIC_RG_VGP2_RSV,
	PMIC_RG_VGP2_VOS_CAL_EN,
	PMIC_RG_VCN33_VOCAL,
	PMIC_RG_VCN33_VOSEL,
	PMIC_RG_VCN33_VOTRIM,
	PMIC_RGS_VCN33_CAL_INDI,
	PMIC_RG_VCN33_OC_TRIM,
	PMIC_RG_VCN33_NDIS_EN,
	PMIC_RG_VCN33_STB_SEL,
	PMIC_RG_VCN33_RSV,
	PMIC_RG_VCN33_VOS_CAL_EN,
	PMIC_RG_VSIM1_VOCAL,
	PMIC_RG_VSIM1_VOSEL,
	PMIC_RG_VSIM1_VOTRIM,
	PMIC_RGS_VSIM1_CAL_INDI,
	PMIC_RG_VSIM1_OC_TRIM,
	PMIC_RG_VSIM1_NDIS_EN,
	PMIC_RG_VSIM1_STB_SEL,
	PMIC_RG_VSIM1_RSV,
	PMIC_RG_VSIM1_VOS_CAL_EN,
	PMIC_RG_VSIM2_VOCAL,
	PMIC_RG_VSIM2_VOSEL,
	PMIC_RG_VSIM2_VOTRIM,
	PMIC_RGS_VSIM2_CAL_INDI,
	PMIC_RG_VSIM2_OC_TRIM,
	PMIC_RG_VSIM2_NDIS_EN,
	PMIC_RG_VSIM2_STB_SEL,
	PMIC_RG_VSIM2_RSV,
	PMIC_RG_VSIM2_VOS_CAL_EN,
	PMIC_RG_VLDO28_VOCAL,
	PMIC_RG_VLDO28_VOSEL,
	PMIC_RG_VLDO28_VOTRIM,
	PMIC_RGS_VLDO28_CAL_INDI,
	PMIC_RG_VLDO28_OC_TRIM,
	PMIC_RG_VLDO28_NDIS_EN,
	PMIC_RG_VLDO28_STB_SEL,
	PMIC_RG_VLDO28_RSV,
	PMIC_RG_VLDO28_VOS_CAL_EN,
	PMIC_RG_VIO28_VOCAL,
	PMIC_RG_VIO28_VOSEL,
	PMIC_RG_VIO28_VOTRIM,
	PMIC_RGS_VIO28_CAL_INDI,
	PMIC_RG_VIO28_OC_TRIM,
	PMIC_RG_VIO28_NDIS_EN,
	PMIC_RG_VIO28_STB_SEL,
	PMIC_RG_VIO28_RSV,
	PMIC_RG_VIO28_VOS_CAL_EN,
	PMIC_RG_VMC_VOCAL,
	PMIC_RG_VMC_VOSEL,
	PMIC_RG_VMC_VOTRIM,
	PMIC_RGS_VMC_CAL_INDI,
	PMIC_RG_VMC_OC_TRIM,
	PMIC_RG_VMC_NDIS_EN,
	PMIC_RG_VMC_STB_SEL,
	PMIC_RG_VMC_RSV,
	PMIC_RG_VMC_VOS_CAL_EN,
	PMIC_RG_VMCH_VOCAL,
	PMIC_RG_VMCH_VOSEL,
	PMIC_RG_VMCH_VOTRIM,
	PMIC_RGS_VMCH_CAL_INDI,
	PMIC_RG_VMCH_OC_TRIM,
	PMIC_RG_VMCH_NDIS_EN,
	PMIC_RG_VMCH_STB_SEL,
	PMIC_RG_VMCH_RSV,
	PMIC_RG_VMCH_VOS_CAL_EN,
	PMIC_RG_VEMC_VOCAL,
	PMIC_RG_VEMC_VOSEL,
	PMIC_RG_VEMC_VOTRIM,
	PMIC_RGS_VEMC_CAL_INDI,
	PMIC_RG_VEMC_OC_TRIM,
	PMIC_RG_VEMC_NDIS_EN,
	PMIC_RG_VEMC_STB_SEL,
	PMIC_RG_VEMC_RSV,
	PMIC_RG_VEMC_VOS_CAL_EN,
	PMIC_RG_VGP_VOCAL,
	PMIC_RG_VGP_VOSEL,
	PMIC_RG_VGP_VOTRIM,
	PMIC_RGS_VGP_CAL_INDI,
	PMIC_RG_VGP_OC_TRIM,
	PMIC_RG_VGP_NDIS_EN,
	PMIC_RG_VGP_STB_SEL,
	PMIC_RG_VGP_RSV,
	PMIC_RG_VGP_VOS_CAL_EN,
	PMIC_RG_VRF18_1_VOCAL,
	PMIC_RG_VRF18_1_VOSEL,
	PMIC_RG_VRF18_1_VOTRIM,
	PMIC_RGS_VRF18_1_CAL_INDI,
	PMIC_RG_VRF18_1_OC_TRIM,
	PMIC_RG_VRF18_1_NDIS_EN,
	PMIC_RG_VRF18_1_STB_SEL,
	PMIC_RG_VRF18_1_RSV,
	PMIC_RG_VRF18_1_VOS_CAL_EN,
	PMIC_RG_VRF18_2_VOCAL,
	PMIC_RG_VRF18_2_VOSEL,
	PMIC_RG_VRF18_2_VOTRIM,
	PMIC_RGS_VRF18_2_CAL_INDI,
	PMIC_RG_VRF18_2_OC_TRIM,
	PMIC_RG_VRF18_2_NDIS_EN,
	PMIC_RG_VRF18_2_STB_SEL,
	PMIC_RG_VRF18_2_RSV,
	PMIC_RG_VRF18_2_VOS_CAL_EN,
	PMIC_RG_VCN18_VOCAL,
	PMIC_RG_VCN18_VOSEL,
	PMIC_RG_VCN18_VOTRIM,
	PMIC_RGS_VCN18_CAL_INDI,
	PMIC_RG_VCN18_OC_TRIM,
	PMIC_RG_VCN18_NDIS_EN,
	PMIC_RG_VCN18_STB_SEL,
	PMIC_RG_VCN18_RSV,
	PMIC_RG_VCN18_VOS_CAL_EN,
	PMIC_RG_VCAMIO_VOCAL,
	PMIC_RG_VCAMIO_VOSEL,
	PMIC_RG_VCAMIO_VOTRIM,
	PMIC_RGS_VCAMIO_CAL_INDI,
	PMIC_RG_VCAMIO_OC_TRIM,
	PMIC_RG_VCAMIO_NDIS_EN,
	PMIC_RG_VCAMIO_STB_SEL,
	PMIC_RG_VCAMIO_RSV,
	PMIC_RG_VCAMIO_VOS_CAL_EN,
	PMIC_RG_VMIPI_VOCAL,
	PMIC_RG_VMIPI_VOSEL,
	PMIC_RG_VMIPI_VOTRIM,
	PMIC_RGS_VMIPI_CAL_INDI,
	PMIC_RG_VMIPI_OC_TRIM,
	PMIC_RG_VMIPI_NDIS_EN,
	PMIC_RG_VMIPI_STB_SEL,
	PMIC_RG_VMIPI_RSV,
	PMIC_RG_VMIPI_VOS_CAL_EN,
	PMIC_RG_VUFS18_VOCAL,
	PMIC_RG_VUFS18_VOSEL,
	PMIC_RG_VUFS18_VOTRIM,
	PMIC_RGS_VUFS18_CAL_INDI,
	PMIC_RG_VUFS18_OC_TRIM,
	PMIC_RG_VUFS18_NDIS_EN,
	PMIC_RG_VUFS18_STB_SEL,
	PMIC_RG_VUFS18_RSV,
	PMIC_RG_VUFS18_VOS_CAL_EN,
	PMIC_RG_VIO18_VOCAL,
	PMIC_RG_VIO18_VOSEL,
	PMIC_RG_VIO18_VOTRIM,
	PMIC_RGS_VIO18_CAL_INDI,
	PMIC_RG_VIO18_OC_TRIM,
	PMIC_RG_VIO18_NDIS_EN,
	PMIC_RG_VIO18_STB_SEL,
	PMIC_RG_VIO18_RSV,
	PMIC_RG_VIO18_VOS_CAL_EN,
	PMIC_RG_VXO18_VOCAL,
	PMIC_RG_VXO18_VOSEL,
	PMIC_RG_VXO18_VOTRIM,
	PMIC_RGS_VXO18_CAL_INDI,
	PMIC_RG_VXO18_OC_TRIM,
	PMIC_RG_VXO18_NDIS_EN,
	PMIC_RG_VXO18_STB_SEL,
	PMIC_RG_VXO18_RSV,
	PMIC_RG_VXO18_VOS_CAL_EN,
	PMIC_RG_VRF12_VOCAL,
	PMIC_RG_VRF12_VOSEL,
	PMIC_RG_VRF12_VOTRIM,
	PMIC_RGS_VRF12_CAL_INDI,
	PMIC_RG_VRF12_OC_TRIM,
	PMIC_RG_VRF12_NDIS_EN,
	PMIC_RG_VRF12_STB_SEL,
	PMIC_RG_VRF12_RSV,
	PMIC_RG_VRF12_VOS_CAL_EN,
	PMIC_RG_VCAMD1_VOCAL,
	PMIC_RG_VCAMD1_VOSEL,
	PMIC_RG_VCAMD1_VOTRIM,
	PMIC_RGS_VCAMD1_CAL_INDI,
	PMIC_RG_VCAMD1_OC_TRIM,
	PMIC_RG_VCAMD1_NDIS_EN,
	PMIC_RG_VCAMD1_STB_SEL,
	PMIC_RG_VCAMD1_RSV,
	PMIC_RG_VCAMD1_VOS_CAL_EN,
	PMIC_RG_VCAMD2_VOCAL,
	PMIC_RG_VCAMD2_VOSEL,
	PMIC_RG_VCAMD2_VOTRIM,
	PMIC_RGS_VCAMD2_CAL_INDI,
	PMIC_RG_VCAMD2_OC_TRIM,
	PMIC_RG_VCAMD2_NDIS_EN,
	PMIC_RG_VCAMD2_STB_SEL,
	PMIC_RG_VCAMD2_RSV,
	PMIC_RG_VCAMD2_VOS_CAL_EN,
	PMIC_RG_VA10_VOTRIM,
	PMIC_RGS_VA10_CAL_INDI,
	PMIC_RG_VA10_OC_TRIM,
	PMIC_RG_VA10_NDIS_EN,
	PMIC_RG_VA10_STB_SEL,
	PMIC_RG_VA10_RSV,
	PMIC_RG_VA10_VOS_CAL_EN,
	PMIC_RG_VA12_VOCAL,
	PMIC_RG_VA12_VOSEL,
	PMIC_RG_VA12_VOTRIM,
	PMIC_RGS_VA12_CAL_INDI,
	PMIC_RG_VA12_OC_TRIM,
	PMIC_RG_VA12_NDIS_EN,
	PMIC_RG_VA12_STB_SEL,
	PMIC_RG_VA12_RSV,
	PMIC_RG_VA12_VOS_CAL_EN,
	PMIC_RG_VSRAM_PROC_OC_TRIM,
	PMIC_RG_VSRAM_PROC_STB_SEL,
	PMIC_RG_VSRAM_PROC_NDIS_EN,
	PMIC_RG_VSRAM_PROC_NDIS_PLCUR,
	PMIC_RG_VSRAM_PROC_PLCUR_EN,
	PMIC_RG_VSRAM_PROC_RSV_H,
	PMIC_RG_VSRAM_PROC_RSV_L,
	PMIC_RG_VSRAM_CORE_OC_TRIM,
	PMIC_RG_VSRAM_CORE_STB_SEL,
	PMIC_RG_VSRAM_CORE_NDIS_EN,
	PMIC_RG_VSRAM_CORE_NDIS_PLCUR,
	PMIC_RG_VSRAM_CORE_PLCUR_EN,
	PMIC_RG_VSRAM_CORE_RSV_H,
	PMIC_RG_VSRAM_CORE_RSV_L,
	PMIC_RG_VSRAM_GPU_OC_TRIM,
	PMIC_RG_VSRAM_GPU_STB_SEL,
	PMIC_RG_VSRAM_GPU_NDIS_EN,
	PMIC_RG_VSRAM_GPU_NDIS_PLCUR,
	PMIC_RG_VSRAM_GPU_PLCUR_EN,
	PMIC_RG_VSRAM_GPU_RSV_H,
	PMIC_RG_VSRAM_GPU_RSV_L,
	PMIC_RG_VSRAM_MD_OC_TRIM,
	PMIC_RG_VSRAM_MD_STB_SEL,
	PMIC_RG_VSRAM_MD_NDIS_EN,
	PMIC_RG_VSRAM_MD_NDIS_PLCUR,
	PMIC_RG_VSRAM_MD_PLCUR_EN,
	PMIC_RG_VSRAM_MD_RSV_H,
	PMIC_RG_VSRAM_MD_RSV_L,
	PMIC_AUDACCDETAUXADCSWCTRL,
	PMIC_AUDACCDETAUXADCSWCTRL_SEL,
	PMIC_RG_AUDACCDETRSV,
	PMIC_ACCDET_EN,
	PMIC_ACCDET_SEQ_INIT,
	PMIC_ACCDET_EINTDET_EN,
	PMIC_ACCDET_EINT_SEQ_INIT,
	PMIC_ACCDET_ANASWCTRL_SEL,
	PMIC_ACCDET_CMP_PWM_EN,
	PMIC_ACCDET_VTH_PWM_EN,
	PMIC_ACCDET_MBIAS_PWM_EN,
	PMIC_ACCDET_EINT_PWM_EN,
	PMIC_ACCDET_CMP_PWM_IDLE,
	PMIC_ACCDET_VTH_PWM_IDLE,
	PMIC_ACCDET_MBIAS_PWM_IDLE,
	PMIC_ACCDET_EINT_PWM_IDLE,
	PMIC_ACCDET_PWM_WIDTH,
	PMIC_ACCDET_PWM_THRESH,
	PMIC_ACCDET_RISE_DELAY,
	PMIC_ACCDET_FALL_DELAY,
	PMIC_ACCDET_DEBOUNCE0,
	PMIC_ACCDET_DEBOUNCE1,
	PMIC_ACCDET_DEBOUNCE2,
	PMIC_ACCDET_DEBOUNCE3,
	PMIC_ACCDET_DEBOUNCE4,
	PMIC_ACCDET_IVAL_CUR_IN,
	PMIC_ACCDET_EINT_IVAL_CUR_IN,
	PMIC_ACCDET_IVAL_SAM_IN,
	PMIC_ACCDET_EINT_IVAL_SAM_IN,
	PMIC_ACCDET_IVAL_MEM_IN,
	PMIC_ACCDET_EINT_IVAL_MEM_IN,
	PMIC_ACCDET_EINT_IVAL_SEL,
	PMIC_ACCDET_IVAL_SEL,
	PMIC_ACCDET_IRQ,
	PMIC_ACCDET_EINT_IRQ,
	PMIC_ACCDET_IRQ_CLR,
	PMIC_ACCDET_EINT_IRQ_CLR,
	PMIC_ACCDET_EINT_IRQ_POLARITY,
	PMIC_ACCDET_TEST_MODE0,
	PMIC_ACCDET_CMP_SWSEL,
	PMIC_ACCDET_VTH_SWSEL,
	PMIC_ACCDET_MBIAS_SWSEL,
	PMIC_ACCDET_TEST_MODE4,
	PMIC_ACCDET_TEST_MODE5,
	PMIC_ACCDET_PWM_SEL,
	PMIC_ACCDET_IN_SW,
	PMIC_ACCDET_CMP_EN_SW,
	PMIC_ACCDET_VTH_EN_SW,
	PMIC_ACCDET_MBIAS_EN_SW,
	PMIC_ACCDET_PWM_EN_SW,
	PMIC_ACCDET_IN,
	PMIC_ACCDET_CUR_IN,
	PMIC_ACCDET_SAM_IN,
	PMIC_ACCDET_MEM_IN,
	PMIC_ACCDET_STATE,
	PMIC_ACCDET_MBIAS_CLK,
	PMIC_ACCDET_VTH_CLK,
	PMIC_ACCDET_CMP_CLK,
	PMIC_DA_AUDACCDETAUXADCSWCTRL,
	PMIC_ACCDET_EINT_DEB_SEL,
	PMIC_ACCDET_EINT_DEBOUNCE,
	PMIC_ACCDET_EINT_PWM_THRESH,
	PMIC_ACCDET_EINT_PWM_WIDTH,
	PMIC_ACCDET_EINT_PWM_FALL_DELAY,
	PMIC_ACCDET_EINT_PWM_RISE_DELAY,
	PMIC_ACCDET_TEST_MODE13,
	PMIC_ACCDET_TEST_MODE12,
	PMIC_ACCDET_TEST_MODE11,
	PMIC_ACCDET_TEST_MODE10,
	PMIC_ACCDET_EINTCMPOUT_SW,
	PMIC_ACCDET_TEST_MODE9,
	PMIC_ACCDET_TEST_MODE8,
	PMIC_ACCDET_AUXADC_CTRL_SW,
	PMIC_ACCDET_TEST_MODE7,
	PMIC_ACCDET_TEST_MODE6,
	PMIC_ACCDET_EINTCMP_EN_SW,
	PMIC_ACCDET_EINT_STATE,
	PMIC_ACCDET_AUXADC_DEBOUNCE_END,
	PMIC_ACCDET_AUXADC_CONNECT_PRE,
	PMIC_ACCDET_EINT_CUR_IN,
	PMIC_ACCDET_EINT_SAM_IN,
	PMIC_ACCDET_EINT_MEM_IN,
	PMIC_AD_EINTCMPOUT,
	PMIC_DA_NI_EINTCMPEN,
	PMIC_ACCDET_CUR_DEB,
	PMIC_ACCDET_EINT_CUR_DEB,
	PMIC_ACCDET_RSV_CON0,
	PMIC_ACCDET_RSV_CON1,
	PMIC_ACCDET_AUXADC_CONNECT_TIME,
	PMIC_ACCDET_HWMODE_SEL,
	PMIC_ACCDET_EINT_DEB_OUT_DFF,
	PMIC_ACCDET_EINT_REVERSE,
	PMIC_RG_OTP_PA,
	PMIC_RG_OTP_PDIN,
	PMIC_RG_OTP_PTM,
	PMIC_RG_OTP_PWE,
	PMIC_RG_OTP_PPROG,
	PMIC_RG_OTP_PWE_SRC,
	PMIC_RG_OTP_PROG_PKEY,
	PMIC_RG_OTP_RD_PKEY,
	PMIC_RG_OTP_RD_TRIG,
	PMIC_RG_RD_RDY_BYPASS,
	PMIC_RG_SKIP_OTP_OUT,
	PMIC_RG_OTP_RD_SW,
	PMIC_RG_OTP_DOUT_SW,
	PMIC_RG_OTP_RD_BUSY,
	PMIC_RG_OTP_RD_ACK,
	PMIC_RG_OTP_PA_SW,
	PMIC_RG_OTP_DOUT_0_15,
	PMIC_RG_OTP_DOUT_16_31,
	PMIC_RG_OTP_DOUT_32_47,
	PMIC_RG_OTP_DOUT_48_63,
	PMIC_RG_OTP_DOUT_64_79,
	PMIC_RG_OTP_DOUT_80_95,
	PMIC_RG_OTP_DOUT_96_111,
	PMIC_RG_OTP_DOUT_112_127,
	PMIC_RG_OTP_DOUT_128_143,
	PMIC_RG_OTP_DOUT_144_159,
	PMIC_RG_OTP_DOUT_160_175,
	PMIC_RG_OTP_DOUT_176_191,
	PMIC_RG_OTP_DOUT_192_207,
	PMIC_RG_OTP_DOUT_208_223,
	PMIC_RG_OTP_DOUT_224_239,
	PMIC_RG_OTP_DOUT_240_255,
	PMIC_RG_OTP_DOUT_256_271,
	PMIC_RG_OTP_DOUT_272_287,
	PMIC_RG_OTP_DOUT_288_303,
	PMIC_RG_OTP_DOUT_304_319,
	PMIC_RG_OTP_DOUT_320_335,
	PMIC_RG_OTP_DOUT_336_351,
	PMIC_RG_OTP_DOUT_352_367,
	PMIC_RG_OTP_DOUT_368_383,
	PMIC_RG_OTP_DOUT_384_399,
	PMIC_RG_OTP_DOUT_400_415,
	PMIC_RG_OTP_DOUT_416_431,
	PMIC_RG_OTP_DOUT_432_447,
	PMIC_RG_OTP_DOUT_448_463,
	PMIC_RG_OTP_DOUT_464_479,
	PMIC_RG_OTP_DOUT_480_495,
	PMIC_RG_OTP_DOUT_496_511,
	PMIC_RG_OTP_DOUT_512_527,
	PMIC_RG_OTP_DOUT_528_543,
	PMIC_RG_OTP_DOUT_544_559,
	PMIC_RG_OTP_DOUT_560_575,
	PMIC_RG_OTP_DOUT_576_591,
	PMIC_RG_OTP_DOUT_592_607,
	PMIC_RG_OTP_DOUT_608_623,
	PMIC_RG_OTP_DOUT_624_639,
	PMIC_RG_OTP_DOUT_640_655,
	PMIC_RG_OTP_DOUT_656_671,
	PMIC_RG_OTP_DOUT_672_687,
	PMIC_RG_OTP_DOUT_688_703,
	PMIC_RG_OTP_DOUT_704_719,
	PMIC_RG_OTP_DOUT_720_735,
	PMIC_RG_OTP_DOUT_736_751,
	PMIC_RG_OTP_DOUT_752_767,
	PMIC_RG_OTP_DOUT_768_783,
	PMIC_RG_OTP_DOUT_784_799,
	PMIC_RG_OTP_DOUT_800_815,
	PMIC_RG_OTP_DOUT_816_831,
	PMIC_RG_OTP_DOUT_832_847,
	PMIC_RG_OTP_DOUT_848_863,
	PMIC_RG_OTP_DOUT_864_879,
	PMIC_RG_OTP_DOUT_880_895,
	PMIC_RG_OTP_DOUT_896_911,
	PMIC_RG_OTP_DOUT_912_927,
	PMIC_RG_OTP_DOUT_928_943,
	PMIC_RG_OTP_DOUT_944_959,
	PMIC_RG_OTP_DOUT_960_975,
	PMIC_RG_OTP_DOUT_976_991,
	PMIC_RG_OTP_DOUT_992_1007,
	PMIC_RG_OTP_DOUT_1008_1023,
	PMIC_RG_OTP_DOUT_1024_1039,
	PMIC_RG_OTP_DOUT_1040_1055,
	PMIC_RG_OTP_DOUT_1056_1071,
	PMIC_RG_OTP_DOUT_1072_1087,
	PMIC_RG_OTP_DOUT_1088_1103,
	PMIC_RG_OTP_DOUT_1104_1119,
	PMIC_RG_OTP_DOUT_1120_1135,
	PMIC_RG_OTP_DOUT_1136_1151,
	PMIC_RG_OTP_DOUT_1152_1167,
	PMIC_RG_OTP_DOUT_1168_1183,
	PMIC_RG_OTP_DOUT_1184_1199,
	PMIC_RG_OTP_DOUT_1200_1215,
	PMIC_RG_OTP_DOUT_1216_1231,
	PMIC_RG_OTP_DOUT_1232_1247,
	PMIC_RG_OTP_DOUT_1248_1263,
	PMIC_RG_OTP_DOUT_1264_1279,
	PMIC_RG_OTP_DOUT_1280_1295,
	PMIC_RG_OTP_DOUT_1296_1311,
	PMIC_RG_OTP_DOUT_1312_1327,
	PMIC_RG_OTP_DOUT_1328_1343,
	PMIC_RG_OTP_DOUT_1344_1359,
	PMIC_RG_OTP_DOUT_1360_1375,
	PMIC_RG_OTP_DOUT_1376_1391,
	PMIC_RG_OTP_DOUT_1392_1407,
	PMIC_RG_OTP_DOUT_1408_1423,
	PMIC_RG_OTP_DOUT_1424_1439,
	PMIC_RG_OTP_DOUT_1440_1455,
	PMIC_RG_OTP_DOUT_1456_1471,
	PMIC_RG_OTP_DOUT_1472_1487,
	PMIC_RG_OTP_DOUT_1488_1503,
	PMIC_RG_OTP_DOUT_1504_1519,
	PMIC_RG_OTP_DOUT_1520_1535,
	PMIC_RG_OTP_VAL_0_15,
	PMIC_RG_OTP_VAL_16_31,
	PMIC_RG_OTP_VAL_32_47,
	PMIC_RG_OTP_VAL_48_63,
	PMIC_RG_OTP_VAL_64_79,
	PMIC_RG_OTP_VAL_80_95,
	PMIC_RG_OTP_VAL_96_111,
	PMIC_RG_OTP_VAL_112_127,
	PMIC_RG_OTP_VAL_128_143,
	PMIC_RG_OTP_VAL_144_159,
	PMIC_RG_OTP_VAL_160_175,
	PMIC_RG_OTP_VAL_176_191,
	PMIC_RG_OTP_VAL_192_207,
	PMIC_RG_OTP_VAL_208_223,
	PMIC_RG_OTP_VAL_224_239,
	PMIC_RG_OTP_VAL_240_255,
	PMIC_RG_OTP_VAL_256_271,
	PMIC_RG_OTP_VAL_272_287,
	PMIC_RG_OTP_VAL_288_303,
	PMIC_RG_OTP_VAL_304_319,
	PMIC_RG_OTP_VAL_320_335,
	PMIC_RG_OTP_VAL_336_351,
	PMIC_RG_OTP_VAL_352_367,
	PMIC_RG_OTP_VAL_368_383,
	PMIC_RG_OTP_VAL_384_399,
	PMIC_RG_OTP_VAL_400_415,
	PMIC_RG_OTP_VAL_416_431,
	PMIC_RG_OTP_VAL_432_447,
	PMIC_RG_OTP_VAL_448_463,
	PMIC_RG_OTP_VAL_464_479,
	PMIC_RG_OTP_VAL_480_495,
	PMIC_RG_OTP_VAL_496_511,
	PMIC_RG_OTP_VAL_512_527,
	PMIC_RG_OTP_VAL_528_543,
	PMIC_RG_OTP_VAL_544_559,
	PMIC_RG_OTP_VAL_560_575,
	PMIC_RG_OTP_VAL_576_591,
	PMIC_RG_OTP_VAL_592_607,
	PMIC_RG_OTP_VAL_608_623,
	PMIC_RG_OTP_VAL_624_639,
	PMIC_RG_OTP_VAL_640_655,
	PMIC_RG_OTP_VAL_656_671,
	PMIC_RG_OTP_VAL_672_687,
	PMIC_RG_OTP_VAL_688_703,
	PMIC_RG_OTP_VAL_704_719,
	PMIC_RG_OTP_VAL_720_735,
	PMIC_RG_OTP_VAL_736_751,
	PMIC_RG_OTP_VAL_752_767,
	PMIC_RG_OTP_VAL_768_783,
	PMIC_RG_OTP_VAL_784_799,
	PMIC_RG_OTP_VAL_800_815,
	PMIC_RG_OTP_VAL_816_831,
	PMIC_RG_OTP_VAL_832_847,
	PMIC_RG_OTP_VAL_848_863,
	PMIC_RG_OTP_VAL_864_879,
	PMIC_RG_OTP_VAL_880_895,
	PMIC_RG_OTP_VAL_896_911,
	PMIC_RG_OTP_VAL_912_927,
	PMIC_RG_OTP_VAL_928_943,
	PMIC_RG_OTP_VAL_944_959,
	PMIC_RG_OTP_VAL_960_975,
	PMIC_RG_OTP_VAL_976_991,
	PMIC_RG_OTP_VAL_992_1007,
	PMIC_RG_OTP_VAL_1008_1023,
	PMIC_RG_OTP_VAL_1024_1039,
	PMIC_RG_OTP_VAL_1040_1055,
	PMIC_RG_OTP_VAL_1056_1071,
	PMIC_RG_OTP_VAL_1072_1087,
	PMIC_RG_OTP_VAL_1088_1103,
	PMIC_RG_OTP_VAL_1104_1119,
	PMIC_RG_OTP_VAL_1120_1135,
	PMIC_RG_OTP_VAL_1136_1151,
	PMIC_RG_OTP_VAL_1152_1167,
	PMIC_RG_OTP_VAL_1168_1183,
	PMIC_RG_OTP_VAL_1184_1199,
	PMIC_RG_OTP_VAL_1200_1215,
	PMIC_RG_OTP_VAL_1216_1231,
	PMIC_RG_OTP_VAL_1232_1247,
	PMIC_RG_OTP_VAL_1248_1263,
	PMIC_RG_OTP_VAL_1264_1279,
	PMIC_RG_OTP_VAL_1280_1295,
	PMIC_RG_OTP_VAL_1296_1311,
	PMIC_RG_OTP_VAL_1312_1327,
	PMIC_RG_OTP_VAL_1328_1343,
	PMIC_RG_OTP_VAL_1344_1359,
	PMIC_RG_OTP_VAL_1360_1375,
	PMIC_RG_OTP_VAL_1376_1391,
	PMIC_RG_OTP_VAL_1392_1407,
	PMIC_RG_OTP_VAL_1408_1423,
	PMIC_RG_OTP_VAL_1424_1439,
	PMIC_RG_OTP_VAL_1440_1455,
	PMIC_RG_OTP_VAL_1456_1471,
	PMIC_RG_OTP_VAL_1472_1487,
	PMIC_RG_OTP_VAL_1488_1503,
	PMIC_RG_OTP_VAL_1504_1519,
	PMIC_RG_OTP_VAL_1520_1535,
	PMIC_XO_EXTBUF1_MODE,
	PMIC_XO_EXTBUF1_EN_M,
	PMIC_XO_EXTBUF2_MODE,
	PMIC_XO_EXTBUF2_EN_M,
	PMIC_XO_EXTBUF3_MODE,
	PMIC_XO_EXTBUF3_EN_M,
	PMIC_XO_EXTBUF4_MODE,
	PMIC_XO_EXTBUF4_EN_M,
	PMIC_XO_BB_LPM_EN,
	PMIC_XO_ENBB_MAN,
	PMIC_XO_ENBB_EN_M,
	PMIC_XO_CLKSEL_MAN,
	PMIC_DCXO_CW00_SET,
	PMIC_DCXO_CW00_CLR,
	PMIC_XO_CLKSEL_EN_M,
	PMIC_XO_EXTBUF1_CKG_MAN,
	PMIC_XO_EXTBUF1_CKG_EN_M,
	PMIC_XO_EXTBUF2_CKG_MAN,
	PMIC_XO_EXTBUF2_CKG_EN_M,
	PMIC_XO_EXTBUF3_CKG_MAN,
	PMIC_XO_EXTBUF3_CKG_EN_M,
	PMIC_XO_EXTBUF4_CKG_MAN,
	PMIC_XO_EXTBUF4_CKG_EN_M,
	PMIC_XO_INTBUF_MAN,
	PMIC_XO_PBUF_EN_M,
	PMIC_XO_IBUF_EN_M,
	PMIC_XO_LPMBUF_MAN,
	PMIC_XO_LPM_PREBUF_EN_M,
	PMIC_XO_LPBUF_EN_M,
	PMIC_XO_BBLPM_CKSEL_M,
	PMIC_XO_EN32K_MAN,
	PMIC_XO_EN32K_M,
	PMIC_XO_XMODE_MAN,
	PMIC_XO_XMODE_M,
	PMIC_XO_STRUP_MODE,
	PMIC_XO_AAC_FPM_TIME,
	PMIC_XO_AAC_MODE_LPM,
	PMIC_XO_AAC_MODE_FPM,
	PMIC_XO_EN26M_OFFSQ_EN,
	PMIC_XO_LDOCAL_EN,
	PMIC_XO_CBANK_SYNC_DYN,
	PMIC_XO_26MLP_MAN_EN,
	PMIC_XO_BUFLDOK_EN,
	PMIC_XO_RESERVED2,
	PMIC_XO_EXTBUF6_CKG_MAN,
	PMIC_XO_EXTBUF6_CKG_EN_M,
	PMIC_XO_EXTBUF7_CKG_MAN,
	PMIC_XO_EXTBUF7_CKG_EN_M,
	PMIC_XO_LPM_ISEL_MAN,
	PMIC_XO_FPM_ISEL_MAN,
	PMIC_XO_CDAC_FPM,
	PMIC_XO_CDAC_LPM,
	PMIC_XO_32KDIV_NFRAC_FPM,
	PMIC_XO_COFST_FPM,
	PMIC_XO_32KDIV_NFRAC_LPM,
	PMIC_XO_COFST_LPM,
	PMIC_XO_CORE_MAN,
	PMIC_XO_CORE_EN_M,
	PMIC_XO_CORE_TURBO_EN_M,
	PMIC_XO_CORE_AAC_EN_M,
	PMIC_XO_STARTUP_EN_M,
	PMIC_XO_CORE_VBFPM_EN_M,
	PMIC_XO_CORE_VBLPM_EN_M,
	PMIC_XO_LPMBIAS_EN_M,
	PMIC_XO_VTCGEN_EN_M,
	PMIC_XO_IAAC_COMP_EN_M,
	PMIC_XO_IFPM_COMP_EN_M,
	PMIC_XO_ILPM_COMP_EN_M,
	PMIC_XO_CORE_BYPCAS_FPM,
	PMIC_XO_CORE_GMX2_FPM,
	PMIC_XO_CORE_IDAC_FPM,
	PMIC_XO_AAC_COMP_MAN,
	PMIC_XO_AAC_EN_M,
	PMIC_XO_AAC_MONEN_M,
	PMIC_XO_COMP_EN_M,
	PMIC_XO_COMP_TSTEN_M,
	PMIC_XO_AAC_HV_FPM,
	PMIC_XO_AAC_IBIAS_FPM,
	PMIC_XO_AAC_VOFST_FPM,
	PMIC_XO_AAC_COMP_HV_FPM,
	PMIC_XO_AAC_VSEL_FPM,
	PMIC_XO_AAC_COMP_POL,
	PMIC_XO_CORE_BYPCAS_LPM,
	PMIC_XO_CORE_GMX2_LPM,
	PMIC_XO_CORE_IDAC_LPM,
	PMIC_XO_AAC_COMP_HV_LPM,
	PMIC_XO_AAC_VSEL_LPM,
	PMIC_XO_AAC_HV_LPM,
	PMIC_XO_AAC_IBIAS_LPM,
	PMIC_XO_AAC_VOFST_LPM,
	PMIC_XO_AAC_FPM_SWEN,
	PMIC_XO_SWRST,
	PMIC_XO_32KDIV_SWRST,
	PMIC_XO_32KDIV_RATIO_MAN,
	PMIC_XO_32KDIV_TEST_EN,
	PMIC_XO_CBANK_SYNC_MAN,
	PMIC_XO_CBANK_SYNC_EN_M,
	PMIC_XO_CTL_SYNC_MAN,
	PMIC_XO_CTL_SYNC_EN_M,
	PMIC_XO_LDO_MAN,
	PMIC_XO_LDOPBUF_EN_M,
	PMIC_XO_LDOPBUF_VSET_M,
	PMIC_XO_LDOVTST_EN_M,
	PMIC_XO_TEST_VCAL_EN_M,
	PMIC_XO_VBIST_EN_M,
	PMIC_XO_VTEST_SEL_MUX,
	PMIC_XO_RESERVED3,
	PMIC_XO_EXTBUF6_MODE,
	PMIC_XO_EXTBUF6_EN_M,
	PMIC_XO_EXTBUF7_MODE,
	PMIC_XO_EXTBUF7_EN_M,
	PMIC_XO_BUFLDOK_MAN,
	PMIC_XO_BUF1LDO_CAL_M,
	PMIC_DCXO_CW11_SET,
	PMIC_DCXO_CW11_CLR,
	PMIC_XO_BUFLDO_CAL_M,
	PMIC_XO_EXTBUF4_CLKSEL_MAN,
	PMIC_XO_VIO18PG_BUFEN,
	PMIC_XO_CAL_EN_MAN,
	PMIC_XO_CAL_EN_M,
	PMIC_RG_XO_CORE_OSCTD,
	PMIC_XO_THADC_EN,
	PMIC_RG_XO_SYNC_CKPOL,
	PMIC_RG_XO_CBANK_POL,
	PMIC_RG_XO_CBANK_SYNC_BYP,
	PMIC_RG_XO_CTL_POL,
	PMIC_RG_XO_CTL_SYNC_BYP,
	PMIC_RG_XO_LPBUF_INV,
	PMIC_RG_XO_LDOPBUF_BYP,
	PMIC_RG_XO_LDOPBUF_ENCL,
	PMIC_RG_XO_VGBIAS_VSET,
	PMIC_RG_XO_PBUF_ISET,
	PMIC_RG_XO_IBUF_ISET,
	PMIC_RG_XO_RESERVED4,
	PMIC_RG_XO_VOW_EN,
	PMIC_RG_XO_VOW_DIV,
	PMIC_RG_XO_BUFLDO24_ENCL,
	PMIC_RG_XO_BUFLDO24_IBX2,
	PMIC_RG_XO_RESERVED5,
	PMIC_RG_XO_BUFLDO13_ENCL,
	PMIC_RG_XO_BUFLDO13_IBX2,
	PMIC_RG_XO_BUFLDO13_IX2,
	PMIC_RG_XO_LVLDO_I_CTRL,
	PMIC_RG_XO_BUFLDO67_ENCL,
	PMIC_RG_XO_BUFLDO67_IBX2,
	PMIC_RG_XO_BUFLDO67_IX2,
	PMIC_RG_XO_LVLDO_RFB,
	PMIC_RG_XO_EXTBUF_INV,
	PMIC_RG_XO_RESERVED0,
	PMIC_XO_EXTBUF2_CLKSEL_MAN,
	PMIC_XO_AUDIO_EN_M,
	PMIC_RG_XO_AUDIO_ATTEN,
	PMIC_RG_XO_AUDIO_ISET,
	PMIC_RG_XO_EXTBUF1_HD,
	PMIC_RG_XO_EXTBUF2_HD,
	PMIC_RG_XO_EXTBUF3_HD,
	PMIC_RG_XO_EXTBUF4_HD,
	PMIC_RG_XO_RESERVED8,
	PMIC_RG_XO_EXTBUF6_HD,
	PMIC_RG_XO_EXTBUF7_HD,
	PMIC_XO_EXTBUF1_ISET_M,
	PMIC_XO_EXTBUF2_ISET_M,
	PMIC_XO_EXTBUF3_ISET_M,
	PMIC_XO_EXTBUF4_ISET_M,
	PMIC_XO_RESERVED9,
	PMIC_XO_EXTBUF6_ISET_M,
	PMIC_XO_EXTBUF7_ISET_M,
	PMIC_RG_XO_LPM_PREBUF_ISET,
	PMIC_RG_XO_RESERVED1,
	PMIC_XO_THADC_EN_MAN,
	PMIC_RG_XO_TSOURCE_EN,
	PMIC_XO_BUFLDO13_VSET_M,
	PMIC_XO_BUFLDO24_VSET_M,
	PMIC_XO_BUFLDO67_VSET_M,
	PMIC_XO_STATIC_AUXOUT_SEL,
	PMIC_XO_AUXOUT_SEL,
	PMIC_XO_STATIC_AUXOUT,
	PMIC_RG_XO_PCTAT_COMP_EN,
	PMIC_RG_XO_PCTAT_RDEG_SEL,
	PMIC_RG_XO_GS_VTEMP,
	PMIC_RG_XO_HEATER_SEL,
	PMIC_RG_XO_CORNER_DETECT_EN,
	PMIC_RG_XO_CORNER_DETECT_EN_MAN,
	PMIC_RG_XO_RESRVED10,
	PMIC_RG_XO_CORNER_SETTING_TUNE,
	PMIC_RG_XO_RESRVED11,
	PMIC_RG_AD_XO_CORNER_CAL_DONE,
	PMIC_RG_AD_XO_CORNER_SEL,
	PMIC_RG_VCDT_HV_EN,
	PMIC_RG_VCDT_DEB_SEL,
	PMIC_RG_PCHR_FT_CTRL,
	PMIC_RGS_CHRDET,
	PMIC_RGS_VCDT_LV_DET,
	PMIC_RGS_VCDT_HV_DET,
	PMIC_RG_VCDT_LV_VTH,
	PMIC_RG_VCDT_HV_VTH,
	PMIC_RGS_PCHR_FLAG_OUT,
	PMIC_RG_PCHR_FLAG_EN,
	PMIC_RG_PCHR_FLAG_SEL,
	PMIC_RG_PCHR_RSV,
	PMIC_RG_ENVTEM_D,
	PMIC_RG_ENVTEM_EN,
	PMIC_RG_CHR_CON6_RSV,
	PMIC_RG_ADCIN_VSEN_MUX_EN,
	PMIC_RG_ADCIN_VSEN_EXT_BATON_EN,
	PMIC_RG_ADCIN_VBAT_EN,
	PMIC_RG_ADCIN_VSEN_EN,
	PMIC_RG_ADCIN_CHR_EN,
	PMIC_DA_QI_BATON_LT_EN,
	PMIC_DA_QI_BGR_EXT_BUF_EN,
	PMIC_BATON_TDET_EN,
	PMIC_RG_BGR_UNCHOP,
	PMIC_RG_BGR_UNCHOP_PH,
	PMIC_RG_BGR_RSEL,
	PMIC_RG_BGR_TRIM_EN,
	PMIC_RG_BGR_TEST_RSTB,
	PMIC_RG_BGR_TRIM,
	PMIC_RG_BGR_TEST_EN,
	PMIC_RG_VCDT_TRIM,
	PMIC_RG_BATON_EN,
	PMIC_RG_BATON_HT_TRIM,
	PMIC_RG_HW_VTH1,
	PMIC_RG_HW_VTH2,
	PMIC_RG_HW_VTH_CTRL,
	PMIC_RG_OTG_BVALID_EN,
	PMIC_RG_UVLO_VTHL,
	PMIC_RG_UVLO_VH_LAT,
	PMIC_RG_LBAT_INT_VTH,
	PMIC_RG_PCHR_RV,
	PMIC_RGS_BATON_UNDET,
	PMIC_RGS_OTG_BVALID_DET,
	PMIC_RGS_CHR_LDO_DET,
	PMIC_RGS_BATON_HV,
	PMIC_RG_PCHR_ANA3_RSV,
	PMIC_RG_VCDT_UVLO_VTH,
	PMIC_GPIO_DIR0,
	PMIC_GPIO_DIR0_SET,
	PMIC_GPIO_DIR0_CLR,
	PMIC_GPIO_PULLEN0,
	PMIC_GPIO_PULLEN0_SET,
	PMIC_GPIO_PULLEN0_CLR,
	PMIC_GPIO_PULLSEL0,
	PMIC_GPIO_PULLSEL0_SET,
	PMIC_GPIO_PULLSEL0_CLR,
	PMIC_GPIO_DINV0,
	PMIC_GPIO_DINV0_SET,
	PMIC_GPIO_DINV0_CLR,
	PMIC_GPIO_DOUT0,
	PMIC_GPIO_DOUT0_SET,
	PMIC_GPIO_DOUT0_CLR,
	PMIC_GPIO_PI0,
	PMIC_GPIO_POE0,
	PMIC_GPIO0_MODE,
	PMIC_GPIO1_MODE,
	PMIC_GPIO2_MODE,
	PMIC_GPIO3_MODE,
	PMIC_GPIO4_MODE,
	PMIC_GPIO_MODE0_SET,
	PMIC_GPIO_MODE0_CLR,
	PMIC_GPIO5_MODE,
	PMIC_GPIO6_MODE,
	PMIC_GPIO7_MODE,
	PMIC_GPIO8_MODE,
	PMIC_GPIO9_MODE,
	PMIC_GPIO_MODE1_SET,
	PMIC_GPIO_MODE1_CLR,
	PMIC_GPIO10_MODE,
	PMIC_GPIO11_MODE,
	PMIC_GPIO12_MODE,
	PMIC_GPIO13_MODE,
	PMIC_GPIO_MODE2_SET,
	PMIC_GPIO_MODE2_CLR,
	PMIC_GPIO_RSV,
	PMIC_RTC_SEC_DUMMY,
	PMIC_RTC_DUMMY,
	PMIC_EOSC_CALI_START,
	PMIC_EOSC_CALI_TD,
	PMIC_EOSC_CALI_TEST,
	PMIC_EOSC_CALI_DCXO_RDY_TD,
	PMIC_FRC_VTCXO0_ON,
	PMIC_EOSC_CALI_RSV,
	PMIC_MIX_EOSC32_STP_LPDTB,
	PMIC_MIX_EOSC32_STP_LPDEN,
	PMIC_MIX_XOSC32_STP_PWDB,
	PMIC_MIX_XOSC32_STP_LPDTB,
	PMIC_MIX_XOSC32_STP_LPDEN,
	PMIC_MIX_XOSC32_STP_LPDRST,
	PMIC_MIX_XOSC32_STP_CALI,
	PMIC_STMP_MODE,
	PMIC_MIX_EOSC32_STP_CHOP_EN,
	PMIC_MIX_DCXO_STP_LVSH_EN,
	PMIC_MIX_PMU_STP_DDLO_VRTC,
	PMIC_MIX_PMU_STP_DDLO_VRTC_EN,
	PMIC_MIX_RTC_STP_XOSC32_ENB,
	PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE,
	PMIC_MIX_EOSC32_STP_RSV,
	PMIC_MIX_EOSC32_VCT_EN,
	PMIC_MIX_EOSC32_OPT,
	PMIC_MIX_DCXO_STP_LVSH_EN_INT,
	PMIC_MIX_RTC_GPIO_COREDETB,
	PMIC_MIX_RTC_GPIO_F32KOB,
	PMIC_MIX_RTC_GPIO_GPO,
	PMIC_MIX_RTC_GPIO_OE,
	PMIC_MIX_RTC_STP_DEBUG_OUT,
	PMIC_MIX_RTC_STP_DEBUG_SEL,
	PMIC_MIX_RTC_STP_K_EOSC32_EN,
	PMIC_MIX_RTC_STP_EMBCK_SEL,
	PMIC_MIX_STP_BBWAKEUP,
	PMIC_MIX_STP_RTC_DDLO,
	PMIC_MIX_RTC_XOSC32_ENB,
	PMIC_MIX_EFUSE_XOSC32_ENB_OPT,
	PMIC_VRTC_PWM_MODE,
	PMIC_VRTC_PWM_RSV,
	PMIC_VRTC_PWM_L_DUTY,
	PMIC_VRTC_PWM_H_DUTY,
	PMIC_VRTC_CAP_SEL,
	PMIC_BIF_COMMAND_0,
	PMIC_BIF_COMMAND_1,
	PMIC_BIF_COMMAND_2,
	PMIC_BIF_COMMAND_3,
	PMIC_BIF_COMMAND_4,
	PMIC_BIF_COMMAND_5,
	PMIC_BIF_COMMAND_6,
	PMIC_BIF_COMMAND_7,
	PMIC_BIF_COMMAND_8,
	PMIC_BIF_COMMAND_9,
	PMIC_BIF_COMMAND_10,
	PMIC_BIF_COMMAND_11,
	PMIC_BIF_COMMAND_12,
	PMIC_BIF_COMMAND_13,
	PMIC_BIF_COMMAND_14,
	PMIC_BIF_RSV,
	PMIC_BIF_COMMAND_TYPE,
	PMIC_BIF_TRASFER_NUM,
	PMIC_BIF_LOGIC_0_SET,
	PMIC_BIF_LOGIC_1_SET,
	PMIC_BIF_STOP_SET,
	PMIC_BIF_DEBOUNCE_EN,
	PMIC_BIF_READ_EXPECT_NUM,
	PMIC_BIF_TRASACT_TRIGGER,
	PMIC_BIF_DATA_NUM,
	PMIC_BIF_RESPONSE,
	PMIC_BIF_DATA_0,
	PMIC_BIF_ACK_0,
	PMIC_BIF_ERROR_0,
	PMIC_BIF_DATA_1,
	PMIC_BIF_ACK_1,
	PMIC_BIF_ERROR_1,
	PMIC_BIF_DATA_2,
	PMIC_BIF_ACK_2,
	PMIC_BIF_ERROR_2,
	PMIC_BIF_DATA_3,
	PMIC_BIF_ACK_3,
	PMIC_BIF_ERROR_3,
	PMIC_BIF_DATA_4,
	PMIC_BIF_ACK_4,
	PMIC_BIF_ERROR_4,
	PMIC_BIF_DATA_5,
	PMIC_BIF_ACK_5,
	PMIC_BIF_ERROR_5,
	PMIC_BIF_DATA_6,
	PMIC_BIF_ACK_6,
	PMIC_BIF_ERROR_6,
	PMIC_BIF_DATA_7,
	PMIC_BIF_ACK_7,
	PMIC_BIF_ERROR_7,
	PMIC_BIF_DATA_8,
	PMIC_BIF_ACK_8,
	PMIC_BIF_ERROR_8,
	PMIC_BIF_DATA_9,
	PMIC_BIF_ACK_9,
	PMIC_BIF_ERROR_9,
	PMIC_BIF_TEST_MODE0,
	PMIC_BIF_TEST_MODE1,
	PMIC_BIF_TEST_MODE2,
	PMIC_BIF_TEST_MODE3,
	PMIC_BIF_TEST_MODE4,
	PMIC_BIF_TEST_MODE5,
	PMIC_BIF_TEST_MODE6,
	PMIC_BIF_TEST_MODE7,
	PMIC_BIF_TEST_MODE8,
	PMIC_BIF_BAT_LOST_SW,
	PMIC_BIF_RX_DATA_SW,
	PMIC_BIF_TX_DATA_SW,
	PMIC_BIF_RX_EN_SW,
	PMIC_BIF_TX_EN_SW,
	PMIC_BIF_BACK_NORMAL,
	PMIC_BIF_IRQ_CLR,
	PMIC_BIF_IRQ,
	PMIC_BIF_TIMEOUT,
	PMIC_BIF_BAT_UNDET,
	PMIC_BIF_TOTAL_VALID,
	PMIC_BIF_BUS_STATUS,
	PMIC_BIF_POWER_UP_COUNT,
	PMIC_BIF_POWER_UP,
	PMIC_BIF_RX_ERROR_UNKNOW,
	PMIC_BIF_RX_ERROR_INSUFF,
	PMIC_BIF_RX_ERROR_LOWPHASE,
	PMIC_BIF_RX_STATE,
	PMIC_BIF_FLOW_CTL_STATE,
	PMIC_BIF_TX_STATE,
	PMIC_AD_QI_BIF_RX_DATA,
	PMIC_DA_QI_BIF_RX_EN,
	PMIC_DA_QI_BIF_TX_DATA,
	PMIC_DA_QI_BIF_TX_EN,
	PMIC_BIF_TX_DATA_FIANL,
	PMIC_BIF_RX_DATA_SAMPLING,
	PMIC_BIF_RX_DATA_RECOVERY,
	PMIC_RG_BATON_HT_EN,
	PMIC_RG_BATON_HT_EN_DLY_TIME,
	PMIC_BIF_TIMEOUT_SET,
	PMIC_BIF_RX_DEG_WND,
	PMIC_BIF_RX_DEG_EN,
	PMIC_BIF_RSV1,
	PMIC_BIF_RSV0,
	PMIC_DA_QI_BATON_HT_EN,
	PMIC_RG_BATON_DEBOUNCE_WND,
	PMIC_RG_BATON_DEBOUNCE_THD,
	PMIC_RG_BATON_VBIF_STB,
	PMIC_RG_BATON_CHRDET_TEST_MODE,
	PMIC_RG_BATON_UNDET_TEST_MODE,
	PMIC_RG_BATON_AUXADC_TEST_MODE,
	PMIC_RG_BATON_FGADC_TEST_MODE,
	PMIC_RG_BATON_RTC_TEST_MODE,
	PMIC_RG_BATON_BIF_TEST_MODE,
	PMIC_RG_BATON_RSV,
	PMIC_RG_BATON_CHRDET_SW,
	PMIC_RG_BATON_UNDET_SW,
	PMIC_RG_BATON_AUXADC_SW,
	PMIC_RG_BATON_FGADC_SW,
	PMIC_RG_BATON_RTC_SW,
	PMIC_RG_BATON_BIF_SW,
	PMIC_RG_BATON_RSV_SW,
	PMIC_BATON_STATUS,
	PMIC_BATON_AUXADC_SET,
	PMIC_BATON_DEB_VALID,
	PMIC_BATON_BIF_STATUS,
	PMIC_BATON_RTC_STATUS,
	PMIC_BATON_FGADC_STATUS,
	PMIC_BATON_AUXADC_TRIG,
	PMIC_BATON_CHRDET_DEB,
	PMIC_BATON_IVGEN_ENB,
	PMIC_BATON_VBIF28_STB,
	PMIC_BATON_VBIF28_EN,
	PMIC_BATON_RSV_0,
	PMIC_RG_BIF_BATID_SW_EN,
	PMIC_FG_ON,
	PMIC_FG_CAL,
	PMIC_FG_AUTOCALRATE,
	PMIC_FG_SON_SLP_EN,
	PMIC_FG_SOFF_SLP_EN,
	PMIC_FG_ZCV_DET_EN,
	PMIC_FG_AUXADC_R,
	PMIC_FG_IAVG_MODE,
	PMIC_FG_SW_READ_PRE,
	PMIC_FG_SW_RSTCLR,
	PMIC_FG_SW_CR,
	PMIC_FG_SW_CLEAR,
	PMIC_FG_OFFSET_RST,
	PMIC_FG_TIME_RST,
	PMIC_FG_CHARGE_RST,
	PMIC_FG_N_CHARGE_RST,
	PMIC_FG_SOFF_RST,
	PMIC_FG_LATCHDATA_ST,
	PMIC_EVENT_FG_BAT0_L,
	PMIC_EVENT_FG_BAT0_H,
	PMIC_EVENT_FG_BAT1_L,
	PMIC_EVENT_FG_BAT1_H,
	PMIC_EVENT_FG_CUR_L,
	PMIC_EVENT_FG_CUR_H,
	PMIC_EVENT_FG_IAVG_L,
	PMIC_EVENT_FG_IAVG_H,
	PMIC_EVENT_FG_N_CHARGE_L,
	PMIC_EVENT_FG_TIME_H,
	PMIC_EVENT_FG_DISCHARGE,
	PMIC_EVENT_FG_CHARGE,
	PMIC_EVENT_FG_ZCV,
	PMIC_FG_OSR1,
	PMIC_FG_OSR2,
	PMIC_FG_FIR1BYPASS,
	PMIC_FG_FIR2BYPASS,
	PMIC_FG_ADJ_OFFSET_EN,
	PMIC_FG_ADC_AUTORST,
	PMIC_FG_ADC_RSTDETECT,
	PMIC_FG_VA18_AON,
	PMIC_FG_VA18_AOFF,
	PMIC_FG_SON_SW,
	PMIC_FG_SON_SW_MODE,
	PMIC_FGADC_CON4_RSV,
	PMIC_FG_RSTB_STATUS,
	PMIC_FG_R_CURR,
	PMIC_FG_CURRENT_OUT,
	PMIC_FG_CUR_LTH,
	PMIC_FG_CUR_HTH,
	PMIC_FG_CIC2,
	PMIC_FG_CAR_31_16,
	PMIC_FG_CAR_15_00,
	PMIC_FG_BAT0_LTH_31_16,
	PMIC_FG_BAT0_LTH_15_14,
	PMIC_FG_BAT0_HTH_31_16,
	PMIC_FG_BAT0_HTH_15_14,
	PMIC_FG_BAT1_LTH_31_16,
	PMIC_FG_BAT1_LTH_15_14,
	PMIC_FG_BAT1_HTH_31_16,
	PMIC_FG_BAT1_HTH_15_14,
	PMIC_FG_NCAR_31_16,
	PMIC_FG_NCAR_15_00,
	PMIC_FG_N_CHARGE_LTH_31_16,
	PMIC_FG_N_CHARGE_LTH_15_14,
	PMIC_FG_IAVG_27_16,
	PMIC_FG_IAVG_VLD,
	PMIC_FG_IAVG_15_00,
	PMIC_FG_IAVG_LTH_28_16,
	PMIC_FG_IAVG_LTH_15_00,
	PMIC_FG_IAVG_HTH_28_16,
	PMIC_FG_IAVG_HTH_15_00,
	PMIC_FG_NTER_29_16,
	PMIC_FG_NTER_15_00,
	PMIC_FG_TIME_HTH_29_16,
	PMIC_FG_TIME_HTH_15_00,
	PMIC_FG_OFFSET,
	PMIC_FG_ADJUST_OFFSET_VALUE,
	PMIC_FG_GAIN,
	PMIC_FG_SON_SLP_CUR_TH,
	PMIC_FG_SON_SLP_TIME,
	PMIC_FG_SON_DET_TIME,
	PMIC_FG_FP_FTIME,
	PMIC_FG_SOFF_SLP_CUR_TH,
	PMIC_FG_SOFF_SLP_TIME,
	PMIC_FG_SOFF_DET_TIME,
	PMIC_FG_SOFF_TIME_29_16,
	PMIC_FG_SOFF,
	PMIC_FG_SOFF_TIME_15_00,
	PMIC_FG_PWR_TIME0,
	PMIC_FG_PWR_TIME1,
	PMIC_FG_PWR_TIME2,
	PMIC_FG_ZCV_DET_IV,
	PMIC_FG_ZCV_CAR_TH_30_16,
	PMIC_FG_ZCV_CAR_TH_15_00,
	PMIC_FG_ZCV_CAR_31_16,
	PMIC_FG_ZCV_CAR_15_00,
	PMIC_FG_ZCV_CURR,
	PMIC_RG_FGANALOGTEST_3_1,
	PMIC_RG_FGRINTMODE,
	PMIC_RG_SPARE,
	PMIC_RG_FG_OFFSET_SWAP,
	PMIC_FG_MODE,
	PMIC_FG_RST_SW,
	PMIC_FG_FGCAL_EN_SW,
	PMIC_FG_FGADC_EN_SW,
	PMIC_FG_RNG_BIT_MODE,
	PMIC_FG_RNG_BIT_SW,
	PMIC_FG_RNG_EN_MODE,
	PMIC_FG_RNG_EN_SW,
	PMIC_FG_DWA_T0,
	PMIC_FG_DWA_T1,
	PMIC_FG_DWA_RST_MODE,
	PMIC_FG_DWA_RST_SW,
	PMIC_FG_DWA_RST,
	PMIC_FG_RSV_CON0_RSV,
	PMIC_FG_RSV_CON1_RSV,
	PMIC_FG_RSV_CON2_RSV,
	PMIC_FG_RSV_CON3_RSV,
	PMIC_SYSTEM_INFO_CON0,
	PMIC_SYSTEM_INFO_CON1,
	PMIC_SYSTEM_INFO_CON2,
	PMIC_SYSTEM_INFO_CON3,
	PMIC_SYSTEM_INFO_CON4,
	PMIC_RG_FGADC_GAINERROR_CAL,
	PMIC_AUXADC_ADC_OUT_CH0,
	PMIC_AUXADC_ADC_RDY_CH0,
	PMIC_AUXADC_ADC_OUT_CH1,
	PMIC_AUXADC_ADC_RDY_CH1,
	PMIC_AUXADC_ADC_OUT_CH2,
	PMIC_AUXADC_ADC_RDY_CH2,
	PMIC_AUXADC_ADC_OUT_CH3,
	PMIC_AUXADC_ADC_RDY_CH3,
	PMIC_AUXADC_ADC_OUT_CH4,
	PMIC_AUXADC_ADC_RDY_CH4,
	PMIC_AUXADC_ADC_OUT_CH5,
	PMIC_AUXADC_ADC_RDY_CH5,
	PMIC_AUXADC_ADC_OUT_CH6,
	PMIC_AUXADC_ADC_RDY_CH6,
	PMIC_AUXADC_ADC_OUT_CH7,
	PMIC_AUXADC_ADC_RDY_CH7,
	PMIC_AUXADC_ADC_OUT_CH8,
	PMIC_AUXADC_ADC_RDY_CH8,
	PMIC_AUXADC_ADC_OUT_CH9,
	PMIC_AUXADC_ADC_RDY_CH9,
	PMIC_AUXADC_ADC_OUT_CH10,
	PMIC_AUXADC_ADC_RDY_CH10,
	PMIC_AUXADC_ADC_OUT_CH11,
	PMIC_AUXADC_ADC_RDY_CH11,
	PMIC_AUXADC_ADC_OUT_CH12_15,
	PMIC_AUXADC_ADC_RDY_CH12_15,
	PMIC_AUXADC_ADC_OUT_THR_HW,
	PMIC_AUXADC_ADC_RDY_THR_HW,
	PMIC_AUXADC_ADC_OUT_LBAT,
	PMIC_AUXADC_ADC_RDY_LBAT,
	PMIC_AUXADC_ADC_OUT_LBAT2,
	PMIC_AUXADC_ADC_RDY_LBAT2,
	PMIC_AUXADC_ADC_OUT_CH7_BY_GPS,
	PMIC_AUXADC_ADC_RDY_CH7_BY_GPS,
	PMIC_AUXADC_ADC_OUT_CH7_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH7_BY_MD,
	PMIC_AUXADC_ADC_OUT_CH7_BY_AP,
	PMIC_AUXADC_ADC_RDY_CH7_BY_AP,
	PMIC_AUXADC_ADC_OUT_CH4_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH4_BY_MD,
	PMIC_AUXADC_ADC_OUT_PWRON_PCHR,
	PMIC_AUXADC_ADC_RDY_PWRON_PCHR,
	PMIC_AUXADC_ADC_OUT_PWRON_SWCHR,
	PMIC_AUXADC_ADC_RDY_PWRON_SWCHR,
	PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR,
	PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR,
	PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR,
	PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR,
	PMIC_AUXADC_ADC_OUT_CH0_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH0_BY_MD,
	PMIC_AUXADC_ADC_OUT_CH0_BY_AP,
	PMIC_AUXADC_ADC_RDY_CH0_BY_AP,
	PMIC_AUXADC_ADC_OUT_CH1_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH1_BY_MD,
	PMIC_AUXADC_ADC_OUT_CH1_BY_AP,
	PMIC_AUXADC_ADC_RDY_CH1_BY_AP,
	PMIC_AUXADC_ADC_OUT_BAT_TEMP,
	PMIC_AUXADC_ADC_RDY_BAT_TEMP,
	PMIC_AUXADC_ADC_OUT_FGADC_PCHR,
	PMIC_AUXADC_ADC_RDY_FGADC_PCHR,
	PMIC_AUXADC_ADC_OUT_FGADC_SWCHR,
	PMIC_AUXADC_ADC_RDY_FGADC_SWCHR,
	PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR,
	PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR,
	PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_SWCHR,
	PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_SWCHR,
	PMIC_AUXADC_ADC_OUT_IMP,
	PMIC_AUXADC_ADC_RDY_IMP,
	PMIC_AUXADC_ADC_OUT_IMP_AVG,
	PMIC_AUXADC_ADC_RDY_IMP_AVG,
	PMIC_AUXADC_ADC_OUT_RAW,
	PMIC_AUXADC_ADC_OUT_MDRT,
	PMIC_AUXADC_ADC_RDY_MDRT,
	PMIC_AUXADC_ADC_OUT_MDBG,
	PMIC_AUXADC_ADC_RDY_MDBG,
	PMIC_AUXADC_ADC_OUT_JEITA,
	PMIC_AUXADC_ADC_RDY_JEITA,
	PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS,
	PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS,
	PMIC_AUXADC_ADC_OUT_DCXO_BY_MD,
	PMIC_AUXADC_ADC_RDY_DCXO_BY_MD,
	PMIC_AUXADC_ADC_OUT_DCXO_BY_AP,
	PMIC_AUXADC_ADC_RDY_DCXO_BY_AP,
	PMIC_AUXADC_ADC_OUT_DCXO_MDRT,
	PMIC_AUXADC_ADC_RDY_DCXO_MDRT,
	PMIC_AUXADC_ADC_OUT_NAG,
	PMIC_AUXADC_ADC_RDY_NAG,
	PMIC_AUXADC_ADC_OUT_BATID,
	PMIC_AUXADC_ADC_RDY_BATID,
	PMIC_AUXADC_BUF_OUT_00,
	PMIC_AUXADC_BUF_RDY_00,
	PMIC_AUXADC_BUF_OUT_01,
	PMIC_AUXADC_BUF_RDY_01,
	PMIC_AUXADC_BUF_OUT_02,
	PMIC_AUXADC_BUF_RDY_02,
	PMIC_AUXADC_BUF_OUT_03,
	PMIC_AUXADC_BUF_RDY_03,
	PMIC_AUXADC_BUF_OUT_04,
	PMIC_AUXADC_BUF_RDY_04,
	PMIC_AUXADC_BUF_OUT_05,
	PMIC_AUXADC_BUF_RDY_05,
	PMIC_AUXADC_BUF_OUT_06,
	PMIC_AUXADC_BUF_RDY_06,
	PMIC_AUXADC_BUF_OUT_07,
	PMIC_AUXADC_BUF_RDY_07,
	PMIC_AUXADC_BUF_OUT_08,
	PMIC_AUXADC_BUF_RDY_08,
	PMIC_AUXADC_BUF_OUT_09,
	PMIC_AUXADC_BUF_RDY_09,
	PMIC_AUXADC_BUF_OUT_10,
	PMIC_AUXADC_BUF_RDY_10,
	PMIC_AUXADC_BUF_OUT_11,
	PMIC_AUXADC_BUF_RDY_11,
	PMIC_AUXADC_BUF_OUT_12,
	PMIC_AUXADC_BUF_RDY_12,
	PMIC_AUXADC_BUF_OUT_13,
	PMIC_AUXADC_BUF_RDY_13,
	PMIC_AUXADC_BUF_OUT_14,
	PMIC_AUXADC_BUF_RDY_14,
	PMIC_AUXADC_BUF_OUT_15,
	PMIC_AUXADC_BUF_RDY_15,
	PMIC_AUXADC_BUF_OUT_16,
	PMIC_AUXADC_BUF_RDY_16,
	PMIC_AUXADC_BUF_OUT_17,
	PMIC_AUXADC_BUF_RDY_17,
	PMIC_AUXADC_BUF_OUT_18,
	PMIC_AUXADC_BUF_RDY_18,
	PMIC_AUXADC_BUF_OUT_19,
	PMIC_AUXADC_BUF_RDY_19,
	PMIC_AUXADC_BUF_OUT_20,
	PMIC_AUXADC_BUF_RDY_20,
	PMIC_AUXADC_BUF_OUT_21,
	PMIC_AUXADC_BUF_RDY_21,
	PMIC_AUXADC_BUF_OUT_22,
	PMIC_AUXADC_BUF_RDY_22,
	PMIC_AUXADC_BUF_OUT_23,
	PMIC_AUXADC_BUF_RDY_23,
	PMIC_AUXADC_BUF_OUT_24,
	PMIC_AUXADC_BUF_RDY_24,
	PMIC_AUXADC_BUF_OUT_25,
	PMIC_AUXADC_BUF_RDY_25,
	PMIC_AUXADC_BUF_OUT_26,
	PMIC_AUXADC_BUF_RDY_26,
	PMIC_AUXADC_BUF_OUT_27,
	PMIC_AUXADC_BUF_RDY_27,
	PMIC_AUXADC_BUF_OUT_28,
	PMIC_AUXADC_BUF_RDY_28,
	PMIC_AUXADC_BUF_OUT_29,
	PMIC_AUXADC_BUF_RDY_29,
	PMIC_AUXADC_BUF_OUT_30,
	PMIC_AUXADC_BUF_RDY_30,
	PMIC_AUXADC_BUF_OUT_31,
	PMIC_AUXADC_BUF_RDY_31,
	PMIC_AUXADC_ADC_BUSY_IN,
	PMIC_AUXADC_ADC_BUSY_IN_LBAT,
	PMIC_AUXADC_ADC_BUSY_IN_LBAT2,
	PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP,
	PMIC_AUXADC_ADC_BUSY_IN_WAKEUP,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS,
	PMIC_AUXADC_ADC_BUSY_IN_JEITA,
	PMIC_AUXADC_ADC_BUSY_IN_MDRT,
	PMIC_AUXADC_ADC_BUSY_IN_MDBG,
	PMIC_AUXADC_ADC_BUSY_IN_SHARE,
	PMIC_AUXADC_ADC_BUSY_IN_IMP,
	PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR,
	PMIC_AUXADC_ADC_BUSY_IN_FGADC_SWCHR,
	PMIC_AUXADC_ADC_BUSY_IN_GPS_AP,
	PMIC_AUXADC_ADC_BUSY_IN_GPS_MD,
	PMIC_AUXADC_ADC_BUSY_IN_GPS,
	PMIC_AUXADC_ADC_BUSY_IN_THR_HW,
	PMIC_AUXADC_ADC_BUSY_IN_THR_MD,
	PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR,
	PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_SWCHR,
	PMIC_AUXADC_ADC_BUSY_IN_BATID,
	PMIC_AUXADC_ADC_BUSY_IN_PWRON,
	PMIC_AUXADC_ADC_BUSY_IN_NAG,
	PMIC_AUXADC_RQST_CH0,
	PMIC_AUXADC_RQST_CH1,
	PMIC_AUXADC_RQST_CH2,
	PMIC_AUXADC_RQST_CH3,
	PMIC_AUXADC_RQST_CH4,
	PMIC_AUXADC_RQST_CH5,
	PMIC_AUXADC_RQST_CH6,
	PMIC_AUXADC_RQST_CH7,
	PMIC_AUXADC_RQST_CH8,
	PMIC_AUXADC_RQST_CH9,
	PMIC_AUXADC_RQST_CH10,
	PMIC_AUXADC_RQST_CH11,
	PMIC_AUXADC_RQST_CH12,
	PMIC_AUXADC_RQST_CH13,
	PMIC_AUXADC_RQST_CH14,
	PMIC_AUXADC_RQST_CH15,
	PMIC_AUXADC_RQST0_SET,
	PMIC_AUXADC_RQST0_CLR,
	PMIC_AUXADC_RQST_CH0_BY_MD,
	PMIC_AUXADC_RQST_CH1_BY_MD,
	PMIC_AUXADC_RQST_RSV0,
	PMIC_AUXADC_RQST_BATID,
	PMIC_AUXADC_RQST_CH4_BY_MD,
	PMIC_AUXADC_RQST_CH7_BY_MD,
	PMIC_AUXADC_RQST_CH7_BY_GPS,
	PMIC_AUXADC_RQST_DCXO_BY_MD,
	PMIC_AUXADC_RQST_DCXO_BY_GPS,
	PMIC_AUXADC_RQST_RSV1,
	PMIC_AUXADC_RQST1_SET,
	PMIC_AUXADC_RQST1_CLR,
	PMIC_AUXADC_CK_ON_EXTD,
	PMIC_AUXADC_SRCLKEN_SRC_SEL,
	PMIC_AUXADC_ADC_PWDB,
	PMIC_AUXADC_ADC_PWDB_SWCTRL,
	PMIC_AUXADC_STRUP_CK_ON_ENB,
	PMIC_AUXADC_SRCLKEN_CK_EN,
	PMIC_AUXADC_CK_AON_GPS,
	PMIC_AUXADC_CK_AON_MD,
	PMIC_AUXADC_CK_AON,
	PMIC_AUXADC_CON0_SET,
	PMIC_AUXADC_CON0_CLR,
	PMIC_AUXADC_AVG_NUM_SMALL,
	PMIC_AUXADC_AVG_NUM_LARGE,
	PMIC_AUXADC_SPL_NUM,
	PMIC_AUXADC_AVG_NUM_SEL,
	PMIC_AUXADC_AVG_NUM_SEL_SHARE,
	PMIC_AUXADC_AVG_NUM_SEL_LBAT,
	PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP,
	PMIC_AUXADC_AVG_NUM_SEL_WAKEUP,
	PMIC_AUXADC_SPL_NUM_LARGE,
	PMIC_AUXADC_SPL_NUM_SLEEP,
	PMIC_AUXADC_SPL_NUM_SLEEP_SEL,
	PMIC_AUXADC_SPL_NUM_SEL,
	PMIC_AUXADC_SPL_NUM_SEL_SHARE,
	PMIC_AUXADC_SPL_NUM_SEL_LBAT,
	PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP,
	PMIC_AUXADC_SPL_NUM_SEL_WAKEUP,
	PMIC_AUXADC_SPL_NUM_CH0,
	PMIC_AUXADC_SPL_NUM_CH3,
	PMIC_AUXADC_SPL_NUM_CH7,
	PMIC_AUXADC_AVG_NUM_LBAT,
	PMIC_AUXADC_AVG_NUM_CH7,
	PMIC_AUXADC_AVG_NUM_CH3,
	PMIC_AUXADC_AVG_NUM_CH0,
	PMIC_AUXADC_AVG_NUM_HPC,
	PMIC_AUXADC_AVG_NUM_DCXO,
	PMIC_AUXADC_TRIM_CH0_SEL,
	PMIC_AUXADC_TRIM_CH1_SEL,
	PMIC_AUXADC_TRIM_CH2_SEL,
	PMIC_AUXADC_TRIM_CH3_SEL,
	PMIC_AUXADC_TRIM_CH4_SEL,
	PMIC_AUXADC_TRIM_CH5_SEL,
	PMIC_AUXADC_TRIM_CH6_SEL,
	PMIC_AUXADC_TRIM_CH7_SEL,
	PMIC_AUXADC_TRIM_CH8_SEL,
	PMIC_AUXADC_TRIM_CH9_SEL,
	PMIC_AUXADC_TRIM_CH10_SEL,
	PMIC_AUXADC_TRIM_CH11_SEL,
	PMIC_AUXADC_ADC_2S_COMP_ENB,
	PMIC_AUXADC_ADC_TRIM_COMP,
	PMIC_AUXADC_SW_GAIN_TRIM,
	PMIC_AUXADC_SW_OFFSET_TRIM,
	PMIC_AUXADC_RNG_EN,
	PMIC_AUXADC_TEST_MODE,
	PMIC_AUXADC_BIT_SEL,
	PMIC_AUXADC_START_SW,
	PMIC_AUXADC_START_SWCTRL,
	PMIC_AUXADC_TS_VBE_SEL,
	PMIC_AUXADC_TS_VBE_SEL_SWCTRL,
	PMIC_AUXADC_VBUF_EN,
	PMIC_AUXADC_VBUF_EN_SWCTRL,
	PMIC_AUXADC_OUT_SEL,
	PMIC_AUXADC_DA_DAC,
	PMIC_AUXADC_DA_DAC_SWCTRL,
	PMIC_AD_AUXADC_COMP,
	PMIC_RG_AUXADC_CALI,
	PMIC_RG_AUX_RSV,
	PMIC_RG_VBUF_BYP,
	PMIC_RG_VBUF_CALEN,
	PMIC_RG_VBUF_EXTEN,
	PMIC_AUXADC_ADCIN_VSEN_EN,
	PMIC_AUXADC_ADCIN_VBAT_EN,
	PMIC_AUXADC_ADCIN_VSEN_MUX_EN,
	PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN,
	PMIC_AUXADC_ADCIN_CHR_EN,
	PMIC_AUXADC_ADCIN_BATON_TDET_EN,
	PMIC_AUXADC_ACCDET_ANASWCTRL_EN,
	PMIC_AUXADC_XO_THADC_EN,
	PMIC_AUXADC_ADCIN_BATID_SW_EN,
	PMIC_AUXADC_DIG0_RSV0,
	PMIC_AUXADC_CHSEL,
	PMIC_AUXADC_SWCTRL_EN,
	PMIC_AUXADC_SOURCE_LBAT_SEL,
	PMIC_AUXADC_SOURCE_LBAT2_SEL,
	PMIC_AUXADC_START_EXTD,
	PMIC_AUXADC_DAC_EXTD,
	PMIC_AUXADC_DAC_EXTD_EN,
	PMIC_AUXADC_PMU_THR_PDN_SW,
	PMIC_AUXADC_PMU_THR_PDN_SEL,
	PMIC_AUXADC_PMU_THR_PDN_STATUS,
	PMIC_AUXADC_DIG0_RSV1,
	PMIC_AUXADC_START_SHADE_NUM,
	PMIC_AUXADC_START_SHADE_EN,
	PMIC_AUXADC_START_SHADE_SEL,
	PMIC_AUXADC_ADC_RDY_WAKEUP_CLR,
	PMIC_AUXADC_ADC_RDY_FGADC_CLR,
	PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR,
	PMIC_AUXADC_ADC_RDY_PWRON_CLR,
	PMIC_AUXADC_DATA_REUSE_SEL,
	PMIC_AUXADC_CH0_DATA_REUSE_SEL,
	PMIC_AUXADC_CH1_DATA_REUSE_SEL,
	PMIC_AUXADC_DCXO_DATA_REUSE_SEL,
	PMIC_AUXADC_DATA_REUSE_EN,
	PMIC_AUXADC_CH0_DATA_REUSE_EN,
	PMIC_AUXADC_CH1_DATA_REUSE_EN,
	PMIC_AUXADC_DCXO_DATA_REUSE_EN,
	PMIC_AUXADC_AUTORPT_PRD,
	PMIC_AUXADC_AUTORPT_EN,
	PMIC_AUXADC_LBAT_DEBT_MAX,
	PMIC_AUXADC_LBAT_DEBT_MIN,
	PMIC_AUXADC_LBAT_DET_PRD_15_0,
	PMIC_AUXADC_LBAT_DET_PRD_19_16,
	PMIC_AUXADC_LBAT_VOLT_MAX,
	PMIC_AUXADC_LBAT_IRQ_EN_MAX,
	PMIC_AUXADC_LBAT_EN_MAX,
	PMIC_AUXADC_LBAT_MAX_IRQ_B,
	PMIC_AUXADC_LBAT_VOLT_MIN,
	PMIC_AUXADC_LBAT_IRQ_EN_MIN,
	PMIC_AUXADC_LBAT_EN_MIN,
	PMIC_AUXADC_LBAT_MIN_IRQ_B,
	PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN,
	PMIC_AUXADC_ACCDET_AUTO_SPL,
	PMIC_AUXADC_ACCDET_AUTO_RQST_CLR,
	PMIC_AUXADC_ACCDET_DIG1_RSV0,
	PMIC_AUXADC_ACCDET_DIG0_RSV0,
	PMIC_AUXADC_THR_DEBT_MAX,
	PMIC_AUXADC_THR_DEBT_MIN,
	PMIC_AUXADC_THR_DET_PRD_15_0,
	PMIC_AUXADC_THR_DET_PRD_19_16,
	PMIC_AUXADC_THR_VOLT_MAX,
	PMIC_AUXADC_THR_IRQ_EN_MAX,
	PMIC_AUXADC_THR_EN_MAX,
	PMIC_AUXADC_THR_MAX_IRQ_B,
	PMIC_AUXADC_THR_VOLT_MIN,
	PMIC_AUXADC_THR_IRQ_EN_MIN,
	PMIC_AUXADC_THR_EN_MIN,
	PMIC_AUXADC_THR_MIN_IRQ_B,
	PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN,
	PMIC_EFUSE_GAIN_CH4_TRIM,
	PMIC_EFUSE_OFFSET_CH4_TRIM,
	PMIC_EFUSE_GAIN_CH0_TRIM,
	PMIC_EFUSE_OFFSET_CH0_TRIM,
	PMIC_EFUSE_GAIN_CH7_TRIM,
	PMIC_EFUSE_OFFSET_CH7_TRIM,
	PMIC_AUXADC_FGADC_START_SW,
	PMIC_AUXADC_FGADC_START_SEL,
	PMIC_AUXADC_FGADC_R_SW,
	PMIC_AUXADC_FGADC_R_SEL,
	PMIC_AUXADC_BAT_PLUGIN_START_SW,
	PMIC_AUXADC_BAT_PLUGIN_START_SEL,
	PMIC_AUXADC_DBG_DIG0_RSV2,
	PMIC_AUXADC_DBG_DIG1_RSV2,
	PMIC_AUXADC_IMPEDANCE_CNT,
	PMIC_AUXADC_IMPEDANCE_CHSEL,
	PMIC_AUXADC_IMPEDANCE_IRQ_CLR,
	PMIC_AUXADC_IMPEDANCE_IRQ_STATUS,
	PMIC_AUXADC_CLR_IMP_CNT_STOP,
	PMIC_AUXADC_IMPEDANCE_MODE,
	PMIC_AUXADC_IMP_AUTORPT_PRD,
	PMIC_AUXADC_IMP_AUTORPT_EN,
	PMIC_AUXADC_BAT_TEMP_FROZE_EN,
	PMIC_AUXADC_BAT_TEMP_DEBT_MAX,
	PMIC_AUXADC_BAT_TEMP_DEBT_MIN,
	PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0,
	PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16,
	PMIC_AUXADC_BAT_TEMP_VOLT_MAX,
	PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX,
	PMIC_AUXADC_BAT_TEMP_EN_MAX,
	PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B,
	PMIC_AUXADC_BAT_TEMP_VOLT_MIN,
	PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN,
	PMIC_AUXADC_BAT_TEMP_EN_MIN,
	PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B,
	PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN,
	PMIC_AUXADC_LBAT2_DEBT_MAX,
	PMIC_AUXADC_LBAT2_DEBT_MIN,
	PMIC_AUXADC_LBAT2_DET_PRD_15_0,
	PMIC_AUXADC_LBAT2_DET_PRD_19_16,
	PMIC_AUXADC_LBAT2_VOLT_MAX,
	PMIC_AUXADC_LBAT2_IRQ_EN_MAX,
	PMIC_AUXADC_LBAT2_EN_MAX,
	PMIC_AUXADC_LBAT2_MAX_IRQ_B,
	PMIC_AUXADC_LBAT2_VOLT_MIN,
	PMIC_AUXADC_LBAT2_IRQ_EN_MIN,
	PMIC_AUXADC_LBAT2_EN_MIN,
	PMIC_AUXADC_LBAT2_MIN_IRQ_B,
	PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN,
	PMIC_AUXADC_MDBG_DET_PRD,
	PMIC_AUXADC_MDBG_DET_EN,
	PMIC_AUXADC_MDBG_R_PTR,
	PMIC_AUXADC_MDBG_W_PTR,
	PMIC_AUXADC_MDBG_BUF_LENGTH,
	PMIC_AUXADC_MDRT_DET_PRD,
	PMIC_AUXADC_MDRT_DET_EN,
	PMIC_AUXADC_MDRT_DET_WKUP_START_CNT,
	PMIC_AUXADC_MDRT_DET_WKUP_START_CLR,
	PMIC_AUXADC_MDRT_DET_WKUP_START,
	PMIC_AUXADC_MDRT_DET_WKUP_START_SEL,
	PMIC_AUXADC_MDRT_DET_WKUP_EN,
	PMIC_AUXADC_MDRT_DET_SRCLKEN_IND,
	PMIC_AUXADC_MDRT_DET_RDY_ST_PRD,
	PMIC_AUXADC_MDRT_DET_RDY_ST_EN,
	PMIC_AUXADC_MDRT_DET_START_SEL,
	PMIC_AUXADC_JEITA_IRQ_EN,
	PMIC_AUXADC_JEITA_EN,
	PMIC_AUXADC_JEITA_DET_PRD,
	PMIC_AUXADC_JEITA_DEBT,
	PMIC_AUXADC_JEITA_MIPI_DIS,
	PMIC_AUXADC_JEITA_FROZE_EN,
	PMIC_AUXADC_JEITA_VOLT_HOT,
	PMIC_AUXADC_JEITA_HOT_IRQ,
	PMIC_AUXADC_JEITA_VOLT_WARM,
	PMIC_AUXADC_JEITA_WARM_IRQ,
	PMIC_AUXADC_JEITA_VOLT_COOL,
	PMIC_AUXADC_JEITA_COOL_IRQ,
	PMIC_AUXADC_JEITA_VOLT_COLD,
	PMIC_AUXADC_JEITA_COLD_IRQ,
	PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COLD,
	PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_COOL,
	PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_WARM,
	PMIC_AUXADC_JEITA_DEBOUNCE_COUNT_HOT,
	PMIC_AUXADC_DCXO_MDRT_DET_PRD,
	PMIC_AUXADC_DCXO_MDRT_DET_EN,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START,
	PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND,
	PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL,
	PMIC_AUXADC_NAG_EN,
	PMIC_AUXADC_NAG_CLR,
	PMIC_AUXADC_NAG_VBAT1_SEL,
	PMIC_AUXADC_NAG_PRD,
	PMIC_AUXADC_NAG_IRQ_EN,
	PMIC_AUXADC_NAG_C_DLTV_IRQ,
	PMIC_AUXADC_NAG_ZCV,
	PMIC_AUXADC_NAG_C_DLTV_TH_15_0,
	PMIC_AUXADC_NAG_C_DLTV_TH_26_16,
	PMIC_AUXADC_NAG_CNT_15_0,
	PMIC_AUXADC_NAG_CNT_25_16,
	PMIC_AUXADC_NAG_DLTV,
	PMIC_AUXADC_NAG_C_DLTV_15_0,
	PMIC_AUXADC_NAG_C_DLTV_26_16,
	PMIC_AUXADC_EFUSE_DEGC_CALI,
	PMIC_AUXADC_EFUSE_ADC_CALI_EN,
	PMIC_AUXADC_EFUSE_1RSV0,
	PMIC_AUXADC_EFUSE_O_VTS,
	PMIC_AUXADC_EFUSE_2RSV0,
	PMIC_AUXADC_EFUSE_O_SLOPE,
	PMIC_AUXADC_EFUSE_O_SLOPE_SIGN,
	PMIC_AUXADC_EFUSE_3RSV0,
	PMIC_AUXADC_EFUSE_AUXADC_RSV,
	PMIC_AUXADC_EFUSE_ID,
	PMIC_AUXADC_EFUSE_4RSV0,
	PMIC_AUXADC_RSV_1RSV0,
	PMIC_DA_ADCIN_VBAT_EN,
	PMIC_DA_AUXADC_VBAT_EN,
	PMIC_DA_ADCIN_VSEN_MUX_EN,
	PMIC_DA_ADCIN_VSEN_EN,
	PMIC_DA_ADCIN_CHR_EN,
	PMIC_DA_BATON_TDET_EN,
	PMIC_DA_ADCIN_BATID_SW_EN,
	PMIC_RG_AUXADC_IMP_CK_SW_MODE,
	PMIC_RG_AUXADC_IMP_CK_SW_EN,
	PMIC_RG_AUXADC_LBAT_CK_SW_MODE,
	PMIC_RG_AUXADC_LBAT_CK_SW_EN,
	PMIC_RG_AUXADC_THR_CK_SW_MODE,
	PMIC_RG_AUXADC_THR_CK_SW_EN,
	PMIC_RG_AUXADC_BAT_TEMP_CK_SW_MODE,
	PMIC_RG_AUXADC_BAT_TEMP_CK_SW_EN,
	PMIC_RG_AUXADC_LBAT2_CK_SW_MODE,
	PMIC_RG_AUXADC_LBAT2_CK_SW_EN,
	PMIC_RG_AUXADC_JEITA_CK_SW_MODE,
	PMIC_RG_AUXADC_JEITA_CK_SW_EN,
	PMIC_RG_AUXADC_NAG_CK_SW_MODE,
	PMIC_RG_AUXADC_NAG_CK_SW_EN,
	PMIC_RG_AUXADC_NEW_PRIORITY_LIST_SEL,
	PMIC_RG_ISINK_TRIM_EN,
	PMIC_RG_ISINK_TRIM_SEL,
	PMIC_RG_ISINK_TRIM_BIAS,
	PMIC_RG_ISINK_RSV,
	PMIC_RG_ISINK0_CHOP_EN,
	PMIC_RG_ISINK1_CHOP_EN,
	PMIC_RG_ISINK2_CHOP_EN,
	PMIC_RG_ISINK3_CHOP_EN,
	PMIC_RG_ISINK0_DOUBLE,
	PMIC_RG_ISINK1_DOUBLE,
	PMIC_RG_ISINK2_DOUBLE,
	PMIC_RG_ISINK3_DOUBLE,
	PMIC_ISINK0_RSV1,
	PMIC_ISINK0_RSV0,
	PMIC_ISINK_CH0_STEP,
	PMIC_ISINK1_RSV1,
	PMIC_ISINK1_RSV0,
	PMIC_ISINK_CH1_STEP,
	PMIC_ISINK2_RSV1,
	PMIC_ISINK2_RSV0,
	PMIC_ISINK_CH2_STEP,
	PMIC_ISINK3_RSV1,
	PMIC_ISINK3_RSV0,
	PMIC_ISINK_CH3_STEP,
	PMIC_AD_NI_ISINK0_STATUS,
	PMIC_AD_NI_ISINK1_STATUS,
	PMIC_AD_NI_ISINK2_STATUS,
	PMIC_AD_NI_ISINK3_STATUS,
	PMIC_ISINK_CH3_EN,
	PMIC_ISINK_CH2_EN,
	PMIC_ISINK_CH1_EN,
	PMIC_ISINK_CH0_EN,
	PMIC_ISINK_CHOP3_EN,
	PMIC_ISINK_CHOP2_EN,
	PMIC_ISINK_CHOP1_EN,
	PMIC_ISINK_CHOP0_EN,
	PMIC_ISINK_CH3_BIAS_EN,
	PMIC_ISINK_CH2_BIAS_EN,
	PMIC_ISINK_CH1_BIAS_EN,
	PMIC_ISINK_CH0_BIAS_EN,
	PMIC_RG_AUDDACLPWRUP_VAUDP32,
	PMIC_RG_AUDDACRPWRUP_VAUDP32,
	PMIC_RG_AUD_DAC_PWR_UP_VA32,
	PMIC_RG_AUD_DAC_PWL_UP_VA32,
	PMIC_RG_AUDHPLPWRUP_VAUDP32,
	PMIC_RG_AUDHPRPWRUP_VAUDP32,
	PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP32,
	PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP32,
	PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP32,
	PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP32,
	PMIC_RG_AUDHPLSCDISABLE_VAUDP32,
	PMIC_RG_AUDHPRSCDISABLE_VAUDP32,
	PMIC_RG_AUDHPLBSCCURRENT_VAUDP32,
	PMIC_RG_AUDHPRBSCCURRENT_VAUDP32,
	PMIC_RG_AUDHPLOUTPWRUP_VAUDP32,
	PMIC_RG_AUDHPROUTPWRUP_VAUDP32,
	PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP32,
	PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP32,
	PMIC_RG_HPLAUXFBRSW_EN_VAUDP32,
	PMIC_RG_HPRAUXFBRSW_EN_VAUDP32,
	PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP32,
	PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP32,
	PMIC_RG_HPLOUTSTGCTRL_VAUDP32,
	PMIC_RG_HPROUTSTGCTRL_VAUDP32,
	PMIC_RG_HPLOUTPUTSTBENH_VAUDP32,
	PMIC_RG_HPROUTPUTSTBENH_VAUDP32,
	PMIC_RG_AUDHPSTARTUP_VAUDP32,
	PMIC_RG_AUDREFN_DERES_EN_VAUDP32,
	PMIC_RG_HPPSHORT2VCM_VAUDP32,
	PMIC_RG_AUDHPLTRIM_VAUDP32,
	PMIC_RG_AUDHPRTRIM_VAUDP32,
	PMIC_RG_AUDHPLFINETRIM_VAUDP32,
	PMIC_RG_AUDHPRFINETRIM_VAUDP32,
	PMIC_RG_AUDHPTRIM_EN_VAUDP32,
	PMIC_RG_HPINPUTSTBENH_VAUDP32,
	PMIC_RG_HPINPUTRESET0_VAUDP32,
	PMIC_RG_HPOUTPUTRESET0_VAUDP32,
	PMIC_RG_AUDHPDIFFINPBIASADJ_VAUDP32,
	PMIC_RG_AUDHPLFCOMPRESSEL_VAUDP32,
	PMIC_RG_AUDHPHFCOMPRESSEL_VAUDP32,
	PMIC_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32,
	PMIC_RG_AUDHPCOMP_EN_VAUDP32,
	PMIC_RG_AUDHPDECMGAINADJ_VAUDP32,
	PMIC_RG_AUDHPDEDMGAINADJ_VAUDP32,
	PMIC_RG_AUDHSPWRUP_VAUDP32,
	PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP32,
	PMIC_RG_AUDHSMUXINPUTSEL_VAUDP32,
	PMIC_RG_AUDHSSCDISABLE_VAUDP32,
	PMIC_RG_AUDHSBSCCURRENT_VAUDP32,
	PMIC_RG_AUDHSSTARTUP_VAUDP32,
	PMIC_RG_HSOUTPUTSTBENH_VAUDP32,
	PMIC_RG_HSINPUTSTBENH_VAUDP32,
	PMIC_RG_HSINPUTRESET0_VAUDP32,
	PMIC_RG_HSOUTPUTRESET0_VAUDP32,
	PMIC_RG_HSOUT_SHORTVCM_VAUDP32,
	PMIC_RG_AUDLOLPWRUP_VAUDP32,
	PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP32,
	PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP32,
	PMIC_RG_AUDLOLSCDISABLE_VAUDP32,
	PMIC_RG_AUDLOLBSCCURRENT_VAUDP32,
	PMIC_RG_AUDLOSTARTUP_VAUDP32,
	PMIC_RG_LOINPUTSTBENH_VAUDP32,
	PMIC_RG_LOOUTPUTSTBENH_VAUDP32,
	PMIC_RG_LOINPUTRESET0_VAUDP32,
	PMIC_RG_LOOUTPUTRESET0_VAUDP32,
	PMIC_RG_LOOUT_SHORTVCM_VAUDP32,
	PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32,
	PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP32,
	PMIC_RG_AUDTRIMBUF_EN_VAUDP32,
	PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32,
	PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32,
	PMIC_RG_AUDHPSPKDET_EN_VAUDP32,
	PMIC_RG_ABIDEC_RSVD0_VA32,
	PMIC_RG_ABIDEC_RSVD0_VAUDP32,
	PMIC_RG_ABIDEC_RSVD1_VAUDP32,
	PMIC_RG_ABIDEC_RSVD2_VAUDP32,
	PMIC_RG_AUDZCDMUXSEL_VAUDP32,
	PMIC_RG_AUDZCDCLKSEL_VAUDP32,
	PMIC_RG_AUDBIASADJ_0_VAUDP32,
	PMIC_RG_AUDBIASADJ_1_VAUDP32,
	PMIC_RG_AUDIBIASPWRDN_VAUDP32,
	PMIC_RG_RSTB_DECODER_VA32,
	PMIC_RG_SEL_DECODER_96K_VA32,
	PMIC_RG_SEL_DELAY_VCORE,
	PMIC_RG_AUDGLB_PWRDN_VA32,
	PMIC_RG_AUDGLB_LP_VOW_EN_VA32,
	PMIC_RG_AUDGLB_LP2_VOW_EN_VA32,
	PMIC_RG_LCLDO_DEC_EN_VA32,
	PMIC_RG_LCLDO_DEC_PDDIS_EN_VA18,
	PMIC_RG_LCLDO_DEC_REMOTE_SENSE_VA18,
	PMIC_RG_NVREG_EN_VAUDP32,
	PMIC_RG_NVREG_PULL0V_VAUDP32,
	PMIC_RG_AUDPMU_RSVD_VA18,
	PMIC_RG_AUDPREAMPLON,
	PMIC_RG_AUDPREAMPLDCCEN,
	PMIC_RG_AUDPREAMPLDCPRECHARGE,
	PMIC_RG_AUDPREAMPLPGATEST,
	PMIC_RG_AUDPREAMPLVSCALE,
	PMIC_RG_AUDPREAMPLINPUTSEL,
	PMIC_RG_AUDPREAMPLGAIN,
	PMIC_RG_BULKL_VCM_EN,
	PMIC_RG_AUDADCLPWRUP,
	PMIC_RG_AUDADCLINPUTSEL,
	PMIC_RG_AUDPREAMPRON,
	PMIC_RG_AUDPREAMPRDCCEN,
	PMIC_RG_AUDPREAMPRDCPRECHARGE,
	PMIC_RG_AUDPREAMPRPGATEST,
	PMIC_RG_AUDPREAMPRVSCALE,
	PMIC_RG_AUDPREAMPRINPUTSEL,
	PMIC_RG_AUDPREAMPRGAIN,
	PMIC_RG_BULKR_VCM_EN,
	PMIC_RG_AUDADCRPWRUP,
	PMIC_RG_AUDADCRINPUTSEL,
	PMIC_RG_AUDULHALFBIAS,
	PMIC_RG_AUDGLBVOWLPWEN,
	PMIC_RG_AUDPREAMPLPEN,
	PMIC_RG_AUDADC1STSTAGELPEN,
	PMIC_RG_AUDADC2NDSTAGELPEN,
	PMIC_RG_AUDADCFLASHLPEN,
	PMIC_RG_AUDPREAMPIDDTEST,
	PMIC_RG_AUDADC1STSTAGEIDDTEST,
	PMIC_RG_AUDADC2NDSTAGEIDDTEST,
	PMIC_RG_AUDADCREFBUFIDDTEST,
	PMIC_RG_AUDADCFLASHIDDTEST,
	PMIC_RG_AUDADCCLKRSTB,
	PMIC_RG_AUDADCCLKSEL,
	PMIC_RG_AUDADCCLKSOURCE,
	PMIC_RG_AUDADCCLKGENMODE,
	PMIC_RG_AUDADCDAC0P25FS,
	PMIC_RG_AUDPREAMPAAFEN,
	PMIC_RG_DCCVCMBUFLPMODSEL,
	PMIC_RG_DCCVCMBUFLPSWEN,
	PMIC_RG_AUDSPAREPGA,
	PMIC_RG_AUDADC1STSTAGESDENB,
	PMIC_RG_AUDADC2NDSTAGERESET,
	PMIC_RG_AUDADC3RDSTAGERESET,
	PMIC_RG_AUDADCFSRESET,
	PMIC_RG_AUDADCWIDECM,
	PMIC_RG_AUDADCNOPATEST,
	PMIC_RG_AUDADCBYPASS,
	PMIC_RG_AUDADCFFBYPASS,
	PMIC_RG_AUDADCDACFBCURRENT,
	PMIC_RG_AUDADCDACIDDTEST,
	PMIC_RG_AUDADCDACNRZ,
	PMIC_RG_AUDADCNODEM,
	PMIC_RG_AUDADCDACTEST,
	PMIC_RG_AUDADCTESTDATA,
	PMIC_RG_AUDRCTUNEL,
	PMIC_RG_AUDRCTUNELSEL,
	PMIC_RG_AUDRCTUNER,
	PMIC_RG_AUDRCTUNERSEL,
	PMIC_RGS_AUDRCTUNELREAD,
	PMIC_RGS_AUDRCTUNERREAD,
	PMIC_RG_AUDSPAREVA30,
	PMIC_RG_AUDSPAREVA18,
	PMIC_RG_AUDDIGMICEN,
	PMIC_RG_AUDDIGMICBIAS,
	PMIC_RG_DMICHPCLKEN,
	PMIC_RG_AUDDIGMICPDUTY,
	PMIC_RG_AUDDIGMICNDUTY,
	PMIC_RG_DMICMONEN,
	PMIC_RG_DMICMONSEL,
	PMIC_RG_AUDSPAREVMIC,
	PMIC_RG_AUDPWDBMICBIAS0,
	PMIC_RG_AUDMICBIAS0DCSW0P1EN,
	PMIC_RG_AUDMICBIAS0DCSW0P2EN,
	PMIC_RG_AUDMICBIAS0DCSW0NEN,
	PMIC_RG_AUDMICBIAS0VREF,
	PMIC_RG_AUDMICBIAS0LOWPEN,
	PMIC_RG_AUDPWDBMICBIAS2,
	PMIC_RG_AUDMICBIAS0DCSW2P1EN,
	PMIC_RG_AUDMICBIAS0DCSW2P2EN,
	PMIC_RG_AUDMICBIAS0DCSW2NEN,
	PMIC_RG_AUDPWDBMICBIAS1,
	PMIC_RG_AUDMICBIAS1DCSW1PEN,
	PMIC_RG_AUDMICBIAS1DCSW1NEN,
	PMIC_RG_AUDMICBIAS1VREF,
	PMIC_RG_AUDMICBIAS1LOWPEN,
	PMIC_RG_AUDMICBIAS1HVEN,
	PMIC_RG_AUDMICBIAS1HVVREF,
	PMIC_RG_BANDGAPGEN,
	PMIC_RG_AUDACCDETMICBIAS0PULLLOW,
	PMIC_RG_AUDACCDETMICBIAS1PULLLOW,
	PMIC_RG_AUDACCDETMICBIAS2PULLLOW,
	PMIC_RG_AUDACCDETVIN1PULLLOW,
	PMIC_RG_EINTHIRENB,
	PMIC_RG_AUDACCDETVTHACAL,
	PMIC_RG_AUDACCDETVTHBCAL,
	PMIC_RG_AUDACCDETTVDET,
	PMIC_RG_ACCDETSEL,
	PMIC_RG_SWBUFMODSEL,
	PMIC_RG_SWBUFSWEN,
	PMIC_RG_EINTCOMPVTH,
	PMIC_RG_EINTCONFIGACCDET,
	PMIC_RG_ACCDETSPAREVA30,
	PMIC_RG_AUDENCSPAREVA30,
	PMIC_RG_AUDENCSPAREVA18,
	PMIC_RG_PLL_EN,
	PMIC_RG_PLLBS_RST,
	PMIC_RG_PLL_DCKO_SEL,
	PMIC_RG_PLL_DIV1,
	PMIC_RG_PLL_RLATCH_EN,
	PMIC_RG_PLL_PDIV1_EN,
	PMIC_RG_PLL_PDIV1,
	PMIC_RG_PLL_BC,
	PMIC_RG_PLL_BP,
	PMIC_RG_PLL_BR,
	PMIC_RG_CKO_SEL,
	PMIC_RG_PLL_IBSEL,
	PMIC_RG_PLL_CKT_SEL,
	PMIC_RG_PLL_VCT_EN,
	PMIC_RG_PLL_CKT_EN,
	PMIC_RG_PLL_HPM_EN,
	PMIC_RG_PLL_DCHP_EN,
	PMIC_RG_PLL_CDIV,
	PMIC_RG_VCOBAND,
	PMIC_RG_CKDRV_EN,
	PMIC_RG_PLL_DCHP_AEN,
	PMIC_RG_PLL_RSVA,
	PMIC_RG_AUDZCDENABLE,
	PMIC_RG_AUDZCDGAINSTEPTIME,
	PMIC_RG_AUDZCDGAINSTEPSIZE,
	PMIC_RG_AUDZCDTIMEOUTMODESEL,
	PMIC_RG_AUDZCDCLKSEL_VAUDP15,
	PMIC_RG_AUDZCDMUXSEL_VAUDP15,
	PMIC_RG_AUDLOLGAIN,
	PMIC_RG_AUDLORGAIN,
	PMIC_RG_AUDHPLGAIN,
	PMIC_RG_AUDHPRGAIN,
	PMIC_RG_AUDHSGAIN,
	PMIC_RG_AUDIVLGAIN,
	PMIC_RG_AUDIVRGAIN,
	PMIC_RG_AUDINTGAIN1,
	PMIC_RG_AUDINTGAIN2,
	PMIC_RSV_CON0_RSV,
	PMU_COMMAND_MAX
} PMU_FLAGS_LIST_ENUM;

typedef struct {
	PMU_FLAGS_LIST_ENUM flagname;
	unsigned short offset;
	unsigned short mask;
	unsigned char shift;
} PMU_FLAG_TABLE_ENTRY;

#endif /* _LK_MT_UPMU_SW_MT6355_H_ */