mtk-lk/platform/mt6885/include/platform/mt_irq.h

/* Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein
 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
 * Without the prior written permission of MediaTek inc. and/or its licensors,
 * any reproduction, modification, use or disclosure of MediaTek Software,
 * and information contained herein, in whole or in part, shall be strictly prohibited.
 */
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 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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 */

#ifndef __MT_IRQ_H__
#define __MT_IRQ_H__

#include <stdint.h>

#define GIC_DIST_CTRL           0x000
#define GIC_DIST_ENABLE_SET     0x100
#define GIC_DIST_ENABLE_CLEAR       0x180
#define GIC_DIST_PENDING_SET        0x200
#define GIC_DIST_PENDING_CLEAR      0x280
#define GIC_DIST_ACTIVE_SET        0x300
#define GIC_DIST_ACTIVE_CLEAR      0x380
#define GIC_DIST_PRI            0x400
#define GIC_DIST_CONFIG         0xc00
#define GIC_DIST_IGRPMODR       0xd00
#define GIC_DIST_ROUTE          0x6100
#define GIC_REDIS_WAKER         0x14

#define MTK_POL_DEPRECATED

#define INT_MSK_CTL0  (MCUCFG_BASE + 0xd6d0)

/* GIC600 */

#define GIC600
#define GICR_PWRR	0x0024

/* GICR_PWRR fields */
#define PWRR_RDPD_SHIFT		0
#define PWRR_RDGPD_SHIFT	2
#define PWRR_RDGPO_SHIFT	3

#define PWRR_RDGPD		(1 << PWRR_RDGPD_SHIFT)
#define PWRR_RDGPO		(1 << PWRR_RDGPO_SHIFT)

/* Values to write to GICR_PWRR register to power redistributor */
#define PWRR_ON			(0 << PWRR_RDPD_SHIFT)
#define PWRR_OFF		(1 << PWRR_RDPD_SHIFT)

/*
 * Define hadware registers.
 */

/*
 * Define IRQ code.
 */

#define GIC_PRIVATE_SIGNALS (32)

#define GIC_PPI_OFFSET          (27)
#define GIC_PPI_GLOBAL_TIMER    (GIC_PPI_OFFSET + 0)
#define GIC_PPI_LEGACY_FIQ      (GIC_PPI_OFFSET + 1)
#define GIC_PPI_PRIVATE_TIMER   (GIC_PPI_OFFSET + 2)
#define GIC_PPI_WATCHDOG_TIMER  (GIC_PPI_OFFSET + 3)
#define GIC_PPI_LEGACY_IRQ      (GIC_PPI_OFFSET + 4)


#define MT_GPT_IRQ_ID   243
#define MT_USB0_IRQ_ID  128
#define MT_SSUSB_IRQ_ID 104
#define MT_NFI_IRQ_ID   128 /* fixme: need to confirm after SB do nand flash boot */
#define MT_MSDC0_IRQ_ID 131
#define MT_MSDC1_IRQ_ID 135
#define MT_UFS_IRQ_ID   137

#define MT_NR_PPI   (5)
#define MT_NR_SPI   (241)//(224)
#define NR_IRQ_LINE  (GIC_PPI_OFFSET + MT_NR_PPI + MT_NR_SPI)    // 5 PPIs and 224 SPIs

#define MT65xx_EDGE_SENSITIVE 0
#define MT65xx_LEVEL_SENSITIVE 1

#define MT65xx_POLARITY_LOW   0
#define MT65xx_POLARITY_HIGH  1

#endif  /* !__MT_IRQ_H__ */