mtk-lk/platform/mt6885/include/platform/mtk_auxadc_hw.h

#ifndef _MTK_ADC_HW_H
#define _MTK_ADC_HW_H

//#include <mach/mt6577_reg_base.h>

//#define AUXADC_BASE 0x70020000 // will modify
//#define AUXADC_BASE 0xF1006000
#ifdef AUXADC_BASE
#undef AUXADC_BASE
#endif
#define AUXADC_BASE 0x11001000

#if 0
#define AUXADC_CON0                     (AUXADC_BASE + 0x000)
#define AUXADC_CON1                     (AUXADC_BASE + 0x004)
#define AUXADC_CON2                     (AUXADC_BASE + 0x008)
#define AUXADC_CON3                     (AUXADC_BASE + 0x00C)

#define AUXADC_DAT0                     (AUXADC_BASE + 0x010)
#define AUXADC_DAT1                     (AUXADC_BASE + 0x014)
#define AUXADC_DAT2                     (AUXADC_BASE + 0x018)
#define AUXADC_DAT3                     (AUXADC_BASE + 0x01C)
#define AUXADC_DAT4                     (AUXADC_BASE + 0x020)
#define AUXADC_DAT5                     (AUXADC_BASE + 0x024)
#define AUXADC_DAT6                     (AUXADC_BASE + 0x028)
#define AUXADC_DAT7                     (AUXADC_BASE + 0x02C)
#define AUXADC_DAT8                     (AUXADC_BASE + 0x030)
#define AUXADC_DAT9                     (AUXADC_BASE + 0x034)
#define AUXADC_DAT10                    (AUXADC_BASE + 0x038)
#define AUXADC_DAT11                    (AUXADC_BASE + 0x03C)
#define AUXADC_DAT12                    (AUXADC_BASE + 0x040)
#define AUXADC_DAT13                    (AUXADC_BASE + 0x044)
#endif
#define AUXADC_CON0                     (AUXADC_BASE + 0x000)
#define AUXADC_CON1                     (AUXADC_BASE + 0x004)
#define AUXADC_CON1_SET                 (AUXADC_BASE + 0x008)
#define AUXADC_CON1_CLR                 (AUXADC_BASE + 0x00C)
#define AUXADC_CON2                     (AUXADC_BASE + 0x010)
//#define AUXADC_CON3                     (AUXADC_BASE + 0x014)
#define AUXADC_DAT0                     (AUXADC_BASE + 0x014)

#define AUXADC_TP_CMD            (AUXADC_BASE + 0x005c)
#define AUXADC_TP_ADDR           (AUXADC_BASE + 0x0060)
#define AUXADC_TP_CON0           (AUXADC_BASE + 0x0064)
#define AUXADC_TP_DATA0          (AUXADC_BASE + 0x0074)

#define PAD_AUX_XP              13
#define TP_CMD_ADDR_X           0x0005

#define AUXADC_CON_RTP      (10209000 + 0x0404)

#define AUXADC_DET_VOLT                 (AUXADC_BASE + 0x084)
#define AUXADC_DET_SEL                  (AUXADC_BASE + 0x088)
#define AUXADC_DET_PERIOD               (AUXADC_BASE + 0x08C)
#define AUXADC_DET_DEBT                 (AUXADC_BASE + 0x090)
#define AUXADC_MISC                     (AUXADC_BASE + 0x094)
#define AUXADC_ECC                      (AUXADC_BASE + 0x098)
#define AUXADC_SAMPLE_LIST              (AUXADC_BASE + 0x09c)
#define AUXADC_ABIST_PERIOD             (AUXADC_BASE + 0x0A0)

//-----------------------------------------------------------------------------
#if 0
/*AUXADC_SYNC on AUXADC_CON0*/
#define AUXADC_SYNC_CHAN(_line)         (0x0001<<_line)   /*Time event 1*/

/*AUXADC_IMM on AUXADC_CON1*/
#define AUXADC_IMM_CHAN(_line)          (0x0001<<_line)

/*AUXADC_SYN on AUXADC_CON2*/
#define AUXADC_SYN_BIT                  (0x0001)         /*Time event 0*/

/*AUXADC_CON3*/
#define AUXADC_CON3_STATUS_MASK         (0x0001)
#define AUXADC_CON3_STATUS_OFFSET       (0)
#define AUXADC_STATUS_BUSY              (0x01)
#define AUXADC_STATUS_IDLE              (0x00)

#define AUXADC_CON3_SOFT_RST_MASK       (0x0080)
#define AUXADC_CON3_SOFT_RST_OFFSET     (7)

#define AUXADC_CON3_AUTOCLR0_MASK       (0x0100)
#define AUXADC_CON3_AUTOCLR0_OFFSET     (8)

#define AUXADC_CON3_AUTOCLR1_MASK       (0x0200)
#define AUXADC_CON3_AUTOCLR1_OFFSET     (9)

#define AUXADC_CON3_PUWAIT_EN_MASK      (0x0800)
#define AUXADC_CON3_PUWAIT_EN_OFFSET    (11)

#define AUXADC_CON3_AUTOSET_MASK        (0x8000)
#define AUXADC_CON3_AUTOSET_OFFSET      (15)
#endif
#endif   /*_MTK_ADC_HW_H*/