mtk-lk/platform/mt6785/include/platform/ddp_reg_ovl.h

/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2015. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#ifndef _DDP_REG_OVL_H_
#define _DDP_REG_OVL_H_

/* field definition */
/* ------------------------------------------------------------- */
/* OVL */
#define DISP_REG_OVL_STA						((DISPSYS_OVL0_BASE) + 0x000UL)
	#define STA_FLD_RUN							REG_FLD_MSB_LSB(0, 0)
	#define STA_FLD_RDMA0_IDLE					REG_FLD_MSB_LSB(1, 1)
	#define STA_FLD_RDMA1_IDLE					REG_FLD_MSB_LSB(2, 2)
	#define STA_FLD_RDMA2_IDLE					REG_FLD_MSB_LSB(3, 3)
	#define STA_FLD_RDMA3_IDLE					REG_FLD_MSB_LSB(4, 4)

#define DISP_REG_OVL_INTEN						((DISPSYS_OVL0_BASE) + 0x004UL)
	#define INTEN_FLD_REG_CMT_INTEN				REG_FLD_MSB_LSB(0, 0)
	#define INTEN_FLD_FME_CPL_INTEN				REG_FLD_MSB_LSB(1, 1)
	#define INTEN_FLD_FME_UND_INTEN				REG_FLD_MSB_LSB(2, 2)
	#define INTEN_FLD_FME_SWRST_DONE_INTEN		REG_FLD_MSB_LSB(3, 3)
	#define INTEN_FLD_FME_HWRST_DONE_INTEN		REG_FLD_MSB_LSB(4, 4)
	#define INTEN_FLD_RDMA0_EOF_ABNORMAL_INTEN	REG_FLD_MSB_LSB(5, 5)
	#define INTEN_FLD_RDMA1_EOF_ABNORMAL_INTEN	REG_FLD_MSB_LSB(6, 6)
	#define INTEN_FLD_RDMA2_EOF_ABNORMAL_INTEN	REG_FLD_MSB_LSB(7, 7)
	#define INTEN_FLD_RDMA3_EOF_ABNORMAL_INTEN	REG_FLD_MSB_LSB(8, 8)
	#define INTEN_FLD_RDMA0_SMI_UNDERFLOW_INTEN	REG_FLD_MSB_LSB(9, 9)
	#define INTEN_FLD_RDMA1_SMI_UNDERFLOW_INTEN	REG_FLD_MSB_LSB(10, 10)
	#define INTEN_FLD_RDMA2_SMI_UNDERFLOW_INTEN	REG_FLD_MSB_LSB(11, 11)
	#define INTEN_FLD_RDMA3_SMI_UNDERFLOW_INTEN	REG_FLD_MSB_LSB(12, 12)
	#define INTEN_FLD_ABNORMAL_SOF				REG_FLD_MSB_LSB(13, 13)
	#define INTEN_FLD_START_INTEN				REG_FLD_MSB_LSB(14, 14)

#define DISP_REG_OVL_INTSTA						((DISPSYS_OVL0_BASE) + 0x008UL)
	#define INTSTA_FLD_REG_CMT_INTSTA			REG_FLD_MSB_LSB(0, 0)
	#define INTSTA_FLD_FME_CPL_INTSTA			REG_FLD_MSB_LSB(1, 1)
	#define INTSTA_FLD_FME_UND_INTSTA			REG_FLD_MSB_LSB(2, 2)
	#define INTSTA_FLD_FME_SWRST_DONE_INTSTA	REG_FLD_MSB_LSB(3, 3)
	#define INTSTA_FLD_FME_HWRST_DONE_INTSTA	REG_FLD_MSB_LSB(4, 4)
	#define INTSTA_FLD_RDMA0_EOF_ABNORMAL_INTSTA	REG_FLD_MSB_LSB(5, 5)
	#define INTSTA_FLD_RDMA1_EOF_ABNORMAL_INTSTA	REG_FLD_MSB_LSB(6, 6)
	#define INTSTA_FLD_RDMA2_EOF_ABNORMAL_INTSTA	REG_FLD_MSB_LSB(7, 7)
	#define INTSTA_FLD_RDMA3_EOF_ABNORMAL_INTSTA	REG_FLD_MSB_LSB(8, 8)
	#define INTSTA_FLD_RDMA0_SMI_UNDERFLOW_INTSTA	REG_FLD_MSB_LSB(9, 9)
	#define INTSTA_FLD_RDMA1_SMI_UNDERFLOW_INTSTA	REG_FLD_MSB_LSB(10, 10)
	#define INTSTA_FLD_RDMA2_SMI_UNDERFLOW_INTSTA	REG_FLD_MSB_LSB(11, 11)
	#define INTSTA_FLD_RDMA3_SMI_UNDERFLOW_INTSTA	REG_FLD_MSB_LSB(12, 12)
	#define INTSTA_FLD_ABNORMAL_SOF				REG_FLD_MSB_LSB(13, 13)
	#define INTSTA_FLD_START_INTEN				REG_FLD_MSB_LSB(14, 14)

#define DISP_REG_OVL_TRIG						((DISPSYS_OVL0_BASE) + 0x010UL)
	#define TRIG_FLD_SW_TRIG					REG_FLD_MSB_LSB(0, 0)

#define DISP_REG_OVL_RST						((DISPSYS_OVL0_BASE) + 0x014UL)
#define DISP_REG_OVL_ROI_SIZE					((DISPSYS_OVL0_BASE) + 0x020UL)
	#define ROI_SIZE_FLD_ROI_W					REG_FLD_MSB_LSB(12, 0)
	#define ROI_SIZE_FLD_ROI_H					REG_FLD_MSB_LSB(28, 16)

#define DISP_REG_OVL_ROI_BGCLR					((DISPSYS_OVL0_BASE) + 0x028UL)
	#define ROI_BGCLR_FLD_BLUE					REG_FLD_MSB_LSB(7, 0)
	#define ROI_BGCLR_FLD_GREEN					REG_FLD_MSB_LSB(18, 8)
	#define ROI_BGCLR_FLD_RED					REG_FLD_MSB_LSB(23, 16)
	#define ROI_BGCLR_FLD_ALPHA					REG_FLD_MSB_LSB(31, 24)

#define DISP_REG_OVL_SRC_CON					((DISPSYS_OVL0_BASE) + 0x02CUL)
	#define SRC_CON_FLD_L0_EN					REG_FLD_MSB_LSB(0, 0)
	#define SRC_CON_FLD_L1_EN					REG_FLD_MSB_LSB(1, 1)
	#define SRC_CON_FLD_L2_EN					REG_FLD_MSB_LSB(2, 2)
	#define SRC_CON_FLD_L3_EN					REG_FLD_MSB_LSB(3, 3)
	#define SRC_CON_FLD_LC_EN					REG_FLD_MSB_LSB(4, 4)
	#define SRC_CON_FLD_L_EN			REG_FLD_MSB_LSB(3, 0)
	#define SRC_CON_FORCE_RELAY_MODE		REG_FLD_MSB_LSB(8, 8)
	#define SRC_CON_RELAY_MODE_EN			REG_FLD_MSB_LSB(9, 9)

#define DISP_REG_OVL_L0_CON						((DISPSYS_OVL0_BASE) + 0x030UL)
	#define L_CON_FLD_APHA						REG_FLD_MSB_LSB(7, 0)
	#define L_CON_FLD_AEN						REG_FLD_MSB_LSB(8, 8)
	#define L_CON_FLD_VIRTICAL_FLIP					REG_FLD_MSB_LSB(9, 9)
	#define L_CON_FLD_HORI_FLIP					REG_FLD_MSB_LSB(10, 10)
	#define L_CON_FLD_EXT_MTX_EN					REG_FLD_MSB_LSB(11, 11)
	#define L_CON_FLD_CFMT						REG_FLD_MSB_LSB(15, 12)
	#define L_CON_FLD_MTX						REG_FLD_MSB_LSB(19, 16)
	#define L_CON_FLD_BTSW						REG_FLD_MSB_LSB(24, 24)
	#define L_CON_FLD_CLRFMT_MAN					REG_FLD_MSB_LSB(23, 23)
	#define L_CON_FLD_RGB_SWAP					REG_FLD_MSB_LSB(25, 25)
	#define L_CON_FLD_LSRC						REG_FLD_MSB_LSB(29, 28)
	#define L_CON_FLD_SKEN						REG_FLD_MSB_LSB(30, 30)

#define DISP_REG_OVL_L0_SRCKEY					((DISPSYS_OVL0_BASE) + 0x034UL)
#define DISP_REG_OVL_L0_SRC_SIZE				((DISPSYS_OVL0_BASE) + 0x038UL)
#define DISP_REG_OVL_L0_OFFSET					((DISPSYS_OVL0_BASE) + 0x03CUL)
#define DISP_REG_OVL_L0_ADDR					((DISPSYS_OVL0_BASE) + 0xf40UL)
#define DISP_REG_OVL_L0_PITCH					((DISPSYS_OVL0_BASE) + 0x044UL)
	#define L_PITCH_FLD_LSP					REG_FLD_MSB_LSB(15, 0)
	#define L_PITCH_FLD_SUR_ALFA				REG_FLD_MSB_LSB(31, 16)
	#define L_PITCH_FLD_CONST_BLD				REG_FLD_MSB_LSB(28, 28)
	#define L_PITCH_FLD_SRGB_SEL				REG_FLD_MSB_LSB(19, 18)
	#define L_PITCH_FLD_DRGB_SEL				REG_FLD_MSB_LSB(23, 22)
	#define L_PITCH_FLD_SURFL_EN				REG_FLD_MSB_LSB(31, 31)

#define DISP_REG_OVL_L0_TILE					((DISPSYS_OVL0_BASE) + 0x048UL)
#define DISP_REG_OVL_L0_CLIP					((DISPSYS_OVL0_BASE) + 0x04CUL)
	#define OVL_L_CLIP_FLD_LEFT					REG_FLD_MSB_LSB(7, 0)
	#define OVL_L_CLIP_FLD_RIGHT				REG_FLD_MSB_LSB(15, 8)
	#define OVL_L_CLIP_FLD_TOP					REG_FLD_MSB_LSB(23, 16)
	#define OVL_L_CLIP_FLD_BOTTOM				REG_FLD_MSB_LSB(31, 24)

#define DISP_REG_OVL_L1_CON						((DISPSYS_OVL0_BASE) + 0x050UL)
#define DISP_REG_OVL_L1_SRCKEY					((DISPSYS_OVL0_BASE) + 0x054UL)
#define DISP_REG_OVL_L1_SRC_SIZE				((DISPSYS_OVL0_BASE) + 0x058UL)
#define DISP_REG_OVL_L1_OFFSET					((DISPSYS_OVL0_BASE) + 0x05CUL)
#define DISP_REG_OVL_L1_ADDR					((DISPSYS_OVL0_BASE) + 0xf60UL)
#define DISP_REG_OVL_L1_PITCH					((DISPSYS_OVL0_BASE) + 0x064UL)
#define DISP_REG_OVL_L1_TILE					((DISPSYS_OVL0_BASE) + 0x068UL)
#define DISP_REG_OVL_L1_CLIP					((DISPSYS_OVL0_BASE) + 0x06CUL)
#define DISP_REG_OVL_L2_CON						((DISPSYS_OVL0_BASE) + 0x070UL)
#define DISP_REG_OVL_L2_SRCKEY					((DISPSYS_OVL0_BASE) + 0x074UL)
#define DISP_REG_OVL_L2_SRC_SIZE				((DISPSYS_OVL0_BASE) + 0x078UL)
#define DISP_REG_OVL_L2_OFFSET					((DISPSYS_OVL0_BASE) + 0x07CUL)
#define DISP_REG_OVL_L2_ADDR					((DISPSYS_OVL0_BASE) + 0xf80UL)
#define DISP_REG_OVL_L2_PITCH					((DISPSYS_OVL0_BASE) + 0x084UL)
#define DISP_REG_OVL_L2_TILE					((DISPSYS_OVL0_BASE) + 0x088UL)
#define DISP_REG_OVL_L2_CLIP					((DISPSYS_OVL0_BASE) + 0x08CUL)
#define DISP_REG_OVL_L3_CON						((DISPSYS_OVL0_BASE) + 0x090UL)
#define DISP_REG_OVL_L3_SRCKEY					((DISPSYS_OVL0_BASE) + 0x094UL)
#define DISP_REG_OVL_L3_SRC_SIZE				((DISPSYS_OVL0_BASE) + 0x098UL)
#define DISP_REG_OVL_L3_OFFSET					((DISPSYS_OVL0_BASE) + 0x09CUL)
#define DISP_REG_OVL_L3_ADDR					((DISPSYS_OVL0_BASE) + 0xfA0UL)
#define DISP_REG_OVL_L3_PITCH					((DISPSYS_OVL0_BASE) + 0x0A4UL)
#define DISP_REG_OVL_L3_TILE					((DISPSYS_OVL0_BASE) + 0x0A8UL)
#define DISP_REG_OVL_L3_CLIP					((DISPSYS_OVL0_BASE) + 0x0ACUL)
#define DISP_REG_OVL_RDMA0_CTRL					((DISPSYS_OVL0_BASE) + 0x0C0UL)
	#define RDMA0_CTRL_FLD_RDMA_EN				REG_FLD_MSB_LSB(0, 0)
	#define RDMA0_CTRL_FLD_RMDA_FIFO_USED_SZ	REG_FLD_MSB_LSB(27, 16)

#define DISP_REG_OVL_RDMA0_MEM_SLOW_CON				((DISPSYS_OVL0_BASE) + 0x0CCUL)

#define DISP_REG_OVL_RDMA1_CTRL						((DISPSYS_OVL0_BASE) + 0x0E0UL)
#define DISP_REG_OVL_RDMA1_MEM_GMC_SETTING			((DISPSYS_OVL0_BASE) + 0x0E8UL)
#define DISP_REG_OVL_RDMA1_MEM_SLOW_CON				((DISPSYS_OVL0_BASE) + 0x0ECUL)
#define DISP_REG_OVL_RDMA1_FIFO_CTRL				((DISPSYS_OVL0_BASE) + 0x0F0UL)
#define DISP_REG_OVL_RDMA2_CTRL						((DISPSYS_OVL0_BASE) + 0x100UL)
#define DISP_REG_OVL_RDMA2_MEM_GMC_SETTING			((DISPSYS_OVL0_BASE) + 0x108UL)
#define DISP_REG_OVL_RDMA2_MEM_SLOW_CON				((DISPSYS_OVL0_BASE) + 0x10CUL)
#define DISP_REG_OVL_RDMA2_FIFO_CTRL				((DISPSYS_OVL0_BASE) + 0x110UL)
#define DISP_REG_OVL_RDMA3_CTRL						((DISPSYS_OVL0_BASE) + 0x120UL)
#define DISP_REG_OVL_RDMA3_MEM_GMC_SETTING			((DISPSYS_OVL0_BASE) + 0x128UL)
#define DISP_REG_OVL_RDMA3_MEM_SLOW_CON				((DISPSYS_OVL0_BASE) + 0x12CUL)
#define DISP_REG_OVL_RDMA3_FIFO_CTRL				((DISPSYS_OVL0_BASE) + 0x130UL)

#define DISP_REG_OVL_L0_Y2R_PARA_R0					((DISPSYS_OVL0_BASE) + 0x134UL)
#define DISP_REG_OVL_L0_Y2R_PARA_R1					((DISPSYS_OVL0_BASE) + 0x138UL)
#define DISP_REG_OVL_L0_Y2R_PARA_G0					((DISPSYS_OVL0_BASE) + 0x13CUL)
#define DISP_REG_OVL_L0_Y2R_PARA_G1					((DISPSYS_OVL0_BASE) + 0x140UL)
#define DISP_REG_OVL_L0_Y2R_PARA_B0					((DISPSYS_OVL0_BASE) + 0x144UL)
#define DISP_REG_OVL_L0_Y2R_PARA_B1					((DISPSYS_OVL0_BASE) + 0x148UL)
#define DISP_REG_OVL_L0_Y2R_PARA_YUV_A_0			((DISPSYS_OVL0_BASE) + 0x14CUL)
#define DISP_REG_OVL_L0_Y2R_PARA_YUV_A_1			((DISPSYS_OVL0_BASE) + 0x150UL)
#define DISP_REG_OVL_L0_Y2R_PARA_RGB_A_0			((DISPSYS_OVL0_BASE) + 0x154UL)
#define DISP_REG_OVL_L0_Y2R_PARA_RGB_A_1			((DISPSYS_OVL0_BASE) + 0x158UL)
#define DISP_REG_OVL_L1_Y2R_PARA_R0					((DISPSYS_OVL0_BASE) + 0x15CUL)
#define DISP_REG_OVL_L1_Y2R_PARA_R1					((DISPSYS_OVL0_BASE) + 0x160UL)
#define DISP_REG_OVL_L1_Y2R_PARA_G0					((DISPSYS_OVL0_BASE) + 0x164UL)
#define DISP_REG_OVL_L1_Y2R_PARA_G1					((DISPSYS_OVL0_BASE) + 0x168UL)
#define DISP_REG_OVL_L1_Y2R_PARA_B0					((DISPSYS_OVL0_BASE) + 0x16CUL)
#define DISP_REG_OVL_L1_Y2R_PARA_B1					((DISPSYS_OVL0_BASE) + 0x170UL)
#define DISP_REG_OVL_L1_Y2R_PARA_YUV_A_0			((DISPSYS_OVL0_BASE) + 0x174UL)
#define DISP_REG_OVL_L1_Y2R_PARA_YUV_A_1			((DISPSYS_OVL0_BASE) + 0x178UL)
#define DISP_REG_OVL_L1_Y2R_PARA_RGB_A_0			((DISPSYS_OVL0_BASE) + 0x17CUL)
#define DISP_REG_OVL_L1_Y2R_PARA_RGB_A_1			((DISPSYS_OVL0_BASE) + 0x180UL)
#define DISP_REG_OVL_L2_Y2R_PARA_R0					((DISPSYS_OVL0_BASE) + 0x184UL)
#define DISP_REG_OVL_L2_Y2R_PARA_R1					((DISPSYS_OVL0_BASE) + 0x188UL)
#define DISP_REG_OVL_L2_Y2R_PARA_G0					((DISPSYS_OVL0_BASE) + 0x18CUL)
#define DISP_REG_OVL_L2_Y2R_PARA_G1					((DISPSYS_OVL0_BASE) + 0x190UL)
#define DISP_REG_OVL_L2_Y2R_PARA_B0					((DISPSYS_OVL0_BASE) + 0x194UL)
#define DISP_REG_OVL_L2_Y2R_PARA_B1					((DISPSYS_OVL0_BASE) + 0x198UL)
#define DISP_REG_OVL_L2_Y2R_PARA_YUV_A_0			((DISPSYS_OVL0_BASE) + 0x19CUL)
#define DISP_REG_OVL_L2_Y2R_PARA_YUV_A_1			((DISPSYS_OVL0_BASE) + 0x1A0UL)
#define DISP_REG_OVL_L2_Y2R_PARA_RGB_A_0			((DISPSYS_OVL0_BASE) + 0x1A4UL)
#define DISP_REG_OVL_L2_Y2R_PARA_RGB_A_1			((DISPSYS_OVL0_BASE) + 0x1A8UL)
#define DISP_REG_OVL_L3_Y2R_PARA_R0					((DISPSYS_OVL0_BASE) + 0x1ACUL)
#define DISP_REG_OVL_L3_Y2R_PARA_R1					((DISPSYS_OVL0_BASE) + 0x1B0UL)
#define DISP_REG_OVL_L3_Y2R_PARA_G0					((DISPSYS_OVL0_BASE) + 0x1B4UL)
#define DISP_REG_OVL_L3_Y2R_PARA_G1					((DISPSYS_OVL0_BASE) + 0x1B8UL)
#define DISP_REG_OVL_L3_Y2R_PARA_B0					((DISPSYS_OVL0_BASE) + 0x1BCUL)
#define DISP_REG_OVL_L3_Y2R_PARA_B1					((DISPSYS_OVL0_BASE) + 0x1C0UL)
#define DISP_REG_OVL_L3_Y2R_PARA_YUV_A_0			((DISPSYS_OVL0_BASE) + 0x1C4UL)
#define DISP_REG_OVL_L3_Y2R_PARA_YUV_A_1			((DISPSYS_OVL0_BASE) + 0x1C8UL)
#define DISP_REG_OVL_L3_Y2R_PARA_RGB_A_0			((DISPSYS_OVL0_BASE) + 0x1CCUL)
#define DISP_REG_OVL_L3_Y2R_PARA_RGB_A_1			((DISPSYS_OVL0_BASE) + 0x1D0UL)
#define DISP_REG_OVL_DEBUG_MON_SEL					((DISPSYS_OVL0_BASE) + 0x1D4UL)
#define DISP_REG_OVL_RDMA_BURST_CON0				((DISPSYS_OVL0_BASE) + 0x1F0UL)

#define DISP_REG_OVL_DUMMY_REG						((DISPSYS_OVL0_BASE) + 0x200UL)
#define DISP_REG_OVL_GDRDY_PRD						((DISPSYS_OVL0_BASE) + 0x208UL)

#define DISP_REG_OVL_RDMA0_BUF_LOW					((DISPSYS_OVL0_BASE) + 0x210UL)
#define DISP_REG_OVL_RDMA1_BUF_LOW					((DISPSYS_OVL0_BASE) + 0x214UL)
#define DISP_REG_OVL_RDMA2_BUF_LOW					((DISPSYS_OVL0_BASE) + 0x218UL)
#define DISP_REG_OVL_RDMA3_BUF_LOW					((DISPSYS_OVL0_BASE) + 0x21cUL)

#define DISP_REG_OVL_SMI_DBG						((DISPSYS_OVL0_BASE) + 0x230UL)
#define DISP_REG_OVL_GREQ_LAYER_CNT					((DISPSYS_OVL0_BASE) + 0x234UL)
#define DISP_REG_OVL_GDRDY_PRD_NUM					((DISPSYS_OVL0_BASE) + 0x238UL)
#define DISP_REG_OVL_FLOW_CTRL_DBG					((DISPSYS_OVL0_BASE) + 0x240UL)
#define DISP_REG_OVL_ADDCON_DBG						((DISPSYS_OVL0_BASE) + 0x244UL)
	#define ADDCON_DBG_FLD_ROI_X					REG_FLD_MSB_LSB(12, 0)
	#define ADDCON_DBG_FLD_L0_WIN_HIT				REG_FLD_MSB_LSB(14, 14)
	#define ADDCON_DBG_FLD_L1_WIN_HIT				REG_FLD_MSB_LSB(15, 15)
	#define ADDCON_DBG_FLD_ROI_Y					REG_FLD_MSB_LSB(28, 16)
	#define ADDCON_DBG_FLD_L3_WIN_HIT				REG_FLD_MSB_LSB(31, 31)
	#define ADDCON_DBG_FLD_L2_WIN_HIT				REG_FLD_MSB_LSB(30, 30)
#define DISP_REG_OVL_RDMA0_DBG						((DISPSYS_OVL0_BASE) + 0x24CUL)
	#define RDMA0_DBG_FLD_RDMA0_WRAM_RST_CS			REG_FLD_MSB_LSB(2, 0)
	#define RDMA0_DBG_FLD_RDMA0_LAYER_GREQ          REG_FLD_MSB_LSB(3, 3)
	#define RDMA0_DBG_FLD_RDMA0_OUT_DATA			REG_FLD_MSB_LSB(27 4)
	#define RDMA0_DBG_FLD_RDMA0_OUT_READY			REG_FLD_MSB_LSB(28, 28)
	#define RDMA0_DBG_FLD_RDMA0_OUT_VALID			REG_FLD_MSB_LSB(29, 29)
	#define RDMA0_DBG_FLD_RDMA0_SMI_BUSY			REG_FLD_MSB_LSB(30, 30)
	#define RDMA0_DBG_FLD_RDMA0_SMI_GREQ			REG_FLD_MSB_LSB(31, 31)

#define DISP_REG_OVL_RDMA1_DBG						((DISPSYS_OVL0_BASE) + 0x250UL)
#define DISP_REG_OVL_RDMA2_DBG						((DISPSYS_OVL0_BASE) + 0x254UL)
#define DISP_REG_OVL_RDMA3_DBG						((DISPSYS_OVL0_BASE) + 0x258UL)
#define DISP_REG_OVL_L0_CLR							((DISPSYS_OVL0_BASE) + 0x25cUL)
#define DISP_REG_OVL_L1_CLR							((DISPSYS_OVL0_BASE) + 0x260UL)
#define DISP_REG_OVL_L2_CLR							((DISPSYS_OVL0_BASE) + 0x264UL)
#define DISP_REG_OVL_L3_CLR							((DISPSYS_OVL0_BASE) + 0x268UL)
#define DISP_REG_OVL_LC_CLR							((DISPSYS_OVL0_BASE) + 0x26cUL)
#define DISP_REG_OVL_CRC							((DISPSYS_OVL0_BASE) + 0x270UL)
#define DISP_REG_OVL_LC_CON							((DISPSYS_OVL0_BASE) + 0x280UL)
#define DISP_REG_OVL_LC_SRCKEY						((DISPSYS_OVL0_BASE) + 0x284UL)
#define DISP_REG_OVL_LC_SRC_SIZE					((DISPSYS_OVL0_BASE) + 0x288UL)
#define DISP_REG_OVL_LC_OFFSET						((DISPSYS_OVL0_BASE) + 0x28cUL)
#define DISP_REG_OVL_LC_SRC_SEL						((DISPSYS_OVL0_BASE) + 0x290UL)
	#define LC_SRC_SEL_FLD_L_SEL			REG_FLD_MSB_LSB(2, 0)
#define DISP_REG_OVL_BANK_CON						((DISPSYS_OVL0_BASE) + 0x29cUL)
#define DISP_REG_OVL_FUNC_DCM0						((DISPSYS_OVL0_BASE) + 0x2a0UL)
#define DISP_REG_OVL_FUNC_DCM1						((DISPSYS_OVL0_BASE) + 0x2a4UL)
#define DISP_REG_OVL_DVFS_L0_ROI					((DISPSYS_OVL0_BASE) + 0x2B0UL)
#define DISP_REG_OVL_DVFS_L1_ROI					((DISPSYS_OVL0_BASE) + 0x2B4UL)
#define DISP_REG_OVL_DVFS_L2_ROI					((DISPSYS_OVL0_BASE) + 0x2B8UL)
#define DISP_REG_OVL_DVFS_L3_ROI					((DISPSYS_OVL0_BASE) + 0x2BCUL)
#define DISP_REG_OVL_DVFS_EL0_ROI					((DISPSYS_OVL0_BASE) + 0x2C0UL)
#define DISP_REG_OVL_DVFS_EL1_ROI					((DISPSYS_OVL0_BASE) + 0x2C4UL)
#define DISP_REG_OVL_DVFS_EL2_ROI					((DISPSYS_OVL0_BASE) + 0x2C8UL)
#define DISP_REG_OVL_DATAPATH_EXT_CON				((DISPSYS_OVL0_BASE) + 0x324UL)
#define DISP_REG_OVL_EL0_CON						((DISPSYS_OVL0_BASE) + 0x330UL)
#define DISP_REG_OVL_EL0_SRCKEY						((DISPSYS_OVL0_BASE) + 0x334UL)
#define DISP_REG_OVL_EL0_SRC_SIZE					((DISPSYS_OVL0_BASE) + 0x338UL)
#define DISP_REG_OVL_EL0_OFFSET						((DISPSYS_OVL0_BASE) + 0x33CUL)
#define DISP_REG_OVL_EL0_ADDR						((DISPSYS_OVL0_BASE) + 0xFB0UL)
#define DISP_REG_OVL_EL0_PITCH						((DISPSYS_OVL0_BASE) + 0x344UL)
#define DISP_REG_OVL_EL0_TILE						((DISPSYS_OVL0_BASE) + 0x348UL)
#define DISP_REG_OVL_EL0_CLIP						((DISPSYS_OVL0_BASE) + 0x34CUL)
#define DISP_REG_OVL_EL1_CON						((DISPSYS_OVL0_BASE) + 0x350UL)
#define DISP_REG_OVL_EL1_SRCKEY						((DISPSYS_OVL0_BASE) + 0x354UL)
#define DISP_REG_OVL_EL1_SRC_SIZE					((DISPSYS_OVL0_BASE) + 0x358UL)
#define DISP_REG_OVL_EL1_OFFSET						((DISPSYS_OVL0_BASE) + 0x35CUL)
#define DISP_REG_OVL_EL1_ADDR						((DISPSYS_OVL0_BASE) + 0xFB4UL)
#define DISP_REG_OVL_EL1_PITCH						((DISPSYS_OVL0_BASE) + 0x364UL)
#define DISP_REG_OVL_EL1_TILE						((DISPSYS_OVL0_BASE) + 0x368UL)
#define DISP_REG_OVL_EL1_CLIP						((DISPSYS_OVL0_BASE) + 0x36CUL)
#define DISP_REG_OVL_EL2_CON						((DISPSYS_OVL0_BASE) + 0x370UL)
#define DISP_REG_OVL_EL2_SRCKEY						((DISPSYS_OVL0_BASE) + 0x374UL)
#define DISP_REG_OVL_EL2_SRC_SIZE					((DISPSYS_OVL0_BASE) + 0x378UL)
#define DISP_REG_OVL_EL2_OFFSET						((DISPSYS_OVL0_BASE) + 0x37CUL)
#define DISP_REG_OVL_EL2_ADDR						((DISPSYS_OVL0_BASE) + 0xFB8UL)
#define DISP_REG_OVL_EL2_PITCH						((DISPSYS_OVL0_BASE) + 0x384UL)
#define DISP_REG_OVL_EL2_TILE						((DISPSYS_OVL0_BASE) + 0x388UL)
#define DISP_REG_OVL_EL2_CLIP						((DISPSYS_OVL0_BASE) + 0x38CUL)
#define DISP_REG_OVL_EL0_CLEAR						((DISPSYS_OVL0_BASE) + 0x390UL)
#define DISP_REG_OVL_EL1_CLEAR						((DISPSYS_OVL0_BASE) + 0x394UL)
#define DISP_REG_OVL_EL2_CLEAR						((DISPSYS_OVL0_BASE) + 0x398UL)
#define DISP_REG_OVL_SECURE							((DISPSYS_OVL0_BASE) + 0xFC0UL)

/* for ovl golden setting */
#define DISP_REG_OVL_RDMA0_MEM_GMC_SETTING		((DISPSYS_OVL0_BASE) + 0x0C8UL)
	#define FLD_OVL_RDMA_MEM_GMC_ULTRA_THRESHOLD	REG_FLD_MSB_LSB(9, 0)
	#define FLD_OVL_RDMA_MEM_GMC_PRE_ULTRA_THRESHOLD REG_FLD_MSB_LSB(25, 16)
	#define FLD_OVL_RDMA_MEM_GMC_ULTRA_THRESHOLD_HIGH_OFS \
							REG_FLD_MSB_LSB(28, 28)
	#define FLD_OVL_RDMA_MEM_GMC_PRE_ULTRA_THRESHOLD_HIGH_OFS \
							REG_FLD_MSB_LSB(31, 31)

#define DISP_REG_OVL_RDMA0_FIFO_CTRL			((DISPSYS_OVL0_BASE) + 0x0D0UL)
	#define FLD_OVL_RDMA_FIFO_THRD			REG_FLD_MSB_LSB(9, 0)
	#define FLD_OVL_RDMA_FIFO_SIZE			REG_FLD_MSB_LSB(27, 16)
	#define FLD_OVL_RDMA_FIFO_UND_EN		REG_FLD_MSB_LSB(31, 31)

#define DISP_REG_OVL_RDMA0_MEM_GMC_S2			((DISPSYS_OVL0_BASE) + 0x1E0UL)
	#define FLD_OVL_RDMA_MEM_GMC2_ISSUE_REQ_THRES	REG_FLD_MSB_LSB(11, 0)
	#define FLD_OVL_RDMA_MEM_GMC2_ISSUE_REQ_THRES_URG \
							REG_FLD_MSB_LSB(27, 16)
	#define FLD_OVL_RDMA_MEM_GMC2_REQ_THRES_PREULTRA REG_FLD_MSB_LSB(28, 28)
	#define FLD_OVL_RDMA_MEM_GMC2_REQ_THRES_ULTRA	REG_FLD_MSB_LSB(29, 29)
	#define FLD_OVL_RDMA_MEM_GMC2_FORCE_REQ_THRES	REG_FLD_MSB_LSB(30, 30)

#define DISP_REG_OVL_RDMA_BURST_CON1			((DISPSYS_OVL0_BASE) + 0x1F4UL)
	#define FLD_RDMA_BURST_CON1_BURST16_EN		REG_FLD_MSB_LSB(28, 28)

#define DISP_REG_OVL_RDMA_GREQ_NUM			((DISPSYS_OVL0_BASE) + 0x1F8UL)
	#define FLD_OVL_RDMA_GREQ_LAYER0_GREQ_NUM	REG_FLD_MSB_LSB(3, 0)
	#define FLD_OVL_RDMA_GREQ_LAYER1_GREQ_NUM	REG_FLD_MSB_LSB(7, 4)
	#define FLD_OVL_RDMA_GREQ_LAYER2_GREQ_NUM	REG_FLD_MSB_LSB(11, 8)
	#define FLD_OVL_RDMA_GREQ_LAYER3_GREQ_NUM	REG_FLD_MSB_LSB(15, 12)
	#define FLD_OVL_RDMA_GREQ_OSTD_GREQ_NUM		REG_FLD_MSB_LSB(23, 16)
	#define FLD_OVL_RDMA_GREQ_GREQ_DIS_CNT		REG_FLD_MSB_LSB(26, 24)
	#define FLD_OVL_RDMA_GREQ_STOP_EN		REG_FLD_MSB_LSB(27, 27)
	#define FLD_OVL_RDMA_GREQ_GRP_END_STOP		REG_FLD_MSB_LSB(28, 28)
	#define FLD_OVL_RDMA_GREQ_GRP_BRK_STOP		REG_FLD_MSB_LSB(29, 29)
	#define FLD_OVL_RDMA_GREQ_IOBUF_FLUSH_PREULTRA	REG_FLD_MSB_LSB(30, 30)
	#define FLD_OVL_RDMA_GREQ_IOBUF_FLUSH_ULTRA	REG_FLD_MSB_LSB(31, 31)

#define DISP_REG_OVL_RDMA_GREQ_URG_NUM			((DISPSYS_OVL0_BASE) + 0x1FCUL)
	#define FLD_OVL_RDMA_GREQ_LAYER0_GREQ_URG_NUM	REG_FLD_MSB_LSB(3, 0)
	#define FLD_OVL_RDMA_GREQ_LAYER1_GREQ_URG_NUM	REG_FLD_MSB_LSB(7, 4)
	#define FLD_OVL_RDMA_GREQ_LAYER2_GREQ_URG_NUM	REG_FLD_MSB_LSB(11, 8)
	#define FLD_OVL_RDMA_GREQ_LAYER3_GREQ_URG_NUM	REG_FLD_MSB_LSB(15, 12)
	#define FLD_OVL_RDMA_GREQ_ARG_GREQ_URG_TH	REG_FLD_MSB_LSB(25, 16)
	#define FLD_OVL_RDMA_GREQ_ARG_URG_BIAS		REG_FLD_MSB_LSB(28, 28)
	#define FLD_OVL_RDMA_GREQ_NUM_SHT_VAL		REG_FLD_MSB_LSB(29, 29)

#define DISP_REG_OVL_RDMA_ULTRA_SRC			((DISPSYS_OVL0_BASE) + 0x20CUL)
	#define FLD_OVL_RDMA_PREULTRA_BUF_SRC		REG_FLD_MSB_LSB(1, 0)
	#define FLD_OVL_RDMA_PREULTRA_SMI_SRC		REG_FLD_MSB_LSB(3, 2)
	#define FLD_OVL_RDMA_PREULTRA_ROI_END_SRC	REG_FLD_MSB_LSB(5, 4)
	#define FLD_OVL_RDMA_PREULTRA_RDMA_SRC		REG_FLD_MSB_LSB(7, 6)
	#define FLD_OVL_RDMA_ULTRA_BUF_SRC		REG_FLD_MSB_LSB(9, 8)
	#define FLD_OVL_RDMA_ULTRA_SMI_SRC		REG_FLD_MSB_LSB(11, 10)
	#define FLD_OVL_RDMA_ULTRA_ROI_END_SRC		REG_FLD_MSB_LSB(13, 12)
	#define FLD_OVL_RDMA_ULTRA_RDMA_SRC		REG_FLD_MSB_LSB(15, 14)

#define DISP_REG_OVL_RDMAn_BUF_LOW(layer)		((DISPSYS_OVL0_BASE) + 0x210UL + ((layer)<<2))
	#define FLD_OVL_RDMA_BUF_LOW_ULTRA_TH		REG_FLD_MSB_LSB(11, 0)
	#define FLD_OVL_RDMA_BUF_LOW_PREULTRA_TH	REG_FLD_MSB_LSB(23, 12)

#define DISP_REG_OVL_RDMAn_BUF_HIGH(layer)		((DISPSYS_OVL0_BASE) + 0x220UL + ((layer)<<2))
	#define FLD_OVL_RDMA_BUF_HIGH_PREULTRA_TH	REG_FLD_MSB_LSB(23, 12)
	#define FLD_OVL_RDMA_BUF_HIGH_PREULTRA_DIS	REG_FLD_MSB_LSB(31, 31)

#define DISP_REG_OVL_EN					((DISPSYS_OVL0_BASE) + 0x00CUL)
	#define EN_FLD_OVL_EN				REG_FLD_MSB_LSB(0, 0)
	#define EN_FLD_OP_8BIT_MODE			REG_FLD_MSB_LSB(4, 4)
	#define EN_FLD_OP_10BIT_MODE			REG_FLD_MSB_LSB(5, 5)
	#define EN_FLD_ARB_16F_NO_RND			REG_FLD_MSB_LSB(7, 7)
	#define EN_FLD_HG_FOVL_CK_ON			REG_FLD_MSB_LSB(8, 8)
	#define EN_FLD_HG_FSMI_CK_ON			REG_FLD_MSB_LSB(9, 9)
	#define EN_FLD_HF_FOVL_CK_ON			REG_FLD_MSB_LSB(10, 10)
	#define EN_FLD_IGNORE_ABN_SOF			REG_FLD_MSB_LSB(16, 16)
	#define EN_FLD_BLOCK_EXT_ULTRA			REG_FLD_MSB_LSB(18, 18)
	#define EN_FLD_BLOCK_EXT_PREULTRA		REG_FLD_MSB_LSB(19, 19)
	#define EN_FLD_NO_FORM_HDR_ULTRA		REG_FLD_MSB_LSB(28, 28)
	#define EN_FLD_NO_FORM_HDR_PREULTRA		REG_FLD_MSB_LSB(29, 29)


#define DISP_REG_OVL_DATAPATH_CON			((DISPSYS_OVL0_BASE) + 0x024UL)
	#define DATAPATH_CON_FLD_LAYER_SMI_ID_EN	REG_FLD_MSB_LSB(0, 0)
	#define DATAPATH_CON_FLD_RANDOM_BGCLR_EN	REG_FLD_MSB_LSB(1, 1)
	#define DATAPATH_CON_FLD_BGCLR_IN_SEL		REG_FLD_MSB_LSB(2, 2)
	#define DATAPATH_CON_FLD_OUTPUT_NO_RND		REG_FLD_MSB_LSB(3, 3)
	#define DATAPATH_CON_FLD_L0_FBDC_EN		REG_FLD_MSB_LSB(4, 4)
	#define DATAPATH_CON_FLD_L1_FBDC_EN		REG_FLD_MSB_LSB(5, 5)
	#define DATAPATH_CON_FLD_L2_FBDC_EN		REG_FLD_MSB_LSB(6, 6)
	#define DATAPATH_CON_FLD_L3_FBDC_EN		REG_FLD_MSB_LSB(7, 7)
	#define DATAPATH_CON_FLD_L0_GPU_MODE		REG_FLD_MSB_LSB(8, 8)
	#define DATAPATH_CON_FLD_L1_GPU_MODE		REG_FLD_MSB_LSB(9, 9)
	#define DATAPATH_CON_FLD_L2_GPU_MODE		REG_FLD_MSB_LSB(10, 10)
	#define DATAPATH_CON_FLD_L3_GPU_MODE		REG_FLD_MSB_LSB(11, 11)
	#define DATAPATH_CON_FLD_ADOBE_MODE		REG_FLD_MSB_LSB(12, 12)
	#define DATAPATH_CON_FLD_ADOBE_LAYER		REG_FLD_MSB_LSB(14, 13)
	#define DATAPATH_CON_FLD_OVL_GAMMA_OUT		REG_FLD_MSB_LSB(15, 15)
	#define DATAPATH_CON_FLD_PQ_OUT_SEL		REG_FLD_MSB_LSB(18, 16)
	#define DATAPATH_CON_FLD_PQ_OUT_EN		REG_FLD_MSB_LSB(19, 19)
	#define DATAPATH_CON_FLD_RDMA0_OUT_SEL		REG_FLD_MSB_LSB(20, 20)
	#define DATAPATH_CON_FLD_RDMA1_OUT_SEL		REG_FLD_MSB_LSB(21, 21)
	#define DATAPATH_CON_FLD_RDMA2_OUT_SEL		REG_FLD_MSB_LSB(22, 22)
	#define DATAPATH_CON_FLD_PQ_OUT_OPT		REG_FLD_MSB_LSB(23, 23)
	#define DATAPATH_CON_FLD_GCLAST_EN		REG_FLD_MSB_LSB(24, 24)
	#define DATAPATH_CON_FLD_HDR_GCLAST_EN		REG_FLD_MSB_LSB(25, 25)
	#define DATAPATH_CON_FLD_OUTPUT_CLAMP		REG_FLD_MSB_LSB(26, 26)
	#define DATAPATH_CON_FLD_OUTPUT_INTERLACE	REG_FLD_MSB_LSB(27, 27)

#define DISP_REG_OVL_FBDC_CFG1				((DISPSYS_OVL0_BASE) + 0x804UL)
	#define FLD_EL0_FBDC_PXLFMT			REG_FLD_MSB_LSB(6, 0)
	#define FLD_EL0_FBDC_PXLFMT_EN			REG_FLD_MSB_LSB(7, 7)
	#define FLD_EL1_FBDC_PXLFMT			REG_FLD_MSB_LSB(14, 8)
	#define FLD_EL1_FBDC_PXLFMT_EN			REG_FLD_MSB_LSB(15, 15)
	#define FLD_EL2_FBDC_PXLFMT			REG_FLD_MSB_LSB(22, 16)
	#define FLD_EL2_FBDC_PXLFMT_EN			REG_FLD_MSB_LSB(23, 23)
	#define FLD_FBDC_8XE_MODE			REG_FLD_MSB_LSB(24, 24)
	#define FLD_FBDC_MODE_V3_1_EN			REG_FLD_MSB_LSB(25, 25)
	#define FLD_FBDC_FILTER_EN			REG_FLD_MSB_LSB(28, 28)
	#define FLD_FBDC_FILTER_CLEAR			REG_FLD_MSB_LSB(31, 29)

enum GS_OVL_FLD {
	GS_OVL_RDMA_ULTRA_TH = 0,
	GS_OVL_RDMA_PRE_ULTRA_TH,
	GS_OVL_RDMA_FIFO_THRD,
	GS_OVL_RDMA_FIFO_SIZE,
	GS_OVL_RDMA_ISSUE_REQ_TH,
	GS_OVL_RDMA_ISSUE_REQ_TH_URG,
	GS_OVL_RDMA_REQ_TH_PRE_ULTRA,
	GS_OVL_RDMA_REQ_TH_ULTRA,
	GS_OVL_RDMA_FORCE_REQ_TH,
	GS_OVL_RDMA_GREQ_NUM, /* whole reg */
	GS_OVL_RDMA_GREQ_URG_NUM, /* whole reg */
	GS_OVL_RDMA_ULTRA_SRC, /* whole reg */
	GS_OVL_RDMA_ULTRA_LOW_TH,
	GS_OVL_RDMA_PRE_ULTRA_LOW_TH,
	GS_OVL_RDMA_PRE_ULTRA_HIGH_TH,
	GS_OVL_RDMA_PRE_ULTRA_HIGH_DIS,
	GS_OVL_BLOCK_EXT_ULTRA,
	GS_OVL_BLOCK_EXT_PRE_ULTRA,
	GS_OVL_FLD_NUM,
};

#endif