log_store_lk.h 6.7 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein is
  5. * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
  6. * the prior written permission of MediaTek inc. and/or its licensors, any
  7. * reproduction, modification, use or disclosure of MediaTek Software, and
  8. * information contained herein, in whole or in part, shall be strictly
  9. * prohibited.
  10. *
  11. * MediaTek Inc. (C) 2010. All rights reserved.
  12. *
  13. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  14. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  15. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
  16. * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
  17. * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
  18. * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
  19. * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
  20. * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
  21. * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
  22. * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
  23. * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
  24. * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
  25. * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
  26. * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  27. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
  28. * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
  29. * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
  30. * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
  31. * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  32. *
  33. * The following software/firmware and/or related documentation ("MediaTek
  34. * Software") have been modified by MediaTek Inc. All revisions are subject to
  35. * any receiver's applicable license agreements with MediaTek Inc.
  36. */
  37. #ifndef __LOG_STORE_LK_H__
  38. #define __LOG_STORE_LK_H__
  39. #include <stdio.h>
  40. #include <string.h>
  41. #include <platform/mt_typedefs.h>
  42. #include "ram_console.h"
  43. #ifdef LK_LOG_LEVEL_SUPPORT
  44. #define LOG_LEVEL_MASK (0xABC0)
  45. #endif
  46. #define SRAM_HEADER_SIG (0xabcd1234)
  47. #define DRAM_HEADER_SIG (0x5678ef90)
  48. #define LOG_STORE_SIG (0xcdab3412)
  49. #define LOG_EMMC_SIG (0x785690ef)
  50. #define FLAG_DISABLE 0X44495341 // acsii-DISA
  51. #define FLAG_ENABLE 0X454E454E // acsii-ENEN
  52. #define MAX_DRAM_COUNT 2
  53. #define LOG_STORE_SIZE 0x40000 /* DRAM buff 256KB */
  54. #define LOG_STORE_SIZE_MIRROR 0x40000 /* mirror DRAM buff 256KB */
  55. /* log flag */
  56. #define BUFF_VALID 0x01
  57. #define CAN_FREE 0x02
  58. #define NEED_SAVE_TO_EMMC 0x04
  59. #define RING_BUFF 0x08
  60. /* ring buf, if buf_full, buf_point is the start of the buf, else buf_point is the buf end, other buf is not used */
  61. #define BUFF_FULL 0x10 /* buf is full */
  62. #define ARRAY_BUFF 0X20 /* array buf type, buf_point is the used buf end */
  63. #define BUFF_ALLOC_ERROR 0X40
  64. #define BUFF_ERROR 0x80
  65. #define BUFF_NOT_READY 0x100
  66. #define BUFF_READY 0x200
  67. /* total 32 bytes <= u32(4 bytes) * 8 = 32 bytes */
  68. struct pl_lk_log {
  69. u32 sig; // default 0xabcd1234
  70. u32 buff_size; // total buf size
  71. u32 off_pl; // pl offset, sizeof(struct pl_lk_log)
  72. u32 sz_pl; // preloader size
  73. u32 pl_flag; // pl log flag
  74. u32 off_lk; // lk offset, sizeof((struct pl_lk_log) + sz_pl
  75. u32 sz_lk; // lk log size
  76. u32 lk_flag; // lk log flag
  77. };
  78. /* total 40 bytes <= u32(4 bytes) * 10 = 40 bytes */
  79. struct dram_buf_header {
  80. u32 sig;
  81. u32 flag;
  82. u32 buf_addr;
  83. u32 buf_size;
  84. u32 buf_offsize;
  85. u32 buf_point;
  86. u32 klog_addr;
  87. u32 klog_size;
  88. u32 atf_log_addr;
  89. u32 atf_log_len;
  90. } __attribute__((packed));
  91. /* total 256 bytes */
  92. struct sram_log_header {
  93. u32 sig;
  94. u32 reboot_count;
  95. u32 save_to_emmc;
  96. struct dram_buf_header dram_buf; // 40 bytes
  97. struct pl_lk_log dram_curlog_header; // 32 bytes
  98. u32 gz_log_addr;
  99. u32 gz_log_len;
  100. u32 reserve[41]; // reserve 41 * 4 char size(164 bytes)
  101. /* reserve[0] sram_log record log size */
  102. /* reserve[1] save block size for kernel use*/
  103. } __attribute__((packed));
  104. #define SRAM_RECORD_LOG_SIZE 0X00
  105. #define SRAM_BLOCK_SIZE 0x01
  106. #define SRAM_PMIC_BOOT_PHASE 0x02
  107. /* emmc last block struct */
  108. struct log_emmc_header {
  109. u32 sig;
  110. u32 offset;
  111. //u32 uart_flag;
  112. u32 reserve_flag[11];
  113. /* [0] used to save uart flag */
  114. /* [1] used to save emmc_log index */
  115. /* [2] used to save printk ratalimit flag */
  116. /* [3] used to save kedump contrl flag */
  117. /* [4] used to save boot step */
  118. };
  119. enum EMMC_STORE_FLAG_TYPE {
  120. UART_LOG = 0x00,
  121. LOG_INDEX = 0X01,
  122. PRINTK_RATELIMIT = 0X02,
  123. KEDUMP_CTL = 0x03,
  124. BOOT_STEP = 0x04,
  125. EMMC_STORE_FLAG_TYPE_NR,
  126. };
  127. #define BOOT_PHASE_MASK 0xf // b1111
  128. #define NOW_BOOT_PHASE_SHIFT 0x0
  129. #define LAST_BOOT_PHASE_SHIFT 0x4
  130. #define PMIC_BOOT_PHASE_SHIFT 0x8
  131. #define PMIC_LAST_BOOT_PHASE_SHIFT 0Xc
  132. #define HEADER_INDEX_MAX 0x10
  133. /* emmc store log */
  134. struct emmc_log {
  135. u32 type;
  136. u32 start;
  137. u32 end;
  138. };
  139. #define LOG_PLLK 0x01
  140. #define LOG_PL 0x02
  141. #define LOG_KERNEL 0x03
  142. #define LOG_ATF 0x04
  143. #define LOG_GZ 0x05
  144. #define LOG_LAST_KERNEL 0x06
  145. #define BOOT_PHASE_PL 0x01
  146. #define BOOT_PHASE_LK 0x02
  147. #define BOOT_PHASE_KERNEL 0x03
  148. #define BOOT_PHASE_ANDROID 0x04
  149. #define BOOT_PHASE_PL_COLD_REBOOT 0X05
  150. #define BOOT_PHASE_SUSPEND 0x06
  151. #define BOOT_PHASE_RESUME 0X07
  152. #ifdef LOG_STORE_SUPPORT
  153. extern bool log_store_enable;
  154. void set_uart_log_flag(bool enable);
  155. void set_printk_ratelimit(bool enable);
  156. void read_ratelimit_config(void);
  157. int read_kedump_config(void);
  158. void lk_log_store(char c);
  159. u32 mirror_buf_addr_get(void);
  160. u32 mirror_buf_pl_lk_log_size_get(void);
  161. u32 current_buf_addr_get(void);
  162. u32 current_lk_buf_addr_get(void);
  163. u32 current_buf_pl_lk_log_size_get(void);
  164. void save_pllk_log(void);
  165. u32 get_last_boot_phase(void);
  166. void set_boot_phase(u32 step);
  167. #else /* no log store feature set function null*/
  168. inline void set_uart_log_flag(bool enable){}
  169. inline void set_printk_ratelimit(bool enable){}
  170. inline void read_ratelimit_config(void){}
  171. inline int read_kedump_config(void)
  172. {
  173. return 1;
  174. }
  175. inline void lk_log_store(char c){}
  176. inline u32 mirror_buf_addr_get(void){return 0;}
  177. inline u32 mirror_buf_pl_lk_log_size_get(void){return 0;}
  178. inline u32 current_buf_addr_get(void){return 0;}
  179. inline u32 current_lk_buf_addr_get(void){return 0;}
  180. inline u32 current_buf_pl_lk_log_size_get(void){return 0;}
  181. inline void save_pllk_log(void){}
  182. inline u32 get_last_boot_phase(void){return 0;}
  183. inline void set_boot_phase(u32 step) {};
  184. #endif
  185. #endif