mtk_auxadc.c 8.8 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. /*****************************************************************************
  32. *
  33. * Filename:
  34. * ---------
  35. * mt6582_auxadc.c
  36. *
  37. * Project:
  38. * --------
  39. * Android_Software
  40. *
  41. * Description:
  42. * ------------
  43. * This Module defines functions of mt6573 AUXADC
  44. *
  45. * Author:
  46. * -------
  47. * James Lo
  48. *
  49. ****************************************************************************/
  50. //#include <common.h>
  51. //#include <asm/io.h>
  52. #include <stdio.h>
  53. #include <platform/mt_gpt.h>
  54. #include <platform/mtk_auxadc_sw.h>
  55. #include <platform/mtk_auxadc_hw.h>
  56. #include <platform/mt_reg_base.h>
  57. ///////////////////////////////////////////////////////////////////////////////////////////
  58. //// Define
  59. static int adc_auto_set =0;
  60. static int adc_rtp_set =1;
  61. static unsigned short mt_tpd_read_adc(unsigned short pos)
  62. {
  63. *(volatile unsigned short *)AUXADC_TP_ADDR = pos;
  64. *(volatile unsigned short *)AUXADC_TP_CON0 = 0x01;
  65. while (0x01 & *(volatile unsigned short *)AUXADC_TP_CON0) { ; } //wait for write finish
  66. return *(volatile unsigned short *)AUXADC_TP_DATA0;
  67. }
  68. #define CLK_GATING_CTRL1 (TOPCKGEN_BASE + 0x24)
  69. #define SET_CLK_GATING_CTRL1 (TOPCKGEN_BASE + 0x54)
  70. #define CLR_CLK_GATING_CTRL1 (TOPCKGEN_BASE + 0x84)
  71. #define MT_CG_ADC_SW_CG 30
  72. #define ADC_SET_BITS(REG, BS) ((*(volatile unsigned int*)(REG)) |= (unsigned int)(BS))
  73. #define ADC_CLR_BITS(REG, BS) ((*(volatile unsigned int*)(REG)) &= ~((unsigned int)(BS)))
  74. void mt_ADC_power_on()
  75. {
  76. ADC_SET_BITS(CLR_CLK_GATING_CTRL1, (1<<MT_CG_ADC_SW_CG));
  77. // ADCDBG("enable_clock ADC\n");
  78. mdelay(100);
  79. }
  80. void mt_ADC_power_off ()
  81. {
  82. ADC_SET_BITS(SET_CLK_GATING_CTRL1, (1<<(MT_CG_ADC_SW_CG))); //disable clock
  83. // ADCDBG("disable_clock ADC\n");
  84. }
  85. static void mt_auxadc_disable_penirq(void)
  86. {
  87. //disable RTP
  88. if (adc_rtp_set) {
  89. adc_rtp_set = 0;
  90. *(volatile unsigned short *)AUXADC_CON_RTP = 1;
  91. }
  92. //Turn off PENIRQ detection circuit
  93. *(volatile unsigned short *)AUXADC_TP_CMD = 1;
  94. //run once touch function
  95. mt_tpd_read_adc(TP_CMD_ADDR_X);
  96. }
  97. //step1 check con3 if auxadc is busy
  98. //step2 clear bit
  99. //step3 read channle and make sure old ready bit ==0
  100. //step4 set bit to trigger sample
  101. //step5 read channle and make sure ready bit ==1
  102. //step6 read data
  103. ///////////////////////////////////////////////////////////////////////////////////////////
  104. ///////////////////////////////////////////////////////////////////////////////////////////
  105. //// Common API
  106. int IMM_GetOneChannelValue(int dwChannel, int data[4], int* rawdata)
  107. {
  108. unsigned int channel[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
  109. int idle_count =0;
  110. int data_ready_count=0;
  111. // mutex_lock(&mutex_get_cali_value);
  112. /* in uboot no pms api
  113. if(enable_clock(MT65XX_PDN_PERI_AUXADC,"AUXADC"))
  114. {
  115. //dprintf(1,"hwEnableClock AUXADC !!!.");
  116. if(enable_clock(MT65XX_PDN_PERI_AUXADC,"AUXADC"))
  117. {dprintf(1,"hwEnableClock AUXADC failed.");}
  118. }
  119. */
  120. mt_ADC_power_on();
  121. if (dwChannel == PAD_AUX_XP)mt_auxadc_disable_penirq();
  122. //step1 check con3 if auxadc is busy
  123. while ((*(volatile unsigned short *)AUXADC_CON2) & 0x01) {
  124. dprintf(1,"[adc_api]: wait for module idle\n");
  125. udelay(10000);
  126. idle_count++;
  127. if (idle_count>30) {
  128. //wait for idle time out
  129. dprintf(1,"[adc_api]: wait for aux/adc idle time out\n");
  130. return -1;
  131. }
  132. }
  133. // step2 clear bit
  134. if (0 == adc_auto_set) {
  135. //clear bit
  136. *(volatile unsigned short *)AUXADC_CON1 = *(volatile unsigned short *)AUXADC_CON1 & (~(1 << dwChannel));
  137. }
  138. //step3 read channle and make sure old ready bit ==0
  139. while ((*(volatile unsigned short *)(AUXADC_DAT0 + dwChannel * 0x04)) & (1<<12)) {
  140. dprintf(1,"[adc_api]: wait for channel[%d] ready bit clear\n",dwChannel);
  141. udelay(10000);
  142. data_ready_count++;
  143. if (data_ready_count>30) {
  144. //wait for idle time out
  145. dprintf(1,"[adc_api]: wait for channel[%d] ready bit clear time out\n",dwChannel);
  146. return -2;
  147. }
  148. }
  149. //step4 set bit to trigger sample
  150. if (0==adc_auto_set) {
  151. *(volatile unsigned short *)AUXADC_CON1 = *(volatile unsigned short *)AUXADC_CON1 | (1 << dwChannel);
  152. }
  153. //step5 read channle and make sure ready bit ==1
  154. udelay(25);//we must dealay here for hw sample channel data
  155. while (0==((*(volatile unsigned short *)(AUXADC_DAT0 + dwChannel * 0x04)) & (1<<12))) {
  156. dprintf(1,"[adc_api]: wait for channel[%d] ready bit ==1\n",dwChannel);
  157. udelay(10000);
  158. data_ready_count++;
  159. if (data_ready_count>30) {
  160. //wait for idle time out
  161. dprintf(1,"[adc_api]: wait for channel[%d] data ready time out\n",dwChannel);
  162. return -3;
  163. }
  164. }
  165. ////step6 read data
  166. channel[dwChannel] = (*(volatile unsigned short *)(AUXADC_DAT0 + dwChannel * 0x04)) & 0x0FFF;
  167. if (rawdata) {
  168. *rawdata = channel[dwChannel];
  169. }
  170. //dprintf(1,"[adc_api: imm mode raw data => channel[%d] = %d\n",dwChannel, channel[dwChannel]);
  171. //dprintf(1,"[adc_api]: imm mode => channel[%d] = %d.%d\n", dwChannel, (channel[dwChannel] * 250 / 4096 / 100), ((channel[dwChannel] * 250 / 4096) % 100));
  172. data[0] = (channel[dwChannel] * 150 / 4096 / 100);
  173. data[1] = ((channel[dwChannel] * 150 / 4096) % 100);
  174. /*
  175. if(disable_clock(MT65XX_PDN_PERI_AUXADC,"AUXADC"))
  176. {
  177. dprintf(1,"hwEnableClock AUXADC failed.");
  178. }
  179. mutex_unlock(&mutex_get_cali_value);
  180. */
  181. mt_ADC_power_off();
  182. return 0;
  183. }
  184. // 1v == 1000000 uv
  185. // this function voltage Unit is uv
  186. int IMM_GetOneChannelValue_Cali(int Channel, int*voltage)
  187. {
  188. int ret = 0, data[4], rawvalue;
  189. ret = IMM_GetOneChannelValue( Channel, data, &rawvalue);
  190. if (ret) {
  191. ret = IMM_GetOneChannelValue( Channel, data, &rawvalue);
  192. if (ret) {
  193. dprintf(1,"[adc_api]:IMM_GetOneChannelValue_Cali get raw value error %d \n",ret);
  194. return -1;
  195. }
  196. }
  197. //*voltage = rawvalue*1500000 / 4096;
  198. *voltage = (int)((long long)rawvalue*1500000 / (long long)4096);
  199. //dprintf(1,"[adc_api]:IMM_GetOneChannelValue_Cali voltage= %d uv \n",*voltage);
  200. return 0;
  201. }
  202. static int IMM_auxadc_get_evrage_data(int times, int Channel)
  203. {
  204. int ret = 0, data[4], i, ret_value = 0, ret_temp = 0;
  205. i = times;
  206. while (i--) {
  207. ret_value = IMM_GetOneChannelValue(Channel, data, &ret_temp);
  208. ret += ret_temp;
  209. dprintf(1,"[auxadc_get_data(channel%d)]: ret_temp=%d, ret = %d.\n",Channel,ret_temp,ret_value);
  210. }
  211. ret = ret / times;
  212. return ret;
  213. }
  214. int auxadc_test(void )
  215. {
  216. int i = 0, data[4] = {0,0,0,0};
  217. int res =0;
  218. int rawdata=0;
  219. //int Voltiage_cali =0;
  220. for (i = 0; i < 16; i++) {
  221. //dprintf(1,"[adc_driver]: i=%d\n",i);
  222. res = IMM_GetOneChannelValue(i,data,&rawdata);
  223. if (res < 0) {
  224. dprintf(1,"[adc_lk]: get data error\n");
  225. break;
  226. } else {
  227. dprintf(1,"[adc_lk]: channel[%d]raw =%d\n",i,rawdata);
  228. //dprintf(1,"[adc_lk]: channel[%d]=%d.%.02d \n",i,data[0],data[1]);
  229. }
  230. #if 0
  231. res= IMM_GetOneChannelValue_Cali(i, &Voltiage_cali);
  232. if (res < 0) {
  233. dprintf(1,"[adc_driver]: get cali voltage error\n");
  234. break;
  235. } else {
  236. dprintf(1,"[adc_driver]: channel[%d] cali_voltage =%d\n",i,Voltiage_cali);
  237. }
  238. #endif
  239. }
  240. return 0;
  241. }
  242. ///////////////////////////////////////////////////////////////////////////////////////////