msdc_tune_async.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509
  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #if defined(FEATURE_ASYNC_PATH_ENABLE)
  32. #if defined(FEATURE_MMC_CM_TUNING)
  33. int msdc_async_tune_cmd(struct mmc_host *host, struct mmc_command *cmd)
  34. {
  35. int result = MMC_ERR_CMDTUNEFAIL;
  36. unsigned int orig_rsmpl, cur_rsmpl, rsmpl, orig_clkmode;
  37. unsigned int orig_dly1 = 0, orig_dly1_sel, cur_dly1;
  38. unsigned int orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly2_sel;
  39. unsigned int orig_dly = 0, cur_dly;
  40. unsigned int dly;
  41. u32 base = host->base;
  42. u8 hs400 = 0;
  43. MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
  44. hs400 = (orig_clkmode == 3) ? 1 : 0;
  45. MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
  46. if (!host->base_top) {
  47. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRDLY, orig_dly1);
  48. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL, orig_dly1_sel);
  49. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE1_CMDRDLY2, orig_dly2);
  50. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE1_CMDRRDLY2SEL, orig_dly2_sel);
  51. } else {
  52. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, orig_dly1);
  53. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL, orig_dly1_sel);
  54. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY2, orig_dly2);
  55. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY2_SEL, orig_dly2_sel);
  56. }
  57. orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
  58. //printf("BBB1 %x %x %x\n", MSDC_READ32(0x112400b0), MSDC_READ32(0x112400b4), MSDC_READ32(0x112400b8));
  59. dly = 0;
  60. do {
  61. for (rsmpl = 0; rsmpl < 2; rsmpl++) {
  62. cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
  63. msdc_set_smpl(host, hs400, cur_rsmpl, TYPE_CMD_RESP_EDGE);
  64. if (host->cur_bus_clk <= 400000) {
  65. msdc_set_smpl(host, hs400, 0, TYPE_CMD_RESP_EDGE);
  66. }
  67. if (cmd->opcode != MMC_CMD_STOP_TRANSMISSION) {
  68. if (host->app_cmd){
  69. host->app_cmd = false;
  70. result = msdc_app_cmd(host);
  71. host->app_cmd = true;
  72. if (result != MMC_ERR_NONE)
  73. return MMC_ERR_CMDTUNEFAIL;
  74. }
  75. result = msdc_send_cmd(host, cmd);
  76. if (result == MMC_ERR_TIMEOUT)
  77. rsmpl--;
  78. if (result != MMC_ERR_NONE && cmd->opcode != MMC_CMD_STOP_TRANSMISSION) {
  79. if (cmd->opcode == MMC_CMD_READ_MULTIPLE_BLOCK
  80. || cmd->opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK
  81. || cmd->opcode == MMC_CMD_READ_SINGLE_BLOCK
  82. || cmd->opcode == MMC_CMD_WRITE_BLOCK
  83. || cmd->opcode == MMC_CMD_SEND_WRITE_PROT_TYPE)
  84. msdc_abort_handler(host,1);
  85. continue;
  86. }
  87. result = msdc_wait_rsp(host, cmd);
  88. } else if (cmd->opcode == MMC_CMD_STOP_TRANSMISSION) {
  89. result = MMC_ERR_NONE;
  90. goto Pass;
  91. } else
  92. result = MMC_ERR_BADCRC;
  93. #if MSDC_TUNE_LOG
  94. /* for debugging */
  95. {
  96. u32 t_dly1, t_dly2, t_dly1_sel, t_dly2_sel, t_rsmpl;
  97. MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_RSPL, t_rsmpl);
  98. if (!host->base_top) {
  99. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRDLY, t_dly1);
  100. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL, t_dly1_sel);
  101. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRDLY2, t_dly2);
  102. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRRDLY2SEL, t_dly2_sel);
  103. } else {
  104. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, t_dly1);
  105. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL, t_dly1_sel);
  106. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY2, t_dly2);
  107. MSDC_GET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY2_SEL, t_dly2_sel);
  108. }
  109. times++;
  110. MSG(INF, "[SD%d] <TUNE_CMD%d><%d><%s> CMDRRDLY=%d, RSPL=%dh\n",
  111. host->id, (cmd->opcode & (~(SD_CMD_BIT | SD_CMD_APP_BIT))),
  112. times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
  113. t_dly1 * t_dly1_sel + t_dly2 * t_dly2_sel, t_rsmpl);
  114. MSG(INF, "[SD%d] <TUNE_CMD><%d><%s> CMDRRDLY1=%xh, CMDRRDLY1SEL=%x,"
  115. " CMDRRDLY2=%xh, CMDRRDLY2SEL=%xh\n",
  116. host->id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
  117. t_dly1, t_dly1_sel, t_dly2, t_dly2_sel);
  118. }
  119. #endif
  120. if (result == MMC_ERR_NONE) {
  121. host->app_cmd = false;
  122. goto Pass;
  123. }
  124. if (cmd->opcode == MMC_CMD_READ_MULTIPLE_BLOCK
  125. || cmd->opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK
  126. || cmd->opcode == MMC_CMD_READ_SINGLE_BLOCK
  127. ||cmd->opcode == MMC_CMD_WRITE_BLOCK)
  128. msdc_abort_handler(host,1);
  129. }
  130. cur_dly = (orig_dly + dly + 1) % 63;
  131. if (cur_dly < 32) {
  132. cur_dly1 = cur_dly;
  133. cur_dly2 = 0;
  134. cur_dly2_sel = 0;
  135. } else {
  136. cur_dly1 = 31;
  137. cur_dly2 = cur_dly - 31;
  138. cur_dly2_sel = 1;
  139. }
  140. if (!host->base_top) {
  141. MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRRDLYSEL);
  142. MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_CMDRDLY, cur_dly1);
  143. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRDLY2, cur_dly2);
  144. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_CMDRRDLY2SEL, cur_dly2_sel);
  145. } else {
  146. MSDC_SET_BIT32(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL);
  147. MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY, cur_dly1);
  148. MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RXDLY2, cur_dly2);
  149. MSDC_SET_FIELD(EMMC_TOP_CMD, PAD_CMD_RD_RXDLY2_SEL, cur_dly2_sel);
  150. }
  151. } while (++dly <= 62);
  152. MSG(INF, "Msdc async tune CMD failed\n");
  153. return MMC_ERR_CMDTUNEFAIL;
  154. Pass:
  155. MSG(INF, "Msdc async tune CMD Pass\n");
  156. return result;
  157. }
  158. #endif
  159. #if defined(FEATURE_MMC_RD_TUNING)
  160. int msdc_async_tune_bread(struct mmc_host *host, uchar *dst, ulong src, ulong nblks)
  161. {
  162. int result = MMC_ERR_CMDTUNEFAIL;
  163. unsigned int orig_rdsmpl, cur_rdsmpl, rdsmpl, orig_clkmode;
  164. unsigned int rdsmpl_end;
  165. unsigned int orig_dly1 = 0, orig_dly1_sel, cur_dly1;
  166. unsigned int orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly2_sel;
  167. unsigned int orig_dly = 0, cur_dly;
  168. unsigned int dly;
  169. u32 dcrc = 0;
  170. u32 hs400;
  171. u32 base = host->base;
  172. u8 ddr = 0;
  173. MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
  174. hs400 = (orig_clkmode==3) ? 1 : 0;
  175. if (orig_clkmode==2 || orig_clkmode==3)
  176. ddr = 1;
  177. else
  178. ddr = 0;
  179. MSDC_GET_FIELD(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL, orig_rdsmpl);
  180. if (!host->base_top) {
  181. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, orig_dly1);
  182. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, orig_dly1_sel);
  183. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, orig_dly2);
  184. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, orig_dly2_sel);
  185. } else {
  186. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, orig_dly1);
  187. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, orig_dly1_sel);
  188. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, orig_dly2);
  189. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, orig_dly2_sel);
  190. }
  191. orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
  192. if (ddr)
  193. rdsmpl_end = 0;
  194. else
  195. rdsmpl_end = 1;
  196. dly = 0;
  197. do {
  198. for (rdsmpl = 0; rdsmpl <= rdsmpl_end; rdsmpl++) {
  199. cur_rdsmpl = (orig_rdsmpl + rdsmpl) % 2;
  200. msdc_set_smpl(host, hs400, cur_rdsmpl, TYPE_READ_DATA_EDGE);
  201. result = host->blk_read(host, dst, src, nblks);
  202. if (result == MMC_ERR_CMDTUNEFAIL || result == MMC_ERR_CMD_RSPCRC || result == MMC_ERR_ACMD_RSPCRC)
  203. goto Pass;
  204. MSDC_GET_FIELD(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc);
  205. #if MSDC_TUNE_LOG
  206. /* for debugging */
  207. {
  208. u32 t_dly1, t_dly2, t_dly1_sel, t_dly2_sel, t_rdsmpl;
  209. times++;
  210. if (hs400)
  211. MSDC_GET_FIELD(MSDC_IOCON, MSDC_IOCON_R_D_SMPL, t_rdsmpl);
  212. else
  213. MSDC_GET_FIELD(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL, t_rdsmpl);
  214. if (!host->base_top) {
  215. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, t_dly1);
  216. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, t_dly1_sel);
  217. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, t_dly2);
  218. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, t_dly2_sel);
  219. } else {
  220. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, t_dly1);
  221. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, t_dly1_sel);
  222. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, t_dly2);
  223. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, t_dly2_sel);
  224. }
  225. MSG(INF, "[SD%d] <TUNE_READ><%d><%s> DATRRDLY=%d, RSPL=%dh\n",
  226. host->id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
  227. t_dly1 * t_dly1_sel + t_dly2 * t_dly2_sel, t_rdsmpl);
  228. MSG(INF, "[SD%d] <TUNE_READ><%d><%s> DATRRDLY1=%xh, DATRRDLY1SEL=%x,"
  229. " DATRRDLY2=%xh, DATRRDLY2SEL=%xh\n",
  230. host->id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
  231. t_dly1, t_dly1_sel, t_dly2, t_dly2_sel);
  232. }
  233. #endif
  234. if (result == MMC_ERR_NONE && dcrc == 0) {
  235. goto Pass;
  236. } else {
  237. result = MMC_ERR_BADCRC;
  238. }
  239. }
  240. cur_dly = (orig_dly + dly + 1) % 63;
  241. if (cur_dly < 32) {
  242. cur_dly1 = cur_dly;
  243. cur_dly2 = 0;
  244. cur_dly2_sel = 0;
  245. } else {
  246. cur_dly1 = 31;
  247. cur_dly2 = cur_dly - 31;
  248. cur_dly2_sel = 1;
  249. }
  250. if (!host->base_top) {
  251. MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
  252. MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, cur_dly1);
  253. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, cur_dly2);
  254. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, cur_dly2_sel);
  255. } else {
  256. MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
  257. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, cur_dly1);
  258. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, cur_dly2);
  259. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, cur_dly2_sel);
  260. }
  261. } while (dly++ <= 62);
  262. MSG(INF, "Msdc async tune bread failed\n");
  263. return MMC_ERR_CMDTUNEFAIL;
  264. Pass:
  265. MSG(INF, "Msdc async tune bread Pass\n");
  266. return result;
  267. }
  268. int msdc_async_tune_read(struct mmc_host *host)
  269. {
  270. int result = MMC_ERR_CMDTUNEFAIL;
  271. unsigned int orig_rdsmpl, cur_rdsmpl, orig_clkmode;
  272. unsigned int orig_dly1 = 0, orig_dly1_sel, cur_dly1;
  273. unsigned int orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly2_sel;
  274. unsigned int orig_dly = 0, cur_dly;
  275. unsigned int hs400;
  276. u32 base = host->base;
  277. u32 tune_limit_times;
  278. u8 ddr = 0;
  279. MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
  280. hs400 = (orig_clkmode==3) ? 1 : 0;
  281. if (orig_clkmode==2 || orig_clkmode==3)
  282. ddr = 1;
  283. else
  284. ddr = 0;
  285. if (ddr) {
  286. tune_limit_times = 64;
  287. } else {
  288. tune_limit_times = 127;
  289. MSDC_GET_FIELD(MSDC_PATCH_BIT0, MSDC_PB0_RD_DAT_SEL, orig_rdsmpl);
  290. cur_rdsmpl = (orig_rdsmpl + 1) % 2;
  291. msdc_set_smpl(host, hs400, cur_rdsmpl, TYPE_READ_DATA_EDGE);
  292. if (cur_rdsmpl == 1)
  293. goto out;
  294. }
  295. if (!host->base_top) {
  296. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, orig_dly1);
  297. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, orig_dly1_sel);
  298. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, orig_dly2);
  299. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, orig_dly2_sel);
  300. } else {
  301. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, orig_dly1);
  302. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, orig_dly1_sel);
  303. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, orig_dly2);
  304. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, orig_dly2_sel);
  305. }
  306. orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
  307. cur_dly = (orig_dly + 1) % 63;
  308. if (cur_dly < 32) {
  309. cur_dly1 = cur_dly;
  310. cur_dly2 = 0;
  311. cur_dly2_sel = 0;
  312. } else {
  313. cur_dly1 = 31;
  314. cur_dly2 = cur_dly - 31;
  315. cur_dly2_sel = 1;
  316. }
  317. if (!host->base_top) {
  318. MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
  319. MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, cur_dly1);
  320. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, cur_dly2);
  321. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, cur_dly2_sel);
  322. } else {
  323. MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
  324. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, cur_dly1);
  325. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, cur_dly2);
  326. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, cur_dly2_sel);
  327. }
  328. out:
  329. ++(host->time_read);
  330. if (host->time_read == tune_limit_times)
  331. result = MMC_ERR_READTUNEFAIL;
  332. return result;
  333. }
  334. #endif
  335. #if defined(FEATURE_MMC_WR_TUNING)
  336. int msdc_async_tune_bwrite(struct mmc_host *host, ulong dst, uchar *src, ulong nblks)
  337. {
  338. int result = MMC_ERR_CMDTUNEFAIL;
  339. unsigned int orig_dsmpl, cur_dsmpl, dsmpl, dsmpl_end, orig_clkmode;
  340. unsigned int orig_dly1 = 0, orig_dly1_sel, cur_dly1;
  341. unsigned int orig_dly2 = 0, orig_dly2_sel, cur_dly2, cur_dly2_sel;
  342. unsigned int orig_dly = 0, cur_dly;
  343. unsigned int dly;
  344. u32 base = host->base;
  345. u8 hs400 = 0, ddr;
  346. MSDC_GET_FIELD(MSDC_CFG, MSDC_CFG_CKMOD, orig_clkmode);
  347. hs400 = (orig_clkmode == 3) ? 1 : 0;
  348. if (orig_clkmode==2 || orig_clkmode==3)
  349. ddr = 1;
  350. else
  351. ddr = 0;
  352. if (host->id==0) {
  353. if (hs400)
  354. MSDC_GET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_EDGE, orig_dsmpl);
  355. else
  356. MSDC_GET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, orig_dsmpl);
  357. } else {
  358. MSDC_GET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, orig_dsmpl);
  359. }
  360. if (!host->base_top) {
  361. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, orig_dly1);
  362. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, orig_dly1_sel);
  363. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, orig_dly2);
  364. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, orig_dly2_sel);
  365. } else {
  366. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, orig_dly1);
  367. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, orig_dly1_sel);
  368. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, orig_dly2);
  369. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, orig_dly2_sel);
  370. }
  371. orig_dly = orig_dly1 * orig_dly1_sel + orig_dly2 * orig_dly2_sel;
  372. if (ddr)
  373. dsmpl_end = 0;
  374. else
  375. dsmpl_end = 1;
  376. dly = 0;
  377. do {
  378. for (dsmpl = 0; dsmpl <= dsmpl_end; dsmpl++) {
  379. cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
  380. msdc_set_smpl(host, hs400, cur_dsmpl, TYPE_WRITE_CRC_EDGE);
  381. result = host->blk_write(host, dst, src, nblks);
  382. if (result == MMC_ERR_CMDTUNEFAIL || result == MMC_ERR_CMD_RSPCRC || result == MMC_ERR_ACMD_RSPCRC)
  383. goto Pass;
  384. #if MSDC_TUNE_LOG
  385. /* for debugging */
  386. {
  387. u32 t_dly1, t_dly2, t_dly1_sel, t_dly2_sel, t_dsmpl;
  388. times++;
  389. if (hs400)
  390. MSDC_GET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_CRC_STS_EDGE, t_dsmpl);
  391. else
  392. MSDC_GET_FIELD(MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, t_dsmpl);
  393. if (!host->base_top) {
  394. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, t_dly1);
  395. MSDC_GET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL, t_dly1_sel);
  396. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, t_dly2);
  397. MSDC_GET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, t_dly2_sel);
  398. } else {
  399. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, t_dly1);
  400. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL, t_dly1_sel);
  401. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, t_dly2);
  402. MSDC_GET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, t_dly2_sel);
  403. }
  404. MSG(INF, "[SD%d] <TUNE_WRITE><%d><%s> DATRRDLY=%d, RDSPL=%dh\n",
  405. host->id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
  406. t_dly1 * t_dly1_sel + t_dly2 * t_dly2_sel, t_dsmpl);
  407. MSG(INF, "[SD%d] <TUNE_WRITE><%d><%s> DATRRDLY1=%xh, DATRRDLY1SEL=%x,"
  408. " DATRRDLY2=%xh, DATRRDLY2SEL=%xh\n",
  409. host->id, times, (result == MMC_ERR_NONE) ? "PASS" : "FAIL",
  410. t_dly1, t_dly1_sel, t_dly2, t_dly2_sel);
  411. }
  412. #endif
  413. if (result == MMC_ERR_NONE) {
  414. goto Pass;
  415. } else {
  416. result = MMC_ERR_BADCRC;
  417. }
  418. }
  419. cur_dly = (orig_dly + dly + 1) % 63;
  420. if (cur_dly < 32) {
  421. cur_dly1 = cur_dly;
  422. cur_dly2 = 0;
  423. cur_dly2_sel = 0;
  424. } else {
  425. cur_dly1 = 31;
  426. cur_dly2 = cur_dly - 31;
  427. cur_dly2_sel = 1;
  428. }
  429. if (!host->base_top) {
  430. MSDC_SET_BIT32(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLYSEL);
  431. MSDC_SET_FIELD(MSDC_PAD_TUNE0, MSDC_PAD_TUNE0_DATRRDLY, cur_dly1);
  432. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2, cur_dly2);
  433. MSDC_SET_FIELD(MSDC_PAD_TUNE1, MSDC_PAD_TUNE1_DATRRDLY2SEL, cur_dly2_sel);
  434. } else {
  435. MSDC_SET_BIT32(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY_SEL);
  436. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY, cur_dly1);
  437. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2, cur_dly2);
  438. MSDC_SET_FIELD(EMMC_TOP_CONTROL, PAD_DAT_RD_RXDLY2_SEL, cur_dly2_sel);
  439. }
  440. } while (dly++ <= 62);
  441. MSG(INF, "Msdc async tune bwrite failed\n");
  442. return MMC_ERR_CMDTUNEFAIL;
  443. Pass:
  444. MSG(INF, "Msdc async tune bwrite Pass\n");
  445. return result;
  446. }
  447. #endif
  448. #endif