mtk-lk/platform/mt6785/include/platform/mtk_dcm.h

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#ifndef __MTK_DCM_H__
#define __MTK_DCM_H__

/* #define DCM_DEFAULT_ALL_OFF */
/* #define DCM_BRINGUP */

#define DCM_OFF (0)
#define DCM_ON (1)

/* Note: ENABLE_DCM_IN_LK is used in kernel if DCM is enabled in LK */
#define ENABLE_DCM_IN_LK
#ifdef ENABLE_DCM_IN_LK
#define INIT_DCM_TYPE_BY_K	0
#endif

/* MT6785 big core DCM in AO domain. */
/* #define CTRL_BIGCORE_DCM_IN_KERNEL */

typedef enum {
	ARMCORE_DCM_OFF = DCM_OFF,
	ARMCORE_DCM_MODE1 = DCM_ON,
	ARMCORE_DCM_MODE2 = DCM_ON+1,
} ENUM_ARMCORE_DCM;

typedef enum {
	INFRA_DCM_OFF = DCM_OFF,
	INFRA_DCM_ON = DCM_ON,
} ENUM_INFRA_DCM;

typedef enum {
	PERI_DCM_OFF = DCM_OFF,
	PERI_DCM_ON = DCM_ON,
} ENUM_PERI_DCM;

typedef enum {
	MCUSYS_DCM_OFF = DCM_OFF,
	MCUSYS_DCM_ON = DCM_ON,
} ENUM_MCUSYS_DCM;

typedef enum {
	DRAMC_AO_DCM_OFF = DCM_OFF,
	DRAMC_AO_DCM_ON = DCM_ON,
} ENUM_DRAMC_AO_DCM;

typedef enum {
	DDRPHY_DCM_OFF = DCM_OFF,
	DDRPHY_DCM_ON = DCM_ON,
} ENUM_DDRPHY_DCM;

typedef enum {
	EMI_DCM_OFF = DCM_OFF,
	EMI_DCM_ON = DCM_ON,
} ENUM_EMI_DCM;

typedef enum {
	STALL_DCM_OFF = DCM_OFF,
	STALL_DCM_ON = DCM_ON,
} ENUM_STALL_DCM;

typedef enum {
	BIG_CORE_DCM_OFF = DCM_OFF,
	BIG_CORE_DCM_ON = DCM_ON,
} ENUM_BIG_CORE_DCM;

typedef enum {
	GIC_SYNC_DCM_OFF = DCM_OFF,
	GIC_SYNC_DCM_ON = DCM_ON,
} ENUM_GIC_SYNC_DCM;

typedef enum {
	LAST_CORE_DCM_OFF = DCM_OFF,
	LAST_CORE_DCM_ON = DCM_ON,
} ENUM_LAST_CORE_DCM;

typedef enum {
	RGU_DCM_OFF = DCM_OFF,
	RGU_DCM_ON = DCM_ON,
} ENUM_RGU_DCM;

typedef enum {
	TOPCKG_DCM_OFF = DCM_OFF,
	TOPCKG_DCM_ON = DCM_ON,
} ENUM_TOPCKG_DCM;

typedef enum {
	LPDMA_DCM_OFF = DCM_OFF,
	LPDMA_DCM_ON = DCM_ON,
} ENUM_LPDMA_DCM;

typedef enum {
	PWRAP_DCM_OFF = DCM_OFF,
	PWRAP_DCM_ON = DCM_ON,
} ENUM_PWRAP_DCM;

typedef enum {
	MCSI_DCM_OFF = DCM_OFF,
	MCSI_DCM_ON = DCM_ON,
} ENUM_MCSI_DCM;

enum {
	ARMCORE_DCM = 0,
	MCUSYS_DCM,
	INFRA_DCM,
	PERI_DCM,
	EMI_DCM,
	DRAMC_DCM,
	DDRPHY_DCM,
	STALL_DCM,
	BIG_CORE_DCM,
	GIC_SYNC_DCM,
	LAST_CORE_DCM,
	RGU_DCM,
	TOPCKG_DCM,
	LPDMA_DCM,
	MCSI_DCM,
	NR_DCM,
};

enum {
	ARMCORE_DCM_TYPE	= (1U << ARMCORE_DCM),
	MCUSYS_DCM_TYPE		= (1U << MCUSYS_DCM),
	INFRA_DCM_TYPE		= (1U << INFRA_DCM),
	PERI_DCM_TYPE		= (1U << PERI_DCM),
	EMI_DCM_TYPE		= (1U << EMI_DCM),
	DRAMC_DCM_TYPE		= (1U << DRAMC_DCM),
	DDRPHY_DCM_TYPE		= (1U << DDRPHY_DCM),
	STALL_DCM_TYPE		= (1U << STALL_DCM),
	BIG_CORE_DCM_TYPE	= (1U << BIG_CORE_DCM),
	GIC_SYNC_DCM_TYPE	= (1U << GIC_SYNC_DCM),
	LAST_CORE_DCM_TYPE	= (1U << LAST_CORE_DCM),
	RGU_DCM_TYPE		= (1U << RGU_DCM),
	TOPCKG_DCM_TYPE		= (1U << TOPCKG_DCM),
	LPDMA_DCM_TYPE		= (1U << LPDMA_DCM),
	MCSI_DCM_TYPE		= (1U << MCSI_DCM),
	NR_DCM_TYPE = NR_DCM,
};

enum {
	DCM_CPU_CLUSTER_LL	= (1U << 0),
	DCM_CPU_CLUSTER_L	= (1U << 1),
	DCM_CPU_CLUSTER_B	= (1U << 2),
};

#define SYNC_DCM_CLK_MIN_FREQ		52
#define SYNC_DCM_MAX_DIV_VAL		127

#define MCUCFG_SYNC_DCM_MP0_REG		SYNC_DCM_CONFIG
#define MCUCFG_SYNC_DCM_MP2_REG		MP2_CA15M_SYNC_DCM
#define MCUCFG_SYNC_DCM_CCI_REG		SYNC_DCM_CONFIG

#define MCUCFG_SYNC_DCM_CCI		(1)
#define MCUCFG_SYNC_DCM_MP0		(11)
#define MCUCFG_SYNC_DCM_MP2		(1)
#define MCUCFG_SYNC_DCM_CCI_TOGMASK	(0x1 << MCUCFG_SYNC_DCM_CCI)
#define MCUCFG_SYNC_DCM_MP0_TOGMASK	(0x1 << MCUCFG_SYNC_DCM_MP0)
#define MCUCFG_SYNC_DCM_MP2_TOGMASK	(0x1 << MCUCFG_SYNC_DCM_MP2)
#define MCUCFG_SYNC_DCM_TOGMASK	(MCUCFG_SYNC_DCM_CCI_TOGMASK | \
					MCUCFG_SYNC_DCM_MP0_TOGMASK

#define MCUCFG_SYNC_DCM_TOG1		MCUCFG_SYNC_DCM_TOGMASK
#define MCUCFG_SYNC_DCM_CCI_TOG1		MCUCFG_SYNC_DCM_CCI_TOGMASK
#define MCUCFG_SYNC_DCM_MP0_TOG1	MCUCFG_SYNC_DCM_MP0_TOGMASK
#define MCUCFG_SYNC_DCM_MP2_TOG1	MCUCFG_SYNC_DCM_MP2_TOGMASK
#define MCUCFG_SYNC_DCM_CCI_TOG0		(0x0 << MCUCFG_SYNC_DCM_CCI)
#define MCUCFG_SYNC_DCM_MP0_TOG0	(0x0 << MCUCFG_SYNC_DCM_MP0)
#define MCUCFG_SYNC_DCM_MP2_TOG0	(0x0 << MCUCFG_SYNC_DCM_MP2)
#define MCUCFG_SYNC_DCM_TOG0		(MCUCFG_SYNC_DCM_CCI_TOG0 | \
					MCUCFG_SYNC_DCM_MP0_TOG0

#define MCUCFG_SYNC_DCM_SEL_CCI		(2)
#define MCUCFG_SYNC_DCM_SEL_MP0		(12)
#define MCUCFG_SYNC_DCM_SEL_MP2		(2)
#define MCUCFG_SYNC_DCM_SEL_CCI_MASK	(0x7F << MCUCFG_SYNC_DCM_SEL_CCI)
#define MCUCFG_SYNC_DCM_SEL_MP0_MASK	(0x7F << MCUCFG_SYNC_DCM_SEL_MP0)
#define MCUCFG_SYNC_DCM_SEL_MP2_MASK	(0x7F << MCUCFG_SYNC_DCM_SEL_MP2)
#define MCUCFG_SYNC_DCM_SEL_MASK	(MCUCFG_SYNC_DCM_SEL_CCI_MASK | \
					 MCUCFG_SYNC_DCM_SEL_MP0_MASK)

int dcm_armcore(ENUM_ARMCORE_DCM mode);
int dcm_infra(ENUM_INFRA_DCM on);
int dcm_peri(ENUM_PERI_DCM on);
int dcm_mcusys(ENUM_MCUSYS_DCM on);
int dcm_dramc_ao(ENUM_DRAMC_AO_DCM on);
int dcm_emi(ENUM_EMI_DCM on);
int dcm_ddrphy(ENUM_DDRPHY_DCM on);
int dcm_stall(ENUM_STALL_DCM on);
int dcm_big_core(ENUM_BIG_CORE_DCM on);
int dcm_gic_sync(ENUM_GIC_SYNC_DCM on);
int dcm_last_core(ENUM_LAST_CORE_DCM on);
int dcm_rgu(ENUM_RGU_DCM on);
int dcm_topckg(ENUM_TOPCKG_DCM on);
int dcm_lpdma(ENUM_LPDMA_DCM on);

void dcm_infracfg_ao_emi_indiv(int on);

int mt_dcm_init(void);
void mt_dcm_disable(void);
void mt_dcm_restore(void);

/* unit of frequency is MHz */
int sync_dcm_set_cpu_freq(unsigned int cci, unsigned int mp0, unsigned int mp1, unsigned int mp2);
int sync_dcm_set_cpu_div(unsigned int cci, unsigned int mp0, unsigned int mp1, unsigned int mp2);
extern int sync_dcm_set_cci_freq(unsigned int cci);
extern int sync_dcm_set_mp0_freq(unsigned int mp0);
extern int sync_dcm_set_mp1_freq(unsigned int mp1);
extern int sync_dcm_set_mp2_freq(unsigned int mp2);

#endif /* #ifndef __MTK_DCM_H__ */