mtk-lk/platform/mt6785/include/platform/platform_debug.h

/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
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*
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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*/
#ifndef __PLATFORM_DEBUG_H__
#define __PLATFORM_DEBUG_H__

#include <latch.h>
#include <dfd.h>

const struct plt_cfg_pc_latch cfg_pc_latch = {
	.nr_max_core = 8,
	.nr_max_big_core = 2,
	.anake_core_dbg_sel = 0x0220,
	.anake_core_dbg_mon = 0x0224,
	.spm_pwr_sts = 0xAB88,
	.plat_sram_flag0 = 0x0,
	.version = LASTPC_V2,
};

const struct plt_cfg_return_stack cfg_return_stack = {
	.nr_max_core = 8,
	.nr_max_big = 2,
	.nr_entry = 8,
	.dump = NULL,
	.decode = NULL,
};

int plt_lastbus_is_timeout(const struct plt_cfg_bus_latch *self);
int plt_lastbus_dump(const struct plt_cfg_bus_latch *self, char *buf, int *wp);
void plat_perisys_monitor_init(const struct plt_cfg_bus_latch *self);
void no_need_dump(void);

const struct plt_cfg_bus_latch cfg_bus_latch = {
	.supported = 1,
	.num_master_port = 3,
	.num_slave_port = 5,
	.num_perisys_mon = 21,
	.num_infrasys_mon = 48,
	.mcusys_offsets = {
		.bus_mcu_m0 = 0x8320,
		.bus_mcu_s1 = 0x8340,
		.bus_mcu_m0_m = 0x8240,
		.bus_mcu_s1_m = 0x8260,
	},
	.perisys_offsets = {
		.bus_peri_r0 = 0x0500,
		.bus_peri_r1 = 0x0504,
		.bus_peri_mon = 0x0508,
	},
	.secure_perisys = 0,
	.perisys_enable = 0xc,
	.perisys_timeout = 0x3fff,
	.perisys_ops = {
		.is_timeout = plt_lastbus_is_timeout,
		.init = plat_perisys_monitor_init,
		.dump = no_need_dump,
	},
	.infrasys_offsets = {
		.bus_infra_ctrl = 0x0d04,
		.bus_infra_snapshot = 0x0d08,
		.bus_infra_mask_l = 0x0d00,
		.bus_infra_mask_h = 0x0df0,
	},
	.infrasys_config = 0xffff000c,
	.infrasys_ops = {
		.is_timeout = plt_lastbus_is_timeout,
		.dump = plt_lastbus_dump,
	},
};

const struct plt_cfg_l2_parity_latch cfg_l2_parity_latch = {
	.supported = 0,
	.mp0_l2_cache_parity1_rdata = 0x007c,
	.mp0_l2_cache_parity2_rdata = 0x0080,
	.mp1_l2_cache_parity1_rdata = 0x22d0,
	.mp1_l2_cache_parity2_rdata = 0x22d4,
};

const struct plt_cfg_big_core cfg_big_core[] = {
	{
		.cpuid = 6,
		.nr_circular_buffer_entry = 96,
		.circular_buffer_addr = 0x0C533400,
	},
	{
		.cpuid = 7,
		.nr_circular_buffer_entry = 96,
		.circular_buffer_addr = 0x0C533C00,
	},
};

struct plt_circular_buffer_op circular_buffer_op = {
	.lock = NULL,
	.unlock = NULL,
};

#define MCU_ALL_PWR_ON_CTRL	(0x0C530B58)

/******* dfd *******/
#include "dfd.h"

const struct plt_cfg_dfd cfg_dfd = {
	.version = DFD_V3_0,
	.sw_version = DFD_SW_V3,
	.nr_header_row = 0,
	.buffer_addr = 0x0c600000,
	.buffer_length = 0x62000,
	.large_buffer_length = 0x500000,
	.plat_sram_flag1 = 0,
	.plat_sram_flag2 = 0,
	.dfd_disable_devinfo_index = 7,
	.dfd_disable_bit = 29,
	.chip_id_offset = 0x18,
	.chip_id = {'6','7','8','5',0,0,0,0},
};

struct plt_dfd_op dfd_op = {
	.acquire_ram_control = NULL,
	.release_ram_control = NULL,
	.setup_dfd_file_name = plt_setup_dfd_file_name,
};

/******* etb *******/
#include "etb.h"
const struct plt_cfg_etb cfg_etb = {
	.nr_etb = 0,
};

#endif