otm9608_wvga_dsi_cmd.c 16 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. *
  31. * The following software/firmware and/or related documentation ("MediaTek Software")
  32. * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
  33. * applicable license agreements with MediaTek Inc.
  34. */
  35. #include <debug.h>
  36. #include "lcm_drv.h"
  37. // ---------------------------------------------------------------------------
  38. // Local Constants
  39. // ---------------------------------------------------------------------------
  40. #define FRAME_WIDTH (480)
  41. #define FRAME_HEIGHT (800)
  42. // ---------------------------------------------------------------------------
  43. // Local Variables
  44. // ---------------------------------------------------------------------------
  45. static LCM_UTIL_FUNCS lcm_util = {0};
  46. #define SET_RESET_PIN(v) (lcm_util.set_reset_pin((v)))
  47. #define UDELAY(n) (lcm_util.udelay(n))
  48. #define MDELAY(n) (lcm_util.mdelay(n))
  49. #define REGFLAG_DELAY 0XFD
  50. #define REGFLAG_END_OF_TABLE 0xFE // END OF REGISTERS MARKER
  51. // ---------------------------------------------------------------------------
  52. // Local Functions
  53. // ---------------------------------------------------------------------------
  54. #define dsi_set_cmdq_V2(cmd, count, ppara, force_update) lcm_util.dsi_set_cmdq_V2(cmd, count, ppara, force_update)
  55. #define dsi_set_cmdq(pdata, queue_size, force_update) lcm_util.dsi_set_cmdq(pdata, queue_size, force_update)
  56. #define wrtie_cmd(cmd) lcm_util.dsi_write_cmd(cmd)
  57. #define write_regs(addr, pdata, byte_nums) lcm_util.dsi_write_regs(addr, pdata, byte_nums)
  58. //#define read_reg lcm_util.dsi_read_reg()
  59. #define read_reg_v2(cmd, buffer, buffer_size) lcm_util.dsi_dcs_read_lcm_reg_v2(cmd, buffer, buffer_size)
  60. #define LCM_DSI_CMD_MODE
  61. struct LCM_setting_table {
  62. unsigned cmd;
  63. unsigned char count;
  64. unsigned char para_list[64];
  65. };
  66. static struct LCM_setting_table lcm_initialization_setting[] = {
  67. /*
  68. Note :
  69. Data ID will depends on the following rule.
  70. count of parameters > 1 => Data ID = 0x39
  71. count of parameters = 1 => Data ID = 0x15
  72. count of parameters = 0 => Data ID = 0x05
  73. Structure Format :
  74. {DCS command, count of parameters, {parameter list}}
  75. {REGFLAG_DELAY, milliseconds of time, {}},
  76. ...
  77. Setting ending by predefined flag
  78. {REGFLAG_END_OF_TABLE, 0x00, {}}
  79. */
  80. {0x00, 1, {0x00}},
  81. {0xFF,3, {0x96, 0x08, 0x01}},// Enable cmd
  82. {0x00,1, {0x80}},
  83. {0xFF,2, {0x96, 0x08}},// Enable cmd
  84. {0x00,1, {0x00}},
  85. {0xA0,1, {0x00}},//OTP select region
  86. {0x00,1, {0x80}},
  87. {0xB3,5, {0x00, 0x00, 0x20, 0x00, 0x00}},//Command Set Option Parameter
  88. {0x00,1, {0xC0}},
  89. {0xB3,1, {0x09}},//SRAM Setting
  90. {0x00,1, {0x80}},
  91. {0xC0,9, {0x00, 0x4C, 0x00, 0x10, 0x10, 0x00, 0x47, 0x10, 0x10}},//TCON Setting Parameters
  92. {0x00,1, {0x92}},
  93. {0xC0,4, {0x00, 0x10, 0x00, 0x13}},//Panel Timing Setting Parameter
  94. {0x00,1, {0xA2}},
  95. {0xC0,3, {0x0C, 0x05, 0x02}},//Panel Timing Setting Parameter
  96. {0x00,1, {0xB3}},
  97. {0xC0,2, {0x00, 0x50}},//Interval Scan Frame Setting
  98. {0x00,1, {0x81}},
  99. {0xC1,1, {0x66}},//Oscillator Adjustment for Idle/Normal Mode
  100. {0x00,1, {0x80}},
  101. {0xC4,3, {0x00, 0x84, 0xFC}},
  102. {0x00,1, {0xA0}},
  103. {0xB3,2, {0x10, 0x00} },
  104. {0x00,1, {0xA0}},
  105. {0xC0,1, {0x00}},
  106. {0x00,1, {0x88}},
  107. {0xC4,1, {0x40}},//488=source pl£¬±ÜÃâ?Áô?ºÉ È~¹¤
  108. {0x00,1, {0xA0}},
  109. {0xC4,8, {0x33, 0x09, 0x90, 0x2B, 0x33, 0x09, 0x90, 0x54}},//DC2DC Setting
  110. {0x00,1, {0x80}},
  111. {0xC5,4, {0x08, 0x00, 0xA0, 0x11}},
  112. {0x00,1, {0x90}},
  113. {0xC5,7, {0x96, 0x57, 0x01, 0x57, 0x33, 0x33, 0x34}},//Power Control Setting2 for Normal Mode
  114. {0x00,1, {0xA0}},
  115. {0xC5,7, {0x96, 0x57, 0x00, 0x57, 0x33, 0x33, 0x34}},//Power Control Setting3 for Idle Mode
  116. {0x00,1, {0xB0}},
  117. {0xC5,7, {0x04, 0xAC, 0x01, 0x00, 0x71, 0xB1, 0x83}},//Power Control Setting3 for DC Voltage Settings
  118. {0x00,1, {0x00}},
  119. {0xD9,1, {0x61}},//Vcom setting
  120. {0x00,1, {0x80}},
  121. {0xC6,1, {0x64}},//ABC Parameter
  122. {0x00,1, {0xB0}},
  123. {0xC6,5, {0x03, 0x10, 0x00, 0x1F, 0x12}},//ABC Parameter
  124. {0x00,1, {0x00}},
  125. {0xD0,1, {0x40}},//ID1
  126. {0x00,1, {0x00}},
  127. {0xD1,2, {0x00, 0x00}},//ID2&ID3
  128. {0x00,1, {0xB7}},
  129. {0xB0,1, {0x10}},
  130. {0x00,1, {0xC0}},
  131. {0xB0,1, {0x55}},
  132. {0x00,1, {0xB1}},
  133. {0xB0,1, {0x03}},
  134. {0x00,1, {0x81}},
  135. {0xD6,1, {0x00}},//Sharpness Off
  136. {0x00,1, {0x00}},
  137. {0xE1,16, {0x01, 0x07, 0x0B, 0x0C, 0x05, 0x0D, 0x0A, 0x08, 0x06, 0x08, 0x0D, 0x06, 0x0D, 0x16, 0x10, 0x01}},
  138. {0x00,1, {0x00}},
  139. {0xE2,16, {0x02, 0x06, 0x0A, 0x0D, 0x05, 0x0C, 0x09, 0x08, 0x05, 0x08, 0x0E, 0x07, 0x0D, 0x16, 0x10, 0x00}},
  140. {0x00,1, {0x80}},
  141. {0xCB,10, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  142. {0x00,1, {0x90}},
  143. {0xCB,15, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  144. {0x00,1, {0xA0}},
  145. {0xCB,15, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  146. {0x00,1, {0xB0}},
  147. {0xCB,10, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  148. {0x00,1, {0xC0}},
  149. {0xCB,15, {0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x08, 0x04, 0x08, 0x04, 0x08, 0x04, 0x04, 0x04, 0x08}},//TCON GOA WAVE(Panel timing state control)
  150. {0x00,1, {0xD0}},
  151. {0xCB,15, {0x08, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x08, 0x04, 0x08, 0x04}},//TCON GOA WAVE(Panel timing state control)
  152. {0x00,1, {0xE0}},
  153. {0xCB,10, {0x08, 0x04, 0x04, 0x04, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  154. {0x00,1, {0xF0}},
  155. {0xCB,10, {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}},//TCON GOA WAVE(Panel timing state control)
  156. {0x00,1, {0x80}},
  157. {0xCC,10, {0x26, 0x25, 0x23, 0x24, 0x00, 0x0F, 0x00, 0x0D, 0x00, 0x0B}},//TCON GOA WAVE(Panel timing state control)
  158. {0x00,1, {0x90}},
  159. {0xCC,15, {0x00, 0x09, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x25, 0x21, 0x22, 0x00}},//TCON GOA WAVE(Panel timing state control)
  160. {0x00,1, {0xA0}},
  161. {0xCC,15, {0x10, 0x00, 0x0E, 0x00, 0x0C, 0x00, 0x0A, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  162. {0x00,1, {0xB0}},
  163. {0xCC,10, {0x25, 0x26, 0x21, 0x22, 0x00, 0x0A, 0x00, 0x0C, 0x00, 0x0E}},//TCON GOA WAVE(Panel timing state control)
  164. {0x00,1, {0xC0}},
  165. {0xCC,15, {0x00, 0x10, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x26, 0x23, 0x24, 0x00}},//TCON GOA WAVE(Panel timing state control)
  166. {0x00,1, {0xD0}},
  167. {0xCC,15, {0x09, 0x00, 0x0B, 0x00, 0x0D, 0x00, 0x0F, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},//TCON GOA WAVE(Panel timing state control)
  168. {0x00,1, {0x80}},
  169. {0xCE,12, {0x8A, 0x03, 0x06, 0x89, 0x03, 0x06, 0x88, 0x03, 0x06, 0x87, 0x03, 0x06}},
  170. {0x00,1, {0x90}},
  171. {0xCE,14, {0xF0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00}},//GOA VEND and Group Setting
  172. {0x00,1, {0xA0}},
  173. {0xCE,14, {0x38, 0x02, 0x03, 0xC1, 0x00, 0x06, 0x00, 0x38, 0x01, 0x03, 0xC2, 0x00, 0x06, 0x00}},//GOA CLK1 and GOA CLK2 Setting
  174. {0x00,1, {0xB0}},
  175. {0xCE,14, {0x38, 0x00, 0x03, 0xC3, 0x00, 0x06, 0x00, 0x30, 0x00, 0x03, 0xC4, 0x00, 0x06, 0x00}},//GOA CLK3 and GOA CLK4 Setting
  176. {0x00,1, {0xC0}},
  177. {0xCE,14, {0x38, 0x06, 0x03, 0xBD, 0x00, 0x06, 0x00, 0x38, 0x05, 0x03, 0xBE, 0x00, 0x06, 0x00}},//GOA CLKB1 and GOA CLKB2 Setting
  178. {0x00,1, {0xD0}},
  179. {0xCE,14, {0x38, 0x04, 0x03, 0xBF, 0x00, 0x06, 0x00, 0x38, 0x03, 0x03, 0xC0, 0x00, 0x06, 0x00}},//GOA CLKB3 and GOA CLKB4 Setting
  180. {0x00,1, {0x80}},
  181. {0xCF,14, {0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00}},//GOA CLKC1 and GOA CLKC2 Setting
  182. {0x00,1, {0x90}},
  183. {0xCF,14, {0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00}},//GOA CLKC3 and GOA CLKC4 Setting
  184. {0x00,1, {0xA0}},
  185. {0xCF,14, {0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00}},//GOA CLKD1 and GOA CLKD2 Setting
  186. {0x00,1, {0xB0}},
  187. {0xCF,14, {0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00}},//GOA CLKD3 and GOA CLKD4 Setting
  188. {0x00,1, {0xC0}},
  189. {0xCF,10, {0x02, 0x02, 0x20, 0x20, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02}},//GOA ECLK Setting and GOA Other Options1 and GOA Signal Toggle Option Setting
  190. {0x00,1, {0x00}},
  191. {0xD8,2, {/*{0xA7, 0xA7}*/0x67,0x67}},// GVDD=5.2V, NGVDD=-5.2V
  192. {0x11,0,{}},
  193. {REGFLAG_DELAY, 120, {}},
  194. {0x35,1,{0}},
  195. {0x29,0,{}},
  196. {REGFLAG_DELAY, 40, {}},
  197. // Note
  198. // Strongly recommend not to set Sleep out / Display On here. That will cause messed frame to be shown as later the backlight is on.
  199. // Setting ending by predefined flag
  200. {REGFLAG_END_OF_TABLE, 0x00, {}}
  201. };
  202. void push_table(struct LCM_setting_table *table, unsigned int count, unsigned char force_update)
  203. {
  204. unsigned int i;
  205. for (i = 0; i < count; i++) {
  206. unsigned cmd;
  207. cmd = table[i].cmd;
  208. switch (cmd) {
  209. case REGFLAG_DELAY :
  210. MDELAY(table[i].count);
  211. break;
  212. case REGFLAG_END_OF_TABLE :
  213. break;
  214. default:
  215. dsi_set_cmdq_V2(cmd, table[i].count, table[i].para_list, force_update);
  216. }
  217. }
  218. }
  219. // ---------------------------------------------------------------------------
  220. // LCM Driver Implementations
  221. // ---------------------------------------------------------------------------
  222. static void lcm_set_util_funcs(const LCM_UTIL_FUNCS *util)
  223. {
  224. memcpy(&lcm_util, util, sizeof(LCM_UTIL_FUNCS));
  225. }
  226. static void lcm_get_params(LCM_PARAMS *params)
  227. {
  228. memset(params, 0, sizeof(LCM_PARAMS));
  229. params->type = LCM_TYPE_DSI;
  230. params->width = FRAME_WIDTH;
  231. params->height = FRAME_HEIGHT;
  232. // enable tearing-free
  233. params->dbi.te_mode = LCM_DBI_TE_MODE_VSYNC_ONLY;
  234. params->dbi.te_edge_polarity = LCM_POLARITY_RISING;
  235. #if defined(LCM_DSI_CMD_MODE)
  236. params->dsi.mode = CMD_MODE;
  237. #else
  238. params->dsi.mode = SYNC_PULSE_VDO_MODE;
  239. #endif
  240. // DSI
  241. /* Command mode setting */
  242. params->dsi.LANE_NUM = LCM_TWO_LANE;
  243. //The following defined the fomat for data coming from LCD engine.
  244. params->dsi.data_format.color_order = LCM_COLOR_ORDER_RGB;
  245. params->dsi.data_format.trans_seq = LCM_DSI_TRANS_SEQ_MSB_FIRST;
  246. params->dsi.data_format.padding = LCM_DSI_PADDING_ON_LSB;
  247. params->dsi.data_format.format = LCM_DSI_FORMAT_RGB888;
  248. // Highly depends on LCD driver capability.
  249. // Not support in MT6573
  250. params->dsi.DSI_WMEM_CONTI=0x3C;
  251. params->dsi.DSI_RMEM_CONTI=0x3E;
  252. params->dsi.packet_size=256;
  253. // Video mode setting
  254. params->dsi.intermediat_buffer_num = 2;
  255. params->dsi.PS=LCM_PACKED_PS_24BIT_RGB888;
  256. params->dsi.vertical_sync_active = 3;
  257. params->dsi.vertical_backporch = 12;
  258. params->dsi.vertical_frontporch = 2;
  259. params->dsi.vertical_active_line = FRAME_HEIGHT;
  260. params->dsi.horizontal_sync_active = 10;
  261. params->dsi.horizontal_backporch = 50;
  262. params->dsi.horizontal_frontporch = 50;
  263. params->dsi.horizontal_active_pixel = FRAME_WIDTH;
  264. // Bit rate calculation
  265. params->dsi.PLL_CLOCK = 260;
  266. params->dsi.clk_lp_per_line_enable = 0;
  267. params->dsi.esd_check_enable = 1;
  268. params->dsi.customization_esd_check_enable = 1;
  269. params->dsi.lcm_esd_check_table[0].cmd = 0x0A;
  270. params->dsi.lcm_esd_check_table[0].count = 1;
  271. params->dsi.lcm_esd_check_table[0].para_list[0] = 0x9C;
  272. }
  273. static unsigned int lcm_compare_id(void)
  274. {
  275. int array[4];
  276. char buffer[3];
  277. char id0=0;
  278. char id1=0;
  279. char id2=0;
  280. SET_RESET_PIN(0);
  281. MDELAY(200);
  282. SET_RESET_PIN(1);
  283. MDELAY(200);
  284. array[0] = 0x00033700;// read id return two byte,version and id
  285. dsi_set_cmdq(array, 1, 1);
  286. read_reg_v2(0xDA,buffer, 1);
  287. array[0] = 0x00033700;// read id return two byte,version and id
  288. dsi_set_cmdq(array, 1, 1);
  289. read_reg_v2(0xDB,buffer+1, 1);
  290. array[0] = 0x00033700;// read id return two byte,version and id
  291. dsi_set_cmdq(array, 1, 1);
  292. read_reg_v2(0xDC,buffer+2, 1);
  293. id0 = buffer[0]; //should be 0x00
  294. id1 = buffer[1];//should be 0xaa
  295. id2 = buffer[2];//should be 0x55
  296. dprintf(INFO, "%s, id0 = 0x%08x\n", __func__, id0);//should be 0x00
  297. dprintf(INFO, "%s, id1 = 0x%08x\n", __func__, id1);//should be 0xaa
  298. dprintf(INFO, "%s, id2 = 0x%08x\n", __func__, id2);//should be 0x55
  299. return 1;
  300. }
  301. static void lcm_init(void)
  302. {
  303. SET_RESET_PIN(0);
  304. MDELAY(10);
  305. SET_RESET_PIN(1);
  306. MDELAY(10);
  307. push_table(lcm_initialization_setting, sizeof(lcm_initialization_setting) / sizeof(struct LCM_setting_table), 1);
  308. }
  309. static void lcm_suspend(void)
  310. {
  311. unsigned int data_array[2];
  312. data_array[0] = 0x00280500; // Display Off
  313. dsi_set_cmdq(data_array, 1, 1);
  314. MDELAY(10);
  315. data_array[0] = 0x00100500; // Sleep In
  316. dsi_set_cmdq(data_array, 1, 1);
  317. MDELAY(100);
  318. dprintf(INFO, "lk %s\n", __func__);
  319. }
  320. static void lcm_resume(void)
  321. {
  322. dprintf(INFO, "lk %s\n", __func__);
  323. // push_table(lcm_sleep_out_setting, sizeof(lcm_sleep_out_setting) / sizeof(struct LCM_setting_table), 1);
  324. lcm_init();
  325. }
  326. static void lcm_update(unsigned int x, unsigned int y,
  327. unsigned int width, unsigned int height)
  328. {
  329. unsigned int x0 = x;
  330. unsigned int y0 = y;
  331. unsigned int x1 = x0 + width - 1;
  332. unsigned int y1 = y0 + height - 1;
  333. unsigned char x0_MSB = ((x0>>8)&0xFF);
  334. unsigned char x0_LSB = (x0&0xFF);
  335. unsigned char x1_MSB = ((x1>>8)&0xFF);
  336. unsigned char x1_LSB = (x1&0xFF);
  337. unsigned char y0_MSB = ((y0>>8)&0xFF);
  338. unsigned char y0_LSB = (y0&0xFF);
  339. unsigned char y1_MSB = ((y1>>8)&0xFF);
  340. unsigned char y1_LSB = (y1&0xFF);
  341. unsigned int data_array[16];
  342. dprintf(INFO, "lk %s\n", __func__);
  343. data_array[0]= 0x00053902;
  344. data_array[1]= (x1_MSB<<24)|(x0_LSB<<16)|(x0_MSB<<8)|0x2a;
  345. data_array[2]= (x1_LSB);
  346. data_array[3]= 0x00053902;
  347. data_array[4]= (y1_MSB<<24)|(y0_LSB<<16)|(y0_MSB<<8)|0x2b;
  348. data_array[5]= (y1_LSB);
  349. data_array[6]= 0x002c3909;
  350. dsi_set_cmdq(data_array, 7, 0);
  351. }
  352. LCM_DRIVER otm9608_wvga_dsi_cmd_drv = {
  353. .name = "otm9608a_wvga_dsi_cmd",
  354. .set_util_funcs = lcm_set_util_funcs,
  355. .compare_id = lcm_compare_id,
  356. .get_params = lcm_get_params,
  357. .init = lcm_init,
  358. .suspend = lcm_suspend,
  359. .resume = lcm_resume,
  360. #if defined(LCM_DSI_CMD_MODE)
  361. .update = lcm_update,
  362. #endif
  363. };