ddp_misc.c 7.2 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. *
  31. * The following software/firmware and/or related documentation ("MediaTek Software")
  32. * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
  33. * applicable license agreements with MediaTek Inc.
  34. */
  35. #define LOG_TAG "MISC"
  36. #include <platform/disp_drv_platform.h>
  37. #include <platform/ddp_reg.h>
  38. #include <platform/ddp_misc.h>
  39. #include <platform/ddp_info.h>
  40. void ddp_bypass_color(int idx, unsigned int width, unsigned int height, void * handle)
  41. {
  42. DISP_REG_SET(handle,DISP_COLOR_INTERNAL_IP_WIDTH+(idx*DISP_INDEX_OFFSET), width); // width
  43. DISP_REG_SET(handle,DISP_COLOR_INTERNAL_IP_HEIGHT+(idx*DISP_INDEX_OFFSET), height); // height
  44. DISP_REG_SET(handle,DISP_COLOR_CFG_MAIN+(idx*DISP_INDEX_OFFSET), 0x200032bc); //bypass color engine
  45. DISP_REG_SET(handle,DISP_COLOR_START+(idx*DISP_INDEX_OFFSET), 0x2); // start
  46. DISP_REG_SET(handle,DISP_COLOR_START+(idx*DISP_INDEX_OFFSET), 0x3); // start
  47. DISP_REG_SET(handle,DISP_COLOR_CM1_EN+(idx*DISP_INDEX_OFFSET), 0); // disable R2Y
  48. DISP_REG_SET(handle,DISP_COLOR_CM2_EN+(idx*DISP_INDEX_OFFSET), 0); // disable Y2R
  49. }
  50. void ddp_bypass_ccorr(unsigned int width, unsigned int height, void * handle)
  51. {
  52. DISP_REG_SET(NULL,DISP_REG_CCORR_SIZE, (width<<16) | height); // size
  53. DISP_REG_SET(NULL,DISP_REG_CCORR_EN, 1);
  54. DISP_REG_MASK(NULL,DISP_REG_CCORR_CFG, 1, 1);
  55. }
  56. void ddp_bypass_aal(unsigned int width, unsigned int height, void * handle)
  57. {
  58. DISP_REG_SET(handle,DISP_AAL_EN, 0x0); //bypass mode
  59. DISP_REG_SET_FIELD(handle,CFG_FLD_RELAY_MODE, DISP_AAL_CFG, 0x1); //relay_mode
  60. DISP_REG_SET_FIELD(handle,SIZE_FLD_HSIZE, DISP_AAL_SIZE, width); //width
  61. DISP_REG_SET_FIELD(handle,SIZE_FLD_VSIZE, DISP_AAL_SIZE, height); //height
  62. }
  63. void ddp_bypass_gamma(unsigned int width, unsigned int height, void * handle)
  64. {
  65. //Disable means bypass, so don't need to set any thing
  66. DISP_REG_SET(handle,DISP_REG_GAMMA_EN, 0x0); //bypass mode
  67. DISP_REG_SET(handle,DISP_REG_GAMMA_SIZE, (width<<16)|height);
  68. }
  69. #if defined(MTK_FB_OD_SUPPORT)
  70. void ddp_bypass_od(unsigned int width, unsigned int height, void * handle)
  71. {
  72. DISP_REG_SET(handle,DISP_REG_OD_SIZE, (width<<16)|height);
  73. DISP_REG_SET(handle,DISP_REG_OD_CFG, 0x1);
  74. DISP_REG_SET(handle,DISP_REG_OD_EN, 0x1);
  75. }
  76. #endif
  77. static int config_color(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  78. {
  79. int color_idx;
  80. if (module == DISP_MODULE_COLOR0)
  81. color_idx = 0;
  82. else
  83. color_idx = 1;
  84. if (!pConfig->dst_dirty) {
  85. return 0;
  86. }
  87. ddp_bypass_color(color_idx,pConfig->dst_w, pConfig->dst_h,cmdq);
  88. ddp_bypass_ccorr(pConfig->dst_w, pConfig->dst_h,cmdq);
  89. return 0;
  90. }
  91. static int config_aal(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  92. {
  93. if (!pConfig->dst_dirty) {
  94. return 0;
  95. }
  96. ddp_bypass_aal(pConfig->dst_w, pConfig->dst_h,cmdq);
  97. return 0;
  98. }
  99. #if defined(MTK_FB_OD_SUPPORT)
  100. static int config_od(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  101. {
  102. if (!pConfig->dst_dirty) {
  103. return 0;
  104. }
  105. ddp_bypass_od(pConfig->dst_w, pConfig->dst_h,cmdq);
  106. return 0;
  107. }
  108. #endif
  109. static int config_gamma(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  110. {
  111. if (!pConfig->dst_dirty) {
  112. return 0;
  113. }
  114. ddp_bypass_gamma(pConfig->dst_w, pConfig->dst_h,cmdq);
  115. return 0;
  116. }
  117. static int clock_on(DISP_MODULE_ENUM module,void * handle)
  118. {
  119. ddp_enable_module_clock(module);
  120. return 0;
  121. }
  122. static int clock_off(DISP_MODULE_ENUM module,void * handle)
  123. {
  124. ddp_disable_module_clock(module);
  125. return 0;
  126. }
  127. ///////////////////////////////////////////////////////////
  128. // color
  129. DDP_MODULE_DRIVER ddp_driver_color = {
  130. .init = clock_on,
  131. .deinit = clock_off,
  132. .config = config_color,
  133. .start = NULL,
  134. .trigger = NULL,
  135. .stop = NULL,
  136. .reset = NULL,
  137. .power_on = clock_on,
  138. .power_off = clock_off,
  139. .is_idle = NULL,
  140. .is_busy = NULL,
  141. .dump_info = NULL,
  142. .bypass = NULL,
  143. .build_cmdq = NULL,
  144. .set_lcm_utils = NULL,
  145. };
  146. // aal
  147. DDP_MODULE_DRIVER ddp_driver_aal = {
  148. .init = clock_on,
  149. .deinit = clock_off,
  150. .config = config_aal,
  151. .start = NULL,
  152. .trigger = NULL,
  153. .stop = NULL,
  154. .reset = NULL,
  155. .power_on = clock_on,
  156. .power_off = clock_off,
  157. .is_idle = NULL,
  158. .is_busy = NULL,
  159. .dump_info = NULL,
  160. .bypass = NULL,
  161. .build_cmdq = NULL,
  162. .set_lcm_utils = NULL,
  163. };
  164. // od
  165. #if defined(MTK_FB_OD_SUPPORT)
  166. DDP_MODULE_DRIVER ddp_driver_od = {
  167. .init = clock_on,
  168. .deinit = clock_off,
  169. .config = config_od,
  170. .start = NULL,
  171. .trigger = NULL,
  172. .stop = NULL,
  173. .reset = NULL,
  174. .power_on = clock_on,
  175. .power_off = clock_off,
  176. .is_idle = NULL,
  177. .is_busy = NULL,
  178. .dump_info = NULL,
  179. .bypass = NULL,
  180. .build_cmdq = NULL,
  181. .set_lcm_utils = NULL,
  182. };
  183. #endif
  184. // gamma
  185. DDP_MODULE_DRIVER ddp_driver_gamma = {
  186. .init = clock_on,
  187. .deinit = clock_off,
  188. .config = config_gamma,
  189. .start = NULL,
  190. .trigger = NULL,
  191. .stop = NULL,
  192. .reset = NULL,
  193. .power_on = clock_on,
  194. .power_off = clock_off,
  195. .is_idle = NULL,
  196. .is_busy = NULL,
  197. .dump_info = NULL,
  198. .bypass = NULL,
  199. .build_cmdq = NULL,
  200. .set_lcm_utils = NULL,
  201. };