msdc_dma.c 32 KB

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  1. /*****************************************************************************
  2. * Copyright Statement:
  3. * --------------------
  4. * This software is protected by Copyright and the information contained
  5. * herein is confidential. The software may not be copied and the information
  6. * contained herein may not be used or disclosed except with the written
  7. * permission of MediaTek Inc. (C) 2010
  8. *
  9. * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  10. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  11. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
  12. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  13. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  14. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  15. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  16. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  17. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
  18. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
  19. * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
  20. * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
  21. *
  22. * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
  23. * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  24. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  25. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
  26. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  27. *
  28. * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
  29. * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
  30. * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
  31. * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
  32. * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
  33. *
  34. *****************************************************************************/
  35. #include "msdc.h"
  36. #if defined(MMC_MSDC_DRV_CTP)
  37. #include <common.h>
  38. #include "api.h" //For invocation cache_clean_invalidate()
  39. #include "cache_api.h" //For invocation cache_clean_invalidate()
  40. #endif
  41. #if defined(MMC_MSDC_DRV_LK)
  42. #include <arch/ops.h>
  43. //For arch_clean_invalidate_cache_range() is defined in bootable/bootloader/include/arch/ops.h
  44. #endif
  45. static gpd_t msdc_gpd_pool[MSDC_MAX_NUM][MAX_GPD_POOL_SZ];
  46. static bd_t msdc_bd_pool[MSDC_MAX_NUM][MAX_BD_POOL_SZ];
  47. #if MSDC_DEBUG
  48. void msdc_dump_dma_desc(struct mmc_host *host);
  49. #endif
  50. #if defined(MSDC_ENABLE_DMA_MODE)
  51. void msdc_init_gpd_bd(struct mmc_host *host)
  52. {
  53. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  54. gpd_t *gpd;
  55. bd_t *bd;
  56. int id=host->id;
  57. gpd = &msdc_gpd_pool[id][0];
  58. bd = &msdc_bd_pool[id][0];
  59. memset(gpd, 0, sizeof(gpd_t) * MAX_GPD_POOL_SZ);
  60. memset(bd, 0, sizeof(bd_t) * MAX_BD_POOL_SZ);
  61. priv->bd_pool = bd;
  62. priv->gpd_pool = gpd;
  63. }
  64. void msdc_flush_membuf(void *buf, u32 len)
  65. {
  66. #if defined(MMC_MSDC_DRV_LK)
  67. arch_clean_invalidate_cache_range((addr_t)buf, len);
  68. #elif defined(MMC_MSDC_DRV_CTP)
  69. cache_clean_invalidate();
  70. #endif
  71. }
  72. u8 msdc_cal_checksum(u8 *buf, u32 len)
  73. {
  74. u32 i, sum = 0;
  75. for (i = 0; i < len; i++) {
  76. sum += buf[i];
  77. }
  78. return 0xFF - (u8)sum;
  79. }
  80. /* allocate gpd link-list from gpd_pool */
  81. gpd_t *msdc_alloc_gpd(struct mmc_host *host, int num)
  82. {
  83. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  84. gpd_t *gpd, *ptr, *prev;
  85. if (priv->alloc_gpd + num + 1 > MAX_GPD_POOL_SZ || num == 0)
  86. return NULL;
  87. gpd = priv->gpd_pool + priv->alloc_gpd;
  88. priv->alloc_gpd += (num + 1); /* include null gpd */
  89. memset(gpd, 0, sizeof(gpd_t) * (num + 1));
  90. ptr = gpd + num - 1;
  91. ptr->next = (void*)(gpd + num); /* pointer to null gpd */
  92. /* create link-list */
  93. if (ptr != gpd) {
  94. do {
  95. prev = ptr - 1;
  96. prev->next = ptr;
  97. ptr = prev;
  98. } while (ptr != gpd);
  99. }
  100. return gpd;
  101. }
  102. /* allocate bd link-list from bd_pool */
  103. bd_t *msdc_alloc_bd(struct mmc_host *host, int num)
  104. {
  105. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  106. bd_t *bd, *ptr, *prev;
  107. if (priv->alloc_bd + num > MAX_BD_POOL_SZ || num == 0)
  108. return NULL;
  109. bd = priv->bd_pool + priv->alloc_bd;
  110. priv->alloc_bd += num;
  111. memset(bd, 0, sizeof(bd_t) * num);
  112. ptr = bd + num - 1;
  113. ptr->eol = 1;
  114. ptr->next = 0;
  115. /* create link-list */
  116. if (ptr != bd) {
  117. do {
  118. prev = ptr - 1;
  119. prev->next = ptr;
  120. prev->eol = 0;
  121. ptr = prev;
  122. } while (ptr != bd);
  123. }
  124. return bd;
  125. }
  126. /* queue bd link-list to one gpd */
  127. void msdc_queue_bd(struct mmc_host *host, gpd_t *gpd, bd_t *bd)
  128. {
  129. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  130. BUG_ON(gpd->ptr);
  131. gpd->hwo = 1;
  132. gpd->bdp = 1;
  133. gpd->ptr = (void*)bd;
  134. if ((priv->cfg.flags & DMA_FLAG_EN_CHKSUM) == 0)
  135. return;
  136. /* calculate and fill bd checksum */
  137. while (bd) {
  138. bd->chksum = msdc_cal_checksum((u8*)bd, 16);
  139. bd = bd->next;
  140. }
  141. }
  142. /* queue data buf to one gpd */
  143. void msdc_queue_buf(struct mmc_host *host, gpd_t *gpd, u8 *buf)
  144. {
  145. BUG_ON(gpd->ptr);
  146. gpd->hwo = 1;
  147. gpd->bdp = 0;
  148. gpd->ptr = (void*)buf;
  149. }
  150. /* add gpd link-list to active list */
  151. void msdc_add_gpd(struct mmc_host *host, gpd_t *gpd, int num)
  152. {
  153. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  154. if (num > 0) {
  155. if (!priv->active_head) {
  156. priv->active_head = gpd;
  157. } else {
  158. priv->active_tail->next = gpd;
  159. }
  160. priv->active_tail = gpd + num - 1;
  161. if ((priv->cfg.flags & DMA_FLAG_EN_CHKSUM) == 0)
  162. return;
  163. /* calculate and fill gpd checksum */
  164. while (gpd) {
  165. gpd->chksum = msdc_cal_checksum((u8 *)gpd, 16);
  166. gpd = gpd->next;
  167. }
  168. }
  169. }
  170. void msdc_reset_gpd(struct mmc_host *host)
  171. {
  172. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  173. priv->alloc_bd = 0;
  174. priv->alloc_gpd = 0;
  175. priv->active_head = NULL;
  176. priv->active_tail = NULL;
  177. }
  178. void msdc_set_dma(struct mmc_host *host, u8 burstsz, u32 flags)
  179. {
  180. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  181. struct dma_config *cfg = &priv->cfg;
  182. cfg->burstsz = burstsz;
  183. cfg->flags = flags;
  184. }
  185. int msdc_sg_init(struct scatterlist *sg, void *buf, u64 buflen)
  186. {
  187. int i = MAX_SG_POOL_SZ;
  188. char *ptr = (char *)buf;
  189. BUG_ON(buflen >(u64) MAX_SG_POOL_SZ * MAX_SG_BUF_SZ);
  190. msdc_flush_membuf(buf, buflen);
  191. while (i > 0) {
  192. if (buflen > MAX_SG_BUF_SZ) {
  193. sg->addr = (u32)ptr;
  194. sg->len = MAX_SG_BUF_SZ;
  195. buflen -= MAX_SG_BUF_SZ;
  196. ptr += MAX_SG_BUF_SZ;
  197. sg++; i--;
  198. } else {
  199. sg->addr = (u32)ptr;
  200. sg->len = buflen;
  201. i--;
  202. break;
  203. }
  204. }
  205. return MAX_SG_POOL_SZ - i;
  206. }
  207. void msdc_dma_init(struct mmc_host *host, struct dma_config *cfg, void *buf, u64 buflen)
  208. {
  209. u32 base = host->base;
  210. cfg->xfersz = buflen;
  211. if (cfg->mode == MSDC_MODE_DMA_BASIC) {
  212. cfg->sglen = 1;
  213. cfg->sg[0].addr = (u32)buf;
  214. cfg->sg[0].len = buflen;
  215. msdc_flush_membuf(buf, buflen);
  216. } else {
  217. cfg->sglen = msdc_sg_init(cfg->sg, buf, buflen);
  218. }
  219. msdc_clr_fifo(host);
  220. MSDC_DMA_ON();
  221. }
  222. int msdc_dma_cmd(struct mmc_host *host, struct dma_config *cfg, struct mmc_command *cmd)
  223. {
  224. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  225. u32 opcode = cmd->opcode;
  226. u32 rsptyp = cmd->rsptyp;
  227. u32 rawcmd;
  228. rawcmd = (opcode & ~(SD_CMD_BIT | SD_CMD_APP_BIT)) |
  229. rsptyp << 7 | host->blklen << 16;
  230. if (opcode == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
  231. rawcmd |= ((2 << 11) | (1 << 13));
  232. if (priv->autocmd & MSDC_AUTOCMD12)
  233. rawcmd |= (1 << 28);
  234. else if (priv->autocmd & MSDC_AUTOCMD23)
  235. rawcmd |= (2 << 28);
  236. } else if (opcode == MMC_CMD_WRITE_BLOCK) {
  237. rawcmd |= ((1 << 11) | (1 << 13));
  238. } else if (opcode == MMC_CMD_READ_MULTIPLE_BLOCK) {
  239. rawcmd |= (2 << 11);
  240. if (priv->autocmd & MSDC_AUTOCMD12)
  241. rawcmd |= (1 << 28);
  242. else if (priv->autocmd & MSDC_AUTOCMD23)
  243. rawcmd |= (2 << 28);
  244. } else if (opcode == MMC_CMD_READ_SINGLE_BLOCK) {
  245. rawcmd |= (1 << 11);
  246. #if defined(FEATURE_MMC_SDIO)
  247. } else if (opcode == SD_IO_RW_EXTENDED) {
  248. if (cmd->arg & 0x80000000) /* R/W flag */
  249. rawcmd |= (1 << 13);
  250. if ((cmd->arg & 0x08000000) && ((cmd->arg & 0x1FF) > 1))
  251. rawcmd |= (2 << 11); /* multiple block mode */
  252. else
  253. rawcmd |= (1 << 11);
  254. } else if (opcode == SD_IO_RW_DIRECT) {
  255. if ((cmd->arg & 0x80000000) && ((cmd->arg >> 9) & 0x1FFFF))/* I/O abt */
  256. rawcmd |= (1 << 14);
  257. #endif
  258. } else {
  259. return -1;
  260. }
  261. MSG(DMA, "[SD%d] DMA CMD(%d), AUTOCMD12(%d), AUTOCMD23(%d)\n",
  262. host->id, (opcode & ~(SD_CMD_BIT | SD_CMD_APP_BIT)),
  263. (priv->autocmd & MSDC_AUTOCMD12) ? 1 : 0,
  264. (priv->autocmd & MSDC_AUTOCMD23) ? 1 : 0);
  265. cfg->cmd = rawcmd;
  266. cfg->arg = cmd->arg;
  267. return 0;
  268. }
  269. int msdc_dma_config(struct mmc_host *host, struct dma_config *cfg)
  270. {
  271. u32 base = host->base;
  272. u32 sglen = cfg->sglen;
  273. u32 j;
  274. #ifdef MSDC_ENABLE_ENH_DMA_MODE
  275. u32 i, num, bdlen, arg, xfersz;
  276. #endif
  277. u8 blkpad, dwpad, chksum;
  278. struct scatterlist *sg = cfg->sg;
  279. gpd_t *gpd;
  280. bd_t *bd;
  281. switch (cfg->mode) {
  282. case MSDC_MODE_DMA_BASIC:
  283. BUG_ON(cfg->xfersz > MAX_DMA_CNT);
  284. BUG_ON(cfg->sglen != 1);
  285. MSDC_WRITE32(MSDC_DMA_SA, sg->addr);
  286. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
  287. MSDC_WRITE32(MSDC_DMA_LEN, sg->len);
  288. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, cfg->burstsz);
  289. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
  290. break;
  291. case MSDC_MODE_DMA_DESC:
  292. blkpad = (cfg->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
  293. dwpad = (cfg->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
  294. chksum = (cfg->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
  295. #if 0 /* YD: current design doesn't support multiple GPD in descriptor dma mode */
  296. /* calculate the required number of gpd */
  297. num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
  298. gpd = msdc_alloc_gpd(host, num);
  299. for (i = 0; i < num; i++) {
  300. gpd[i].intr = 0;
  301. if (sglen > MAX_BD_PER_GPD) {
  302. bdlen = MAX_BD_PER_GPD;
  303. sglen -= MAX_BD_PER_GPD;
  304. } else {
  305. bdlen = sglen;
  306. sglen = 0;
  307. }
  308. bd = msdc_alloc_bd(host, bdlen);
  309. for (j = 0; j < bdlen; j++) {
  310. MSDC_INIT_BD(&bd[j], blkpad, dwpad, sg->addr, sg->len);
  311. sg++;
  312. }
  313. msdc_queue_bd(host, &gpd[i], bd);
  314. msdc_flush_membuf(bd, bdlen * sizeof(bd_t));
  315. }
  316. msdc_add_gpd(host, gpd, num);
  317. #if MSDC_DEBUG
  318. msdc_dump_dma_desc(host);
  319. #endif
  320. msdc_flush_membuf(gpd, num * sizeof(gpd_t));
  321. MSDC_WRITE32(MSDC_DMA_SA, (u32)&gpd[0]);
  322. MSDC_SET_FIELD(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
  323. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, cfg->burstsz);
  324. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
  325. #else
  326. /* calculate the required number of gpd */
  327. BUG_ON(sglen > MAX_BD_POOL_SZ);
  328. gpd = msdc_alloc_gpd(host, 1);
  329. gpd->intr = 0;
  330. bd = msdc_alloc_bd(host, sglen);
  331. for (j = 0; j < sglen; j++) {
  332. MSDC_INIT_BD(&bd[j], blkpad, dwpad, sg->addr, sg->len);
  333. sg++;
  334. }
  335. msdc_queue_bd(host, &gpd[0], bd);
  336. msdc_flush_membuf(bd, sglen * sizeof(bd_t));
  337. msdc_add_gpd(host, gpd, 1);
  338. #if MSDC_DEBUG
  339. msdc_dump_dma_desc(host);
  340. #endif
  341. msdc_flush_membuf(gpd, (1 + 1) * sizeof(gpd_t)); /* include null gpd */
  342. MSDC_WRITE32(MSDC_DMA_SA, (u32)&gpd[0]);
  343. MSDC_SET_FIELD(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
  344. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, cfg->burstsz);
  345. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
  346. #endif
  347. break;
  348. #ifdef MSDC_ENABLE_ENH_DMA_MODE
  349. case MSDC_MODE_DMA_ENHANCED:
  350. arg = cfg->arg;
  351. blkpad = (cfg->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
  352. dwpad = (cfg->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
  353. chksum = (cfg->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
  354. /* calculate the required number of gpd */
  355. num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
  356. gpd = msdc_alloc_gpd(host, num);
  357. for (i = 0; i < num; i++) {
  358. xfersz = 0;
  359. if (sglen > MAX_BD_PER_GPD) {
  360. bdlen = MAX_BD_PER_GPD;
  361. sglen -= MAX_BD_PER_GPD;
  362. } else {
  363. bdlen = sglen;
  364. sglen = 0;
  365. }
  366. bd = msdc_alloc_bd(host, bdlen);
  367. for (j = 0; j < bdlen; j++) {
  368. xfersz += sg->len;
  369. MSDC_INIT_BD(&bd[j], blkpad, dwpad, sg->addr, sg->len);
  370. sg++;
  371. }
  372. /* YD: 1 XFER_COMP interrupt will be triggerred by each GPD when it
  373. * is done. For multiple GPDs, multiple XFER_COMP interrupts will be
  374. * triggerred. In such situation, it's not easy to know which
  375. * interrupt indicates the transaction is done. So, we use the
  376. * latest one GPD's INT as the transaction done interrupt.
  377. */
  378. //gpd[i].intr = cfg->intr;
  379. gpd[i].intr = (i == num - 1) ? 0 : 1;
  380. gpd[i].cmd = cfg->cmd;
  381. gpd[i].blknum = xfersz / cfg->blklen;
  382. gpd[i].arg = arg;
  383. gpd[i].extlen = 0xC;
  384. arg += xfersz;
  385. msdc_queue_bd(host, &gpd[i], bd);
  386. msdc_flush_membuf(bd, bdlen * sizeof(bd_t));
  387. }
  388. msdc_add_gpd(host, gpd, num);
  389. #if MSDC_DEBUG
  390. msdc_dump_dma_desc(host);
  391. #endif
  392. msdc_flush_membuf(gpd, (num + 1) * sizeof(gpd_t)); /* include null gpd */
  393. MSDC_WRITE32(MSDC_DMA_SA, (u32)&gpd[0]);
  394. MSDC_SET_FIELD(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
  395. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, cfg->burstsz);
  396. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
  397. break;
  398. #endif
  399. default:
  400. break;
  401. }
  402. MSG(DMA, "[SD%d] DMA_SA = 0x%x\n", host->id, MSDC_READ32(MSDC_DMA_SA));
  403. MSG(DMA, "[SD%d] DMA_CA = 0x%x\n", host->id, MSDC_READ32(MSDC_DMA_CA));
  404. MSG(DMA, "[SD%d] DMA_CTRL = 0x%x\n", host->id, MSDC_READ32(MSDC_DMA_CTRL));
  405. MSG(DMA, "[SD%d] DMA_CFG = 0x%x\n", host->id, MSDC_READ32(MSDC_DMA_CFG));
  406. return 0;
  407. }
  408. void msdc_dma_resume(struct mmc_host *host)
  409. {
  410. u32 base = host->base;
  411. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
  412. MSG(DMA, "[SD%d] DMA resume\n", host->id);
  413. }
  414. void msdc_dma_start(struct mmc_host *host)
  415. {
  416. u32 base = host->base;
  417. #if defined(MMC_MSDC_DRV_LK)
  418. u32 wints = MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR;
  419. #endif
  420. #if defined(MMC_MSDC_DRV_LK)
  421. msdc_intr_unmask(host,wints);
  422. #endif
  423. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
  424. MSG(DMA, "[SD%d] DMA start\n", host->id);
  425. }
  426. void msdc_dma_stop(struct mmc_host *host)
  427. {
  428. u32 base = host->base;
  429. #if defined(MMC_MSDC_DRV_LK)
  430. u32 wints = MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR;
  431. #endif
  432. MSDC_SET_FIELD(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
  433. while ((MSDC_READ32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) != 0);
  434. MSDC_DMA_OFF();
  435. MSG(DMA, "[SD%d] DMA Stopped\n", host->id);
  436. #if defined(MMC_MSDC_DRV_LK)
  437. msdc_intr_mask(host,wints);
  438. #endif
  439. msdc_reset_gpd(host);
  440. }
  441. int msdc_dma_wait_done(struct mmc_host *host, u32 timeout)
  442. {
  443. u32 base = host->base;
  444. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  445. struct dma_config *cfg = &priv->cfg;
  446. u32 status;
  447. u32 error = MMC_ERR_NONE;
  448. u32 wints = MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR |
  449. MSDC_INT_DXFER_DONE | MSDC_INT_DMAQ_EMPTY |
  450. MSDC_INT_ACMDRDY | MSDC_INT_ACMDTMO | MSDC_INT_ACMDCRCERR |
  451. MSDC_INT_CMDRDY | MSDC_INT_CMDTMO | MSDC_INT_RSPCRCERR;
  452. do {
  453. MSG(DMA, "[SD%d] DMA Curr Addr: 0x%x, Active: %d\n", host->id,
  454. MSDC_READ32(MSDC_DMA_CA), MSDC_READ32(MSDC_DMA_CFG) & 0x1);
  455. #if defined(MMC_MSDC_DRV_LK)
  456. status = msdc_lk_intr_wait(host, wints);
  457. #else
  458. status = msdc_intr_wait(host, wints);
  459. #endif
  460. if (status == 0 || status & MSDC_INT_DATTMO) {
  461. MSG(DMA, "[SD%d] DMA DAT timeout(%xh)\n", host->id, status);
  462. error = MMC_ERR_TIMEOUT;
  463. goto end;
  464. } else if (status & MSDC_INT_DATCRCERR) {
  465. MSG(DMA, "[SD%d] DMA DAT CRC error(%xh)\n", host->id, status);
  466. error = MMC_ERR_BADCRC;
  467. goto end;
  468. } else if (status & MSDC_INT_CMDTMO) {
  469. MSG(DMA, "[SD%d] DMA CMD timeout(%xh)\n", host->id, status);
  470. error = MMC_ERR_TIMEOUT;
  471. goto end;
  472. } else if (status & MSDC_INT_RSPCRCERR) {
  473. MSG(DMA, "[SD%d] DMA CMD CRC error(%xh)\n", host->id, status);
  474. error = MMC_ERR_BADCRC;
  475. goto end;
  476. } else if (status & MSDC_INT_ACMDTMO) {
  477. MSG(DMA, "[SD%d] DMA ACMD timeout(%xh)\n", host->id, status);
  478. error = MMC_ERR_TIMEOUT;
  479. goto end;
  480. } else if (status & MSDC_INT_ACMDCRCERR) {
  481. MSG(DMA, "[SD%d] DMA ACMD CRC error(%xh)\n", host->id, status);
  482. error = MMC_ERR_BADCRC;
  483. goto end;
  484. }
  485. #ifdef MSDC_ENABLE_ENH_DMA_MODE
  486. if ((cfg->mode == MSDC_MODE_DMA_ENHANCED) && (status & MSDC_INT_CMDRDY)) {
  487. cfg->rsp = MSDC_READ32(SDC_RESP0);
  488. MSG(DMA, "[SD%d] DMA ENH CMD Rdy, Resp(%xh)\n", host->id, cfg->rsp);
  489. #if MSDC_DEBUG
  490. msdc_dump_card_status(cfg->rsp);
  491. #endif
  492. }
  493. #endif
  494. if (status & MSDC_INT_ACMDRDY) {
  495. cfg->autorsp = MSDC_READ32(SDC_ACMD_RESP);
  496. MSG(DMA, "[SD%d] DMA AUTO CMD Rdy, Resp(%xh)\n", host->id, cfg->autorsp);
  497. #if MSDC_DEBUG
  498. msdc_dump_card_status(cfg->autorsp);
  499. #endif
  500. }
  501. #ifdef MSDC_ENABLE_ENH_DMA_MODE
  502. if (cfg->mode == MSDC_MODE_DMA_ENHANCED) {
  503. /* YD: 1 XFER_COMP interrupt will be triggerred by each GPD when it
  504. * is done. For multiple GPDs, multiple XFER_COMP interrupts will be
  505. * triggerred. In such situation, it's not easy to know which
  506. * interrupt indicates the transaction is done. So, we use the
  507. * latest one GPD's INT as the transaction done interrupt.
  508. */
  509. if (status & MSDC_INT_DXFER_DONE)
  510. break;
  511. } else
  512. #endif
  513. {
  514. if (cfg->inboot && cfg->mode == MSDC_MODE_DMA_BASIC){
  515. //printf("Polling DMA tranfer done in eMMC boot mode\n");
  516. if (status & MSDC_INT_DXFER_DONE)
  517. break;
  518. }
  519. if (status & MSDC_INT_XFER_COMPL)
  520. break;
  521. }
  522. } while (1);
  523. /* check dma status */
  524. do {
  525. status = MSDC_READ32(MSDC_INT);
  526. if (status & MSDC_INT_GPDCSERR) {
  527. MSG(DMA, "[SD%d] GPD checksum error\n", host->id);
  528. error = MMC_ERR_BADCRC;
  529. break;
  530. } else if (status & MSDC_INT_BDCSERR) {
  531. MSG(DMA, "[SD%d] BD checksum error\n", host->id);
  532. error = MMC_ERR_BADCRC;
  533. break;
  534. } else if ((status & MSDC_DMA_CFG_STS) == 0) {
  535. break;
  536. }
  537. } while (1);
  538. end:
  539. if (error)
  540. MSDC_RESET();
  541. //printf("msdc_dma_wait_done status(%xh)\n", status);
  542. return error;
  543. }
  544. #if defined(FEATURE_MMC_SDIO)
  545. int msdc_dma_iorw(struct mmc_card *card, int write, unsigned fn,
  546. unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz)
  547. {
  548. int err = MMC_ERR_NONE, derr = MMC_ERR_NONE;
  549. struct mmc_host *host = card->host;
  550. struct mmc_command cmd;
  551. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  552. struct dma_config *cfg = &priv->cfg;
  553. u32 nblks = (u32)blocks;
  554. u64 totalsz = (u64) nblks * blksz;;
  555. memset(&cmd, 0, sizeof(struct mmc_command));
  556. cmd.opcode = SD_IO_RW_EXTENDED;
  557. cmd.arg = write ? 0x80000000 : 0x00000000;
  558. cmd.arg |= fn << 28;
  559. cmd.arg |= incr_addr ? 0x04000000 : 0x00000000;
  560. cmd.arg |= addr << 9;
  561. if (blocks == 1 && blksz <= 512) {
  562. cmd.arg |= (blksz == 512) ? 0 : blksz; /* byte mode */
  563. } else {
  564. cmd.arg |= 0x08000000 | blocks; /* block mode */
  565. }
  566. cmd.rsptyp = RESP_R5;
  567. cmd.retries = CMD_RETRIES;
  568. cmd.timeout = CMD_TIMEOUT;
  569. if (cfg->mode == MSDC_MODE_DMA_ENHANCED) {
  570. /* NOTICE: SDIO can't not issue multiple commands for one transcation data
  571. * so can't use multiple GPDs for that. But multiple transactions can
  572. * use multiple GPDs.
  573. * If BUG_ON is triggerred, please increase MAX_BD_PER_GPD number.
  574. */
  575. BUG_ON((blocks * blksz / MAX_SG_BUF_SZ) > MAX_BD_PER_GPD);
  576. msdc_set_blklen(host, blksz);
  577. msdc_set_timeout(host, 100000000, 0);
  578. msdc_dma_cmd(host, cfg, &cmd);
  579. msdc_dma_init(host, cfg, (void*)buf, totalsz);
  580. msdc_dma_config(host, cfg);
  581. msdc_dma_start(host);
  582. err = derr = msdc_dma_wait_done(host, 0xFFFFFFFF);
  583. msdc_dma_stop(host);
  584. /* SDIO workaround for CMD53 multiple block transfer */
  585. #if 1
  586. if (!err && nblks > 1) {
  587. struct mmc_command abort;
  588. memset(&abort, 0, sizeof(struct mmc_command));
  589. abort.opcode = SD_IO_RW_DIRECT;
  590. abort.arg = 0x80000000; /* write */
  591. abort.arg |= 0 << 28; /* function 0 */
  592. abort.arg |= SDIO_CCCR_ABORT << 9; /* address */
  593. abort.arg |= 0; /* abort function 0 */
  594. abort.rsptyp = RESP_R1B;
  595. abort.retries = CMD_RETRIES;
  596. abort.timeout = CMD_TIMEOUT;
  597. err = msdc_cmd(host, &abort);
  598. }
  599. #endif
  600. } else {
  601. u64 left_sz, xfer_sz;
  602. msdc_set_blklen(host, blksz);
  603. msdc_set_timeout(host, 100000000, 0);
  604. left_sz = (u64) nblks * blksz;
  605. if (cfg->mode == MSDC_MODE_DMA_BASIC) {
  606. /* NOTICE: SDIO can't not issue multiple commands for one transcation
  607. * data. If BUG_ON is triggerred, please decrease transaction data size.
  608. */
  609. BUG_ON(left_sz > MAX_DMA_CNT);
  610. xfer_sz = left_sz > MAX_DMA_CNT ? MAX_DMA_CNT : left_sz;
  611. nblks = xfer_sz / blksz;
  612. } else {
  613. xfer_sz = left_sz;
  614. }
  615. while (left_sz) {
  616. msdc_set_blknum(host, nblks);
  617. msdc_dma_init(host, cfg, (void*)buf, xfer_sz);
  618. msdc_dma_config(host, cfg);
  619. err = msdc_cmd(host, &cmd);
  620. if (err != MMC_ERR_NONE) {
  621. msdc_reset_gpd(host);
  622. goto done;
  623. }
  624. msdc_dma_start(host);
  625. err = derr = msdc_dma_wait_done(host, 0xFFFFFFFF);
  626. msdc_dma_stop(host);
  627. /* SDIO workaround for CMD53 multiple block transfer */
  628. #if 1
  629. if (!err && nblks > 1) {
  630. struct mmc_command abort;
  631. memset(&abort, 0, sizeof(struct mmc_command));
  632. abort.opcode = SD_IO_RW_DIRECT;
  633. abort.arg = 0x80000000; /* write */
  634. abort.arg |= 0 << 28; /* function 0 */
  635. abort.arg |= SDIO_CCCR_ABORT << 9; /* address */
  636. abort.arg |= 0; /* abort function 0 */
  637. abort.rsptyp = RESP_R1B;
  638. abort.retries = CMD_RETRIES;
  639. abort.timeout = CMD_TIMEOUT;
  640. err = msdc_cmd(host, &abort);
  641. }
  642. #endif
  643. if (err != MMC_ERR_NONE)
  644. goto done;
  645. buf += xfer_sz;
  646. left_sz -= xfer_sz;
  647. if (left_sz) {
  648. xfer_sz = (xfer_sz > left_sz) ? left_sz : xfer_sz;
  649. nblks = (left_sz > xfer_sz) ? nblks : left_sz / blksz;
  650. }
  651. }
  652. }
  653. done:
  654. if (derr != MMC_ERR_NONE) {
  655. printf("[SD%d] <CMD%d> IO DMA data error (%d)\n", host->id, cmd.opcode & ~SD_CMD_BIT, derr);
  656. msdc_abort_handler(host, 0);
  657. }
  658. return err;
  659. }
  660. #endif
  661. int msdc_dma_transfer(struct mmc_host *host, struct mmc_command *cmd, struct mmc_data *data)
  662. {
  663. int err = MMC_ERR_NONE, derr = MMC_ERR_NONE, cmderr= MMC_ERR_NONE;
  664. int multi;
  665. u32 blksz = host->blklen;
  666. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  667. struct dma_config *cfg = &priv->cfg;
  668. u32 base = host->base;
  669. uchar *buf = data->buf;
  670. ulong nblks = data->blks;
  671. u64 totalsz;
  672. totalsz = (u64) nblks * blksz;
  673. BUG_ON(totalsz > MAX_DMA_TRAN_SIZE);
  674. /* used for some debug func */
  675. host->cmd = cmd;
  676. multi = nblks > 1 ? 1 : 0;
  677. #ifdef MSDC_ENABLE_ENH_DMA_MODE
  678. if (cfg->mode == MSDC_MODE_DMA_ENHANCED) {
  679. if (multi && (priv->autocmd == 0))
  680. msdc_set_autocmd(host, MSDC_AUTOCMD12, 1);
  681. msdc_set_blklen(host, blksz);
  682. msdc_set_timeout(host, data->timeout * 1000000, 0);
  683. msdc_dma_cmd(host, cfg, cmd);
  684. msdc_dma_init(host, cfg, (void*)buf, totalsz);
  685. msdc_dma_config(host, cfg);
  686. msdc_dma_start(host);
  687. err = derr = msdc_dma_wait_done(host, 0xFFFFFFFF);
  688. msdc_dma_stop(host);
  689. msdc_flush_membuf(buf,nblks * blksz);
  690. if (multi && (priv->autocmd == 0))
  691. msdc_set_autocmd(host, MSDC_AUTOCMD12, 0);
  692. } else
  693. #endif
  694. {
  695. u64 left_sz, xfer_sz;
  696. msdc_set_blklen(host, blksz);
  697. msdc_set_timeout(host, data->timeout * 1000000, 0);
  698. left_sz = (u64) nblks * blksz;
  699. if (cfg->mode == MSDC_MODE_DMA_BASIC) {
  700. xfer_sz = left_sz > MAX_DMA_CNT ? MAX_DMA_CNT : left_sz;
  701. nblks = xfer_sz / blksz;
  702. } else {
  703. xfer_sz = left_sz;
  704. }
  705. while (left_sz) {
  706. derr = MMC_ERR_NONE;
  707. msdc_set_blknum(host, nblks);
  708. msdc_dma_init(host, cfg, (void*)buf, xfer_sz);
  709. err = msdc_send_cmd(host, cmd);
  710. msdc_dma_config(host, cfg);
  711. if (err != MMC_ERR_NONE) {
  712. msdc_reset_gpd(host);
  713. goto done;
  714. }
  715. err = msdc_wait_rsp(host, cmd);
  716. if (err == MMC_ERR_BADCRC) {
  717. u32 tmp = MSDC_READ32(SDC_CMD);
  718. /* check if data is used by the command or not */
  719. if (tmp & SDC_CMD_DTYP) {
  720. msdc_abort_handler(host, 1);
  721. }
  722. #if defined(FEATURE_MMC_CM_TUNING)
  723. if (host->app_cmd != 2) //Light 20130203, to prevent recursive call path: msdc_tune_cmdrsp->msdc_app_cmd->msdc_cmd->msdc_tune_cmdrsp
  724. {
  725. err = msdc_tune_cmdrsp(host, cmd);
  726. if (err != MMC_ERR_NONE){
  727. msdc_reset_gpd(host);
  728. goto done;
  729. }
  730. }
  731. #endif
  732. }
  733. if (err != MMC_ERR_NONE)
  734. goto done;
  735. msdc_dma_start(host);
  736. err = derr = msdc_dma_wait_done(host, 0xFFFFFFFF);
  737. msdc_dma_stop(host);
  738. msdc_flush_membuf(buf, nblks * blksz);
  739. if (derr != MMC_ERR_NONE)
  740. goto done;
  741. if (multi && (priv->autocmd == 0)) {
  742. cmderr = msdc_cmd_stop(host, cmd);
  743. }
  744. #ifdef MTK_EMMC_POWER_ON_WP
  745. else if(multi && (priv->autocmd & MSDC_AUTOCMD12))
  746. {
  747. if(MSDC_READ32(SDC_ACMD_RESP) & R1_WP_VIOLATION)
  748. {
  749. err = MMC_ERR_WP_VIOLATION;
  750. goto done;
  751. }
  752. }
  753. err = msdc_get_err_from_card_status(host);
  754. #endif
  755. if (cmderr != MMC_ERR_NONE)
  756. goto done;
  757. buf += xfer_sz;
  758. left_sz -= xfer_sz;
  759. /* left_sz > 0 only when in basic dma mode */
  760. if (left_sz) {
  761. cmd->arg += nblks; /* update to next start address */
  762. xfer_sz = (xfer_sz > left_sz) ? left_sz : xfer_sz;
  763. nblks = (left_sz > xfer_sz) ? nblks : left_sz / blksz;
  764. }
  765. }
  766. }
  767. done:
  768. if (err != MMC_ERR_NONE){
  769. /* msdc_cmd will do cmd tuning flow, so if enter here, cmd maybe timeout.
  770. * need reset host */
  771. //Light: msdc_abort_handler() combined from preloader/LK and CTP can not meet this purpose,
  772. // so call msdc_abort() directly
  773. //msdc_abort_handler(host, 0);
  774. msdc_abort(host);
  775. if (derr == MMC_ERR_NONE) //For Enahnced mode
  776. return err; // high level will retry
  777. }
  778. if (derr != MMC_ERR_NONE){
  779. /* crc error find in data transfer. need reset host & send cmd12 */
  780. /* if autocmd crc occur, will enter here too */
  781. printf("[SD%d] <CMD%d> DMA data error (%d)\n", host->id, cmd->opcode, derr);
  782. msdc_abort_handler(host, 1);
  783. return derr;
  784. }
  785. if (cmderr != MMC_ERR_NONE){
  786. /* msdc_cmd will do cmd tuning flow, so if enter here, cmd maybe timeout
  787. * need reset host */
  788. //Light: msdc_abort_handler() combined from preloader/LK and CTP can not meet this purpose,
  789. // so call msdc_abort() directly
  790. //msdc_abort_handler(host, 0);
  791. msdc_abort(host);
  792. return MMC_ERR_FAILED; // high level will retry
  793. }
  794. return err;
  795. }
  796. int msdc_dma_bread(struct mmc_host *host, uchar *dst, ulong src, ulong nblks)
  797. {
  798. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  799. int multi;
  800. struct mmc_command cmd;
  801. struct mmc_data data;
  802. BUG_ON(nblks > host->max_phys_segs);
  803. MSG(OPS, "[SD%d] Read data %ld blks from 0x%lx\n", host->id, nblks, src);
  804. multi = nblks > 1 ? 1 : 0;
  805. /* send read command */
  806. cmd.opcode = multi ? MMC_CMD_READ_MULTIPLE_BLOCK : MMC_CMD_READ_SINGLE_BLOCK;
  807. /* CMD23 with length only 1 */
  808. if (priv->autocmd & MSDC_AUTOCMD23)
  809. cmd.opcode = MMC_CMD_READ_MULTIPLE_BLOCK;
  810. cmd.rsptyp = RESP_R1;
  811. cmd.arg = src;
  812. cmd.retries = 0;
  813. cmd.timeout = CMD_TIMEOUT;
  814. data.blks = nblks;
  815. data.buf = (u8*)dst;
  816. data.timeout = 100; /* 100ms */
  817. return msdc_dma_transfer(host, &cmd, &data);
  818. }
  819. int msdc_dma_bwrite(struct mmc_host *host, ulong dst, uchar *src, ulong nblks)
  820. {
  821. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  822. int multi;
  823. struct mmc_command cmd;
  824. struct mmc_data data;
  825. BUG_ON(nblks > host->max_phys_segs);
  826. MSG(OPS, "[SD%d] Write data %ld blks to 0x%lx\n", host->id, nblks, dst);
  827. multi = nblks > 1 ? 1 : 0;
  828. /* send write command */
  829. cmd.opcode = multi ? MMC_CMD_WRITE_MULTIPLE_BLOCK : MMC_CMD_WRITE_BLOCK;
  830. /* CMD23 with length only 1 */
  831. if (priv->autocmd & MSDC_AUTOCMD23)
  832. cmd.opcode = MMC_CMD_WRITE_MULTIPLE_BLOCK;
  833. cmd.rsptyp = RESP_R1;
  834. cmd.arg = dst;
  835. cmd.retries = 0;
  836. cmd.timeout = CMD_TIMEOUT;
  837. data.blks = nblks;
  838. data.buf = (u8*)src;
  839. data.timeout = 250; /* 250ms */
  840. return msdc_dma_transfer(host, &cmd, &data);
  841. }
  842. #if MSDC_DEBUG
  843. void msdc_dump_dma_desc(struct mmc_host *host)
  844. {
  845. msdc_priv_t *priv = (msdc_priv_t*)host->priv;
  846. int i;
  847. u32 *ptr;
  848. if (MSG_EVT_MASK & MSG_EVT_DMA) {
  849. for (i = 0; i < priv->alloc_gpd; i++) {
  850. ptr = (u32*)&priv->gpd_pool[i];
  851. printf("[SD%d] GD[%d](0x%xh): %xh %xh %xh %xh %xh %xh %xh\n",
  852. host->id, i, (u32)ptr, *ptr, *(ptr+1), *(ptr+2), *(ptr+3), *(ptr+4),
  853. *(ptr+5), *(ptr+6));
  854. }
  855. for (i = 0; i < priv->alloc_bd; i++) {
  856. ptr = (u32*)&priv->bd_pool[i];
  857. printf("[SD%d] BD[%d](0x%xh): %xh %xh %xh %xh\n",
  858. host->id, i, (u32)ptr, *ptr, *(ptr+1), *(ptr+2), *(ptr+3));
  859. }
  860. }
  861. }
  862. #endif
  863. #endif