mt_latch.c 6.2 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <reg.h>
  32. #include <latch.h>
  33. #include <debug.h>
  34. #include <mt_reg_base.h>
  35. #include <platform/mt_latch.h>
  36. int plt_infrasys_is_timeout(const struct plt_cfg_bus_latch *self)
  37. {
  38. unsigned int ctrl;
  39. if (!self) {
  40. dprintf(CRITICAL, "%s:%d: self is Null\n",
  41. __func__, __LINE__);
  42. return 0;
  43. }
  44. ctrl = readl(INFRACFG_AO_BASE +
  45. self->infrasys_offsets.bus_infra_ctrl);
  46. return (ctrl & 0x1);
  47. }
  48. int plat_lastpc_dump(const struct plt_cfg_pc_latch *self, char *buf, int *wp)
  49. {
  50. unsigned int i;
  51. unsigned int cluster, cpu_in_cluster;
  52. unsigned long long pc_value;
  53. unsigned long long fp_value;
  54. unsigned long long sp_value;
  55. unsigned long long pc_value_h;
  56. unsigned long long fp_value_h;
  57. unsigned long long sp_value_h;
  58. for (i = 0; i < cfg_pc_latch.nr_max_core; i++) {
  59. cluster = i / 4;
  60. cpu_in_cluster = i % 4;
  61. pc_value_h =
  62. readl(MP0_DBG_CORE0_PC_HW + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  63. pc_value =
  64. (pc_value_h << 32) |
  65. readl(MP0_DBG_CORE0_PC_LW + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  66. if (g_is_64bit_kernel) {
  67. fp_value_h =
  68. readl(MP0_DBG_CORE0_FP_ARCH64_HW + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  69. fp_value =
  70. (fp_value_h << 32) |
  71. readl(MP0_DBG_CORE0_FP_ARCH64_LW + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  72. sp_value_h =
  73. readl(MP0_DBG_CORE0_SP_ARCH64_HW + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  74. sp_value
  75. = (sp_value_h << 32) |
  76. readl(MP0_DBG_CORE0_SP_ARCH64_LW + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  77. }
  78. else {
  79. fp_value =
  80. readl(MP0_DBG_CORE0_FP_ARCH32 + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  81. sp_value =
  82. readl(MP0_DBG_CORE0_SP_ARCH32 + (CPU_OFFSET * cpu_in_cluster) + (cluster * CLUSTER_OFFSET));
  83. }
  84. /*dprintf(CRITICAL,"[LAST PC] CORE_%d PC = 0x%016llx, FP = 0x%016llx, SP = 0x%016llx\n",
  85. i, pc_value, fp_value, sp_value);*/
  86. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp,
  87. "[LAST PC] CORE_%d PC = 0x%016llx, FP = 0x%016llx, SP = 0x%016llx\n",
  88. i, pc_value, fp_value, sp_value);
  89. }
  90. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, "\n");
  91. return 1;
  92. }
  93. int lastbus_mcusys_dump(const struct plt_cfg_bus_latch *self,
  94. char *buf, int *wp)
  95. {
  96. unsigned int i;
  97. unsigned long meter;
  98. unsigned long debug_raw;
  99. unsigned long w_counter, r_counter, c_counter;
  100. unsigned long mcu_base = MCUCFG_BASE;
  101. for (i = 0; i <= self->num_master_port-1; ++i) {
  102. if (self->mcusys_offsets.bus_mcu_m0 != 0xDEADBEEF)
  103. debug_raw = readl(mcu_base + self->mcusys_offsets.bus_mcu_m0 + 4 * i);
  104. else /* not support */
  105. debug_raw = 0xDEADBEEF;
  106. meter = readl(mcu_base + self->mcusys_offsets.bus_mcu_m0_m + 4 * i);
  107. w_counter = meter & 0x3f;
  108. r_counter = (meter >> 8) & 0x3f;
  109. if ((w_counter != 0) || (r_counter != 0)) {
  110. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, "[LAST BUS] Master %d: ", (i * 2));
  111. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp,
  112. "aw_pending_counter = 0x%02lx, ar_pending_counter = 0x%02lx\n",
  113. w_counter, r_counter);
  114. if (debug_raw != 0xDEADBEEF)
  115. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, "STATUS = %03lx\n", debug_raw & 0x3ff);
  116. }
  117. }
  118. for (i = 0; i <= self->num_slave_port-1; ++i) {
  119. if (self->mcusys_offsets.bus_mcu_s1 != 0xDEADBEEF)
  120. debug_raw = readl(mcu_base + self->mcusys_offsets.bus_mcu_s1 + 4 * i);
  121. else /* not support */
  122. debug_raw = 0xDEADBEEF;
  123. meter = readl(mcu_base + self->mcusys_offsets.bus_mcu_s1_m + 4 * i);
  124. w_counter = meter & 0x3f;
  125. r_counter = (meter >> 8) & 0x3f;
  126. c_counter = (meter >> 16) & 0x3f;
  127. if ((w_counter != 0) || (r_counter != 0) || (c_counter != 0)) {
  128. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, "[LAST BUS] Slave %d: ", i + 4);
  129. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp,
  130. "aw_pending_counter = 0x%02lx, ar_pending_counter = 0x%02lx,",
  131. w_counter, r_counter);
  132. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, " ac_pending_counter = 0x%02lx\n", c_counter);
  133. if (debug_raw != 0xDEADBEEF) {
  134. if (i <= 2)
  135. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, "STATUS = %04lx\n", debug_raw & 0x3fff);
  136. else
  137. *wp += snprintf(buf + *wp, LATCH_BUF_LENGTH - *wp, "STATUS = %04lx\n", debug_raw & 0xffff);
  138. }
  139. }
  140. }
  141. return 0;
  142. }