mt_rtc_6356.c 10 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <debug.h>
  32. #include <platform/mt_typedefs.h>
  33. #include <platform/mt_rtc.h>
  34. #include <platform/boot_mode.h>
  35. #include <platform/mt_pmic_wrap_init.h>
  36. #include <target/board.h>
  37. #include <platform/mtk_wdt.h>
  38. #include <platform/mt_rtc_hw.h>
  39. #define DBG_RTC_C(x...) dprintf(CRITICAL, x)
  40. #define DBG_RTC_I(x...) dprintf(INFO, x)
  41. #define DBG_RTC_S(x...) dprintf(SPEW, x)
  42. #define RTC_RELPWR_WHEN_XRST 1 /* BBPU = 0 when xreset_rstb goes low */
  43. extern BOOT_ARGUMENT *g_boot_arg;
  44. static U16 RTC_Read(U16 addr)
  45. {
  46. U32 rdata=0;
  47. pwrap_read((U32)addr, &rdata);
  48. return (U16)rdata;
  49. }
  50. static void RTC_Write(U16 addr, U16 data)
  51. {
  52. pwrap_write((U32)addr, (U32)data);
  53. }
  54. #define rtc_busy_wait() \
  55. do { \
  56. while (RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY); \
  57. } while (0)
  58. static unsigned long rtc_mktime(int yea, int mth, int dom, int hou, int min, int sec)
  59. {
  60. unsigned long d1, d2, d3;
  61. mth -= 2;
  62. if (mth <= 0) {
  63. mth += 12;
  64. yea -= 1;
  65. }
  66. d1 = (yea - 1) * 365 + (yea / 4 - yea / 100 + yea / 400);
  67. d2 = (367 * mth / 12 - 30) + 59;
  68. d3 = d1 + d2 + (dom - 1) - 719162;
  69. return ((d3 * 24 + hou) * 60 + min) * 60 + sec;
  70. }
  71. static void rtc_write_trigger(void)
  72. {
  73. RTC_Write(RTC_WRTGR, 1);
  74. rtc_busy_wait();
  75. }
  76. void rtc_writeif_unlock(void)
  77. {
  78. RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1);
  79. rtc_write_trigger();
  80. RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2);
  81. rtc_write_trigger();
  82. }
  83. void rtc_writeif_lock(void)
  84. {
  85. RTC_Write(RTC_PROT, 0);
  86. rtc_write_trigger();
  87. }
  88. static void rtc_xosc_write(U16 val)
  89. {
  90. RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
  91. mdelay(1);
  92. RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
  93. mdelay(1);
  94. RTC_Write(RTC_OSC32CON, val);
  95. mdelay(1);
  96. }
  97. void rtc_enable_k_eosc(void)
  98. {
  99. pmic_config_interface(PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR, 1, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT);
  100. pmic_config_interface(PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR, 1, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT);
  101. pmic_config_interface(PMIC_RG_RTC_EOSC32_CK_PDN_ADDR, 0, PMIC_RG_RTC_EOSC32_CK_PDN_MASK, PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
  102. /* If cali eosc every second, needing to add the following configuration, default period is 8 sec */
  103. /* pmic_config_interface(PMIC_EOSC_CALI_TD_ADDR, 0x3, PMIC_EOSC_CALI_TD_MASK, PMIC_EOSC_CALI_TD_SHIFT); */
  104. RTC_Write(RTC_BBPU, RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  105. rtc_write_trigger();
  106. rtc_xosc_write((RTC_Read(RTC_OSC32CON) & ~RTC_EMBCK_SEL_EOSC) | RTC_EMBCK_SEL_K_EOSC | RTC_EMBCK_SRC_SEL);
  107. DBG_RTC_I("[RTC] k_eosc bbpu = 0x%x, con = 0x%x, osc32con = 0x%x, sec = 0x%x, yea = 0x%x\n", RTC_Read(RTC_BBPU), RTC_Read(RTC_CON), RTC_Read(RTC_OSC32CON), RTC_Read(RTC_AL_SEC), RTC_Read(RTC_AL_YEA));
  108. }
  109. void rtc_disable_2sec_reboot(void)
  110. {
  111. U16 reboot;
  112. reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) & ~RTC_BBPU_AUTO_PDN_SEL;
  113. RTC_Write(RTC_AL_SEC, reboot);
  114. rtc_write_trigger();
  115. }
  116. void rtc_bbpu_power_down(void)
  117. {
  118. U16 bbpu;
  119. rtc_disable_2sec_reboot();
  120. rtc_enable_k_eosc();
  121. bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN;
  122. rtc_writeif_unlock();
  123. RTC_Write(RTC_BBPU, bbpu);
  124. rtc_write_trigger();
  125. pmic_power_hold(0);
  126. }
  127. U16 rtc_rdwr_uart_bits(U16 *val)
  128. {
  129. U16 pdn2;
  130. if (val) {
  131. pdn2 = RTC_Read(RTC_PDN2) & ~RTC_PDN2_UART_MASK;
  132. pdn2 |= (*val & (RTC_PDN2_UART_MASK >> RTC_PDN2_UART_SHIFT)) << RTC_PDN2_UART_SHIFT;
  133. RTC_Write(RTC_PDN2, pdn2);
  134. rtc_write_trigger();
  135. }
  136. return (RTC_Read(RTC_PDN2) & RTC_PDN2_UART_MASK) >> RTC_PDN2_UART_SHIFT;
  137. }
  138. bool rtc_boot_check(bool can_alarm_boot)
  139. {
  140. U16 irqsta, pdn1, pdn2, spar0, spar1;
  141. irqsta = RTC_Read(RTC_IRQ_STA); /* read clear */
  142. pdn1 = RTC_Read(RTC_PDN1);
  143. pdn2 = RTC_Read(RTC_PDN2);
  144. spar0 = RTC_Read(RTC_SPAR0);
  145. spar1 = RTC_Read(RTC_SPAR1);
  146. /*printf("irqsta = 0x%x, pdn1 = 0x%x, pdn2 = 0x%x, spar0 = 0x%x, spar1 = 0x%x\n",
  147. irqsta, pdn1, pdn2, spar0, spar1);*/
  148. if (irqsta & RTC_IRQ_STA_AL) {
  149. #if RTC_RELPWR_WHEN_XRST
  150. /* set AUTO bit because AUTO = 0 when PWREN = 1 and alarm occurs */
  151. U16 bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_AUTO;
  152. RTC_Write(RTC_BBPU, bbpu);
  153. rtc_write_trigger();
  154. #endif
  155. if (pdn1 & RTC_PDN1_PWRON_TIME) { /* power-on time is available */
  156. U16 now_sec, now_min, now_hou, now_dom, now_mth, now_yea;
  157. U16 irqen, sec, min, hou, dom, mth, yea;
  158. unsigned long now_time, time;
  159. now_sec = RTC_Read(RTC_TC_SEC);
  160. now_min = RTC_Read(RTC_TC_MIN);
  161. now_hou = RTC_Read(RTC_TC_HOU);
  162. now_dom = RTC_Read(RTC_TC_DOM);
  163. now_mth = RTC_Read(RTC_TC_MTH);
  164. now_yea = RTC_Read(RTC_TC_YEA) + RTC_MIN_YEAR;
  165. if (RTC_Read(RTC_TC_SEC) < now_sec) { /* SEC has carried */
  166. now_sec = RTC_Read(RTC_TC_SEC);
  167. now_min = RTC_Read(RTC_TC_MIN);
  168. now_hou = RTC_Read(RTC_TC_HOU);
  169. now_dom = RTC_Read(RTC_TC_DOM);
  170. now_mth = RTC_Read(RTC_TC_MTH);
  171. now_yea = RTC_Read(RTC_TC_YEA) + RTC_MIN_YEAR;
  172. }
  173. sec = ((spar0 & RTC_SPAR0_PWRON_SEC_MASK) >> RTC_SPAR0_PWRON_SEC_SHIFT);
  174. min = ((spar1 & RTC_SPAR1_PWRON_MIN_MASK) >> RTC_SPAR1_PWRON_MIN_SHIFT);
  175. hou = ((spar1 & RTC_SPAR1_PWRON_HOU_MASK) >> RTC_SPAR1_PWRON_HOU_SHIFT);
  176. dom = ((spar1 & RTC_SPAR1_PWRON_DOM_MASK) >> RTC_SPAR1_PWRON_DOM_SHIFT);
  177. mth = ((pdn2 & RTC_PDN2_PWRON_MTH_MASK) >> RTC_PDN2_PWRON_MTH_SHIFT);
  178. yea = ((pdn2 & RTC_PDN2_PWRON_YEA_MASK) >> RTC_PDN2_PWRON_YEA_SHIFT) + RTC_MIN_YEAR;
  179. now_time = rtc_mktime(now_yea, now_mth, now_dom, now_hou, now_min, now_sec);
  180. time = rtc_mktime(yea, mth, dom, hou, min, sec);
  181. DBG_RTC_I("now = %d/%d/%d %d:%d:%d (%lu)\n",
  182. now_yea, now_mth, now_dom, now_hou, now_min, now_sec, now_time);
  183. DBG_RTC_I("power-on = %d/%d/%d %d:%d:%d (%lu)\n",
  184. yea, mth, dom, hou, min, sec, time);
  185. if (now_time >= time - 1 && now_time <= time + 4) { /* power on */
  186. pdn1 &= ~(RTC_PDN1_PWRON_TIME | RTC_PDN1_FAC_RESET | RTC_PDN1_BYPASS_PWR);
  187. RTC_Write(RTC_PDN1, pdn1);
  188. RTC_Write(RTC_PDN2, pdn2 | RTC_PDN2_PWRON_ALARM);
  189. rtc_write_trigger();
  190. if (can_alarm_boot &&
  191. !(pdn2 & RTC_PDN2_PWRON_LOGO)) { /* no logo means ALARM_BOOT */
  192. g_boot_mode = ALARM_BOOT;
  193. }
  194. return true;
  195. } else if (now_time < time) { /* set power-on alarm */
  196. RTC_Write(RTC_AL_YEA, (RTC_Read(RTC_AL_YEA) & ~(RTC_AL_YEA_MASK)) | ((yea - RTC_MIN_YEAR) & RTC_AL_YEA_MASK));
  197. RTC_Write(RTC_AL_MTH, (RTC_Read(RTC_AL_MTH)&RTC_NEW_SPARE3)|mth);
  198. RTC_Write(RTC_AL_DOM, (RTC_Read(RTC_AL_DOM)&RTC_NEW_SPARE1)|dom);
  199. RTC_Write(RTC_AL_HOU, (RTC_Read(RTC_AL_HOU)&RTC_NEW_SPARE_FG_MASK)|hou);
  200. RTC_Write(RTC_AL_MIN, min);
  201. RTC_Write(RTC_AL_SEC, (RTC_Read(RTC_AL_SEC) & (~RTC_AL_SEC_MASK)) | (sec & RTC_AL_SEC_MASK));
  202. RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW); /* mask DOW */
  203. rtc_write_trigger();
  204. irqen = RTC_Read(RTC_IRQ_EN) | RTC_IRQ_EN_ONESHOT_AL;
  205. RTC_Write(RTC_IRQ_EN, irqen);
  206. rtc_write_trigger();
  207. }
  208. }
  209. }
  210. if ((pdn1 & RTC_PDN1_RECOVERY_MASK) == RTC_PDN1_FAC_RESET) { /* factory data reset */
  211. RTC_Write(RTC_PDN1, pdn1 & ~RTC_PDN1_FAC_RESET);
  212. rtc_write_trigger();
  213. return true;
  214. }
  215. if (pdn1 & RTC_PDN1_BYPASS_PWR) { /* bypass power key detection */
  216. RTC_Write(RTC_PDN1, pdn1 & ~RTC_PDN1_BYPASS_PWR);
  217. rtc_write_trigger();
  218. return true;
  219. }
  220. return false;
  221. }
  222. void Set_Clr_RTC_PDN1_bit13(bool flag)
  223. {
  224. U16 pdn1;
  225. rtc_writeif_unlock();
  226. //use PDN1 bit13 for LK
  227. pdn1 = RTC_Read(RTC_PDN1);
  228. if (flag==true)
  229. pdn1 = pdn1 | RTC_PDN1_FAST_BOOT;
  230. else if (flag==false)
  231. pdn1 = pdn1 & ~RTC_PDN1_FAST_BOOT;
  232. RTC_Write(RTC_PDN1, pdn1);
  233. rtc_write_trigger();
  234. }
  235. bool Check_RTC_PDN1_bit13(void)
  236. {
  237. U16 pdn1;
  238. pdn1 = RTC_Read(RTC_PDN1);
  239. if (pdn1 & RTC_PDN1_FAST_BOOT)
  240. return true;
  241. else
  242. return false;
  243. }
  244. bool Check_RTC_Recovery_Mode(void)
  245. {
  246. U16 pdn1;
  247. pdn1 = RTC_Read(RTC_PDN1);
  248. if ( (pdn1 & RTC_PDN1_RECOVERY_MASK)==RTC_PDN1_FAC_RESET )
  249. return true;
  250. else
  251. return false;
  252. }
  253. #if 1
  254. bool rtc_2sec_boot_check(void)
  255. {
  256. int boot_reason;
  257. if (g_boot_arg->maggic_number == BOOT_ARGUMENT_MAGIC) {
  258. boot_reason = g_boot_arg->boot_reason;
  259. if (boot_reason == BR_2SEC_REBOOT)
  260. return true;
  261. }
  262. return false;
  263. }
  264. #endif
  265. void Set_RTC_Recovery_Mode(bool flag)
  266. {
  267. U16 pdn1;
  268. rtc_writeif_unlock();
  269. pdn1 = RTC_Read(RTC_PDN1);
  270. if (flag==true)
  271. pdn1 = pdn1 | RTC_PDN1_FAC_RESET;
  272. else if (flag==false)
  273. pdn1 = pdn1 & ~RTC_PDN1_FAC_RESET;
  274. RTC_Write(RTC_PDN1, pdn1);
  275. rtc_write_trigger();
  276. DBG_RTC_I("Set_RTC_Fastboot_Mode\n");
  277. }