primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. //#include<linux/timer.h>
  44. #define DDP_LK_BOOT
  45. #ifndef HZ
  46. #define HZ 100
  47. #endif
  48. #ifdef DDP_LK_BOOT
  49. typedef void * cmdqRecHandle;
  50. #endif
  51. #define ALIGN_TO(x, n) \
  52. (((x) + ((n) - 1)) & ~((n) - 1))
  53. int primary_display_use_cmdq = CMDQ_DISABLE;
  54. int primary_display_use_m4u = 0;
  55. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  56. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  57. static UINT32 disp_fb_pages = 3; ///double buffer
  58. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  59. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  60. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  61. extern void video_printf(const char *fmt, ...);
  62. extern void disp_path_clock_on(char *str);
  63. extern int disp_path_clock_off(char* name );
  64. typedef struct _disp_dfo_item {
  65. char name[32];
  66. int value;
  67. } disp_dfo_item_t;
  68. static disp_dfo_item_t disp_dfo_setting[] = {
  69. {"LCM_FAKE_WIDTH", 0},
  70. {"LCM_FAKE_HEIGHT", 0},
  71. {"DISP_DEBUG_SWITCH", 0}
  72. };
  73. typedef struct {
  74. int state;
  75. int need_trigger_overlay;
  76. DISP_PRIMARY_PATH_MODE mode;
  77. unsigned int last_vsync_tick;
  78. #ifndef DDP_LK_BOOT
  79. struct mutex lock;
  80. #endif
  81. disp_lcm_handle * plcm;
  82. cmdqRecHandle cmdq_handle_config;
  83. cmdqRecHandle cmdq_handle_trigger;
  84. disp_path_handle dpmgr_handle;
  85. disp_path_handle ovl2mem_path_handle;
  86. } display_primary_path_context;
  87. #define pgc _get_context()
  88. static display_primary_path_context* _get_context(void)
  89. {
  90. static int is_context_inited = 0;
  91. static display_primary_path_context g_context;
  92. if (!is_context_inited) {
  93. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  94. is_context_inited = 1;
  95. }
  96. return &g_context;
  97. }
  98. static void _primary_path_lock(void)
  99. {
  100. #ifndef DDP_LK_BOOT
  101. disp_sw_mutex_lock(&(pgc->lock));
  102. #endif
  103. }
  104. static void _primary_path_unlock(void)
  105. {
  106. #ifndef DDP_LK_BOOT
  107. disp_sw_mutex_unlock(&(pgc->lock));
  108. #endif
  109. }
  110. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  111. {
  112. if (plcm == NULL) {
  113. DISPERR("plcm is null\n");
  114. return DISP_MODULE_NONE;
  115. }
  116. if (plcm->params->type == LCM_TYPE_DSI) {
  117. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  118. return DISP_MODULE_DSI0;
  119. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  120. return DISP_MODULE_DSI1;
  121. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  122. return DISP_MODULE_DSIDUAL;
  123. } else {
  124. return DISP_MODULE_DSI0;
  125. }
  126. } else if (plcm->params->type == LCM_TYPE_DPI) {
  127. return DISP_MODULE_DPI;
  128. } else {
  129. DISPERR("can't find primary path dst module\n");
  130. return DISP_MODULE_NONE;
  131. }
  132. }
  133. static int _build_path_direct_link(void)
  134. {
  135. int ret = 0;
  136. DISP_MODULE_ENUM dst_module = 0;
  137. DISPFUNC();
  138. pgc->mode = DIRECT_LINK_MODE;
  139. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  140. if (pgc->dpmgr_handle) {
  141. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  142. } else {
  143. DISPCHECK("dpmgr create path FAIL\n");
  144. return -1;
  145. }
  146. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  147. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  148. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  149. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  150. return ret;
  151. }
  152. static int _build_path_decouple(void)
  153. {
  154. return 0;
  155. }
  156. static int _build_path_single_layer(void)
  157. {
  158. return 0;
  159. }
  160. static int _build_path_debug_rdma1_dsi0(void)
  161. {
  162. int ret = 0;
  163. DISP_MODULE_ENUM dst_module = 0;
  164. DISPFUNC();
  165. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  166. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  167. if (pgc->dpmgr_handle) {
  168. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  169. } else {
  170. DISPCHECK("dpmgr create path FAIL\n");
  171. return -1;
  172. }
  173. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  174. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  175. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  176. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  177. return ret;
  178. }
  179. static void _build_cmdq_trigger_loop(void)
  180. {
  181. #ifndef DDP_LK_BOOT
  182. int ret = 0;
  183. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  184. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  185. cmdqRecReset(pgc->cmdq_handle_trigger);
  186. if (primary_display_is_video_mode()) {
  187. // wait and clear stream_done
  188. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  189. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  190. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  191. } else {
  192. // only in DSI Command mode we need to wait these
  193. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  194. // no internal te on fpga now.
  195. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  196. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  197. // block config threads, we'll about to update frame
  198. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  199. // only in DSI command mode we need to enable mutex explicitly
  200. // WRITE mutex enable
  201. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  202. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  203. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  204. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  205. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  206. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  207. // polling DSI idle
  208. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  209. // polling wdma frame done
  210. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  211. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  212. /*********************/
  213. /***build cmdq finished***/
  214. /*********************/
  215. // TODO:
  216. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  217. // RUN forever!!!!
  218. BUG_ON(ret < 0);
  219. }
  220. #endif
  221. }
  222. static void _start_cmdq_trigger_loop(void)
  223. {
  224. #ifndef DDP_LK_BOOT
  225. int ret = 0;
  226. // this should be called only once because trigger loop will nevet stop
  227. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  228. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  229. #endif
  230. }
  231. static void _set_cmdq_config_handle_dirty(void)
  232. {
  233. #ifndef DDP_LK_BOOT
  234. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  235. cmdqRecFlush(pgc->cmdq_handle_config);
  236. #endif
  237. }
  238. static void _reset_cmdq_config_handle(void)
  239. {
  240. #ifndef DDP_LK_BOOT
  241. cmdqRecReset(pgc->cmdq_handle_config);
  242. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  243. #endif
  244. }
  245. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  246. {
  247. if (src && dst) {
  248. dst->inputFormat = src->fmt;
  249. dst->address = src->addr;
  250. dst->width = src->src_w;
  251. dst->height = src->src_h;
  252. dst->pitch = src->src_pitch;
  253. return 0;
  254. } else {
  255. DISPERR("src(0x%08x) or dst(0x%08x) is null\n",
  256. (unsigned int)src, (unsigned int)dst);
  257. return -1;
  258. }
  259. }
  260. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  261. {
  262. if (src && dst) {
  263. dst->layer = src->layer;
  264. dst->layer_en = src->layer_en;
  265. dst->fmt = src->fmt;
  266. dst->addr = src->addr;
  267. dst->vaddr = src->vaddr;
  268. dst->src_x = src->src_x;
  269. dst->src_y = src->src_y;
  270. dst->src_w = src->src_w;
  271. dst->src_h = src->src_h;
  272. dst->src_pitch = src->src_pitch;
  273. dst->dst_x = src->dst_x;
  274. dst->dst_y = src->dst_y;
  275. dst->dst_w = src->dst_w;
  276. dst->dst_h = src->dst_h;
  277. dst->keyEn = src->keyEn;
  278. dst->key = src->key;
  279. dst->aen = src->aen;
  280. dst->alpha = src->alpha;
  281. dst->isDirty = src->isDirty;
  282. dst->buff_idx = src->buff_idx;
  283. dst->identity = src->identity;
  284. dst->connected_type = src->connected_type;
  285. dst->security = src->security;
  286. return 0;
  287. } else {
  288. DISPERR("src(0x%08x) or dst(0x%08x) is null\n",
  289. (unsigned int)src, (unsigned int)dst);
  290. return -1;
  291. }
  292. }
  293. void _dump_lcm_info_by_video_printf(void)
  294. {
  295. LCM_DRIVER *l = NULL;
  296. LCM_PARAMS *p = NULL;
  297. disp_lcm_handle *plcm = pgc->plcm;
  298. if (plcm == NULL) {
  299. DISPERR("plcm is null\n");
  300. return;
  301. }
  302. l = plcm->drv;
  303. p = plcm->params;
  304. if (l && p) {
  305. video_printf("[LCM], name: %s\n", l->name);
  306. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  307. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  308. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  309. switch (p->lcm_if) {
  310. case LCM_INTERFACE_DSI0:
  311. video_printf("[LCM] interface: DSI0\n");
  312. break;
  313. case LCM_INTERFACE_DSI1:
  314. video_printf("[LCM] interface: DSI1\n");
  315. break;
  316. case LCM_INTERFACE_DPI0:
  317. video_printf("[LCM] interface: DPI0\n");
  318. break;
  319. case LCM_INTERFACE_DPI1:
  320. video_printf("[LCM] interface: DPI1\n");
  321. break;
  322. case LCM_INTERFACE_DBI0:
  323. video_printf("[LCM] interface: DBI0\n");
  324. break;
  325. default:
  326. video_printf("[LCM] interface: unknown\n");
  327. break;
  328. }
  329. switch (p->type) {
  330. case LCM_TYPE_DBI:
  331. video_printf("[LCM] Type: DBI\n");
  332. break;
  333. case LCM_TYPE_DSI:
  334. video_printf("[LCM] Type: DSI\n");
  335. break;
  336. case LCM_TYPE_DPI:
  337. video_printf("[LCM] Type: DPI\n");
  338. break;
  339. default:
  340. video_printf("[LCM] TYPE: unknown\n");
  341. break;
  342. }
  343. if (p->type == LCM_TYPE_DSI) {
  344. switch (p->dsi.mode) {
  345. case CMD_MODE:
  346. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  347. break;
  348. case SYNC_PULSE_VDO_MODE:
  349. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  350. break;
  351. case SYNC_EVENT_VDO_MODE:
  352. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  353. break;
  354. case BURST_VDO_MODE:
  355. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  356. break;
  357. default:
  358. video_printf("[LCM] DSI Mode: Unknown\n");
  359. break;
  360. }
  361. }
  362. if (p->type == LCM_TYPE_DSI) {
  363. video_printf("[LCM] LANE_NUM: %d,data_format:(%d,%d,%d,%d)\n",p->dsi.LANE_NUM,
  364. p->dsi.data_format.color_order, p->dsi.data_format.format,
  365. p->dsi.data_format.padding, p->dsi.data_format.trans_seq);
  366. #ifdef MY_TODO
  367. #error
  368. #endif
  369. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  370. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  371. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  372. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  373. }
  374. }
  375. return;
  376. }
  377. unsigned int mt_disp_parse_dfo_setting(void)
  378. {
  379. unsigned int i, j=0 ;
  380. char tmp[11];
  381. char *buffer = NULL;
  382. char *ptr = NULL;
  383. buffer = (char *)get_env("DFO");
  384. DISPMSG("env buffer = %s\n", buffer);
  385. if (buffer != NULL) {
  386. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  387. j = 0;
  388. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  389. ptr = strstr(buffer, disp_dfo_setting[i].name);
  390. if (ptr == NULL) continue;
  391. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  392. do {} while ((*ptr++) != ',');
  393. do {tmp[j++] = *ptr++;}
  394. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  395. disp_dfo_setting[i].value = atoi((const char*)tmp);
  396. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  397. }
  398. } else {
  399. DISPMSG("env buffer = NULL\n");
  400. }
  401. return 0;
  402. }
  403. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  404. {
  405. char *disp_name;
  406. int disp_value;
  407. unsigned int i = 0;
  408. if (string == NULL)
  409. return -1;
  410. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  411. disp_name = disp_dfo_setting[i].name;
  412. disp_value = disp_dfo_setting[i].value;
  413. if (!strcmp(disp_name, string)) {
  414. *value = disp_value;
  415. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  416. return 0;
  417. }
  418. }
  419. return 0;
  420. }
  421. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  422. int primary_display_is_lcm_connected(void)
  423. {
  424. return pgc->plcm->is_connected;
  425. }
  426. const char* primary_display_get_lcm_name(void)
  427. {
  428. return disp_lcm_get_name(pgc->plcm);
  429. }
  430. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  431. {
  432. if (pgc->plcm) {
  433. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  434. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  435. // otherwise we will have a panic in lk(root cause unknown).
  436. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  437. DISPERR("Invalid resolution: %dx%d\n", width, height);
  438. return -1;
  439. }
  440. if (primary_display_is_video_mode()) {
  441. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  442. return -1;
  443. }
  444. pgc->plcm->params->width = width;
  445. pgc->plcm->params->height = height;
  446. return 0;
  447. } else {
  448. return -1;
  449. }
  450. }
  451. int primary_display_init(char *lcm_name)
  452. {
  453. DISPFUNC();
  454. DISP_STATUS ret = DISP_STATUS_OK;
  455. LCM_PARAMS *lcm_param = NULL;
  456. dpmgr_init();
  457. #ifndef DDP_LK_BOOT
  458. mutex_init(&(pgc->lock));
  459. #endif
  460. _primary_path_lock();
  461. if (pgc->plcm == NULL)
  462. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  463. if (pgc->plcm == NULL) {
  464. DISPCHECK("disp_lcm_probe returns null\n");
  465. ret = DISP_STATUS_ERROR;
  466. goto done;
  467. } else {
  468. DISPCHECK("disp_lcm_probe SUCCESS\n");
  469. }
  470. lcm_param = disp_lcm_get_params(pgc->plcm);
  471. if (lcm_param == NULL) {
  472. DISPERR("get lcm params FAILED\n");
  473. ret = DISP_STATUS_ERROR;
  474. goto done;
  475. }
  476. if (primary_display_mode == DIRECT_LINK_MODE) {
  477. _build_path_direct_link();
  478. DISPCHECK("primary display is DIRECT LINK MODE\n");
  479. } else if (primary_display_mode == DECOUPLE_MODE) {
  480. _build_path_decouple();
  481. DISPCHECK("primary display is DECOUPLE MODE\n");
  482. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  483. _build_path_single_layer();
  484. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  485. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  486. _build_path_debug_rdma1_dsi0();
  487. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  488. } else {
  489. DISPCHECK("primary display mode is WRONG\n");
  490. }
  491. _build_cmdq_trigger_loop();
  492. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  493. _start_cmdq_trigger_loop();
  494. DISPCHECK("primary display START cmdq trigger loop finished\n");
  495. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  496. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  497. disp_ddp_path_config data_config;
  498. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  499. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  500. data_config.dst_w = disp_lcm_width(pgc->plcm);
  501. data_config.dst_h = disp_lcm_height(pgc->plcm);
  502. if (lcm_param->type == LCM_TYPE_DSI) {
  503. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  504. data_config.lcm_bpp = 24;
  505. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  506. data_config.lcm_bpp = 16;
  507. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  508. data_config.lcm_bpp = 18;
  509. } else if (lcm_param->type == LCM_TYPE_DPI) {
  510. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  511. data_config.lcm_bpp = 24;
  512. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  513. data_config.lcm_bpp = 16;
  514. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  515. data_config.lcm_bpp = 18;
  516. }
  517. data_config.dst_dirty = 1;
  518. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  519. ret = disp_lcm_init(pgc->plcm);
  520. if (primary_display_is_video_mode()) {
  521. if (lcm_param->dsi.lfr_enable == 1) {
  522. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  523. } else {
  524. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  525. }
  526. } else {
  527. }
  528. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  529. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  530. pgc->state = 1;
  531. done:
  532. _primary_path_unlock();
  533. return ret;
  534. }
  535. // register rdma done event
  536. int primary_display_wait_for_idle(void)
  537. {
  538. DISP_STATUS ret = DISP_STATUS_OK;
  539. DISPFUNC();
  540. _primary_path_lock();
  541. _primary_path_unlock();
  542. return ret;
  543. }
  544. int primary_display_wait_for_dump(void)
  545. {
  546. return 0;
  547. }
  548. static long int get_current_time_us(void)
  549. {
  550. return get_timer(0);
  551. }
  552. int priamry_display_wait_for_vsync(void)
  553. {
  554. int ret = 0;
  555. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  556. if (ret == -2) {
  557. DISPCHECK("vsync for primary display path not enabled yet\n");
  558. return -1;
  559. }
  560. // pgc->last_vsync_tick = get_current_time_us();
  561. pgc->last_vsync_tick = 0;
  562. return 0;
  563. }
  564. int primary_display_suspend(void)
  565. {
  566. DISP_STATUS ret = DISP_STATUS_OK;
  567. DISPFUNC();
  568. _primary_path_lock();
  569. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  570. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  571. #ifndef DDP_LK_BOOT
  572. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  573. #endif
  574. disp_path_clock_off("Primary Display Path");
  575. pgc->state = 0;
  576. _primary_path_unlock();
  577. return ret;
  578. }
  579. int primary_display_resume(void)
  580. {
  581. DISP_STATUS ret = DISP_STATUS_OK;
  582. DISPFUNC();
  583. _primary_path_lock();
  584. disp_path_clock_on("Primary Display Path");
  585. pgc->state = 1;
  586. _primary_path_unlock();
  587. return ret;
  588. }
  589. int primary_display_is_alive(void)
  590. {
  591. unsigned int temp = 0;
  592. DISPFUNC();
  593. _primary_path_lock();
  594. temp = pgc->state;
  595. _primary_path_unlock();
  596. return temp;
  597. }
  598. int primary_display_is_sleepd(void)
  599. {
  600. unsigned int temp = 0;
  601. DISPFUNC();
  602. _primary_path_lock();
  603. temp = !pgc->state;
  604. _primary_path_unlock();
  605. return temp;
  606. }
  607. #ifdef MTK_ROUND_CORNER_SUPPORT
  608. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  609. {
  610. if (pgc->plcm == NULL) {
  611. return NULL;
  612. }
  613. if (pgc->plcm->params) {
  614. return &(pgc->plcm->params->round_corner_params);
  615. } else {
  616. DISPERR("lcm_params is null!\n");
  617. return NULL;
  618. }
  619. }
  620. int disp_get_round_corner_size(void)
  621. {
  622. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  623. int pitch = DISP_GetScreenWidth();
  624. int size = 0;
  625. if (corner_params)
  626. size = corner_params->h * pitch * 2 * 2;
  627. else
  628. DISPERR("corner_params is null!\n");
  629. return size;
  630. }
  631. #endif
  632. int primary_display_get_width(void)
  633. {
  634. if (pgc->plcm == NULL) {
  635. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  636. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  637. if (pgc->plcm == NULL)
  638. return 0;
  639. }
  640. if (pgc->plcm->params) {
  641. return pgc->plcm->params->width;
  642. } else {
  643. DISPERR("lcm_params is null!\n");
  644. return 0;
  645. }
  646. }
  647. int primary_display_get_height(void)
  648. {
  649. if (pgc->plcm == NULL) {
  650. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  651. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  652. if (pgc->plcm == NULL)
  653. return 0;
  654. }
  655. if (pgc->plcm->params) {
  656. return pgc->plcm->params->height;
  657. } else {
  658. DISPERR("lcm_params is null!\n");
  659. return 0;
  660. }
  661. }
  662. int primary_display_get_bpp(void)
  663. {
  664. return 32;
  665. }
  666. int primary_display_get_info(void *dispif_info)
  667. {
  668. #if 0
  669. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  670. switch (pgc->lcm_param->type) {
  671. case LCM_TYPE_DBI: {
  672. dispif_info->displayType = DISPIF_TYPE_DBI;
  673. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  674. dispif_info->isHwVsyncAvailable = 1;
  675. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  676. break;
  677. }
  678. case LCM_TYPE_DPI: {
  679. dispif_info->displayType = DISPIF_TYPE_DPI0;
  680. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  681. dispif_info->isHwVsyncAvailable = 1;
  682. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  683. break;
  684. }
  685. case LCM_TYPE_DSI: {
  686. dispif_info->displayType = DISPIF_TYPE_DSI0;
  687. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  688. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  689. dispif_info->isHwVsyncAvailable = 1;
  690. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  691. } else {
  692. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  693. dispif_info->isHwVsyncAvailable = 1;
  694. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  695. }
  696. break;
  697. }
  698. default:
  699. break;
  700. }
  701. #ifdef MY_TODO
  702. #error
  703. if (disp_if_drv->get_panel_color_format()) {
  704. switch (disp_if_drv->get_panel_color_format()) {
  705. case PANEL_COLOR_FORMAT_RGB565:
  706. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  707. case PANEL_COLOR_FORMAT_RGB666:
  708. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  709. case PANEL_COLOR_FORMAT_RGB888:
  710. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  711. default:
  712. break;
  713. }
  714. }
  715. #endif
  716. dispif_info->displayWidth = primary_display_get_width();
  717. dispif_info->displayHeight = primary_display_get_height();
  718. #ifdef MY_TODO
  719. #error
  720. dispif_info->vsyncFPS = lcd_fps;
  721. #endif
  722. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  723. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  724. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  725. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  726. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  727. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  728. } else {
  729. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  730. }
  731. dispif_info->isConnected = 1;
  732. #ifdef MY_TODO
  733. #error
  734. {
  735. LCM_PARAMS lcm_params_temp;
  736. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  737. if (lcm_drv) {
  738. lcm_drv->get_params(&lcm_params_temp);
  739. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  740. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  741. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  742. } else {
  743. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  744. }
  745. }
  746. #endif
  747. #endif
  748. return 0;
  749. }
  750. int primary_display_get_pages(void)
  751. {
  752. return 3;
  753. }
  754. int primary_display_config_output()
  755. {
  756. return 0;
  757. }
  758. int primary_display_diagnose(void)
  759. {
  760. int ret = 0;
  761. dpmgr_check_status(pgc->dpmgr_handle);
  762. return ret;
  763. }
  764. int primary_display_trigger(int blocking)
  765. {
  766. int ret = 0;
  767. DISPFUNC();
  768. int x=0, y=0;
  769. int width = 0, height =0;
  770. x = disp_lcm_x(pgc->plcm);
  771. y = disp_lcm_y(pgc->plcm);
  772. width = disp_lcm_width(pgc->plcm);
  773. height = disp_lcm_height(pgc->plcm);
  774. _primary_path_lock();
  775. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  776. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  777. if (primary_display_is_video_mode()) {
  778. _primary_path_unlock();
  779. return 0;
  780. }
  781. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  782. }
  783. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  784. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  785. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  786. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  787. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  788. }
  789. //_set_cmdq_config_handle_dirty();
  790. //_reset_cmdq_config_handle();
  791. //if(blocking)
  792. {
  793. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  794. }
  795. } else if (pgc->mode == DECOUPLE_MODE) {
  796. DISPCHECK("trigger mode: DECOUPLE\n");
  797. if (pgc->need_trigger_overlay) {
  798. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  799. if (blocking) {
  800. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  801. }
  802. } else {
  803. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  804. // this request of trigger should be called by AAL or ovl2mem done event
  805. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  806. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  807. }
  808. _set_cmdq_config_handle_dirty();
  809. _reset_cmdq_config_handle();
  810. if (blocking) {
  811. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  812. }
  813. }
  814. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  815. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  816. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  817. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  818. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  819. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  820. }
  821. if (blocking) {
  822. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  823. }
  824. } else {
  825. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  826. }
  827. _primary_path_unlock();
  828. //primary_display_diagnose();
  829. return ret;
  830. }
  831. int primary_display_config_input(disp_input_config* input)
  832. {
  833. int ret = 0;
  834. DISPFUNC();
  835. disp_ddp_path_config data_config;
  836. // all dirty should be cleared in dpmgr_path_get_last_config()
  837. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  838. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  839. data_config.dst_dirty = 0;
  840. data_config.ovl_dirty = 0;
  841. data_config.rdma_dirty = 0;
  842. data_config.wdma_dirty = 0;
  843. _primary_path_lock();
  844. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  845. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  846. if (primary_display_is_video_mode()) {
  847. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  848. }
  849. }
  850. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  851. data_config.ovl_dirty = 1;
  852. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  853. // this is used for decouple mode, to indicate whether we need to trigger ovl
  854. pgc->need_trigger_overlay = 1;
  855. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  856. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  857. data_config.rdma_dirty= 1;
  858. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  859. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  860. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  861. data_config.rdma_dirty= 1;
  862. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  863. // TODO: should use wait_event_timeout_or_idle
  864. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  865. }
  866. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  867. } else {
  868. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  869. }
  870. _primary_path_unlock();
  871. return ret;
  872. }
  873. int primary_display_is_video_mode(void)
  874. {
  875. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  876. return disp_lcm_is_video_mode(pgc->plcm);
  877. }
  878. int primary_display_get_vsync_interval(void)
  879. {
  880. int ret = 0;
  881. unsigned int time0 = 0;
  882. unsigned int time1 = 0;
  883. unsigned int lcd_time = 0;
  884. pgc->plcm->is_connected = false;
  885. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  886. if (ret <= 0)
  887. goto fail;
  888. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  889. if (ret <= 0)
  890. goto fail;
  891. // because we are polling irq status, so the first event should be ignored
  892. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  893. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  894. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  895. if (ret <= 0)
  896. goto fail;
  897. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  898. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  899. if (ret > 0) {
  900. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  901. } else
  902. goto fail;
  903. lcd_time = (time1 - time0)/2;
  904. pgc->plcm->is_connected = true;
  905. if (0 != lcd_time)
  906. return (100000000/lcd_time);
  907. else
  908. return (6000);
  909. fail:
  910. DISPERR("wait event fail\n");
  911. return 0;
  912. }
  913. int primary_display_setbacklight(unsigned int level)
  914. {
  915. DISPMSG("lk %s level=%d\n",__func__,level);
  916. int ret=0;
  917. if (pgc->dpmgr_handle == NULL) {
  918. DISPCHECK("lk set backlight early!\n");
  919. return 0;
  920. }
  921. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  922. DISPCHECK("primary display path is busy\n");
  923. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  924. DISPCHECK("wait frame done ret:%d\n", ret);
  925. }
  926. disp_lcm_set_backlight(pgc->plcm,level);
  927. return 0;
  928. }
  929. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  930. /***********************/
  931. /*****Legacy DISP API*****/
  932. /***********************/
  933. UINT32 DISP_GetScreenWidth(void)
  934. {
  935. return primary_display_get_width();
  936. }
  937. UINT32 DISP_GetScreenHeight(void)
  938. {
  939. return primary_display_get_height();
  940. }
  941. UINT32 DISP_GetActiveHeight(void)
  942. {
  943. if (pgc->plcm == NULL) {
  944. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  945. DISPERR("lcm handle is null, after probe:0x%08x\n",(unsigned int)pgc->plcm);
  946. if (pgc->plcm == NULL)return 0;
  947. }
  948. if (pgc->plcm->params) {
  949. return pgc->plcm->params->physical_height;
  950. } else {
  951. DISPERR("lcm_params is null!\n");
  952. return 0;
  953. }
  954. }
  955. UINT32 DISP_GetActiveWidth(void)
  956. {
  957. if (pgc->plcm == NULL) {
  958. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  959. DISPERR("lcm handle is null, after probe:0x%08x\n",(unsigned int)pgc->plcm);
  960. if (pgc->plcm == NULL)return 0;
  961. }
  962. if (pgc->plcm->params) {
  963. return pgc->plcm->params->physical_width;
  964. } else {
  965. DISPERR("lcm_params is null!\n");
  966. return 0;
  967. }
  968. }
  969. int primary_display_capture_framebuffer(unsigned int *pbuf)
  970. {
  971. return 0;
  972. }
  973. UINT32 DISP_GetPanelBPP(void)
  974. {
  975. #if 0
  976. PANEL_COLOR_FORMAT fmt;
  977. disp_drv_init_context();
  978. if (disp_if_drv->get_panel_color_format == NULL) {
  979. return DISP_STATUS_NOT_IMPLEMENTED;
  980. }
  981. fmt = disp_if_drv->get_panel_color_format();
  982. switch (fmt) {
  983. case PANEL_COLOR_FORMAT_RGB332:
  984. return 8;
  985. case PANEL_COLOR_FORMAT_RGB444:
  986. return 12;
  987. case PANEL_COLOR_FORMAT_RGB565:
  988. return 16;
  989. case PANEL_COLOR_FORMAT_RGB666:
  990. return 18;
  991. case PANEL_COLOR_FORMAT_RGB888:
  992. return 24;
  993. default:
  994. return 0;
  995. }
  996. #endif
  997. return 0;
  998. }
  999. UINT32 DISP_GetScreenBpp(void)
  1000. {
  1001. return disp_fb_bpp;
  1002. }
  1003. UINT32 DISP_GetPages(void)
  1004. {
  1005. return disp_fb_pages; // Double Buffers
  1006. }
  1007. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1008. #define DAL_BPP (2)
  1009. #define DAL_WIDTH (DISP_GetScreenWidth())
  1010. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1011. UINT32 DAL_GetLayerSize(void)
  1012. {
  1013. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1014. }
  1015. UINT32 DISP_GetFBRamSize(void)
  1016. {
  1017. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1018. }
  1019. unsigned int DISP_GetVRamSize(void)
  1020. {
  1021. static UINT32 vramSize = 0;
  1022. unsigned int fb_ram_size =0;
  1023. //FB RAM(n blocks)+(Assert layer size)
  1024. if (0 == vramSize) {
  1025. vramSize = DISP_GetFBRamSize();
  1026. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1027. fb_ram_size = vramSize;
  1028. vramSize += DAL_GetLayerSize();
  1029. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1030. #ifdef MTK_ROUND_CORNER_SUPPORT
  1031. fb_ram_size = vramSize;
  1032. vramSize += disp_get_round_corner_size();
  1033. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1034. #endif
  1035. #if 0
  1036. if (g_is_64bit_kernel) {
  1037. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1038. } else {
  1039. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1040. }
  1041. #else
  1042. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1043. #endif
  1044. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1045. }
  1046. return vramSize;
  1047. }