bq25890.c 37 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <platform/mt_typedefs.h>
  32. #include <platform/mt_reg_base.h>
  33. #include <platform/mt_i2c.h>
  34. #include <platform/mt_pmic.h>
  35. #include <platform/bq25890.h>
  36. #include <printf.h>
  37. #include <platform/mt_pumpexpress.h>
  38. #if !defined(CONFIG_POWER_EXT)
  39. #include <platform/upmu_common.h>
  40. #endif
  41. int g_log_en=0;
  42. /**********************************************************
  43. *
  44. * [I2C Slave Setting]
  45. *
  46. *********************************************************/
  47. #define BQ25890_SLAVE_ADDR_WRITE 0xD6
  48. #define BQ25890_SLAVE_ADDR_READ 0xD7
  49. #define PRECC_BATVOL 2800 //preCC 2.8V
  50. /**********************************************************
  51. *
  52. * [Global Variable]
  53. *
  54. *********************************************************/
  55. kal_uint8 bq25890_reg[bq25890_REG_NUM] = {0};
  56. int g_bq25890_hw_exist=0;
  57. /**********************************************************
  58. *
  59. * [I2C Function For Read/Write bq25890]
  60. *
  61. *********************************************************/
  62. #define BQ25890_I2C_ID I2C1
  63. static struct mt_i2c_t bq25890_i2c;
  64. kal_uint32 bq25890_write_byte(kal_uint8 cmd, kal_uint8 writeData)
  65. {
  66. kal_uint32 ret_code = I2C_OK;
  67. kal_uint8 write_data[2];
  68. kal_uint16 len;
  69. write_data[0]= cmd;
  70. write_data[1] = writeData;
  71. bq25890_i2c.id = BQ25890_I2C_ID;
  72. /* Since i2c will left shift 1 bit, we need to set I2C address to >>1 */
  73. bq25890_i2c.addr = (BQ25890_SLAVE_ADDR_WRITE >> 1);
  74. bq25890_i2c.mode = ST_MODE;
  75. bq25890_i2c.speed = 100;
  76. len = 2;
  77. ret_code = i2c_write(&bq25890_i2c, write_data, len);
  78. if (I2C_OK != ret_code)
  79. dprintf(INFO, "%s: i2c_write: ret_code: %d\n", __func__, ret_code);
  80. return ret_code;
  81. }
  82. kal_uint32 bq25890_read_byte(kal_uint8 cmd, kal_uint8 *returnData)
  83. {
  84. kal_uint32 ret_code = I2C_OK;
  85. kal_uint16 len;
  86. *returnData = cmd;
  87. bq25890_i2c.id = BQ25890_I2C_ID;
  88. /* Since i2c will left shift 1 bit, we need to set I2C address to >>1 */
  89. bq25890_i2c.addr = (BQ25890_SLAVE_ADDR_READ >> 1);
  90. bq25890_i2c.mode = ST_MODE;
  91. bq25890_i2c.speed = 100;
  92. len = 1;
  93. ret_code = i2c_write_read(&bq25890_i2c, returnData, len, len);
  94. if (I2C_OK != ret_code)
  95. dprintf(INFO, "%s: i2c_read: ret_code: %d\n", __func__, ret_code);
  96. return ret_code;
  97. }
  98. /**********************************************************
  99. *
  100. * [Read / Write Function]
  101. *
  102. *********************************************************/
  103. kal_uint32 bq25890_read_interface (kal_uint8 RegNum, kal_uint8 *val, kal_uint8 MASK, kal_uint8 SHIFT)
  104. {
  105. kal_uint8 bq25890_reg = 0;
  106. kal_uint32 ret = 0;
  107. dprintf(INFO, "--------------------------------------------------LK\n");
  108. ret = bq25890_read_byte(RegNum, &bq25890_reg);
  109. dprintf(INFO, "[bq25890_read_interface] Reg[%x]=0x%x\n", RegNum, bq25890_reg);
  110. bq25890_reg &= (MASK << SHIFT);
  111. *val = (bq25890_reg >> SHIFT);
  112. dprintf(INFO, "[bq25890_read_interface] val=0x%x\n", *val);
  113. return ret;
  114. }
  115. kal_uint32 bq25890_config_interface (kal_uint8 RegNum, kal_uint8 val, kal_uint8 MASK, kal_uint8 SHIFT)
  116. {
  117. kal_uint8 bq25890_reg = 0;
  118. kal_uint32 ret = 0;
  119. dprintf(INFO, "--------------------------------------------------\n");
  120. ret = bq25890_read_byte(RegNum, &bq25890_reg);
  121. dprintf(INFO, "[bq25890_config_interface] Reg[%x]=0x%x\n", RegNum, bq25890_reg);
  122. bq25890_reg &= ~(MASK << SHIFT);
  123. bq25890_reg |= (val << SHIFT);
  124. if (RegNum == bq25890_CON1 && val == 1 && MASK ==CON1_RESET_MASK && SHIFT == CON1_RESET_SHIFT) {
  125. // RESET bit
  126. } else if (RegNum == bq25890_CON1) {
  127. bq25890_reg &= ~0x80; //RESET bit read returs 1, so clear it
  128. }
  129. ret = bq25890_write_byte(RegNum, bq25890_reg);
  130. dprintf(INFO, "[bq25890_config_interface] write Reg[%x]=0x%x\n", RegNum, bq25890_reg);
  131. // Check
  132. //bq25890_read_byte(RegNum, &bq25890_reg);
  133. //printk("[bq25890_config_interface] Check Reg[%x]=0x%x\n", RegNum, bq25890_reg);
  134. return ret;
  135. }
  136. //write one register directly
  137. kal_uint32 bq25890_reg_config_interface (kal_uint8 RegNum, kal_uint8 val)
  138. {
  139. kal_uint32 ret = 0;
  140. ret = bq25890_write_byte(RegNum, val);
  141. return ret;
  142. }
  143. /**********************************************************
  144. *
  145. * [Internal Function]
  146. *
  147. *********************************************************/
  148. //CON0----------------------------------------------------
  149. void bq25890_set_en_hiz(kal_uint32 val)
  150. {
  151. kal_uint32 ret=0;
  152. ret=bq25890_config_interface((kal_uint8)(bq25890_CON0),
  153. (kal_uint8)(val),
  154. (kal_uint8)(CON0_EN_HIZ_MASK),
  155. (kal_uint8)(CON0_EN_HIZ_SHIFT)
  156. );
  157. }
  158. void bq25890_set_en_ilim(kal_uint32 val)
  159. {
  160. kal_uint32 ret=0;
  161. ret=bq25890_config_interface((kal_uint8)(bq25890_CON0),
  162. (kal_uint8)(val),
  163. (kal_uint8)(CON0_EN_ILIM_MASK),
  164. (kal_uint8)(CON0_EN_ILIM_SHIFT)
  165. );
  166. }
  167. void bq25890_set_iinlim(kal_uint32 val)
  168. {
  169. kal_uint32 ret=0;
  170. ret=bq25890_config_interface((kal_uint8)(bq25890_CON0),
  171. (val),
  172. (kal_uint8)(CON0_IINLIM_MASK),
  173. (kal_uint8)(CON0_IINLIM_SHIFT)
  174. );
  175. }
  176. //CON1----------------------------------------------------
  177. void bq25890_ADC_start(kal_uint32 val)
  178. {
  179. kal_uint32 ret=0;
  180. ret=bq25890_config_interface((kal_uint8)(bq25890_CON2),
  181. (kal_uint8)(val),
  182. (kal_uint8)(CON2_CONV_START_MASK),
  183. (kal_uint8)(CON2_CONV_START_SHIFT)
  184. );
  185. }
  186. void bq25890_set_ADC_rate(kal_uint32 val)
  187. {
  188. kal_uint32 ret=0;
  189. ret=bq25890_config_interface((kal_uint8)(bq25890_CON2),
  190. (kal_uint8)(val),
  191. (kal_uint8)(CON2_CONV_RATE_MASK),
  192. (kal_uint8)(CON2_CONV_RATE_SHIFT)
  193. );
  194. }
  195. void bq25890_set_vindpm_os(kal_uint32 val)
  196. {
  197. kal_uint32 ret=0;
  198. ret=bq25890_config_interface((kal_uint8)(bq25890_CON1),
  199. (kal_uint8)(val),
  200. (kal_uint8)(CON1_VINDPM_OS_MASK),
  201. (kal_uint8)(CON1_VINDPM_OS_SHIFT)
  202. );
  203. }
  204. //CON2----------------------------------------------------
  205. void bq25890_set_ico_en_start(kal_uint32 val)
  206. {
  207. kal_uint32 ret=0;
  208. ret=bq25890_config_interface((kal_uint8)(bq25890_CON2),
  209. (kal_uint8)(val),
  210. (kal_uint8)(CON2_ICO_EN_MASK),
  211. (kal_uint8)(CON2_ICO_EN_RATE_SHIFT)
  212. );
  213. }
  214. //CON3----------------------------------------------------
  215. void bq25890_wd_reset(kal_uint32 val)
  216. {
  217. kal_uint32 ret=0;
  218. ret=bq25890_config_interface((kal_uint8)(bq25890_CON3),
  219. (val),
  220. (kal_uint8)(CON3_WD_MASK),
  221. (kal_uint8)(CON3_WD_SHIFT)
  222. );
  223. }
  224. void bq25890_otg_en(kal_uint32 val)
  225. {
  226. kal_uint32 ret=0;
  227. ret=bq25890_config_interface((kal_uint8)(bq25890_CON3),
  228. (val),
  229. (kal_uint8)(CON3_OTG_CONFIG_MASK),
  230. (kal_uint8)(CON3_OTG_CONFIG_SHIFT)
  231. );
  232. }
  233. void bq25890_chg_en(kal_uint32 val)
  234. {
  235. kal_uint32 ret=0;
  236. ret=bq25890_config_interface((kal_uint8)(bq25890_CON3),
  237. (val),
  238. (kal_uint8)(CON3_CHG_CONFIG_MASK),
  239. (kal_uint8)(CON3_CHG_CONFIG_SHIFT)
  240. );
  241. }
  242. void bq25890_set_sys_min(kal_uint32 val)
  243. {
  244. kal_uint32 ret=0;
  245. ret=bq25890_config_interface((kal_uint8)(bq25890_CON3),
  246. (val),
  247. (kal_uint8)(CON3_SYS_V_LIMIT_MASK),
  248. (kal_uint8)(CON3_SYS_V_LIMIT_SHIFT)
  249. );
  250. }
  251. //CON4----------------------------------------------------
  252. void bq25890_en_pumpx(kal_uint32 val)
  253. {
  254. kal_uint32 ret=0;
  255. ret=bq25890_config_interface((kal_uint8)(bq25890_CON4),
  256. (kal_uint8)(val),
  257. (kal_uint8)(CON4_EN_PUMPX_MASK),
  258. (kal_uint8)(CON4_EN_PUMPX_SHIFT)
  259. );
  260. }
  261. void bq25890_set_ichg(kal_uint32 val)
  262. {
  263. kal_uint32 ret=0;
  264. ret=bq25890_config_interface((kal_uint8)(bq25890_CON4),
  265. (kal_uint8)(val),
  266. (kal_uint8)(CON4_ICHG_MASK),
  267. (kal_uint8)(CON4_ICHG_SHIFT)
  268. );
  269. }
  270. //CON5----------------------------------------------------
  271. void bq25890_set_iprechg(kal_uint32 val)
  272. {
  273. kal_uint32 ret=0;
  274. ret=bq25890_config_interface((kal_uint8)(bq25890_CON5),
  275. (val),
  276. (kal_uint8)(CON5_IPRECHG_MASK),
  277. (kal_uint8)(CON5_IPRECHG_SHIFT)
  278. );
  279. }
  280. void bq25890_set_iterml(kal_uint32 val)
  281. {
  282. kal_uint32 ret=0;
  283. ret=bq25890_config_interface((kal_uint8)(bq25890_CON5),
  284. (val),
  285. (kal_uint8)(CON5_ITERM_MASK),
  286. (kal_uint8)(CON5_ITERM_SHIFT)
  287. );
  288. }
  289. //CON6----------------------------------------------------
  290. void bq25890_set_vreg(kal_uint32 val)
  291. {
  292. kal_uint32 ret=0;
  293. ret=bq25890_config_interface((kal_uint8)(bq25890_CON6),
  294. (kal_uint8)(val),
  295. (kal_uint8)(CON6_2XTMR_EN_MASK),
  296. (kal_uint8)(CON6_2XTMR_EN_SHIFT)
  297. );
  298. }
  299. void bq25890_set_batlowv(kal_uint32 val)
  300. {
  301. kal_uint32 ret=0;
  302. ret=bq25890_config_interface((kal_uint8)(bq25890_CON6),
  303. (kal_uint8)(val),
  304. (kal_uint8)(CON6_BATLOWV_MASK),
  305. (kal_uint8)(CON6_BATLOWV_SHIFT)
  306. );
  307. }
  308. void bq25890_set_vrechg(kal_uint32 val)
  309. {
  310. kal_uint32 ret=0;
  311. ret=bq25890_config_interface((kal_uint8)(bq25890_CON6),
  312. (kal_uint8)(val),
  313. (kal_uint8)(CON6_VRECHG_MASK),
  314. (kal_uint8)(CON6_VRECHG_SHIFT)
  315. );
  316. }
  317. //CON7----------------------------------------------------
  318. void bq25890_en_term_chg(kal_uint32 val)
  319. {
  320. kal_uint32 ret=0;
  321. ret=bq25890_config_interface((kal_uint8)(bq25890_CON7),
  322. (kal_uint8)(val),
  323. (kal_uint8)(CON7_EN_TERM_CHG_MASK),
  324. (kal_uint8)(CON7_EN_TERM_CHG_SHIFT)
  325. );
  326. }
  327. void bq25890_en_state_dis(kal_uint32 val)
  328. {
  329. kal_uint32 ret=0;
  330. ret=bq25890_config_interface((kal_uint8)(bq25890_CON7),
  331. (kal_uint8)(val),
  332. (kal_uint8)(CON7_STAT_DIS_MASK),
  333. (kal_uint8)(CON7_STAT_DIS_SHIFT)
  334. );
  335. }
  336. void bq25890_set_wd_timer(kal_uint32 val)
  337. {
  338. kal_uint32 ret=0;
  339. ret=bq25890_config_interface((kal_uint8)(bq25890_CON7),
  340. (kal_uint8)(val),
  341. (kal_uint8)(CON7_WTG_TIM_SET_MASK),
  342. (kal_uint8)(CON7_WTG_TIM_SET_SHIFT)
  343. );
  344. }
  345. void bq25890_en_chg_timer(kal_uint32 val)
  346. {
  347. kal_uint32 ret=0;
  348. ret=bq25890_config_interface((kal_uint8)(bq25890_CON7),
  349. (kal_uint8)(val),
  350. (kal_uint8)(CON7_EN_TIM_MASK),
  351. (kal_uint8)(CON7_EN_TIMG_SHIFT)
  352. );
  353. }
  354. void bq25890_set_chg_timer(kal_uint32 val)
  355. {
  356. kal_uint32 ret=0;
  357. ret=bq25890_config_interface((kal_uint8)(bq25890_CON7),
  358. (kal_uint8)(val),
  359. (kal_uint8)(CON7_SET_CHG_TIM_MASK),
  360. (kal_uint8)(CON7_SET_CHG_TIM_SHIFT)
  361. );
  362. }
  363. //CON8---------------------------------------------------
  364. void bq25890_set_thermal_regulation(kal_uint32 val)
  365. {
  366. kal_uint32 ret=0;
  367. ret=bq25890_config_interface((kal_uint8)(bq25890_CON8),
  368. (kal_uint8)(val),
  369. (kal_uint8)(CON8_TREG_MASK),
  370. (kal_uint8)(CON8_TREG_SHIFT)
  371. );
  372. }
  373. void bq25890_set_VBAT_clamp(kal_uint32 val)
  374. {
  375. kal_uint32 ret=0;
  376. ret=bq25890_config_interface((kal_uint8)(bq25890_CON8),
  377. (kal_uint8)(val),
  378. (kal_uint8)(CON8_VCLAMP_MASK),
  379. (kal_uint8)(CON8_VCLAMP_SHIFT)
  380. );
  381. }
  382. void bq25890_set_VBAT_IR_compensation(kal_uint32 val)
  383. {
  384. kal_uint32 ret=0;
  385. ret=bq25890_config_interface((kal_uint8)(bq25890_CON8),
  386. (kal_uint8)(val),
  387. (kal_uint8)(CON8_BAT_COMP_MASK),
  388. (kal_uint8)(CON8_BAT_COMP_SHIFT)
  389. );
  390. }
  391. //CON9----------------------------------------------------
  392. #if PUMPEXP_IN_LK
  393. void bq25890_pumpx_up(kal_uint32 val)
  394. {
  395. kal_uint32 ret=0;
  396. bq25890_en_pumpx(1);
  397. if (val==1) {
  398. ret=bq25890_config_interface((kal_uint8)(bq25890_CON9),
  399. (kal_uint8)(1),
  400. (kal_uint8)(CON9_PUMPX_UP),
  401. (kal_uint8)(CON9_PUMPX_UP_SHIFT)
  402. );
  403. } else {
  404. ret=bq25890_config_interface((kal_uint8)(bq25890_CON9),
  405. (kal_uint8)(1),
  406. (kal_uint8)(CON9_PUMPX_DN),
  407. (kal_uint8)(CON9_PUMPX_DN_SHIFT)
  408. );
  409. }
  410. /* Input current limit = 400 mA, changes after port detection*/
  411. bq25890_set_iinlim(8);
  412. /* CC mode current = 2048 mA*/
  413. bq25890_set_ichg(0x20);
  414. msleep(3000);
  415. }
  416. #endif
  417. //CONA----------------------------------------------------
  418. void bq25890_set_boost_ilim(kal_uint32 val)
  419. {
  420. kal_uint32 ret=0;
  421. ret=bq25890_config_interface((kal_uint8)(bq25890_CONA),
  422. (kal_uint8)(val),
  423. (kal_uint8)(CONA_BOOST_ILIM_MASK),
  424. (kal_uint8)(CONA_BOOST_ILIM_SHIFT)
  425. );
  426. }
  427. void bq25890_set_boost_vlim(kal_uint32 val)
  428. {
  429. kal_uint32 ret=0;
  430. ret=bq25890_config_interface((kal_uint8)(bq25890_CONA),
  431. (kal_uint8)(val),
  432. (kal_uint8)(CONA_BOOST_VLIM_MASK),
  433. (kal_uint8)(CONA_BOOST_VLIM_SHIFT)
  434. );
  435. }
  436. //CONB----------------------------------------------------
  437. kal_uint32 bq25890_get_vbus_state(void )
  438. {
  439. kal_uint32 ret=0;
  440. kal_uint8 val=0;
  441. ret=bq25890_read_interface((kal_uint8)(bq25890_CONB),
  442. (&val),
  443. (kal_uint8)(CONB_VBUS_STAT_MASK),
  444. (kal_uint8)(CONB_VBUS_STAT_SHIFT)
  445. );
  446. return val;
  447. }
  448. kal_uint32 bq25890_get_chrg_state(void )
  449. {
  450. kal_uint32 ret=0;
  451. kal_uint8 val=0;
  452. ret=bq25890_read_interface((kal_uint8)(bq25890_CONB),
  453. (&val),
  454. (kal_uint8)(CONB_CHRG_STAT_MASK),
  455. (kal_uint8)(CONB_CHRG_STAT_SHIFT)
  456. );
  457. return val;
  458. }
  459. kal_uint32 bq25890_get_pg_state(void )
  460. {
  461. kal_uint32 ret=0;
  462. kal_uint8 val=0;
  463. ret=bq25890_read_interface((kal_uint8)(bq25890_CONB),
  464. (&val),
  465. (kal_uint8)(CONB_PG_STAT_MASK),
  466. (kal_uint8)(CONB_PG_STAT_SHIFT)
  467. );
  468. return val;
  469. }
  470. kal_uint32 bq25890_get_sdp_state(void )
  471. {
  472. kal_uint32 ret=0;
  473. kal_uint8 val=0;
  474. ret=bq25890_read_interface((kal_uint8)(bq25890_CONB),
  475. (&val),
  476. (kal_uint8)(CONB_SDP_STAT_MASK),
  477. (kal_uint8)(CONB_SDP_STAT_SHIFT)
  478. );
  479. return val;
  480. }
  481. kal_uint32 bq25890_get_vsys_state(void )
  482. {
  483. kal_uint32 ret=0;
  484. kal_uint8 val=0;
  485. ret=bq25890_read_interface((kal_uint8)(bq25890_CONB),
  486. (&val),
  487. (kal_uint8)(CONB_VSYS_STAT_MASK),
  488. (kal_uint8)(CONB_VSYS_STAT_SHIFT)
  489. );
  490. return val;
  491. }
  492. //CON0C----------------------------------------------------
  493. kal_uint32 bq25890_get_wdt_state(void )
  494. {
  495. kal_uint32 ret=0;
  496. kal_uint8 val=0;
  497. ret=bq25890_read_interface((kal_uint8)(bq25890_CONC),
  498. (&val),
  499. (kal_uint8)(CONB_WATG_STAT_MASK),
  500. (kal_uint8)(CONB_WATG_STAT_SHIFT)
  501. );
  502. return val;
  503. }
  504. kal_uint32 bq25890_get_boost_state(void )
  505. {
  506. kal_uint32 ret=0;
  507. kal_uint8 val=0;
  508. ret=bq25890_read_interface((kal_uint8)(bq25890_CONC),
  509. (&val),
  510. (kal_uint8)(CONB_BOOST_STAT_MASK),
  511. (kal_uint8)(CONB_BOOST_STAT_SHIFT)
  512. );
  513. return val;
  514. }
  515. kal_uint32 bq25890_get_chrg_fault_state(void)
  516. {
  517. kal_uint32 ret=0;
  518. kal_uint8 val=0;
  519. ret=bq25890_read_interface((kal_uint8)(bq25890_CONC),
  520. (&val),
  521. (kal_uint8)(CONB_CHRG_STAT_MASK),
  522. (kal_uint8)(CONB_CHRG_STAT_SHIFT)
  523. );
  524. return val;
  525. }
  526. kal_uint32 bq25890_get_bat_state(void)
  527. {
  528. kal_uint32 ret=0;
  529. kal_uint8 val=0;
  530. ret=bq25890_read_interface((kal_uint8)(bq25890_CONC),
  531. (&val),
  532. (kal_uint8)(CONB_BAT_STAT_MASK),
  533. (kal_uint8)(CONB_BAT_STAT_SHIFT)
  534. );
  535. return val;
  536. }
  537. //COND
  538. void bq25890_set_FORCE_VINDPM(kal_uint32 val)
  539. {
  540. kal_uint32 ret=0;
  541. ret=bq25890_config_interface((kal_uint8)(bq25890_COND),
  542. (kal_uint8)(val),
  543. (kal_uint8)(COND_FORCE_VINDPM_MASK),
  544. (kal_uint8)(COND_FORCE_VINDPM_SHIFT)
  545. );
  546. return val;
  547. }
  548. void bq25890_set_VINDPM(kal_uint32 val)
  549. {
  550. kal_uint32 ret=0;
  551. ret=bq25890_config_interface((kal_uint8)(bq25890_COND),
  552. (kal_uint8)(val),
  553. (kal_uint8)(COND_VINDPM_MASK),
  554. (kal_uint8)(COND_VINDPM_SHIFT)
  555. );
  556. return val;
  557. }
  558. //CON12
  559. kal_uint32 bq25890_get_ichg(void )
  560. {
  561. kal_uint32 ret=0;
  562. kal_uint8 val=0;
  563. ret=bq25890_read_interface((kal_uint8)(bq25890_CON12),
  564. (&val),
  565. (kal_uint8)(CONB_ICHG_STAT_MASK),
  566. (kal_uint8)(CONB_ICHG_STAT_SHIFT)
  567. );
  568. return val;
  569. }
  570. //CON13 ///
  571. kal_uint32 bq25890_get_idpm_state(void )
  572. {
  573. kal_uint32 ret=0;
  574. kal_uint8 val=0;
  575. ret=bq25890_read_interface((kal_uint8)(bq25890_CON13),
  576. (&val),
  577. (kal_uint8)(CONB_IDPM_STAT_MASK),
  578. (kal_uint8)(CONB_IDPM_STAT_SHIFT)
  579. );
  580. return val;
  581. }
  582. kal_uint32 bq25890_get_idpm_lim(void)
  583. {
  584. kal_uint32 ret=0;
  585. kal_uint8 val=0;
  586. ret=bq25890_read_interface((kal_uint8)(bq25890_CON13),
  587. (&val),
  588. (kal_uint8)(CON13_IDPM_LIM_MASK),
  589. (kal_uint8)(CON13_IDPM_LIM_SHIFT)
  590. );
  591. return val;
  592. }
  593. /**********************************************************
  594. *
  595. * [Internal Function]
  596. *
  597. *********************************************************/
  598. void bq25890_dump_register(void)
  599. {
  600. kal_uint8 i=0;
  601. dprintf(CRITICAL, "[bq25890] ");
  602. bq25890_ADC_start(0x1);
  603. for (i=0; i<bq25890_REG_NUM; i++) {
  604. bq25890_read_byte(i, &bq25890_reg[i]);
  605. dprintf(CRITICAL, "[0x%x]=0x%x\n", i, bq25890_reg[i]);
  606. }
  607. dprintf(INFO, "\n");
  608. }
  609. void bq25890_hw_init(void)
  610. {
  611. bq25890_wd_reset(1); // wdt reset
  612. bq25890_otg_en(0); // Disable OTG boost
  613. bq25890_en_chg_timer(1); // Disable Safty timer
  614. bq25890_set_iterml(0x2); // ITERM = TBD 0x02=128mAi
  615. /*Set VBAT = 4.352 V*/
  616. bq25890_set_vreg(0x20);
  617. /*VBAT IR compensation*/
  618. bq25890_set_VBAT_clamp(0x7);/*4.352V + 0.224 V*/
  619. bq25890_set_VBAT_IR_compensation(0x4); /*80mohm*/
  620. /*precharge2cc voltage,BATLOWV, 3.0V*/
  621. bq25890_set_batlowv(0x1);
  622. /*PreCC mode*/
  623. /* precharge current default 0x1:128mA 0xF:1088mA
  624. * Note: 1A is forbidden for dead battery
  625. */
  626. bq25890_set_iprechg(0x1);
  627. /* ICHG 2048mA*/
  628. bq25890_set_ichg(0x20);
  629. /*Iinlim = 3.25mA*/
  630. bq25890_set_iinlim(0x3F);
  631. //bq25890_set_vindpm_off(0); // VINDPM_OFFSET = 0 : 4.2V ; 1 for 10.1 V
  632. //bq25890_set_vindpm_os(0x4); // VINDPM_OFFSET + CODE x 2%
  633. bq25890_set_FORCE_VINDPM(1); //1 or 0 for absolute or relative vth
  634. bq25890_set_VINDPM(0x13); //4.5V
  635. /*Thermal regulation : TBD*/
  636. //bq25890_set_ts_en(0);
  637. bq25890_set_en_hiz(0x0);
  638. //if(get_mt6351_pmic_chip_version() < PMIC6351_E3_CID_CODE)
  639. //bq25890_set_vbreg(0x19); //TBD battery regulation
  640. //else
  641. //bq25890_set_vbreg(0x23); //TBD battery regulation
  642. }
  643. static CHARGER_TYPE g_chr_type_num = CHARGER_UNKNOWN;
  644. int hw_charging_get_charger_type(void);
  645. extern int g_std_ac_large_current_en;
  646. void bq25890_charging_enable(kal_uint32 bEnable)
  647. {
  648. if (KAL_TRUE == bEnable)
  649. bq25890_chg_en(0x1); // charger enable
  650. else
  651. bq25890_chg_en(0); // charger disable
  652. dprintf(CRITICAL, "[BATTERY:bq24196] charger enable/disable %d !\r\n", bEnable);
  653. }
  654. #if defined(CONFIG_POWER_EXT)
  655. int hw_charging_get_charger_type(void)
  656. {
  657. g_chr_type_num = STANDARD_HOST;
  658. return STANDARD_HOST;
  659. }
  660. #else
  661. extern void Charger_Detect_Init(void);
  662. extern void Charger_Detect_Release(void);
  663. extern void mdelay (unsigned long msec);
  664. extern void pmic_set_register_value(PMU_FLAGS_LIST_ENUM flagname,kal_uint32 val);
  665. extern kal_uint16 pmic_get_register_value(PMU_FLAGS_LIST_ENUM flagname);
  666. static void hw_bc11_dump_register(void)
  667. {
  668. #if defined(PMIC_CHIP_MT6353)
  669. dprintf(INFO, "Reg[0x%x]=0x%x,Reg[0x%x]=0x%x\n",
  670. MT6353_CHR_CON20, upmu_get_reg_value(MT6353_CHR_CON20),
  671. MT6353_CHR_CON21, upmu_get_reg_value(MT6353_CHR_CON21)
  672. );
  673. #else
  674. dprintf(INFO, "Reg[0x%x]=0x%x,Reg[0x%x]=0x%x\n",
  675. MT6351_CHR_CON20, upmu_get_reg_value(MT6351_CHR_CON20),
  676. MT6351_CHR_CON21, upmu_get_reg_value(MT6351_CHR_CON21)
  677. );
  678. #endif
  679. }
  680. static void hw_bc11_init(void)
  681. {
  682. mdelay(300);
  683. #if CHARGER_DETECTION
  684. Charger_Detect_Init();
  685. #endif
  686. #if defined(PMIC_CHIP_MT6353)
  687. //RG_bc11_BIAS_EN=1
  688. pmic_set_register_value(PMIC_RG_BC11_BIAS_EN, 0x1);//mt6351_upmu_set_rg_bc11_bias_en(0x1);
  689. //RG_bc11_VSRC_EN[1:0]=00
  690. pmic_set_register_value(PMIC_RG_BC11_VSRC_EN, 0x0);//mt6351_upmu_set_rg_bc11_vsrc_en(0x0);
  691. //RG_bc11_VREF_VTH = [1:0]=00
  692. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  693. //RG_bc11_CMP_EN[1.0] = 00
  694. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  695. //RG_bc11_IPU_EN[1.0] = 00
  696. pmic_set_register_value(PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  697. //RG_bc11_IPD_EN[1.0] = 00
  698. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  699. //bc11_RST=1
  700. pmic_set_register_value(PMIC_RG_BC11_RST, 0x1);//mt6351_upmu_set_rg_bc11_rst(0x1);
  701. //bc11_BB_CTRL=1
  702. pmic_set_register_value(PMIC_RG_BC11_BB_CTRL, 0x1);//mt6351_upmu_set_rg_bc11_bb_ctrl(0x1);
  703. #else
  704. //RG_bc11_BIAS_EN=1
  705. pmic_set_register_value(MT6351_PMIC_RG_BC11_BIAS_EN, 0x1);//mt6351_upmu_set_rg_bc11_bias_en(0x1);
  706. //RG_bc11_VSRC_EN[1:0]=00
  707. pmic_set_register_value(MT6351_PMIC_RG_BC11_VSRC_EN, 0x0);//mt6351_upmu_set_rg_bc11_vsrc_en(0x0);
  708. //RG_bc11_VREF_VTH = [1:0]=00
  709. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  710. //RG_bc11_CMP_EN[1.0] = 00
  711. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  712. //RG_bc11_IPU_EN[1.0] = 00
  713. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  714. //RG_bc11_IPD_EN[1.0] = 00
  715. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  716. //bc11_RST=1
  717. pmic_set_register_value(MT6351_PMIC_RG_BC11_RST, 0x1);//mt6351_upmu_set_rg_bc11_rst(0x1);
  718. //bc11_BB_CTRL=1
  719. pmic_set_register_value(MT6351_PMIC_RG_BC11_BB_CTRL, 0x1);//mt6351_upmu_set_rg_bc11_bb_ctrl(0x1);
  720. #endif
  721. mdelay(50);
  722. if (g_log_en>1) {
  723. dprintf(INFO, "hw_bc11_init() \r\n");
  724. hw_bc11_dump_register();
  725. }
  726. }
  727. static U32 hw_bc11_DCD(void)
  728. {
  729. U32 wChargerAvail = 0;
  730. #if defined(PMIC_CHIP_MT6353)
  731. //RG_bc11_IPU_EN[1.0] = 10
  732. pmic_set_register_value(PMIC_RG_BC11_IPU_EN, 0x2);
  733. //RG_bc11_IPD_EN[1.0] = 01
  734. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x1);//mt6351_upmu_set_rg_bc11_ipd_en(0x1);
  735. //RG_bc11_VREF_VTH = [1:0]=01
  736. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x1);//mt6351_upmu_set_rg_bc11_vref_vth(0x1);
  737. //RG_bc11_CMP_EN[1.0] = 10
  738. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x2);//mt6351_upmu_set_rg_bc11_cmp_en(0x2);
  739. #else
  740. //RG_bc11_IPU_EN[1.0] = 10
  741. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPU_EN, 0x2);
  742. //RG_bc11_IPD_EN[1.0] = 01
  743. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x1);//mt6351_upmu_set_rg_bc11_ipd_en(0x1);
  744. //RG_bc11_VREF_VTH = [1:0]=01
  745. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x1);//mt6351_upmu_set_rg_bc11_vref_vth(0x1);
  746. //RG_bc11_CMP_EN[1.0] = 10
  747. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x2);//mt6351_upmu_set_rg_bc11_cmp_en(0x2);
  748. #endif
  749. mdelay(80);
  750. #if defined(PMIC_CHIP_MT6353)
  751. wChargerAvail = pmic_get_register_value(PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  752. #else
  753. wChargerAvail = pmic_get_register_value(MT6351_PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  754. #endif
  755. if (g_log_en>1) {
  756. dprintf(INFO, "hw_bc11_DCD() \r\n");
  757. hw_bc11_dump_register();
  758. }
  759. #if defined(PMIC_CHIP_MT6353)
  760. //RG_bc11_IPU_EN[1.0] = 00
  761. pmic_set_register_value(PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  762. //RG_bc11_IPD_EN[1.0] = 00
  763. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  764. //RG_bc11_CMP_EN[1.0] = 00
  765. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  766. //RG_bc11_VREF_VTH = [1:0]=00
  767. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  768. #else
  769. //RG_bc11_IPU_EN[1.0] = 00
  770. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  771. //RG_bc11_IPD_EN[1.0] = 00
  772. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  773. //RG_bc11_CMP_EN[1.0] = 00
  774. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  775. //RG_bc11_VREF_VTH = [1:0]=00
  776. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  777. #endif
  778. return wChargerAvail;
  779. }
  780. static U32 hw_bc11_stepA1(void)
  781. {
  782. U32 wChargerAvail = 0;
  783. #if defined(PMIC_CHIP_MT6353)
  784. //RG_bc11_IPD_EN[1.0] = 01
  785. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x1);//mt6351_upmu_set_rg_bc11_ipd_en(0x1);
  786. //RG_bc11_VREF_VTH = [1:0]=00
  787. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  788. //RG_bc11_CMP_EN[1.0] = 01
  789. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x1);//mt6351_upmu_set_rg_bc11_cmp_en(0x1);
  790. #else
  791. //RG_bc11_IPD_EN[1.0] = 01
  792. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x1);//mt6351_upmu_set_rg_bc11_ipd_en(0x1);
  793. //RG_bc11_VREF_VTH = [1:0]=00
  794. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  795. //RG_bc11_CMP_EN[1.0] = 01
  796. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x1);//mt6351_upmu_set_rg_bc11_cmp_en(0x1);
  797. #endif
  798. mdelay(80);
  799. #if defined(PMIC_CHIP_MT6353)
  800. wChargerAvail = pmic_get_register_value(PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  801. #else
  802. wChargerAvail = pmic_get_register_value(MT6351_PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  803. #endif
  804. if (g_log_en>1) {
  805. dprintf(INFO, "hw_bc11_stepA1() \r\n");
  806. hw_bc11_dump_register();
  807. }
  808. #if defined(PMIC_CHIP_MT6353)
  809. //RG_bc11_IPD_EN[1.0] = 00
  810. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  811. //RG_bc11_CMP_EN[1.0] = 00
  812. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  813. #else
  814. //RG_bc11_IPD_EN[1.0] = 00
  815. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  816. //RG_bc11_CMP_EN[1.0] = 00
  817. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  818. #endif
  819. return wChargerAvail;
  820. }
  821. static U32 hw_bc11_stepA2(void)
  822. {
  823. U32 wChargerAvail = 0;
  824. #if defined(PMIC_CHIP_MT6353)
  825. //RG_bc11_VSRC_EN[1.0] = 10
  826. pmic_set_register_value(PMIC_RG_BC11_VSRC_EN, 0x2);//mt6351_upmu_set_rg_bc11_vsrc_en(0x2);
  827. //RG_bc11_IPD_EN[1:0] = 01
  828. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x1);//mt6351_upmu_set_rg_bc11_ipd_en(0x1);
  829. //RG_bc11_VREF_VTH = [1:0]=00
  830. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  831. //RG_bc11_CMP_EN[1.0] = 01
  832. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x1);//mt6351_upmu_set_rg_bc11_cmp_en(0x1);
  833. #else
  834. //RG_bc11_VSRC_EN[1.0] = 10
  835. pmic_set_register_value(MT6351_PMIC_RG_BC11_VSRC_EN, 0x2);//mt6351_upmu_set_rg_bc11_vsrc_en(0x2);
  836. //RG_bc11_IPD_EN[1:0] = 01
  837. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x1);//mt6351_upmu_set_rg_bc11_ipd_en(0x1);
  838. //RG_bc11_VREF_VTH = [1:0]=00
  839. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  840. //RG_bc11_CMP_EN[1.0] = 01
  841. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x1);//mt6351_upmu_set_rg_bc11_cmp_en(0x1);
  842. #endif
  843. mdelay(80);
  844. #if defined(PMIC_CHIP_MT6353)
  845. wChargerAvail = pmic_get_register_value(PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  846. #else
  847. wChargerAvail = pmic_get_register_value(MT6351_PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  848. #endif
  849. if (g_log_en>1) {
  850. dprintf(INFO, "hw_bc11_stepA2() \r\n");
  851. hw_bc11_dump_register();
  852. }
  853. #if defined(PMIC_CHIP_MT6353)
  854. //RG_bc11_VSRC_EN[1:0]=00
  855. pmic_set_register_value(PMIC_RG_BC11_VSRC_EN, 0x2);//mt6351_upmu_set_rg_bc11_vsrc_en(0x0);
  856. //RG_bc11_IPD_EN[1.0] = 00
  857. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  858. //RG_bc11_CMP_EN[1.0] = 00
  859. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  860. #else
  861. //RG_bc11_VSRC_EN[1:0]=00
  862. pmic_set_register_value(MT6351_PMIC_RG_BC11_VSRC_EN, 0x2);//mt6351_upmu_set_rg_bc11_vsrc_en(0x0);
  863. //RG_bc11_IPD_EN[1.0] = 00
  864. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  865. //RG_bc11_CMP_EN[1.0] = 00
  866. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  867. #endif
  868. return wChargerAvail;
  869. }
  870. static U32 hw_bc11_stepB2(void)
  871. {
  872. U32 wChargerAvail = 0;
  873. #if defined(PMIC_CHIP_MT6353)
  874. //RG_bc11_IPU_EN[1:0]=10
  875. pmic_set_register_value(PMIC_RG_BC11_IPU_EN, 0x2);//mt6351_upmu_set_rg_bc11_ipu_en(0x2);
  876. //RG_bc11_VREF_VTH = [1:0]=01
  877. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x1);//mt6351_upmu_set_rg_bc11_vref_vth(0x1);
  878. //RG_bc11_CMP_EN[1.0] = 01
  879. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x1);//mt6351_upmu_set_rg_bc11_cmp_en(0x1);
  880. #else
  881. //RG_bc11_IPU_EN[1:0]=10
  882. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPU_EN, 0x2);//mt6351_upmu_set_rg_bc11_ipu_en(0x2);
  883. //RG_bc11_VREF_VTH = [1:0]=01
  884. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x1);//mt6351_upmu_set_rg_bc11_vref_vth(0x1);
  885. //RG_bc11_CMP_EN[1.0] = 01
  886. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x1);//mt6351_upmu_set_rg_bc11_cmp_en(0x1);
  887. #endif
  888. mdelay(80);
  889. #if defined(PMIC_CHIP_MT6353)
  890. wChargerAvail = pmic_get_register_value(PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  891. #else
  892. wChargerAvail = pmic_get_register_value(MT6351_PMIC_RGS_BC11_CMP_OUT);//mt6351_upmu_get_rgs_bc11_cmp_out();
  893. #endif
  894. if (g_log_en>1) {
  895. dprintf(INFO, "hw_bc11_stepB2() \r\n");
  896. hw_bc11_dump_register();
  897. }
  898. #if defined(PMIC_CHIP_MT6353)
  899. //RG_bc11_IPU_EN[1.0] = 00
  900. pmic_set_register_value(PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  901. //RG_bc11_CMP_EN[1.0] = 00
  902. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  903. //RG_bc11_VREF_VTH = [1:0]=00
  904. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x0); //mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  905. #else
  906. //RG_bc11_IPU_EN[1.0] = 00
  907. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  908. //RG_bc11_CMP_EN[1.0] = 00
  909. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  910. //RG_bc11_VREF_VTH = [1:0]=00
  911. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x0); //mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  912. #endif
  913. return wChargerAvail;
  914. }
  915. static void hw_bc11_done(void)
  916. {
  917. #if defined(PMIC_CHIP_MT6353)
  918. //RG_bc11_VSRC_EN[1:0]=00
  919. pmic_set_register_value(PMIC_RG_BC11_VSRC_EN, 0x0);//mt6351_upmu_set_rg_bc11_vsrc_en(0x0);
  920. //RG_bc11_VREF_VTH = [1:0]=0
  921. pmic_set_register_value(PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  922. //RG_bc11_CMP_EN[1.0] = 00
  923. pmic_set_register_value(PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  924. //RG_bc11_IPU_EN[1.0] = 00
  925. pmic_set_register_value(PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  926. //RG_bc11_IPD_EN[1.0] = 00
  927. pmic_set_register_value(PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  928. //RG_bc11_BIAS_EN=0
  929. pmic_set_register_value(PMIC_RG_BC11_BIAS_EN, 0x0);//mt6351_upmu_set_rg_bc11_bias_en(0x0);
  930. #else
  931. //RG_bc11_VSRC_EN[1:0]=00
  932. pmic_set_register_value(MT6351_PMIC_RG_BC11_VSRC_EN, 0x0);//mt6351_upmu_set_rg_bc11_vsrc_en(0x0);
  933. //RG_bc11_VREF_VTH = [1:0]=0
  934. pmic_set_register_value(MT6351_PMIC_RG_BC11_VREF_VTH, 0x0);//mt6351_upmu_set_rg_bc11_vref_vth(0x0);
  935. //RG_bc11_CMP_EN[1.0] = 00
  936. pmic_set_register_value(MT6351_PMIC_RG_BC11_CMP_EN, 0x0);//mt6351_upmu_set_rg_bc11_cmp_en(0x0);
  937. //RG_bc11_IPU_EN[1.0] = 00
  938. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPU_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipu_en(0x0);
  939. //RG_bc11_IPD_EN[1.0] = 00
  940. pmic_set_register_value(MT6351_PMIC_RG_BC11_IPD_EN, 0x0);//mt6351_upmu_set_rg_bc11_ipd_en(0x0);
  941. //RG_bc11_BIAS_EN=0
  942. pmic_set_register_value(MT6351_PMIC_RG_BC11_BIAS_EN, 0x0);//mt6351_upmu_set_rg_bc11_bias_en(0x0);
  943. #endif
  944. #if CHARGER_DETECTION
  945. Charger_Detect_Release();
  946. #endif
  947. if (g_log_en>1) {
  948. dprintf(INFO, "hw_bc11_done() \r\n");
  949. hw_bc11_dump_register();
  950. }
  951. }
  952. int hw_charging_get_charger_type(void)
  953. {
  954. if (CHARGER_UNKNOWN != g_chr_type_num)
  955. return g_chr_type_num;
  956. /********* Step initial ***************/
  957. hw_bc11_init();
  958. /********* Step DCD ***************/
  959. if (1 == hw_bc11_DCD()) {
  960. /********* Step A1 ***************/
  961. if (1 == hw_bc11_stepA1()) {
  962. g_chr_type_num = APPLE_2_1A_CHARGER;
  963. dprintf(INFO, "step A1 : Apple 2.1A CHARGER!\r\n");
  964. } else {
  965. g_chr_type_num = NONSTANDARD_CHARGER;
  966. dprintf(INFO, "step A1 : Non STANDARD CHARGER!\r\n");
  967. }
  968. } else {
  969. /********* Step A2 ***************/
  970. if (1 == hw_bc11_stepA2()) {
  971. /********* Step B2 ***************/
  972. if (1 == hw_bc11_stepB2()) {
  973. g_chr_type_num = STANDARD_CHARGER;
  974. dprintf(INFO, "step B2 : STANDARD CHARGER!\r\n");
  975. } else {
  976. g_chr_type_num = CHARGING_HOST;
  977. dprintf(INFO, "step B2 : Charging Host!\r\n");
  978. }
  979. } else {
  980. g_chr_type_num = STANDARD_HOST;
  981. dprintf(INFO, "step A2 : Standard USB Host!\r\n");
  982. }
  983. }
  984. /********* Finally setting *******************************/
  985. hw_bc11_done();
  986. return g_chr_type_num;
  987. }
  988. void pumpex_reset_adapter(void)
  989. {
  990. bq25890_set_iinlim(0x00);
  991. mdelay(250);
  992. dprintf(CRITICAL, "PE+ adapter reset back to 5v.\r\n");
  993. }
  994. void pumpex_reset_adapter_enble(int en)
  995. {
  996. if (en == 1)
  997. bq25890_set_iinlim(0x00);
  998. else
  999. bq25890_set_iinlim(0x3F);
  1000. }
  1001. #endif