mt_battery.c 32 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <target/board.h>
  32. #ifdef MTK_KERNEL_POWER_OFF_CHARGING
  33. #define CFG_POWER_CHARGING
  34. #endif
  35. #ifdef CFG_POWER_CHARGING
  36. #include <platform/mt_typedefs.h>
  37. #include <platform/mt_reg_base.h>
  38. #include <platform/mt_pmic.h>
  39. #include <platform/upmu_hw.h>
  40. #include <platform/upmu_common.h>
  41. #include <platform/boot_mode.h>
  42. #include <platform/mt_gpt.h>
  43. #include <platform/mt_rtc.h>
  44. #include <platform/mt_rtc_hw.h>
  45. #include <platform/mt_pmic_wrap_init.h>
  46. #include <platform/mt_pumpexpress.h>
  47. //#include <platform/mt_disp_drv.h>
  48. //#include <platform/mtk_wdt.h>
  49. //#include <platform/mtk_key.h>
  50. //#include <platform/mt_logo.h>
  51. #include <platform/mt_leds.h>
  52. #include <printf.h>
  53. #include <sys/types.h>
  54. #include <target/cust_battery.h>
  55. #if defined(MTK_BQ24261_SUPPORT)
  56. #include <platform/bq24261.h>
  57. #endif
  58. #if defined(MTK_BQ24296_SUPPORT)
  59. #include <platform/bq24296.h>
  60. #endif
  61. #if defined(MTK_NCP1854_SUPPORT)
  62. #include <platform/ncp1854.h>
  63. #endif
  64. #if defined(MTK_BQ25896_SUPPORT)
  65. #include <platform/bq25890.h>
  66. #endif
  67. #define DLPT_FEATURE_SUPPORT
  68. #define V_CHARGER_MAX 6500 // 6.5 V
  69. #undef printf
  70. /*****************************************************************************
  71. * Type define
  72. ****************************************************************************/
  73. #if defined(CUST_BATTERY_LOWVOL_THRESOLD)
  74. #define BATTERY_LOWVOL_THRESOLD CUST_BATTERY_LOWVOL_THRESOLD
  75. #else
  76. #define BATTERY_LOWVOL_THRESOLD 3450
  77. #endif
  78. /*****************************************************************************
  79. * Global Variable
  80. ****************************************************************************/
  81. bool g_boot_reason_change = false;
  82. #if defined(STD_AC_LARGE_CURRENT)
  83. int g_std_ac_large_current_en=1;
  84. #else
  85. int g_std_ac_large_current_en=0;
  86. #endif
  87. /*****************************************************************************
  88. * Externl Variable
  89. ****************************************************************************/
  90. extern bool g_boot_menu;
  91. extern void mtk_wdt_restart(void);
  92. int get_bat_volt(int times)
  93. {
  94. int bat_vol;
  95. #if defined(SWCHR_POWER_PATH)
  96. bat_vol = get_i_sense_volt(times);
  97. #else
  98. bat_vol = get_bat_sense_volt(times);
  99. #endif
  100. return bat_vol;
  101. }
  102. void kick_charger_wdt(void)
  103. {
  104. /*
  105. //mt6325_upmu_set_rg_chrwdt_td(0x0); // CHRWDT_TD, 4s
  106. mt6325_upmu_set_rg_chrwdt_td(0x3); // CHRWDT_TD, 32s for keep charging for lk to kernel
  107. mt6325_upmu_set_rg_chrwdt_wr(1); // CHRWDT_WR
  108. mt6325_upmu_set_rg_chrwdt_int_en(1); // CHRWDT_INT_EN
  109. mt6325_upmu_set_rg_chrwdt_en(1); // CHRWDT_EN
  110. mt6325_upmu_set_rg_chrwdt_flag_wr(1); // CHRWDT_WR
  111. */
  112. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_TD,3); // CHRWDT_TD, 32s for keep charging for lk to kernel
  113. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_WR,1); // CHRWDT_WR
  114. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_INT_EN,1); // CHRWDT_INT_EN
  115. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_EN,1); // CHRWDT_EN
  116. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_FLAG_WR,1);// CHRWDT_WR
  117. }
  118. #if defined(MTK_BATLOWV_NO_PANEL_ON_EARLY)
  119. kal_bool is_low_battery(kal_int32 val)
  120. {
  121. static UINT8 g_bat_low = 0xFF;
  122. //low battery only justice once in lk
  123. if (0xFF != g_bat_low)
  124. return g_bat_low;
  125. else
  126. g_bat_low = FALSE;
  127. #if defined(SWCHR_POWER_PATH)
  128. if (0 == val)
  129. val = get_i_sense_volt(1);
  130. #else
  131. if (0 == val)
  132. val = get_bat_sense_volt(1);
  133. #endif
  134. if (val < BATTERY_LOWVOL_THRESOLD) {
  135. dprintf(INFO, "%s, TRUE\n", __FUNCTION__);
  136. g_bat_low = 0x1;
  137. }
  138. if (FALSE == g_bat_low)
  139. dprintf(INFO, "%s, FALSE\n", __FUNCTION__);
  140. return g_bat_low;
  141. }
  142. #endif
  143. void pchr_turn_on_charging(kal_bool bEnable)
  144. {
  145. pmic_set_register_value(MT6351_PMIC_RG_USBDL_RST,1);//force leave USBDL mode
  146. //mt6325_upmu_set_rg_usbdl_rst(1); //force leave USBDL mode
  147. pmic_set_register_value(MT6351_PMIC_RG_BC11_RST,1);//BC11_RST
  148. kick_charger_wdt();
  149. pmic_set_register_value(MT6351_PMIC_RG_NORM_CS_VTH,0xC); // CS_VTH, 450mA
  150. //mt6325_upmu_set_rg_cs_vth(0xC); // CS_VTH, 450mA
  151. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_EN,bEnable);
  152. //mt6325_upmu_set_rg_csdac_en(1); // CSDAC_EN
  153. pmic_set_register_value(MT6351_PMIC_RG_NORM_CHR_EN,bEnable);
  154. //mt6325_upmu_set_rg_chr_en(1); // CHR_EN
  155. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_MODE,1);//CSDAC_MODE
  156. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_EN,1);
  157. #if defined(MTK_BQ24261_SUPPORT)
  158. bq24261_hw_init();
  159. bq24261_charging_enable(bEnable);
  160. bq24261_dump_register();
  161. #endif
  162. #if defined(MTK_BQ24296_SUPPORT)
  163. bq24296_hw_init();
  164. bq24296_charging_enable(bEnable);
  165. bq24296_dump_register();
  166. #endif
  167. #if defined(MTK_NCP1854_SUPPORT)
  168. ncp1854_hw_init();
  169. ncp1854_charging_enable(bEnable);
  170. ncp1854_dump_register();
  171. #endif
  172. #if defined(MTK_BQ25896_SUPPORT)
  173. bq25890_hw_init();
  174. bq25890_charging_enable(bEnable);
  175. bq25890_dump_register();
  176. #endif
  177. }
  178. void pchr_turn_off_charging(void)
  179. {
  180. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_INT_EN,0);// CHRWDT_INT_EN
  181. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_EN,0);// CHRWDT_EN
  182. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_FLAG_WR,0);// CHRWDT_FLAG
  183. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_EN,0);// CSDAC_EN
  184. pmic_set_register_value(MT6351_PMIC_RG_NORM_CHR_EN,0);// CHR_EN
  185. pmic_set_register_value(MT6351_PMIC_RG_HWCV_EN,0);// RG_HWCV_EN
  186. }
  187. /*
  188. * Switch Charger Power Path switch
  189. */
  190. void switch_charger_power_path_enable(kal_bool enable)
  191. {
  192. #if defined(MTK_BQ25896_SUPPORT)
  193. if (enable == KAL_TRUE) {
  194. bq25890_set_FORCE_VINDPM(1);
  195. bq25890_set_VINDPM(0x14);
  196. } else {
  197. bq25890_set_FORCE_VINDPM(1);
  198. bq25890_set_VINDPM(0x7F);
  199. }
  200. #endif
  201. }
  202. int is_charging = 0;
  203. #define rtc_busy_wait() \
  204. do { \
  205. while (RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY); \
  206. } while (0)
  207. static U16 RTC_Read(U16 addr)
  208. {
  209. U32 rdata=0;
  210. pwrap_read((U32)addr, &rdata);
  211. return (U16)rdata;
  212. }
  213. static void RTC_Write(U16 addr, U16 data)
  214. {
  215. pwrap_write((U32)addr, (U32)data);
  216. }
  217. static void rtc_write_trigger(void)
  218. {
  219. RTC_Write(RTC_WRTGR, 1);
  220. rtc_busy_wait();
  221. }
  222. void lk_set_rtc_to_zero()
  223. {
  224. int tmp_val1, tmp_val2;
  225. tmp_val1 = RTC_Read(RTC_AL_HOU);
  226. RTC_Write(RTC_AL_HOU, (RTC_Read(RTC_AL_HOU)&RTC_AL_HOU_MASK));
  227. rtc_write_trigger();
  228. tmp_val2 = RTC_Read(RTC_AL_HOU);
  229. dprintf(CRITICAL, "LK reset FG_RTC %d => %d\n", tmp_val1>>8, tmp_val2>>8);
  230. }
  231. /*
  232. * enter this function when low battery with charger
  233. * For BQ25896, power path support can provide current and voltage for cell phone to boot directly to kernel.
  234. */
  235. void check_bat_protect_status()
  236. {
  237. kal_int32 bat_val = 0;
  238. int current,chr_volt,cnt=0,i;
  239. #if defined(SWCHR_POWER_PATH)
  240. bat_val = get_i_sense_volt(5);
  241. #else
  242. bat_val = get_bat_sense_volt(5);
  243. #endif
  244. dprintf(CRITICAL, "[%s]: check VBAT=%d mV with %d mV, start charging... \n", __FUNCTION__, bat_val, BATTERY_LOWVOL_THRESOLD);
  245. while (bat_val < BATTERY_LOWVOL_THRESOLD) {
  246. mtk_wdt_restart();
  247. if (upmu_is_chr_det() == KAL_FALSE) {
  248. dprintf(CRITICAL, "[BATTERY] No Charger, Power OFF !\n");
  249. mt6575_power_off();
  250. while (1);
  251. }
  252. chr_volt= get_charger_volt(1);
  253. if (chr_volt>V_CHARGER_MAX) {
  254. dprintf(CRITICAL, "[BATTERY] charger voltage is too high :%d , threshold is %d !\n",chr_volt,V_CHARGER_MAX);
  255. #if defined(SWCHR_POWER_PATH)
  256. mt6575_power_off();
  257. #endif
  258. break;
  259. }
  260. pmic_set_register_value(PMIC_BATON_TDET_EN, 1);
  261. pmic_set_register_value(PMIC_RG_BATON_EN, 1);
  262. if (pmic_get_register_value(PMIC_RGS_BATON_UNDET) == 1) {
  263. dprintf(CRITICAL, "[BATTERY] No battry plug-in. Power Off.");
  264. mt6575_power_off();
  265. break;
  266. }
  267. dprintf(CRITICAL, "[%s]: check VBAT=%d mV with %d mV, start charging... \n", __FUNCTION__, bat_val, BATTERY_LOWVOL_THRESOLD);
  268. is_charging = 1;
  269. pchr_turn_on_charging(KAL_TRUE);
  270. lk_set_rtc_to_zero();
  271. #if defined(SWCHR_POWER_PATH)
  272. thread_sleep(10000);
  273. #else
  274. cnt=0;
  275. for (i=0; i<10; i++) {
  276. current=get_charging_current(1);
  277. chr_volt=get_charger_volt(1);
  278. if (current<100 && chr_volt<4400) {
  279. cnt++;
  280. dprintf(CRITICAL, "[BATTERY] charging current=%d charger volt=%d\n\r",current,chr_volt);
  281. } else {
  282. dprintf(CRITICAL, "[BATTERY] charging current=%d charger volt=%d\n\r",current,chr_volt);
  283. cnt=0;
  284. }
  285. }
  286. if (cnt>=8) {
  287. dprintf(CRITICAL, "[BATTERY] charging current and charger volt too low !! \n\r",cnt);
  288. pchr_turn_off_charging();
  289. #ifndef NO_POWER_OFF
  290. mt6575_power_off();
  291. #endif
  292. while (1) {
  293. dprintf(CRITICAL, "If you see the log, please check with RTC power off API\n\r");
  294. }
  295. }
  296. mdelay(50);
  297. #endif
  298. #if defined(SWCHR_POWER_PATH)
  299. #ifndef MTK_NCP1854_SUPPORT /* NCP1854 needs enable charging to have power path */
  300. pchr_turn_on_charging(KAL_FALSE);
  301. mdelay(100);
  302. #endif
  303. bat_val = get_i_sense_volt(5);
  304. #else
  305. bat_val = get_bat_sense_volt(5);
  306. #endif
  307. dprintf(CRITICAL, "[%s]: check VBAT=%d mV \n", __FUNCTION__, bat_val);
  308. }
  309. mtk_wdt_restart();
  310. dprintf(CRITICAL, "[%s]: check VBAT=%d mV with %d mV, stop charging... \n", __FUNCTION__, bat_val, BATTERY_LOWVOL_THRESOLD);
  311. }
  312. void mt65xx_bat_init(void)
  313. {
  314. kal_int32 bat_vol;
  315. #if defined(SWCHR_POWER_PATH) || defined(MTK_PUMP_EXPRESS_PLUS_SUPPORT)
  316. kal_int32 chr_volt;
  317. #endif
  318. // Low Battery Safety Booting
  319. #if defined(SWCHR_POWER_PATH)
  320. bat_vol = get_i_sense_volt(1);
  321. #else
  322. bat_vol = get_bat_sense_volt(1);
  323. #endif
  324. //pchr_turn_on_charging(KAL_TRUE);
  325. dprintf(INFO, "[mt65xx_bat_init] check VBAT=%d mV with %d mV\n", bat_vol, BATTERY_LOWVOL_THRESOLD);
  326. #if defined(MTK_PUMP_EXPRESS_PLUS_SUPPORT) || defined(MTK_PUMP_EXPRESS_PLUS_20_SUPPORT)
  327. /*Try to reset PE+ adapter once abnormal voltage is found*/
  328. chr_volt = get_charger_volt(1);
  329. if (chr_volt > V_CHARGER_MAX) {
  330. dprintf(CRITICAL, "[mt65xx_bat_init] PE+ adpater should be reset to 5V now\n");
  331. pumpex_reset_adapter_enble(1);
  332. mdelay(250);
  333. pumpex_reset_adapter_enble(0);
  334. }
  335. #endif
  336. if (g_boot_mode == KERNEL_POWER_OFF_CHARGING_BOOT && (pmic_get_register_value(MT6351_PMIC_PWRKEY_DEB)==0) ) {
  337. dprintf(CRITICAL, "[mt65xx_bat_init] KPOC+PWRKEY => change boot mode\n");
  338. g_boot_reason_change = true;
  339. }
  340. rtc_boot_check(false);
  341. #ifndef MTK_DISABLE_POWER_ON_OFF_VOLTAGE_LIMITATION
  342. #ifndef MTK_BATLOWV_NO_PANEL_ON_EARLY
  343. if (bat_vol < BATTERY_LOWVOL_THRESOLD)
  344. #else
  345. if (is_low_battery(bat_vol))
  346. #endif
  347. {
  348. if (g_boot_mode == KERNEL_POWER_OFF_CHARGING_BOOT && upmu_is_chr_det() == KAL_TRUE) {
  349. dprintf(CRITICAL, "[%s] Kernel Low Battery Power Off Charging Mode\n", __func__);
  350. g_boot_mode = LOW_POWER_OFF_CHARGING_BOOT;
  351. check_bat_protect_status();
  352. } else {
  353. dprintf(CRITICAL, "[BATTERY] battery voltage(%dmV) <= CLV ! Can not Boot Linux Kernel !! \n\r",bat_vol);
  354. #ifndef NO_POWER_OFF
  355. mt6575_power_off();
  356. #endif
  357. while (1) {
  358. dprintf(CRITICAL, "If you see the log, please check with RTC power off API\n\r");
  359. }
  360. }
  361. }
  362. #endif
  363. #if defined(SWCHR_POWER_PATH)
  364. chr_volt = get_charger_volt(1);
  365. if (chr_volt > V_CHARGER_MAX) {
  366. dprintf(CRITICAL, "Charger Over Voltage:%d\n, power off...", chr_volt);
  367. mt6575_power_off();
  368. }
  369. #endif
  370. #if defined(DLPT_FEATURE_SUPPORT)
  371. fgauge_initialization(NULL);
  372. if (g_boot_mode != META_BOOT && g_boot_mode != FACTORY_BOOT && g_boot_mode != ATE_FACTORY_BOOT) {
  373. pmic_set_register_value(PMIC_BATON_TDET_EN, 1);
  374. pmic_set_register_value(PMIC_RG_BATON_EN, 1);
  375. if (pmic_get_register_value(PMIC_RGS_BATON_UNDET) == 1) {
  376. dprintf(CRITICAL, "[BATTERY] No battry plug-in. Power Off.");
  377. mt6575_power_off();
  378. }
  379. }
  380. pchr_turn_on_charging(KAL_FALSE);
  381. /* disable SW charger power path */
  382. switch_charger_power_path_enable(KAL_FALSE);
  383. mdelay(50);
  384. get_dlpt_imix_r();
  385. /* after get imix, re-enable SW charger power path */
  386. switch_charger_power_path_enable(KAL_TRUE);
  387. mdelay(50);
  388. check_bat_protect_status();
  389. if (is_charging == 1) {
  390. pchr_turn_on_charging(KAL_TRUE);
  391. dprintf(CRITICAL, "turn on charging \n\r");
  392. }
  393. #endif //#if defined(DLPT_FEATURE_SUPPORT)
  394. return;
  395. }
  396. #if defined(DLPT_FEATURE_SUPPORT)
  397. int imix_r=170;
  398. kal_int32 chip_diff_trim_value_4_0 = 0;
  399. kal_int32 chip_diff_trim_value = 0; // unit = 0.1
  400. #define UNIT_FGCURRENT (158122) // 158.122 uA
  401. /* battery meter parameter */
  402. #define CHANGE_TRACKING_POINT
  403. #define CUST_TRACKING_POINT 1
  404. #define CUST_R_SENSE 68
  405. #define CUST_HW_CC 0
  406. #define AGING_TUNING_VALUE 103
  407. #define CUST_R_FG_OFFSET 0
  408. #define OCV_BOARD_COMPESATE 0 //mV
  409. #define R_FG_BOARD_BASE 1000
  410. #define R_FG_BOARD_SLOPE 1000 //slope
  411. #define CAR_TUNE_VALUE 86 //1.00
  412. /* HW Fuel gague */
  413. #define CURRENT_DETECT_R_FG 10 //1mA
  414. #define MinErrorOffset 1000
  415. #define FG_VBAT_AVERAGE_SIZE 18
  416. #define R_FG_VALUE 10 // mOhm, base is 20
  417. kal_bool g_fg_is_charging = 0;
  418. kal_uint32 ptim_bat_vol=0;
  419. kal_int32 ptim_R_curr=0;
  420. extern kal_uint32 upmu_get_reg_value(kal_uint32 reg);
  421. void get_hw_chip_diff_trim_value(void)
  422. {
  423. #if 1
  424. kal_int32 reg_val = 0;
  425. reg_val = upmu_get_reg_value(0xCB8);
  426. chip_diff_trim_value_4_0 = (reg_val>>7)&0x001F;//chip_diff_trim_value_4_0 = (reg_val>>10)&0x001F;
  427. dprintf(CRITICAL,"[Chip_Trim] Reg[0xCB8]=0x%x, chip_diff_trim_value_4_0=%d\n", reg_val, chip_diff_trim_value_4_0);
  428. #else
  429. dprintf(CRITICAL,"[Chip_Trim] need check reg number\n");
  430. #endif
  431. switch (chip_diff_trim_value_4_0) {
  432. case 0:
  433. chip_diff_trim_value = 1000;
  434. break;
  435. case 1:
  436. chip_diff_trim_value = 1005;
  437. break;
  438. case 2:
  439. chip_diff_trim_value = 1010;
  440. break;
  441. case 3:
  442. chip_diff_trim_value = 1015;
  443. break;
  444. case 4:
  445. chip_diff_trim_value = 1020;
  446. break;
  447. case 5:
  448. chip_diff_trim_value = 1025;
  449. break;
  450. case 6:
  451. chip_diff_trim_value = 1030;
  452. break;
  453. case 7:
  454. chip_diff_trim_value = 1036;
  455. break;
  456. case 8:
  457. chip_diff_trim_value = 1041;
  458. break;
  459. case 9:
  460. chip_diff_trim_value = 1047;
  461. break;
  462. case 10:
  463. chip_diff_trim_value = 1052;
  464. break;
  465. case 11:
  466. chip_diff_trim_value = 1058;
  467. break;
  468. case 12:
  469. chip_diff_trim_value = 1063;
  470. break;
  471. case 13:
  472. chip_diff_trim_value = 1069;
  473. break;
  474. case 14:
  475. chip_diff_trim_value = 1075;
  476. break;
  477. case 15:
  478. chip_diff_trim_value = 1081;
  479. break;
  480. case 31:
  481. chip_diff_trim_value = 995;
  482. break;
  483. case 30:
  484. chip_diff_trim_value = 990;
  485. break;
  486. case 29:
  487. chip_diff_trim_value = 985;
  488. break;
  489. case 28:
  490. chip_diff_trim_value = 980;
  491. break;
  492. case 27:
  493. chip_diff_trim_value = 975;
  494. break;
  495. case 26:
  496. chip_diff_trim_value = 970;
  497. break;
  498. case 25:
  499. chip_diff_trim_value = 966;
  500. break;
  501. case 24:
  502. chip_diff_trim_value = 961;
  503. break;
  504. case 23:
  505. chip_diff_trim_value = 956;
  506. break;
  507. case 22:
  508. chip_diff_trim_value = 952;
  509. break;
  510. case 21:
  511. chip_diff_trim_value = 947;
  512. break;
  513. case 20:
  514. chip_diff_trim_value = 943;
  515. break;
  516. case 19:
  517. chip_diff_trim_value = 938;
  518. break;
  519. case 18:
  520. chip_diff_trim_value = 934;
  521. break;
  522. case 17:
  523. chip_diff_trim_value = 930;
  524. break;
  525. default:
  526. dprintf(CRITICAL, "[Chip_Trim] Invalid value(%d)\n", chip_diff_trim_value_4_0);
  527. break;
  528. }
  529. dprintf(CRITICAL, "[Chip_Trim] chip_diff_trim_value=%d\n", chip_diff_trim_value);
  530. }
  531. static kal_uint32 fg_get_data_ready_status(void)
  532. {
  533. kal_uint32 ret=0;
  534. kal_uint32 temp_val=0;
  535. ret=pmic_read_interface(MT6351_FGADC_CON0, &temp_val, 0xFFFF, 0x0);
  536. dprintf(CRITICAL, "[fg_get_data_ready_status] Reg[0x%x]=0x%x\r\n", MT6351_FGADC_CON0, temp_val);
  537. temp_val = (temp_val & (MT6351_PMIC_FG_LATCHDATA_ST_MASK << MT6351_PMIC_FG_LATCHDATA_ST_SHIFT)) >> MT6351_PMIC_FG_LATCHDATA_ST_SHIFT;
  538. return temp_val;
  539. }
  540. kal_int32 use_chip_trim_value(kal_int32 not_trim_val)
  541. {
  542. kal_int32 ret_val=0;
  543. ret_val=((not_trim_val*chip_diff_trim_value)/1000);
  544. dprintf(CRITICAL, "[use_chip_trim_value] %d -> %d\n", not_trim_val, ret_val);
  545. return ret_val;
  546. }
  547. void fgauge_read_current(void *data)
  548. {
  549. kal_uint16 uvalue16 = 0;
  550. kal_int32 dvalue = 0;
  551. int m = 0;
  552. uint64_t Temp_Value = 0;
  553. kal_int32 Current_Compensate_Value=0;
  554. kal_uint32 ret = 0;
  555. // HW Init
  556. //(1) i2c_write (0x60, 0xC8, 0x01); // Enable VA2
  557. //(2) i2c_write (0x61, 0x15, 0x00); // Enable FGADC clock for digital
  558. //(3) i2c_write (0x61, 0x69, 0x28); // Set current mode, auto-calibration mode and 32KHz clock source
  559. //(4) i2c_write (0x61, 0x69, 0x29); // Enable FGADC
  560. //Read HW Raw Data
  561. //(1) Set READ command
  562. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0200, 0xFF00, 0x0);
  563. //(2) Keep i2c read when status = 1 (0x06)
  564. m=0;
  565. while ( fg_get_data_ready_status() == 0 ) {
  566. m++;
  567. if (m>1000) {
  568. dprintf(CRITICAL, "[fgauge_read_current] fg_get_data_ready_status timeout 1 !\r\n");
  569. break;
  570. }
  571. }
  572. //(3) Read FG_CURRENT_OUT[15:08]
  573. //(4) Read FG_CURRENT_OUT[07:00]
  574. uvalue16 = pmic_get_register_value(MT6351_PMIC_FG_CURRENT_OUT); //mt6325_upmu_get_fg_current_out();
  575. dprintf(CRITICAL, "[fgauge_read_current] : FG_CURRENT = %x\r\n", uvalue16);
  576. //(5) (Read other data)
  577. //(6) Clear status to 0
  578. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0800, 0xFF00, 0x0);
  579. //(7) Keep i2c read when status = 0 (0x08)
  580. //while ( fg_get_sw_clear_status() != 0 )
  581. m=0;
  582. while ( fg_get_data_ready_status() != 0 ) {
  583. m++;
  584. if (m>1000) {
  585. dprintf(CRITICAL, "[fgauge_read_current] fg_get_data_ready_status timeout 2 !\r\n");
  586. break;
  587. }
  588. }
  589. //(8) Recover original settings
  590. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0000, 0xFF00, 0x0);
  591. //calculate the real world data
  592. dvalue = (kal_uint32) uvalue16;
  593. if ( dvalue == 0 ) {
  594. Temp_Value = (uint64_t) dvalue;
  595. g_fg_is_charging = KAL_FALSE;
  596. } else if ( dvalue > 32767 ) { // > 0x8000
  597. Temp_Value = (uint64_t)(dvalue - 65535);
  598. Temp_Value = Temp_Value - (Temp_Value*2);
  599. g_fg_is_charging = KAL_FALSE;
  600. } else {
  601. Temp_Value = (uint64_t) dvalue;
  602. g_fg_is_charging = KAL_TRUE;
  603. }
  604. Temp_Value = Temp_Value * UNIT_FGCURRENT;
  605. //do_div(Temp_Value, 100000);
  606. Temp_Value=Temp_Value/100000;
  607. dvalue = (kal_uint32)Temp_Value;
  608. if ( g_fg_is_charging == KAL_TRUE ) {
  609. dprintf(CRITICAL, "[fgauge_read_current] current(charging) = %d mA\r\n", dvalue);
  610. } else {
  611. dprintf(CRITICAL, "[fgauge_read_current] current(discharging) = %d mA\r\n", dvalue);
  612. }
  613. // Auto adjust value
  614. if (R_FG_VALUE != 20) {
  615. dprintf(CRITICAL, "[fgauge_read_current] Auto adjust value due to the Rfg is %d\n Ori current=%d, ", R_FG_VALUE, dvalue);
  616. dvalue = (dvalue*20)/R_FG_VALUE;
  617. dprintf(CRITICAL, "[fgauge_read_current] new current=%d\n", dvalue);
  618. }
  619. // K current
  620. if (R_FG_BOARD_SLOPE != R_FG_BOARD_BASE) {
  621. dvalue = ( (dvalue*R_FG_BOARD_BASE) + (R_FG_BOARD_SLOPE/2) ) / R_FG_BOARD_SLOPE;
  622. }
  623. // current compensate
  624. if (g_fg_is_charging == KAL_TRUE) {
  625. dvalue = dvalue + Current_Compensate_Value;
  626. } else {
  627. dvalue = dvalue - Current_Compensate_Value;
  628. }
  629. dprintf(CRITICAL, "[fgauge_read_current] ori current=%d\n", dvalue);
  630. dvalue = ((dvalue*CAR_TUNE_VALUE)/100);
  631. dvalue = use_chip_trim_value(dvalue);
  632. dprintf(CRITICAL, "[fgauge_read_current] final current=%d (ratio=%d)\n", dvalue, CAR_TUNE_VALUE);
  633. *(kal_int32*)(data) = dvalue;
  634. return;
  635. }
  636. void fgauge_read_IM_current(void *data)
  637. {
  638. kal_uint16 uvalue16 = 0;
  639. kal_int32 dvalue = 0;
  640. int m = 0;
  641. uint64_t Temp_Value = 0;
  642. kal_int32 Current_Compensate_Value=0;
  643. kal_uint32 ret = 0;
  644. uvalue16 = pmic_get_register_value(MT6351_PMIC_FG_R_CURR);
  645. dprintf(CRITICAL, "[fgauge_read_IM_current] : FG_CURRENT = %x\r\n", uvalue16);
  646. //calculate the real world data
  647. dvalue = (kal_uint32) uvalue16;
  648. if ( dvalue == 0 ) {
  649. Temp_Value = (uint64_t) dvalue;
  650. g_fg_is_charging = KAL_FALSE;
  651. } else if ( dvalue > 32767 ) { // > 0x8000
  652. Temp_Value = (uint64_t)(dvalue - 65535);
  653. Temp_Value = Temp_Value - (Temp_Value*2);
  654. g_fg_is_charging = KAL_FALSE;
  655. } else {
  656. Temp_Value = (uint64_t) dvalue;
  657. g_fg_is_charging = KAL_TRUE;
  658. }
  659. Temp_Value = Temp_Value * UNIT_FGCURRENT;
  660. //do_div(Temp_Value, 100000);
  661. Temp_Value=Temp_Value/100000;
  662. dvalue = (kal_uint32)Temp_Value;
  663. if ( g_fg_is_charging == KAL_TRUE ) {
  664. dprintf(CRITICAL, "[fgauge_read_IM_current] current(charging) = %d mA\r\n", dvalue);
  665. } else {
  666. dprintf(CRITICAL, "[fgauge_read_IM_current] current(discharging) = %d mA\r\n", dvalue);
  667. }
  668. // Auto adjust value
  669. if (R_FG_VALUE != 20) {
  670. dprintf(CRITICAL, "[fgauge_read_IM_current] Auto adjust value due to the Rfg is %d\n Ori current=%d, ", R_FG_VALUE, dvalue);
  671. dvalue = (dvalue*20)/R_FG_VALUE;
  672. dprintf(CRITICAL, "[fgauge_read_IM_current] new current=%d\n", dvalue);
  673. }
  674. // K current
  675. if (R_FG_BOARD_SLOPE != R_FG_BOARD_BASE) {
  676. dvalue = ( (dvalue*R_FG_BOARD_BASE) + (R_FG_BOARD_SLOPE/2) ) / R_FG_BOARD_SLOPE;
  677. }
  678. // current compensate
  679. if (g_fg_is_charging == KAL_TRUE) {
  680. dvalue = dvalue + Current_Compensate_Value;
  681. } else {
  682. dvalue = dvalue - Current_Compensate_Value;
  683. }
  684. dprintf(CRITICAL, "[fgauge_read_IM_current] ori current=%d\n", dvalue);
  685. dvalue = ((dvalue*CAR_TUNE_VALUE)/100);
  686. dvalue = use_chip_trim_value(dvalue);
  687. dprintf(CRITICAL,"[fgauge_read_IM_current] final current=%d (ratio=%d)\n", dvalue, CAR_TUNE_VALUE);
  688. *(kal_int32*)(data) = dvalue;
  689. return;
  690. }
  691. void fgauge_initialization(void *data)
  692. {
  693. kal_uint32 ret=0;
  694. kal_int32 current_temp = 0;
  695. int m = 0;
  696. get_hw_chip_diff_trim_value();
  697. // 1. HW initialization
  698. //FGADC clock is 32768Hz from RTC
  699. //Enable FGADC in current mode at 32768Hz with auto-calibration
  700. //(1) Enable VA2
  701. //(2) Enable FGADC clock for digital
  702. pmic_set_register_value(MT6351_PMIC_RG_FGADC_ANA_CK_PDN,0);// mt6325_upmu_set_rg_fgadc_ana_ck_pdn(0);
  703. pmic_set_register_value(MT6351_PMIC_RG_FGADC_DIG_CK_PDN,0);// mt6325_upmu_set_rg_fgadc_dig_ck_pdn(0);
  704. //(3) Set current mode, auto-calibration mode and 32KHz clock source
  705. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0028, 0x00FF, 0x0);
  706. //(4) Enable FGADC
  707. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0029, 0x00FF, 0x0);
  708. //reset HW FG
  709. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x7100, 0xFF00, 0x0);
  710. dprintf(CRITICAL,"******** [fgauge_initialization] reset HW FG!\n" );
  711. //set FG_OSR
  712. ret=pmic_config_interface(MT6351_FGADC_CON11, 0x8, 0xF, 0x0);
  713. dprintf(CRITICAL, "[fgauge_initialization] Reg[0x%x]=0x%x\n",MT6351_FGADC_CON11, upmu_get_reg_value(MT6351_FGADC_CON11));
  714. //make sure init finish
  715. m = 0;
  716. while (current_temp == 0) {
  717. fgauge_read_current(&current_temp);
  718. m++;
  719. if (m>1000) {
  720. dprintf(CRITICAL, "[fgauge_initialization] timeout!\r\n");
  721. break;
  722. }
  723. }
  724. dprintf(CRITICAL, "******** [fgauge_initialization] Done!\n" );
  725. return ;
  726. }
  727. void do_ptim(void)
  728. {
  729. kal_uint32 i;
  730. kal_uint32 vbat_reg;
  731. //PMICLOG("[do_ptim] start \n");
  732. //pmic_auxadc_lock();
  733. //pmic_set_register_value(PMIC_RG_AUXADC_RST,1);
  734. //pmic_set_register_value(PMIC_RG_AUXADC_RST,0);
  735. upmu_set_reg_value(0x0eac,0x0006);
  736. pmic_set_register_value(MT6351_PMIC_AUXADC_IMP_AUTORPT_PRD,6);
  737. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN,0);
  738. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN_HWEN,0);
  739. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_CK_PDN_HWEN,0);
  740. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_CK_PDN,0);
  741. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,1);
  742. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,1);
  743. //restore to initial state
  744. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,0);
  745. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,0);
  746. //set issue interrupt
  747. //pmic_set_register_value(MT6351_PMIC_RG_INT_EN_AUXADC_IMP,1);
  748. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_CHSEL,0);
  749. pmic_set_register_value(MT6351_PMIC_AUXADC_IMP_AUTORPT_EN,1);
  750. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_CNT,3);
  751. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_MODE,1);
  752. // MT6351_PMICLOG("[do_ptim] end %d %d \n",pmic_get_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN),pmic_get_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN_HWEN));
  753. while (pmic_get_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_STATUS)==0) {
  754. //MT6351_PMICLOG("[do_ptim] MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_STATUS= %d \n",pmic_get_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_STATUS));
  755. mdelay(1);
  756. }
  757. //disable
  758. pmic_set_register_value(MT6351_PMIC_AUXADC_IMP_AUTORPT_EN,0);//typo
  759. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_MODE,0);
  760. //clear irq
  761. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,1);
  762. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,1);
  763. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,0);
  764. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,0);
  765. //MT6351_PMICLOG("[do_ptim2] 0xee8=0x%x 0x2c6=0x%x\n", upmu_get_reg_value(0xee8),upmu_get_reg_value(0x2c6));
  766. //pmic_set_register_value(MT6351_PMIC_RG_INT_STATUS_AUXADC_IMP,1);//write 1 to clear !
  767. //pmic_set_register_value(MT6351_PMIC_RG_INT_EN_AUXADC_IMP,0);
  768. vbat_reg=pmic_get_register_value(MT6351_PMIC_AUXADC_ADC_OUT_IMP_AVG);
  769. ptim_bat_vol=(vbat_reg*3*18000)/32768;
  770. fgauge_read_IM_current((void *)&ptim_R_curr);
  771. }
  772. void enable_dummy_load(kal_uint32 en)
  773. {
  774. kal_uint32 reg;
  775. if (en==1) {
  776. /*1. disable isink pdn */
  777. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK3_CK_PDN, 0);
  778. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK2_CK_PDN, 0);
  779. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK1_CK_PDN, 0);
  780. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK0_CK_PDN, 0);
  781. pmic_set_register_value(MT6351_PMIC_RG_DRV_32K_CK_PDN, 0);
  782. /*1. disable isink pdn */
  783. pmic_set_register_value(MT6351_PMIC_RG_DRV_CHRIND_CK_PDN, 0);
  784. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK7_CK_PDN, 0);
  785. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK6_CK_PDN, 0);
  786. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK5_CK_PDN, 0);
  787. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK4_CK_PDN, 0);
  788. /* enable isink step */
  789. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_STEP, 0x7);
  790. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_STEP, 0x7);
  791. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_STEP, 0x7);
  792. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_STEP, 0x7);
  793. /*enable isink */
  794. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_BIAS_EN, 0x1);
  795. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_BIAS_EN, 0x1);
  796. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_BIAS_EN, 0x1);
  797. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_BIAS_EN, 0x1);
  798. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP7_EN, 0x1);
  799. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP6_EN, 0x1);
  800. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP3_EN, 0x1);
  801. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP2_EN, 0x1);
  802. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_EN, 0x1);
  803. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_EN, 0x1);
  804. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_EN, 0x1);
  805. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_EN, 0x1);
  806. /*PMICLOG("[enable dummy load]\n"); */
  807. pmic_read_interface(0x23a, &reg, 0xffff, 0);
  808. dprintf(INFO, "[isink 2 [0x23a]=0x%x \n", reg);
  809. pmic_read_interface(0x258, &reg, 0xffff, 0);
  810. dprintf(INFO, "[isink 2 [0x258]=0x%x \n", reg);
  811. pmic_read_interface(0x83c, &reg, 0xffff, 0);
  812. dprintf(INFO, "[isink 2 [0x83c]=0x%x \n", reg);
  813. pmic_read_interface(0x83e, &reg, 0xffff, 0);
  814. dprintf(INFO, "[isink 3 [0x83e]=0x%x] \n", reg);
  815. pmic_read_interface(0x840, &reg, 0xffff, 0);
  816. dprintf(INFO, "[isink 6 [0x840]=0x%x] \n", reg);
  817. pmic_read_interface(0x842, &reg, 0xffff, 0);
  818. dprintf(INFO, "[isink 7 [0x842]=0x%x] \n", reg);
  819. pmic_read_interface(0x848, &reg, 0xffff, 0);
  820. dprintf(INFO, "[isink 7 [0x848]=0x%x] \n", reg);
  821. pmic_read_interface(0x844, &reg, 0xffff, 0);
  822. dprintf(INFO, "[isink 7 [0x844]=0x%x] \n", reg);
  823. } else {
  824. /*upmu_set_reg_value(0x828,0x0cc0); */
  825. #if MT6328
  826. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_EN, 0);
  827. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_EN, 0);
  828. #endif
  829. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_EN, 0);
  830. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_EN, 0);
  831. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_EN, 0);
  832. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_EN, 0);
  833. /*pmic_set_register_value(PMIC_RG_VIBR_EN,0); */
  834. /*PMICLOG("[disable dummy load]\n"); */
  835. }
  836. }
  837. int get_rac_val(void)
  838. {
  839. int volt_1=0;
  840. int volt_2=0;
  841. int curr_1=0;
  842. int curr_2=0;
  843. int rac_cal=0;
  844. int ret=0;
  845. kal_bool retry_state = KAL_FALSE;
  846. int retry_count=0;
  847. do {
  848. //adc and fg--------------------------------------------------------
  849. do_ptim();
  850. dprintf(INFO, "[1,Trigger ADC PTIM mode] volt1=%d, curr_1=%d\n", ptim_bat_vol, ptim_R_curr);
  851. volt_1=ptim_bat_vol;
  852. curr_1=ptim_R_curr;
  853. dprintf(INFO, "[2,enable dummy load]");
  854. enable_dummy_load(1);
  855. /* debug to measure bat volt & Isense */
  856. /* pmic_set_register_value(MT6351_PMIC_RG_VIBR_EN, 0x1); */
  857. mdelay(1);
  858. //Wait --------------------------------------------------------------
  859. //adc and fg--------------------------------------------------------
  860. do_ptim();
  861. dprintf(INFO, "[3,Trigger ADC PTIM mode again]0717 volt2=%d, curr_2=%d\n", ptim_bat_vol, ptim_R_curr);
  862. volt_2=ptim_bat_vol;
  863. curr_2=ptim_R_curr;
  864. //Disable dummy load-------------------------------------------------
  865. enable_dummy_load(0);
  866. /* debug to measure bat volt & Isense */
  867. /*pmic_set_register_value(MT6351_PMIC_RG_VIBR_EN, 0); */
  868. //Calculate Rac------------------------------------------------------
  869. if ( (curr_2-curr_1) >= 700 && (curr_2-curr_1) <= 1200 && (volt_1-volt_2)>=80 ) { //40.0mA
  870. rac_cal=((volt_1-volt_2)*1000)/(curr_2-curr_1); //m-ohm
  871. if (rac_cal<0) {
  872. ret = (rac_cal-(rac_cal*2))*1;
  873. } else {
  874. ret = rac_cal*1;
  875. }
  876. } else {
  877. ret=-1;
  878. dprintf(CRITICAL, "[4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA\n");
  879. }
  880. dprintf(INFO, "[5,Calculate Rac] volt_1=%d,volt_2=%d,curr_1=%d,curr_2=%d,rac_cal=%d,ret=%d,retry_count=%d\n",
  881. volt_1,volt_2,curr_1,curr_2,rac_cal,ret,retry_count);
  882. dprintf(CRITICAL, "[6,Calculate Rac] %d,%d,%d,%d,%d,%d,%d\n",
  883. volt_1,volt_2,curr_1,curr_2,rac_cal,ret,retry_count);
  884. //------------------------
  885. retry_count++;
  886. if ((retry_count < 3) && (ret == -1)) retry_state = KAL_TRUE;
  887. else retry_state = KAL_FALSE;
  888. } while (retry_state == KAL_TRUE);
  889. return ret;
  890. }
  891. void get_dlpt_imix_r(void)
  892. {
  893. int rac_val[5],rac_val_avg=0,rac_val_sum=0;
  894. int volt[5],curr[5],volt_avg=0,curr_avg=0;
  895. int imix;
  896. int i;
  897. int validcnt=0;
  898. int min=1000,max=0;
  899. for (i=0; i<5; i++) {
  900. rac_val[i]=get_rac_val();
  901. if (rac_val[i]<=min && rac_val[i]!=-1)
  902. min=rac_val[i];
  903. if (rac_val[i]>=max)
  904. max=rac_val[i];
  905. if (rac_val[i]!=-1) {
  906. rac_val_sum+=rac_val[i];
  907. validcnt++;
  908. }
  909. }
  910. if (validcnt>=4) {
  911. rac_val_sum=rac_val_sum-min-max;
  912. imix_r=rac_val_sum/(validcnt-2);
  913. } else if (validcnt!=0) {
  914. imix_r=rac_val_sum/validcnt;
  915. }
  916. dprintf(CRITICAL, "[dlpt_R] %d,%d,%d,%d,%d [%d:%d:%d]%d\n",rac_val[0],rac_val[1],rac_val[2],rac_val[3],rac_val[4],min,max,validcnt,imix_r);
  917. return;
  918. }
  919. #endif //#if defined(DLPT_FEATURE_SUPPORT)
  920. #else
  921. #include <platform/mt_typedefs.h>
  922. #include <platform/mt_reg_base.h>
  923. #include <printf.h>
  924. int imix_r=170;
  925. void mt65xx_bat_init(void)
  926. {
  927. dprintf(CRITICAL, "[BATTERY] Skip mt65xx_bat_init !!\n\r");
  928. dprintf(CRITICAL, "[BATTERY] If you want to enable power off charging, \n\r");
  929. dprintf(CRITICAL, "[BATTERY] Please #define CFG_POWER_CHARGING!!\n\r");
  930. }
  931. int get_bat_volt(int times)
  932. {
  933. int bat_vol;
  934. #if defined(SWCHR_POWER_PATH)
  935. bat_vol = get_i_sense_volt(times);
  936. #else
  937. bat_vol = get_bat_sense_volt(times);
  938. #endif
  939. return bat_vol;
  940. }
  941. #endif