mt_rtc.c 10 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <debug.h>
  32. #include <platform/mt_typedefs.h>
  33. #include <platform/mt_rtc.h>
  34. #include <platform/boot_mode.h>
  35. #include <platform/pmic_wrap_init.h>
  36. #include <target/board.h>
  37. #include <platform/mtk_wdt.h>
  38. #include <platform/mt_rtc_hw.h>
  39. #define DBG_RTC_C(x...) dprintf(CRITICAL, x)
  40. #define DBG_RTC_I(x...) dprintf(INFO, x)
  41. #define DBG_RTC_S(x...) dprintf(SPEW, x)
  42. #define RTC_RELPWR_WHEN_XRST 1 /* BBPU = 0 when xreset_rstb goes low */
  43. extern BOOT_ARGUMENT *g_boot_arg;
  44. static U16 RTC_Read(U16 addr)
  45. {
  46. U32 rdata=0;
  47. pwrap_read((U32)addr, &rdata);
  48. return (U16)rdata;
  49. }
  50. static void RTC_Write(U16 addr, U16 data)
  51. {
  52. pwrap_write((U32)addr, (U32)data);
  53. }
  54. #define rtc_busy_wait() \
  55. do { \
  56. while (RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY); \
  57. } while (0)
  58. static unsigned long rtc_mktime(int yea, int mth, int dom, int hou, int min, int sec)
  59. {
  60. unsigned long d1, d2, d3;
  61. mth -= 2;
  62. if (mth <= 0) {
  63. mth += 12;
  64. yea -= 1;
  65. }
  66. d1 = (yea - 1) * 365 + (yea / 4 - yea / 100 + yea / 400);
  67. d2 = (367 * mth / 12 - 30) + 59;
  68. d3 = d1 + d2 + (dom - 1) - 719162;
  69. return ((d3 * 24 + hou) * 60 + min) * 60 + sec;
  70. }
  71. static void rtc_write_trigger(void)
  72. {
  73. RTC_Write(RTC_WRTGR, 1);
  74. rtc_busy_wait();
  75. }
  76. void rtc_writeif_unlock(void)
  77. {
  78. RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1);
  79. rtc_write_trigger();
  80. RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2);
  81. rtc_write_trigger();
  82. }
  83. void rtc_writeif_lock(void)
  84. {
  85. RTC_Write(RTC_PROT, 0);
  86. rtc_write_trigger();
  87. }
  88. static void rtc_xosc_write(U16 val)
  89. {
  90. U16 bbpu;
  91. RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
  92. mdelay(1);
  93. RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
  94. mdelay(1);
  95. RTC_Write(RTC_OSC32CON, val);
  96. mdelay(1);
  97. }
  98. void rtc_enable_k_eosc(void)
  99. {
  100. pmic_config_interface(PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR, 1, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT);
  101. pmic_config_interface(PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR, 1, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT);
  102. /* If cali eosc every second, needing to add the following configuration, default period is 8 sec */
  103. //pmic_config_interface(PMIC_EOSC_CALI_TD_ADDR, 0x3, PMIC_EOSC_CALI_TD_MASK, PMIC_EOSC_CALI_TD_SHIFT);
  104. RTC_Write(RTC_BBPU, RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  105. rtc_write_trigger();
  106. DBG_RTC_I("[RTC] first bbpu = 0x%x, con = 0x%x, osc32con = 0x%x, sec = 0x%x, yea = 0x%x\n", RTC_Read(RTC_BBPU), RTC_Read(RTC_CON), RTC_Read(RTC_OSC32CON), RTC_Read(RTC_AL_SEC), RTC_Read(RTC_AL_YEA));
  107. rtc_xosc_write((RTC_Read(RTC_OSC32CON) & ~RTC_EMBCK_SEL_EOSC) | RTC_EMBCK_SEL_K_EOSC | RTC_EMBCK_SRC_SEL);
  108. }
  109. void rtc_disable_2sec_reboot(void)
  110. {
  111. U16 reboot;
  112. reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) & ~RTC_BBPU_AUTO_PDN_SEL;
  113. RTC_Write(RTC_AL_SEC, reboot);
  114. rtc_write_trigger();
  115. }
  116. void rtc_bbpu_power_down(void)
  117. {
  118. U16 bbpu;
  119. rtc_disable_2sec_reboot();
  120. #if defined(PMIC_CHIP_MT6353)
  121. rtc_enable_k_eosc();
  122. #endif
  123. /* pull PWRBB low */
  124. bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN;
  125. rtc_writeif_unlock();
  126. RTC_Write(RTC_BBPU, bbpu);
  127. rtc_write_trigger();
  128. }
  129. U16 rtc_rdwr_uart_bits(U16 *val)
  130. {
  131. U16 pdn2;
  132. if (val) {
  133. pdn2 = RTC_Read(RTC_PDN2) & ~RTC_PDN2_UART_MASK;
  134. pdn2 |= (*val & (RTC_PDN2_UART_MASK >> RTC_PDN2_UART_SHIFT)) << RTC_PDN2_UART_SHIFT;
  135. RTC_Write(RTC_PDN2, pdn2);
  136. rtc_write_trigger();
  137. }
  138. return (RTC_Read(RTC_PDN2) & RTC_PDN2_UART_MASK) >> RTC_PDN2_UART_SHIFT;
  139. }
  140. bool rtc_boot_check(bool can_alarm_boot)
  141. {
  142. U16 irqsta, pdn1, pdn2, spar0, spar1;
  143. irqsta = RTC_Read(RTC_IRQ_STA); /* read clear */
  144. pdn1 = RTC_Read(RTC_PDN1);
  145. pdn2 = RTC_Read(RTC_PDN2);
  146. spar0 = RTC_Read(RTC_SPAR0);
  147. spar1 = RTC_Read(RTC_SPAR1);
  148. /*printf("irqsta = 0x%x, pdn1 = 0x%x, pdn2 = 0x%x, spar0 = 0x%x, spar1 = 0x%x\n",
  149. irqsta, pdn1, pdn2, spar0, spar1);*/
  150. if (irqsta & RTC_IRQ_STA_AL) {
  151. #if RTC_RELPWR_WHEN_XRST
  152. /* set AUTO bit because AUTO = 0 when PWREN = 1 and alarm occurs */
  153. U16 bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_AUTO;
  154. RTC_Write(RTC_BBPU, bbpu);
  155. rtc_write_trigger();
  156. #endif
  157. if (pdn1 & RTC_PDN1_PWRON_TIME) { /* power-on time is available */
  158. U16 now_sec, now_min, now_hou, now_dom, now_mth, now_yea;
  159. U16 irqen, sec, min, hou, dom, mth, yea;
  160. unsigned long now_time, time;
  161. now_sec = RTC_Read(RTC_TC_SEC);
  162. now_min = RTC_Read(RTC_TC_MIN);
  163. now_hou = RTC_Read(RTC_TC_HOU);
  164. now_dom = RTC_Read(RTC_TC_DOM);
  165. now_mth = RTC_Read(RTC_TC_MTH);
  166. now_yea = RTC_Read(RTC_TC_YEA) + RTC_MIN_YEAR;
  167. if (RTC_Read(RTC_TC_SEC) < now_sec) { /* SEC has carried */
  168. now_sec = RTC_Read(RTC_TC_SEC);
  169. now_min = RTC_Read(RTC_TC_MIN);
  170. now_hou = RTC_Read(RTC_TC_HOU);
  171. now_dom = RTC_Read(RTC_TC_DOM);
  172. now_mth = RTC_Read(RTC_TC_MTH);
  173. now_yea = RTC_Read(RTC_TC_YEA) + RTC_MIN_YEAR;
  174. }
  175. sec = ((spar0 & RTC_SPAR0_PWRON_SEC_MASK) >> RTC_SPAR0_PWRON_SEC_SHIFT);
  176. min = ((spar1 & RTC_SPAR1_PWRON_MIN_MASK) >> RTC_SPAR1_PWRON_MIN_SHIFT);
  177. hou = ((spar1 & RTC_SPAR1_PWRON_HOU_MASK) >> RTC_SPAR1_PWRON_HOU_SHIFT);
  178. dom = ((spar1 & RTC_SPAR1_PWRON_DOM_MASK) >> RTC_SPAR1_PWRON_DOM_SHIFT);
  179. mth = ((pdn2 & RTC_PDN2_PWRON_MTH_MASK) >> RTC_PDN2_PWRON_MTH_SHIFT);
  180. yea = ((pdn2 & RTC_PDN2_PWRON_YEA_MASK) >> RTC_PDN2_PWRON_YEA_SHIFT) + RTC_MIN_YEAR;
  181. now_time = rtc_mktime(now_yea, now_mth, now_dom, now_hou, now_min, now_sec);
  182. time = rtc_mktime(yea, mth, dom, hou, min, sec);
  183. DBG_RTC_I("now = %d/%d/%d %d:%d:%d (%lu)\n",
  184. now_yea, now_mth, now_dom, now_hou, now_min, now_sec, now_time);
  185. DBG_RTC_I("power-on = %d/%d/%d %d:%d:%d (%lu)\n",
  186. yea, mth, dom, hou, min, sec, time);
  187. if (now_time >= time - 1 && now_time <= time + 4) { /* power on */
  188. pdn1 &= ~(RTC_PDN1_PWRON_TIME | RTC_PDN1_FAC_RESET | RTC_PDN1_BYPASS_PWR);
  189. RTC_Write(RTC_PDN1, pdn1);
  190. RTC_Write(RTC_PDN2, pdn2 | RTC_PDN2_PWRON_ALARM);
  191. rtc_write_trigger();
  192. if (can_alarm_boot &&
  193. !(pdn2 & RTC_PDN2_PWRON_LOGO)) { /* no logo means ALARM_BOOT */
  194. g_boot_mode = ALARM_BOOT;
  195. }
  196. return true;
  197. } else if (now_time < time) { /* set power-on alarm */
  198. RTC_Write(RTC_AL_YEA, (RTC_Read(RTC_AL_YEA) & ~(RTC_AL_YEA_MASK)) | ((yea - RTC_MIN_YEAR) & RTC_AL_YEA_MASK));
  199. RTC_Write(RTC_AL_MTH, (RTC_Read(RTC_AL_MTH)&RTC_NEW_SPARE3)|mth);
  200. RTC_Write(RTC_AL_DOM, (RTC_Read(RTC_AL_DOM)&RTC_NEW_SPARE1)|dom);
  201. RTC_Write(RTC_AL_HOU, (RTC_Read(RTC_AL_HOU)&RTC_NEW_SPARE_FG_MASK)|hou);
  202. RTC_Write(RTC_AL_MIN, min);
  203. RTC_Write(RTC_AL_SEC, RTC_Read(RTC_AL_SEC) & (~RTC_AL_SEC_MASK) | (sec & RTC_AL_SEC_MASK));
  204. RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW); /* mask DOW */
  205. rtc_write_trigger();
  206. irqen = RTC_Read(RTC_IRQ_EN) | RTC_IRQ_EN_ONESHOT_AL;
  207. RTC_Write(RTC_IRQ_EN, irqen);
  208. rtc_write_trigger();
  209. }
  210. }
  211. }
  212. if ((pdn1 & RTC_PDN1_RECOVERY_MASK) == RTC_PDN1_FAC_RESET) { /* factory data reset */
  213. RTC_Write(RTC_PDN1, pdn1 & ~RTC_PDN1_FAC_RESET);
  214. rtc_write_trigger();
  215. return true;
  216. }
  217. if (pdn1 & RTC_PDN1_BYPASS_PWR) { /* bypass power key detection */
  218. RTC_Write(RTC_PDN1, pdn1 & ~RTC_PDN1_BYPASS_PWR);
  219. rtc_write_trigger();
  220. return true;
  221. }
  222. return false;
  223. }
  224. void Set_Clr_RTC_PDN1_bit13(bool flag)
  225. {
  226. U16 pdn1;
  227. rtc_writeif_unlock();
  228. //use PDN1 bit13 for LK
  229. pdn1 = RTC_Read(RTC_PDN1);
  230. if(flag==true)
  231. pdn1 = pdn1 | RTC_PDN1_FAST_BOOT;
  232. else if(flag==false)
  233. pdn1 = pdn1 & ~RTC_PDN1_FAST_BOOT;
  234. RTC_Write(RTC_PDN1, pdn1);
  235. rtc_write_trigger();
  236. }
  237. bool Check_RTC_PDN1_bit13(void)
  238. {
  239. U16 pdn1;
  240. pdn1 = RTC_Read(RTC_PDN1);
  241. if(pdn1 & RTC_PDN1_FAST_BOOT)
  242. return true;
  243. else
  244. return false;
  245. }
  246. bool Check_RTC_Recovery_Mode(void)
  247. {
  248. U16 pdn1;
  249. pdn1 = RTC_Read(RTC_PDN1);
  250. if( (pdn1 & RTC_PDN1_RECOVERY_MASK)==RTC_PDN1_FAC_RESET )
  251. return true;
  252. else
  253. return false;
  254. }
  255. #if 1
  256. bool rtc_2sec_boot_check(void)
  257. {
  258. int boot_reason;
  259. if (g_boot_arg->maggic_number == BOOT_ARGUMENT_MAGIC) {
  260. boot_reason = g_boot_arg->boot_reason;
  261. if (boot_reason == BR_2SEC_REBOOT)
  262. return true;
  263. }
  264. return false;
  265. }
  266. #endif
  267. void Set_RTC_Recovery_Mode(bool flag)
  268. {
  269. U16 pdn1;
  270. rtc_writeif_unlock();
  271. pdn1 = RTC_Read(RTC_PDN1);
  272. if(flag==true)
  273. pdn1 = pdn1 | RTC_PDN1_FAC_RESET;
  274. else if(flag==false)
  275. pdn1 = pdn1 & ~RTC_PDN1_FAC_RESET;
  276. RTC_Write(RTC_PDN1, pdn1);
  277. rtc_write_trigger();
  278. DBG_RTC_I("Set_RTC_Fastboot_Mode\n");
  279. }
  280. static void rtc_get_tick(struct rtc_time *tm)
  281. {
  282. tm->tm_sec = RTC_Read(RTC_TC_SEC);
  283. tm->tm_min = RTC_Read(RTC_TC_MIN);
  284. tm->tm_hour = RTC_Read(RTC_TC_HOU);
  285. tm->tm_mday = RTC_Read(RTC_TC_DOM);
  286. tm->tm_mon = RTC_Read(RTC_TC_MTH);
  287. tm->tm_year = RTC_Read(RTC_TC_YEA);
  288. }
  289. void rtc_get_time(struct rtc_time *tm) {
  290. rtc_get_tick(tm);
  291. if (RTC_Read(RTC_TC_SEC) < tm->tm_sec) { /* SEC has carried */
  292. rtc_get_tick(tm);
  293. }
  294. tm->tm_year += RTC_MIN_YEAR;
  295. }