mtk-lk/platform/mt6755/pll.c

/* Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
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 * The following software/firmware and/or related documentation ("MediaTek
 * Software") have been modified by MediaTek Inc. All revisions are subject to
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 */

#include <platform/mt_typedefs.h>


#define APMIXED_BASE      (0x1000C000)

//#define MMPLL_CON0              (APMIXED_BASE + 0x240)
//#define MMPLL_PWR_CON0          (APMIXED_BASE + 0x24C)

#define TVDPLL_CON0             (APMIXED_BASE + 0x270)
#define TVDPLL_PWR_CON0         (APMIXED_BASE + 0x27C)


#define APLL1_CON0              (APMIXED_BASE + 0x2A0)
#define APLL1_PWR_CON0          (APMIXED_BASE + 0x2B0)

#define APLL2_CON0              (APMIXED_BASE + 0x2B4)
#define APLL2_PWR_CON0          (APMIXED_BASE + 0x2C4)


#define PLL_PWR_CON0_PWR_ON_BIT 0
#define PLL_PWR_CON0_ISO_EN_BIT 1
#define PLL_CON0_EN_BIT 0

void mt_pll_turn_off(void)
{
	unsigned int temp;

    /***********************
      * xPLL Frequency Disable
      ************************/
	//temp = DRV_Reg32(MMPLL_CON0);
	//DRV_WriteReg32(MMPLL_CON0, temp & ~(1<<PLL_CON0_EN_BIT));

	temp = DRV_Reg32(TVDPLL_CON0);
	DRV_WriteReg32(TVDPLL_CON0, temp & ~(1<<PLL_CON0_EN_BIT));

	temp = DRV_Reg32(APLL1_CON0);
	DRV_WriteReg32(APLL1_CON0, temp & ~(1<<PLL_CON0_EN_BIT));

	temp = DRV_Reg32(APLL2_CON0);
	DRV_WriteReg32(APLL2_CON0, temp & ~(1<<PLL_CON0_EN_BIT));

    /******************
    * xPLL PWR ISO Enable
    *******************/
	//temp = DRV_Reg32(MMPLL_PWR_CON0);
	//DRV_WriteReg32(MMPLL_PWR_CON0, temp | (1<<PLL_PWR_CON0_ISO_EN_BIT));


	temp = DRV_Reg32(TVDPLL_PWR_CON0);
	DRV_WriteReg32(TVDPLL_PWR_CON0, temp | (1<<PLL_PWR_CON0_ISO_EN_BIT));

	temp = DRV_Reg32(APLL1_PWR_CON0);
	DRV_WriteReg32(APLL1_PWR_CON0, temp | (1<<PLL_PWR_CON0_ISO_EN_BIT));

	temp = DRV_Reg32(APLL2_PWR_CON0);
	DRV_WriteReg32(APLL2_PWR_CON0, temp | (1<<PLL_PWR_CON0_ISO_EN_BIT));

    /*************
    * xPLL PWR OFF
    **************/
	//temp = DRV_Reg32(MMPLL_PWR_CON0);
	//DRV_WriteReg32(MMPLL_PWR_CON0, temp & ~(1<<PLL_PWR_CON0_PWR_ON_BIT));


	temp = DRV_Reg32(TVDPLL_PWR_CON0);
	DRV_WriteReg32(TVDPLL_PWR_CON0, temp & ~(1<<PLL_PWR_CON0_PWR_ON_BIT));

	temp = DRV_Reg32(APLL1_PWR_CON0);
	DRV_WriteReg32(APLL1_PWR_CON0, temp & ~(1<<PLL_PWR_CON0_PWR_ON_BIT));

	temp = DRV_Reg32(APLL2_PWR_CON0);
	DRV_WriteReg32(APLL2_PWR_CON0, temp & ~(1<<PLL_PWR_CON0_PWR_ON_BIT));

}