primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. //#include<linux/timer.h>
  44. #define DDP_LK_BOOT
  45. #ifndef HZ
  46. #define HZ 100
  47. #endif
  48. #ifdef DDP_LK_BOOT
  49. typedef void * cmdqRecHandle;
  50. #endif
  51. #define ALIGN_TO(x, n) \
  52. (((x) + ((n) - 1)) & ~((n) - 1))
  53. int primary_display_use_cmdq = CMDQ_DISABLE;
  54. int primary_display_use_m4u = 1;
  55. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  56. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  57. static UINT32 disp_fb_pages = 3; ///double buffer
  58. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  59. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  60. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  61. extern int DISP_IsLcmFound(void);
  62. extern void disp_path_clock_on(char *str);
  63. typedef struct _disp_dfo_item {
  64. char name[32];
  65. int value;
  66. } disp_dfo_item_t;
  67. static disp_dfo_item_t disp_dfo_setting[] = {
  68. {"LCM_FAKE_WIDTH", 0},
  69. {"LCM_FAKE_HEIGHT", 0},
  70. {"DISP_DEBUG_SWITCH", 0}
  71. };
  72. typedef struct {
  73. int state;
  74. int need_trigger_overlay;
  75. DISP_PRIMARY_PATH_MODE mode;
  76. unsigned int last_vsync_tick;
  77. #ifndef DDP_LK_BOOT
  78. struct mutex lock;
  79. #endif
  80. disp_lcm_handle * plcm;
  81. cmdqRecHandle cmdq_handle_config;
  82. cmdqRecHandle cmdq_handle_trigger;
  83. disp_path_handle dpmgr_handle;
  84. disp_path_handle ovl2mem_path_handle;
  85. } display_primary_path_context;
  86. #define pgc _get_context()
  87. static display_primary_path_context* _get_context(void)
  88. {
  89. static int is_context_inited = 0;
  90. static display_primary_path_context g_context;
  91. if (!is_context_inited) {
  92. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  93. is_context_inited = 1;
  94. }
  95. return &g_context;
  96. }
  97. static void _primary_path_lock(void)
  98. {
  99. #ifndef DDP_LK_BOOT
  100. disp_sw_mutex_lock(&(pgc->lock));
  101. #endif
  102. }
  103. static void _primary_path_unlock(void)
  104. {
  105. #ifndef DDP_LK_BOOT
  106. disp_sw_mutex_unlock(&(pgc->lock));
  107. #endif
  108. }
  109. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  110. {
  111. if (plcm == NULL) {
  112. DISPERR("plcm is null\n");
  113. return DISP_MODULE_UNKNOWN;
  114. }
  115. if (plcm->params->type == LCM_TYPE_DSI) {
  116. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  117. return DISP_MODULE_DSI0;
  118. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  119. return DISP_MODULE_DSI1;
  120. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  121. return DISP_MODULE_DSIDUAL;
  122. } else {
  123. return DISP_MODULE_DSI0;
  124. }
  125. } else if (plcm->params->type == LCM_TYPE_DPI) {
  126. return DISP_MODULE_DPI;
  127. } else {
  128. DISPERR("can't find primary path dst module\n");
  129. return DISP_MODULE_UNKNOWN;
  130. }
  131. }
  132. static int _build_path_direct_link(void)
  133. {
  134. int ret = 0;
  135. DISP_MODULE_ENUM dst_module = 0;
  136. DISPFUNC();
  137. pgc->mode = DIRECT_LINK_MODE;
  138. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  139. if (pgc->dpmgr_handle) {
  140. DISPCHECK("dpmgr create path SUCCESS(0x%8p)\n", pgc->dpmgr_handle);
  141. } else {
  142. DISPCHECK("dpmgr create path FAIL\n");
  143. return -1;
  144. }
  145. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  146. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  147. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  148. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  149. return ret;
  150. }
  151. static int _build_path_decouple(void)
  152. {
  153. return 0;
  154. }
  155. static int _build_path_single_layer(void)
  156. {
  157. return 0;
  158. }
  159. static int _build_path_debug_rdma1_dsi0(void)
  160. {
  161. int ret = 0;
  162. DISP_MODULE_ENUM dst_module = 0;
  163. DISPFUNC();
  164. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  165. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  166. if (pgc->dpmgr_handle) {
  167. DISPCHECK("dpmgr create path SUCCESS(0x%8p)\n", pgc->dpmgr_handle);
  168. } else {
  169. DISPCHECK("dpmgr create path FAIL\n");
  170. return -1;
  171. }
  172. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  173. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  174. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  175. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  176. return ret;
  177. }
  178. static void _build_cmdq_trigger_loop(void)
  179. {
  180. #ifndef DDP_LK_BOOT
  181. int ret = 0;
  182. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  183. DISPMSG("primary path trigger thread cmd handle=0x%8p\n", pgc->cmdq_handle_trigger);
  184. cmdqRecReset(pgc->cmdq_handle_trigger);
  185. if (primary_display_is_video_mode()) {
  186. // wait and clear stream_done
  187. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  188. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  189. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  190. } else {
  191. // only in DSI Command mode we need to wait these
  192. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  193. // no internal te on fpga now.
  194. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  195. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  196. // block config threads, we'll about to update frame
  197. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  198. // only in DSI command mode we need to enable mutex explicitly
  199. // WRITE mutex enable
  200. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  201. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  202. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  203. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  204. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  205. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  206. // polling DSI idle
  207. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  208. // polling wdma frame done
  209. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  210. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  211. /*********************/
  212. /***build cmdq finished***/
  213. /*********************/
  214. // TODO:
  215. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  216. // RUN forever!!!!
  217. BUG_ON(ret < 0);
  218. }
  219. #endif
  220. }
  221. static void _start_cmdq_trigger_loop(void)
  222. {
  223. #ifndef DDP_LK_BOOT
  224. int ret = 0;
  225. // this should be called only once because trigger loop will nevet stop
  226. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  227. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  228. #endif
  229. }
  230. static void _set_cmdq_config_handle_dirty(void)
  231. {
  232. #ifndef DDP_LK_BOOT
  233. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  234. cmdqRecFlush(pgc->cmdq_handle_config);
  235. #endif
  236. }
  237. static void _reset_cmdq_config_handle(void)
  238. {
  239. #ifndef DDP_LK_BOOT
  240. cmdqRecReset(pgc->cmdq_handle_config);
  241. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  242. #endif
  243. }
  244. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  245. {
  246. if (src && dst) {
  247. dst->inputFormat = src->fmt;
  248. dst->address = src->addr;
  249. dst->width = src->src_w;
  250. dst->height = src->src_h;
  251. dst->pitch = src->src_pitch;
  252. return 0;
  253. } else {
  254. DISPERR("src(0x%8p) or dst(0x%8p) is null\n", src, dst);
  255. return -1;
  256. }
  257. }
  258. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  259. {
  260. if (src && dst) {
  261. dst->layer = src->layer;
  262. dst->layer_en = src->layer_en;
  263. dst->fmt = src->fmt;
  264. dst->addr = src->addr;
  265. dst->vaddr = src->vaddr;
  266. dst->src_x = src->src_x;
  267. dst->src_y = src->src_y;
  268. dst->src_w = src->src_w;
  269. dst->src_h = src->src_h;
  270. dst->src_pitch = src->src_pitch;
  271. dst->dst_x = src->dst_x;
  272. dst->dst_y = src->dst_y;
  273. dst->dst_w = src->dst_w;
  274. dst->dst_h = src->dst_h;
  275. dst->keyEn = src->keyEn;
  276. dst->key = src->key;
  277. dst->aen = src->aen;
  278. dst->alpha = src->alpha;
  279. dst->isDirty = src->isDirty;
  280. dst->buff_idx = src->buff_idx;
  281. dst->identity = src->identity;
  282. dst->connected_type = src->connected_type;
  283. dst->security = src->security;
  284. return 0;
  285. } else {
  286. DISPERR("src(0x%8p) or dst(0x%8p) is null\n", src, dst);
  287. return -1;
  288. }
  289. }
  290. extern void video_printf (const char *fmt, ...);
  291. void _dump_lcm_info_by_video_printf(void)
  292. {
  293. LCM_DRIVER *l = NULL;
  294. LCM_PARAMS *p = NULL;
  295. disp_lcm_handle *plcm = pgc->plcm;
  296. if (plcm == NULL) {
  297. DISPERR("plcm is null\n");
  298. return;
  299. }
  300. l = plcm->drv;
  301. p = plcm->params;
  302. if (l && p) {
  303. video_printf("[LCM], name: %s\n", l->name);
  304. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  305. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  306. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  307. switch (p->lcm_if) {
  308. case LCM_INTERFACE_DSI0:
  309. video_printf("[LCM] interface: DSI0\n");
  310. break;
  311. case LCM_INTERFACE_DSI1:
  312. video_printf("[LCM] interface: DSI1\n");
  313. break;
  314. case LCM_INTERFACE_DPI0:
  315. video_printf("[LCM] interface: DPI0\n");
  316. break;
  317. case LCM_INTERFACE_DPI1:
  318. video_printf("[LCM] interface: DPI1\n");
  319. break;
  320. case LCM_INTERFACE_DBI0:
  321. video_printf("[LCM] interface: DBI0\n");
  322. break;
  323. default:
  324. video_printf("[LCM] interface: unknown\n");
  325. break;
  326. }
  327. switch (p->type) {
  328. case LCM_TYPE_DBI:
  329. video_printf("[LCM] Type: DBI\n");
  330. break;
  331. case LCM_TYPE_DSI:
  332. video_printf("[LCM] Type: DSI\n");
  333. break;
  334. case LCM_TYPE_DPI:
  335. video_printf("[LCM] Type: DPI\n");
  336. break;
  337. default:
  338. video_printf("[LCM] TYPE: unknown\n");
  339. break;
  340. }
  341. if (p->type == LCM_TYPE_DSI) {
  342. switch (p->dsi.mode) {
  343. case CMD_MODE:
  344. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  345. break;
  346. case SYNC_PULSE_VDO_MODE:
  347. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  348. break;
  349. case SYNC_EVENT_VDO_MODE:
  350. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  351. break;
  352. case BURST_VDO_MODE:
  353. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  354. break;
  355. default:
  356. video_printf("[LCM] DSI Mode: Unknown\n");
  357. break;
  358. }
  359. }
  360. if (p->type == LCM_TYPE_DSI) {
  361. video_printf("[LCM] LANE_NUM: %d, data_format:(%d,%d,%d,%d)\n",
  362. p->dsi.LANE_NUM, p->dsi.data_format.color_order, p->dsi.data_format.format,
  363. p->dsi.data_format.padding, p->dsi.data_format.trans_seq);
  364. #ifdef MY_TODO
  365. #error
  366. #endif
  367. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",
  368. p->dsi.vertical_sync_active, p->dsi.vertical_backporch, p->dsi.vertical_frontporch,
  369. p->dsi.vertical_active_line, p->dsi.horizontal_sync_active, p->dsi.horizontal_backporch,
  370. p->dsi.horizontal_frontporch, p->dsi.horizontal_blanking_pixel);
  371. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",
  372. p->dsi.pll_select, p->dsi.pll_div1, p->dsi.pll_div2, p->dsi.fbk_div, p->dsi.fbk_sel, p->dsi.rg_bir);
  373. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n",
  374. p->dsi.rg_bic, p->dsi.rg_bp, p->dsi.PLL_CLOCK, p->dsi.dsi_clock, p->dsi.ssc_range, p->dsi.ssc_disable, p->dsi.compatibility_for_nvk, p->dsi.cont_clock);
  375. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n",
  376. p->dsi.lcm_ext_te_enable, p->dsi.noncont_clock, p->dsi.noncont_clock_period);
  377. }
  378. }
  379. return;
  380. }
  381. unsigned int mt_disp_parse_dfo_setting(void)
  382. {
  383. unsigned int i, j=0 ;
  384. char tmp[11];
  385. char *buffer = NULL;
  386. char *ptr = NULL;
  387. buffer = (char *)get_env("DFO");
  388. DISPMSG("env buffer = %s\n", buffer);
  389. if (buffer != NULL) {
  390. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  391. j = 0;
  392. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  393. ptr = strstr(buffer, disp_dfo_setting[i].name);
  394. if (ptr == NULL) continue;
  395. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  396. do {} while ((*ptr++) != ',');
  397. do {
  398. tmp[j++] = *ptr++;
  399. } while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  400. disp_dfo_setting[i].value = atoi((const char*)tmp);
  401. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  402. }
  403. } else {
  404. DISPMSG("env buffer = NULL\n");
  405. }
  406. return 0;
  407. }
  408. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  409. {
  410. char *disp_name;
  411. int disp_value;
  412. unsigned int i = 0;
  413. if (string == NULL)
  414. return -1;
  415. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  416. disp_name = disp_dfo_setting[i].name;
  417. disp_value = disp_dfo_setting[i].value;
  418. if (!strcmp(disp_name, string)) {
  419. *value = disp_value;
  420. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  421. return 0;
  422. }
  423. }
  424. return 0;
  425. }
  426. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  427. int primary_display_is_lcm_connected(void)
  428. {
  429. return pgc->plcm->is_connected;
  430. }
  431. const char* primary_display_get_lcm_name(void)
  432. {
  433. return disp_lcm_get_name(pgc->plcm);
  434. }
  435. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  436. {
  437. if (pgc->plcm) {
  438. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  439. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  440. // otherwise we will have a panic in lk(root cause unknown).
  441. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  442. DISPERR("Invalid resolution: %dx%d\n", width, height);
  443. return -1;
  444. }
  445. if (primary_display_is_video_mode()) {
  446. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  447. return -1;
  448. }
  449. pgc->plcm->params->width = width;
  450. pgc->plcm->params->height = height;
  451. return 0;
  452. } else {
  453. return -1;
  454. }
  455. }
  456. int primary_display_init(char *lcm_name)
  457. {
  458. DISPFUNC();
  459. DISP_STATUS ret = DISP_STATUS_OK;
  460. LCM_PARAMS *lcm_param = NULL;
  461. dpmgr_init();
  462. #ifndef DDP_LK_BOOT
  463. mutex_init(&(pgc->lock));
  464. #endif
  465. _primary_path_lock();
  466. if (pgc->plcm == NULL)
  467. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  468. if (pgc->plcm == NULL) {
  469. DISPCHECK("disp_lcm_probe returns null\n");
  470. ret = DISP_STATUS_ERROR;
  471. goto done;
  472. } else {
  473. DISPCHECK("disp_lcm_probe SUCCESS\n");
  474. }
  475. lcm_param = disp_lcm_get_params(pgc->plcm);
  476. if (lcm_param == NULL) {
  477. DISPERR("get lcm params FAILED\n");
  478. ret = DISP_STATUS_ERROR;
  479. goto done;
  480. }
  481. if (primary_display_mode == DIRECT_LINK_MODE) {
  482. _build_path_direct_link();
  483. DISPCHECK("primary display is DIRECT LINK MODE\n");
  484. } else if (primary_display_mode == DECOUPLE_MODE) {
  485. _build_path_decouple();
  486. DISPCHECK("primary display is DECOUPLE MODE\n");
  487. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  488. _build_path_single_layer();
  489. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  490. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  491. _build_path_debug_rdma1_dsi0();
  492. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  493. } else {
  494. DISPCHECK("primary display mode is WRONG\n");
  495. }
  496. _build_cmdq_trigger_loop();
  497. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  498. _start_cmdq_trigger_loop();
  499. DISPCHECK("primary display START cmdq trigger loop finished\n");
  500. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  501. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  502. disp_ddp_path_config data_config;
  503. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  504. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  505. data_config.dst_w = disp_lcm_width(pgc->plcm);
  506. data_config.dst_h = disp_lcm_height(pgc->plcm);
  507. if (lcm_param->type == LCM_TYPE_DSI) {
  508. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  509. data_config.lcm_bpp = 24;
  510. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  511. data_config.lcm_bpp = 16;
  512. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  513. data_config.lcm_bpp = 18;
  514. } else if (lcm_param->type == LCM_TYPE_DPI) {
  515. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  516. data_config.lcm_bpp = 24;
  517. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  518. data_config.lcm_bpp = 16;
  519. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  520. data_config.lcm_bpp = 18;
  521. }
  522. data_config.dst_dirty = 1;
  523. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  524. ret = disp_lcm_init(pgc->plcm);
  525. DISPCHECK("pgc->plcm->is_connected = %d \n",pgc->plcm->is_connected);
  526. if (primary_display_is_video_mode()) {
  527. if (lcm_param->dsi.lfr_enable == 1) {
  528. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  529. } else {
  530. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  531. }
  532. } else {
  533. }
  534. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  535. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  536. pgc->state = 1;
  537. done:
  538. _primary_path_unlock();
  539. return ret;
  540. }
  541. // register rdma done event
  542. int primary_display_wait_for_idle(void)
  543. {
  544. DISP_STATUS ret = DISP_STATUS_OK;
  545. DISPFUNC();
  546. _primary_path_lock();
  547. _primary_path_unlock();
  548. return ret;
  549. }
  550. int primary_display_wait_for_dump(void)
  551. {
  552. return 0;
  553. }
  554. static long int get_current_time_us(void)
  555. {
  556. return get_timer(0);
  557. }
  558. int priamry_display_wait_for_vsync(void)
  559. {
  560. int ret = 0;
  561. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  562. if (ret == -2) {
  563. DISPCHECK("vsync for primary display path not enabled yet\n");
  564. return -1;
  565. }
  566. // pgc->last_vsync_tick = get_current_time_us();
  567. pgc->last_vsync_tick = 0;
  568. return 0;
  569. }
  570. extern int disp_path_clock_off(char* name );
  571. int primary_display_suspend(void)
  572. {
  573. DISP_STATUS ret = DISP_STATUS_OK;
  574. DISPFUNC();
  575. _primary_path_lock();
  576. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  577. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  578. #ifndef DDP_LK_BOOT
  579. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  580. #endif
  581. disp_path_clock_off("Primary Display Path");
  582. pgc->state = 0;
  583. _primary_path_unlock();
  584. return ret;
  585. }
  586. int primary_display_resume(void)
  587. {
  588. DISP_STATUS ret = DISP_STATUS_OK;
  589. DISPFUNC();
  590. _primary_path_lock();
  591. disp_path_clock_on("Primary Display Path");
  592. pgc->state = 1;
  593. _primary_path_unlock();
  594. return ret;
  595. }
  596. int primary_display_is_alive(void)
  597. {
  598. unsigned int temp = 0;
  599. DISPFUNC();
  600. _primary_path_lock();
  601. temp = pgc->state;
  602. _primary_path_unlock();
  603. return temp;
  604. }
  605. int primary_display_is_sleepd(void)
  606. {
  607. unsigned int temp = 0;
  608. DISPFUNC();
  609. _primary_path_lock();
  610. temp = !pgc->state;
  611. _primary_path_unlock();
  612. return temp;
  613. }
  614. int primary_display_get_width(void)
  615. {
  616. if (pgc->plcm == NULL) {
  617. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  618. DISPMSG("lcm handle is null, after probe:0x%8p\n",pgc->plcm);
  619. if (pgc->plcm == NULL)
  620. return 0;
  621. }
  622. if (pgc->plcm->params) {
  623. return pgc->plcm->params->width;
  624. } else {
  625. DISPERR("lcm_params is null!\n");
  626. return 0;
  627. }
  628. }
  629. int primary_display_get_height(void)
  630. {
  631. if (pgc->plcm == NULL) {
  632. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  633. DISPMSG("lcm handle is null, after probe:0x%8p\n",pgc->plcm);
  634. if (pgc->plcm == NULL)
  635. return 0;
  636. }
  637. if (pgc->plcm->params) {
  638. return pgc->plcm->params->height;
  639. } else {
  640. DISPERR("lcm_params is null!\n");
  641. return 0;
  642. }
  643. }
  644. int primary_display_get_bpp(void)
  645. {
  646. return 32;
  647. }
  648. int primary_display_get_info(void *dispif_info)
  649. {
  650. #if 0
  651. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  652. switch (pgc->lcm_param->type) {
  653. case LCM_TYPE_DBI: {
  654. dispif_info->displayType = DISPIF_TYPE_DBI;
  655. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  656. dispif_info->isHwVsyncAvailable = 1;
  657. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  658. break;
  659. }
  660. case LCM_TYPE_DPI: {
  661. dispif_info->displayType = DISPIF_TYPE_DPI0;
  662. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  663. dispif_info->isHwVsyncAvailable = 1;
  664. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  665. break;
  666. }
  667. case LCM_TYPE_DSI: {
  668. dispif_info->displayType = DISPIF_TYPE_DSI0;
  669. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  670. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  671. dispif_info->isHwVsyncAvailable = 1;
  672. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  673. } else {
  674. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  675. dispif_info->isHwVsyncAvailable = 1;
  676. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  677. }
  678. break;
  679. }
  680. default:
  681. break;
  682. }
  683. #ifdef MY_TODO
  684. #error
  685. if (disp_if_drv->get_panel_color_format()) {
  686. switch (disp_if_drv->get_panel_color_format()) {
  687. case PANEL_COLOR_FORMAT_RGB565:
  688. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  689. case PANEL_COLOR_FORMAT_RGB666:
  690. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  691. case PANEL_COLOR_FORMAT_RGB888:
  692. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  693. default:
  694. break;
  695. }
  696. }
  697. #endif
  698. dispif_info->displayWidth = primary_display_get_width();
  699. dispif_info->displayHeight = primary_display_get_height();
  700. #ifdef MY_TODO
  701. #error
  702. dispif_info->vsyncFPS = lcd_fps;
  703. #endif
  704. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  705. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  706. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  707. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  708. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  709. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  710. } else {
  711. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  712. }
  713. dispif_info->isConnected = 1;
  714. #ifdef MY_TODO
  715. #error
  716. {
  717. LCM_PARAMS lcm_params_temp;
  718. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  719. if (lcm_drv) {
  720. lcm_drv->get_params(&lcm_params_temp);
  721. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  722. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  723. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  724. } else {
  725. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  726. }
  727. }
  728. #endif
  729. #endif
  730. return 0;
  731. }
  732. int primary_display_get_pages(void)
  733. {
  734. return 3;
  735. }
  736. int primary_display_config_output()
  737. {
  738. return 0;
  739. }
  740. int primary_display_diagnose(void)
  741. {
  742. int ret = 0;
  743. dpmgr_check_status(pgc->dpmgr_handle);
  744. return ret;
  745. }
  746. int primary_display_trigger(int blocking)
  747. {
  748. int ret = 0;
  749. DISPFUNC();
  750. int x=0, y=0;
  751. int width = 0, height =0;
  752. x = disp_lcm_x(pgc->plcm);
  753. y = disp_lcm_y(pgc->plcm);
  754. width = disp_lcm_width(pgc->plcm);
  755. height = disp_lcm_height(pgc->plcm);
  756. _primary_path_lock();
  757. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  758. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  759. if (primary_display_is_video_mode()) {
  760. _primary_path_unlock();
  761. return 0;
  762. }
  763. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  764. }
  765. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  766. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  767. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  768. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  769. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  770. }
  771. //_set_cmdq_config_handle_dirty();
  772. //_reset_cmdq_config_handle();
  773. //if(blocking)
  774. {
  775. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  776. }
  777. } else if (pgc->mode == DECOUPLE_MODE) {
  778. DISPCHECK("trigger mode: DECOUPLE\n");
  779. if (pgc->need_trigger_overlay) {
  780. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  781. if (blocking) {
  782. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  783. }
  784. } else {
  785. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  786. // this request of trigger should be called by AAL or ovl2mem done event
  787. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  788. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  789. }
  790. _set_cmdq_config_handle_dirty();
  791. _reset_cmdq_config_handle();
  792. if (blocking) {
  793. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  794. }
  795. }
  796. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  797. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  798. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  799. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  800. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  801. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  802. }
  803. if (blocking) {
  804. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  805. }
  806. } else {
  807. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  808. }
  809. _primary_path_unlock();
  810. //primary_display_diagnose();
  811. return ret;
  812. }
  813. int primary_display_config_input(disp_input_config* input)
  814. {
  815. int ret = 0;
  816. DISPFUNC();
  817. disp_ddp_path_config data_config;
  818. // all dirty should be cleared in dpmgr_path_get_last_config()
  819. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  820. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  821. data_config.dst_dirty = 0;
  822. data_config.ovl_dirty = 0;
  823. data_config.rdma_dirty = 0;
  824. data_config.wdma_dirty = 0;
  825. _primary_path_lock();
  826. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  827. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  828. if (primary_display_is_video_mode()) {
  829. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  830. }
  831. }
  832. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  833. data_config.ovl_dirty = 1;
  834. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  835. // this is used for decouple mode, to indicate whether we need to trigger ovl
  836. pgc->need_trigger_overlay = 1;
  837. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  838. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  839. data_config.rdma_dirty= 1;
  840. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  841. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  842. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  843. data_config.rdma_dirty= 1;
  844. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  845. // TODO: should use wait_event_timeout_or_idle
  846. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  847. }
  848. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  849. } else {
  850. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  851. }
  852. _primary_path_unlock();
  853. return ret;
  854. }
  855. int primary_display_is_video_mode(void)
  856. {
  857. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  858. return disp_lcm_is_video_mode(pgc->plcm);
  859. }
  860. int primary_display_get_vsync_interval(void)
  861. {
  862. int ret = 0;
  863. unsigned int time0 = 0;
  864. unsigned int time1 = 0;
  865. unsigned int lcd_time = 0;
  866. if (!primary_display_is_video_mode()) {
  867. DISPCHECK("LCM cmd mode lcm status %d!\n",DISP_IsLcmFound());
  868. if (!DISP_IsLcmFound()) {
  869. DISPCHECK("LCM NOT CONNECTED not cal fps!\n");
  870. goto fail;
  871. }
  872. }
  873. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,2000);
  874. if (ret <= 0)
  875. goto fail;
  876. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,2000);
  877. if (ret <= 0)
  878. goto fail;
  879. // because we are polling irq status, so the first event should be ignored
  880. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  881. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  882. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,2000);
  883. if (ret <= 0)
  884. goto fail;
  885. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  886. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,2000);
  887. if (ret > 0) {
  888. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  889. } else
  890. goto fail;
  891. lcd_time = (time1 - time0)/2;
  892. if (0 != lcd_time)
  893. return (100000000/lcd_time);
  894. else
  895. return (6000);
  896. fail:
  897. DISPERR("wait event fail\n");
  898. return 0;
  899. }
  900. int primary_display_setbacklight(unsigned int level)
  901. {
  902. DISPMSG("lk %s level=%d\n",__func__,level);
  903. int ret=0;
  904. if (pgc->dpmgr_handle == NULL) {
  905. DISPCHECK("lk set backlight early!\n");
  906. return 0;
  907. }
  908. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  909. DISPCHECK("primary display path is busy\n");
  910. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  911. DISPCHECK("wait frame done ret:%d\n", ret);
  912. }
  913. disp_lcm_set_backlight(pgc->plcm,level);
  914. return 0;
  915. }
  916. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  917. /***********************/
  918. /*****Legacy DISP API*****/
  919. /***********************/
  920. UINT32 DISP_GetScreenWidth(void)
  921. {
  922. return primary_display_get_width();
  923. }
  924. UINT32 DISP_GetScreenHeight(void)
  925. {
  926. return primary_display_get_height();
  927. }
  928. UINT32 DISP_GetActiveHeight(void)
  929. {
  930. if (pgc->plcm == NULL) {
  931. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  932. DISPERR("lcm handle is null, after probe:0x%8p\n",pgc->plcm);
  933. if (pgc->plcm == NULL)return 0;
  934. }
  935. if (pgc->plcm->params) {
  936. return pgc->plcm->params->physical_height;
  937. } else {
  938. DISPERR("lcm_params is null!\n");
  939. return 0;
  940. }
  941. }
  942. UINT32 DISP_GetActiveWidth(void)
  943. {
  944. if (pgc->plcm == NULL) {
  945. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  946. DISPERR("lcm handle is null, after probe:0x%8p\n",pgc->plcm);
  947. if (pgc->plcm == NULL)return 0;
  948. }
  949. if (pgc->plcm->params) {
  950. return pgc->plcm->params->physical_width;
  951. } else {
  952. DISPERR("lcm_params is null!\n");
  953. return 0;
  954. }
  955. }
  956. int primary_display_capture_framebuffer(unsigned int *pbuf)
  957. {
  958. return 0;
  959. }
  960. UINT32 DISP_GetPanelBPP(void)
  961. {
  962. #if 0
  963. PANEL_COLOR_FORMAT fmt;
  964. disp_drv_init_context();
  965. if (disp_if_drv->get_panel_color_format == NULL) {
  966. return DISP_STATUS_NOT_IMPLEMENTED;
  967. }
  968. fmt = disp_if_drv->get_panel_color_format();
  969. switch (fmt) {
  970. case PANEL_COLOR_FORMAT_RGB332:
  971. return 8;
  972. case PANEL_COLOR_FORMAT_RGB444:
  973. return 12;
  974. case PANEL_COLOR_FORMAT_RGB565:
  975. return 16;
  976. case PANEL_COLOR_FORMAT_RGB666:
  977. return 18;
  978. case PANEL_COLOR_FORMAT_RGB888:
  979. return 24;
  980. default:
  981. return 0;
  982. }
  983. #else
  984. return 0;
  985. #endif
  986. }
  987. UINT32 DISP_GetScreenBpp(void)
  988. {
  989. return disp_fb_bpp;
  990. }
  991. UINT32 DISP_GetPages(void)
  992. {
  993. return disp_fb_pages; // Double Buffers
  994. }
  995. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  996. #define DAL_BPP (2)
  997. #define DAL_WIDTH (DISP_GetScreenWidth())
  998. #define DAL_HEIGHT (DISP_GetScreenHeight())
  999. UINT32 DAL_GetLayerSize(void)
  1000. {
  1001. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1002. }
  1003. UINT32 DISP_GetFBRamSize(void)
  1004. {
  1005. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * DISP_GetScreenHeight() * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1006. }
  1007. unsigned int DISP_GetVRamSize(void)
  1008. {
  1009. static UINT32 vramSize = 0;
  1010. unsigned int fb_ram_size =0;
  1011. //FB RAM(n blocks)+(Assert layer size)
  1012. if (0 == vramSize) {
  1013. vramSize = DISP_GetFBRamSize();
  1014. DISPMSG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1015. fb_ram_size = vramSize;
  1016. vramSize += DAL_GetLayerSize();
  1017. DISPMSG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1018. #if 0
  1019. if (g_is_64bit_kernel) {
  1020. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1021. } else {
  1022. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1023. }
  1024. #else
  1025. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1026. #endif
  1027. DISPMSG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1028. }
  1029. return vramSize;
  1030. }