sec_efuse.c 4.1 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <platform/mt_typedefs.h>
  32. #include <platform/mtk_wdt.h>
  33. #include <platform/mt_pmic.h>
  34. #include <platform/mt_gpio.h>
  35. #if defined (PMIC_CHIP_MT6353)
  36. #define EFUSE_VEFUSE_EN_DELAY 10
  37. #define EFUSE_VEFUSE_DIS_DELAY 80
  38. #else
  39. #define EFUSE_VEFUSE_EN_DELAY 10
  40. #define EFUSE_VEFUSE_DIS_DELAY 10
  41. #endif
  42. /**************************************************************
  43. * WDT
  44. **************************************************************/
  45. void efuse_wdt_restart(void)
  46. {
  47. mtk_wdt_restart();
  48. }
  49. /****************************************************
  50. * Fsource
  51. * return 0 : success
  52. ****************************************************/
  53. U32 efuse_fsource_set(void)
  54. {
  55. U32 ret_val = 0;
  56. #if defined (PMIC_CHIP_MT6353)
  57. mt_set_gpio_mode(GPIO_VEFUSE_LDO_EN, GPIO_MODE_GPIO);
  58. mt_set_gpio_dir(GPIO_VEFUSE_LDO_EN, GPIO_DIR_OUT);
  59. mt_set_gpio_out(GPIO_VEFUSE_LDO_EN, GPIO_OUT_ONE);
  60. #else
  61. ret_val |= pmic_config_interface((kal_uint32)(MT6351_PMIC_RG_EFUSE_MODE_1_ADDR),
  62. (kal_uint32)(0x1),
  63. (kal_uint32)(MT6351_PMIC_RG_EFUSE_MODE_1_MASK),
  64. (kal_uint32)(MT6351_PMIC_RG_EFUSE_MODE_1_SHIFT)
  65. );
  66. ret_val |= pmic_config_interface((kal_uint32)(MT6351_PMIC_RG_VEFUSE_VOSEL_ADDR),
  67. (kal_uint32)(0x3),
  68. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_VOSEL_MASK),
  69. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_VOSEL_SHIFT)
  70. );
  71. ret_val |= pmic_config_interface((kal_uint32)(MT6351_PMIC_RG_VEFUSE_CAL_ADDR),
  72. (kal_uint32)(0xD),
  73. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_CAL_MASK),
  74. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_CAL_SHIFT)
  75. );
  76. /* Fsource enable */
  77. ret_val |= pmic_config_interface((kal_uint32)(MT6351_PMIC_RG_VEFUSE_EN_ADDR),
  78. (kal_uint32)(0x1),
  79. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_EN_MASK),
  80. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_EN_SHIFT)
  81. );
  82. #endif
  83. mdelay(EFUSE_VEFUSE_EN_DELAY);
  84. return ret_val;
  85. }
  86. U32 efuse_fsource_close(void)
  87. {
  88. U32 ret_val = 0;
  89. #if defined (PMIC_CHIP_MT6353)
  90. mt_set_gpio_out(GPIO_VEFUSE_LDO_EN, GPIO_OUT_ZERO);
  91. #else
  92. ret_val |= pmic_config_interface((kal_uint32)(MT6351_PMIC_RG_VEFUSE_EN_ADDR),
  93. (kal_uint32)(0x0),
  94. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_EN_MASK),
  95. (kal_uint32)(MT6351_PMIC_RG_VEFUSE_EN_SHIFT)
  96. );
  97. #endif
  98. mdelay(EFUSE_VEFUSE_DIS_DELAY);
  99. return ret_val;
  100. }