mt_battery.c 35 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <target/board.h>
  32. #ifdef MTK_KERNEL_POWER_OFF_CHARGING
  33. #define CFG_POWER_CHARGING
  34. #endif
  35. #ifdef CFG_POWER_CHARGING
  36. #include <platform/mt_typedefs.h>
  37. #include <platform/mt_reg_base.h>
  38. #include <platform/mt_pmic.h>
  39. #include <platform/upmu_hw.h>
  40. #include <platform/upmu_common.h>
  41. #include <platform/boot_mode.h>
  42. #include <platform/mt_gpt.h>
  43. #include <platform/mt_rtc.h>
  44. #include <platform/mt_rtc_hw.h>
  45. #include <platform/mt_pmic_wrap_init.h>
  46. #include <platform/mt_pumpexpress.h>
  47. //#include <platform/mt_disp_drv.h>
  48. //#include <platform/mtk_wdt.h>
  49. //#include <platform/mtk_key.h>
  50. //#include <platform/mt_logo.h>
  51. #include <platform/mt_leds.h>
  52. #include <printf.h>
  53. #include <sys/types.h>
  54. #include <target/cust_battery.h>
  55. #if defined(MTK_BQ24261_SUPPORT)
  56. #include <platform/bq24261.h>
  57. #endif
  58. #if defined(MTK_BQ24296_SUPPORT)
  59. #include <platform/bq24296.h>
  60. #endif
  61. #if defined(MTK_NCP1854_SUPPORT)
  62. #include <platform/ncp1854.h>
  63. #endif
  64. #if defined(MTK_BQ25896_SUPPORT)
  65. #include <platform/bq25896.h>
  66. #endif
  67. #ifdef MTK_CHARGER_INTERFACE
  68. #include <platform/mtk_charger_intf.h>
  69. static struct mtk_charger_info *primary_mchr;
  70. #endif
  71. #define DLPT_FEATURE_SUPPORT
  72. #define V_CHARGER_MAX 6500 // 6.5 V
  73. #undef printf
  74. /*****************************************************************************
  75. * Type define
  76. ****************************************************************************/
  77. #if defined(CUST_BATTERY_LOWVOL_THRESOLD)
  78. #define BATTERY_LOWVOL_THRESOLD CUST_BATTERY_LOWVOL_THRESOLD
  79. #else
  80. #define BATTERY_LOWVOL_THRESOLD 3450
  81. #endif
  82. /*****************************************************************************
  83. * Global Variable
  84. ****************************************************************************/
  85. bool g_boot_reason_change = false;
  86. #if defined(STD_AC_LARGE_CURRENT)
  87. int g_std_ac_large_current_en=1;
  88. #else
  89. int g_std_ac_large_current_en=0;
  90. #endif
  91. /*****************************************************************************
  92. * Externl Variable
  93. ****************************************************************************/
  94. extern bool g_boot_menu;
  95. extern void mtk_wdt_restart(void);
  96. int get_bat_volt(int times)
  97. {
  98. int bat_vol;
  99. #if defined(SWCHR_POWER_PATH)
  100. bat_vol = get_i_sense_volt(times);
  101. #else
  102. bat_vol = get_bat_sense_volt(times);
  103. #endif
  104. return bat_vol;
  105. }
  106. void kick_charger_wdt(void)
  107. {
  108. /*
  109. //mt6325_upmu_set_rg_chrwdt_td(0x0); // CHRWDT_TD, 4s
  110. mt6325_upmu_set_rg_chrwdt_td(0x3); // CHRWDT_TD, 32s for keep charging for lk to kernel
  111. mt6325_upmu_set_rg_chrwdt_wr(1); // CHRWDT_WR
  112. mt6325_upmu_set_rg_chrwdt_int_en(1); // CHRWDT_INT_EN
  113. mt6325_upmu_set_rg_chrwdt_en(1); // CHRWDT_EN
  114. mt6325_upmu_set_rg_chrwdt_flag_wr(1); // CHRWDT_WR
  115. */
  116. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_TD,3); // CHRWDT_TD, 32s for keep charging for lk to kernel
  117. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_WR,1); // CHRWDT_WR
  118. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_INT_EN,1); // CHRWDT_INT_EN
  119. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_EN,1); // CHRWDT_EN
  120. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_FLAG_WR,1);// CHRWDT_WR
  121. }
  122. #if defined(MTK_BATLOWV_NO_PANEL_ON_EARLY)
  123. kal_bool is_low_battery(kal_int32 val)
  124. {
  125. static UINT8 g_bat_low = 0xFF;
  126. //low battery only justice once in lk
  127. if (0xFF != g_bat_low)
  128. return g_bat_low;
  129. else
  130. g_bat_low = FALSE;
  131. #if defined(SWCHR_POWER_PATH)
  132. if (0 == val)
  133. val = get_i_sense_volt(1);
  134. #else
  135. if (0 == val)
  136. val = get_bat_sense_volt(1);
  137. #endif
  138. if (val < BATTERY_LOWVOL_THRESOLD) {
  139. dprintf(INFO, "%s, TRUE\n", __FUNCTION__);
  140. g_bat_low = 0x1;
  141. }
  142. if (FALSE == g_bat_low)
  143. dprintf(INFO, "%s, FALSE\n", __FUNCTION__);
  144. return g_bat_low;
  145. }
  146. #endif
  147. void pchr_turn_on_charging(kal_bool bEnable)
  148. {
  149. #ifdef MTK_CHARGER_INTERFACE
  150. int ret = 0;
  151. bool enable = bEnable ? true : false;
  152. #endif
  153. pmic_set_register_value(MT6351_PMIC_RG_USBDL_RST,1);//force leave USBDL mode
  154. //mt6325_upmu_set_rg_usbdl_rst(1); //force leave USBDL mode
  155. pmic_set_register_value(MT6351_PMIC_RG_BC11_RST,1);//BC11_RST
  156. kick_charger_wdt();
  157. pmic_set_register_value(MT6351_PMIC_RG_NORM_CS_VTH,0xC); // CS_VTH, 450mA
  158. //mt6325_upmu_set_rg_cs_vth(0xC); // CS_VTH, 450mA
  159. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_EN,bEnable);
  160. //mt6325_upmu_set_rg_csdac_en(1); // CSDAC_EN
  161. pmic_set_register_value(MT6351_PMIC_RG_NORM_CHR_EN,bEnable);
  162. //mt6325_upmu_set_rg_chr_en(1); // CHR_EN
  163. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_MODE,1);//CSDAC_MODE
  164. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_EN,1);
  165. #if defined(MTK_BQ24261_SUPPORT)
  166. bq24261_hw_init();
  167. bq24261_charging_enable(bEnable);
  168. bq24261_dump_register();
  169. #endif
  170. #if defined(MTK_BQ24296_SUPPORT)
  171. bq24296_hw_init();
  172. bq24296_charging_enable(bEnable);
  173. bq24296_dump_register();
  174. #endif
  175. #if defined(MTK_NCP1854_SUPPORT)
  176. ncp1854_hw_init();
  177. ncp1854_charging_enable(bEnable);
  178. ncp1854_dump_register();
  179. #endif
  180. #if defined(MTK_BQ25896_SUPPORT)
  181. bq25896_hw_init();
  182. bq25896_charging_enable(bEnable);
  183. bq25896_dump_register();
  184. #endif
  185. #ifdef MTK_CHARGER_INTERFACE
  186. ret = mtk_charger_enable_charging(primary_mchr, enable);
  187. if (ret < 0)
  188. dprintf(CRITICAL, "%s: %s charging failed, ret = %d\n",
  189. __func__, (enable ? "enable" : "disable"), ret);
  190. mtk_charger_dump_register(primary_mchr);
  191. if (ret < 0)
  192. dprintf(CRITICAL, "%s: dump register failed, ret = %d\n",
  193. __func__, ret);
  194. #endif
  195. }
  196. void pchr_turn_off_charging(void)
  197. {
  198. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_INT_EN,0);// CHRWDT_INT_EN
  199. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_EN,0);// CHRWDT_EN
  200. pmic_set_register_value(MT6351_PMIC_RG_CHRWDT_FLAG_WR,0);// CHRWDT_FLAG
  201. pmic_set_register_value(MT6351_PMIC_RG_CSDAC_EN,0);// CSDAC_EN
  202. pmic_set_register_value(MT6351_PMIC_RG_NORM_CHR_EN,0);// CHR_EN
  203. pmic_set_register_value(MT6351_PMIC_RG_HWCV_EN,0);// RG_HWCV_EN
  204. }
  205. /*
  206. * Switch Charger Power Path switch
  207. */
  208. void switch_charger_power_path_enable(kal_bool enable)
  209. {
  210. #if defined(MTK_BQ25896_SUPPORT)
  211. if (enable == KAL_TRUE) {
  212. bq25896_set_FORCE_VINDPM(1);
  213. bq25896_set_VINDPM(0x14);
  214. } else {
  215. bq25896_set_FORCE_VINDPM(1);
  216. bq25896_set_VINDPM(0x7F);
  217. }
  218. #elif defined(MTK_CHARGER_INTERFACE)
  219. int ret = 0;
  220. bool _enable = enable ? true : false;
  221. ret = mtk_charger_enable_power_path(primary_mchr, _enable);
  222. if (ret < 0)
  223. dprintf(CRITICAL, "%s: %s power path failed, ret = %d\n",
  224. __func__, (_enable ? "enable" : "disable"), ret);
  225. #endif
  226. }
  227. int is_charging = 0;
  228. #define rtc_busy_wait() \
  229. do { \
  230. while (RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY); \
  231. } while (0)
  232. static U16 RTC_Read(U16 addr)
  233. {
  234. U32 rdata=0;
  235. pwrap_read((U32)addr, &rdata);
  236. return (U16)rdata;
  237. }
  238. static void RTC_Write(U16 addr, U16 data)
  239. {
  240. pwrap_write((U32)addr, (U32)data);
  241. }
  242. static void rtc_write_trigger(void)
  243. {
  244. RTC_Write(RTC_WRTGR, 1);
  245. rtc_busy_wait();
  246. }
  247. void lk_set_rtc_to_zero()
  248. {
  249. int tmp_val1, tmp_val2;
  250. tmp_val1 = RTC_Read(RTC_AL_HOU);
  251. RTC_Write(RTC_AL_HOU, (RTC_Read(RTC_AL_HOU)&RTC_AL_HOU_MASK));
  252. rtc_write_trigger();
  253. tmp_val2 = RTC_Read(RTC_AL_HOU);
  254. dprintf(CRITICAL, "LK reset FG_RTC %d => %d\n", tmp_val1>>8, tmp_val2>>8);
  255. }
  256. /*
  257. * enter this function when low battery with charger
  258. * For BQ25896, power path support can provide current and voltage for cell phone to boot directly to kernel.
  259. */
  260. void check_bat_protect_status()
  261. {
  262. kal_int32 bat_val = 0;
  263. int current,chr_volt,cnt=0,i;
  264. #if defined(SWCHR_POWER_PATH)
  265. bat_val = get_i_sense_volt(5);
  266. #else
  267. bat_val = get_bat_sense_volt(5);
  268. #endif
  269. dprintf(CRITICAL, "[%s]: check VBAT=%d mV with %d mV, start charging... \n", __FUNCTION__, bat_val, BATTERY_LOWVOL_THRESOLD);
  270. while (bat_val < BATTERY_LOWVOL_THRESOLD) {
  271. mtk_wdt_restart();
  272. if (upmu_is_chr_det() == KAL_FALSE) {
  273. dprintf(CRITICAL, "[BATTERY] No Charger, Power OFF !\n");
  274. mt6575_power_off();
  275. while (1);
  276. }
  277. chr_volt= get_charger_volt(1);
  278. if (chr_volt>V_CHARGER_MAX) {
  279. dprintf(CRITICAL, "[BATTERY] charger voltage is too high :%d , threshold is %d !\n",chr_volt,V_CHARGER_MAX);
  280. #if defined(SWCHR_POWER_PATH)
  281. mt6575_power_off();
  282. #endif
  283. break;
  284. }
  285. pmic_set_register_value(PMIC_BATON_TDET_EN, 1);
  286. pmic_set_register_value(PMIC_RG_BATON_EN, 1);
  287. if (pmic_get_register_value(PMIC_RGS_BATON_UNDET) == 1) {
  288. dprintf(CRITICAL, "[BATTERY] No battry plug-in. Power Off.");
  289. mt6575_power_off();
  290. break;
  291. }
  292. dprintf(CRITICAL, "[%s]: check VBAT=%d mV with %d mV, start charging... \n", __FUNCTION__, bat_val, BATTERY_LOWVOL_THRESOLD);
  293. is_charging = 1;
  294. pchr_turn_on_charging(KAL_TRUE);
  295. lk_set_rtc_to_zero();
  296. #if defined(SWCHR_POWER_PATH)
  297. mdelay(5000);
  298. #else
  299. cnt=0;
  300. for (i=0; i<10; i++) {
  301. current=get_charging_current(1);
  302. chr_volt=get_charger_volt(1);
  303. if (current<100 && chr_volt<4400) {
  304. cnt++;
  305. dprintf(CRITICAL, "[BATTERY] charging current=%d charger volt=%d\n\r",current,chr_volt);
  306. } else {
  307. dprintf(CRITICAL, "[BATTERY] charging current=%d charger volt=%d\n\r",current,chr_volt);
  308. cnt=0;
  309. }
  310. }
  311. if (cnt>=8) {
  312. dprintf(CRITICAL, "[BATTERY] charging current and charger volt too low !! \n\r",cnt);
  313. pchr_turn_off_charging();
  314. #ifndef NO_POWER_OFF
  315. mt6575_power_off();
  316. #endif
  317. while (1) {
  318. dprintf(CRITICAL, "If you see the log, please check with RTC power off API\n\r");
  319. }
  320. }
  321. mdelay(50);
  322. #endif
  323. #if defined(SWCHR_POWER_PATH)
  324. #ifndef MTK_NCP1854_SUPPORT /* NCP1854 needs enable charging to have power path */
  325. pchr_turn_on_charging(KAL_FALSE);
  326. mdelay(100);
  327. #endif
  328. bat_val = get_i_sense_volt(5);
  329. #else
  330. bat_val = get_bat_sense_volt(5);
  331. #endif
  332. dprintf(CRITICAL, "[%s]: check VBAT=%d mV \n", __FUNCTION__, bat_val);
  333. }
  334. mtk_wdt_restart();
  335. dprintf(CRITICAL, "[%s]: check VBAT=%d mV with %d mV, stop charging... \n", __FUNCTION__, bat_val, BATTERY_LOWVOL_THRESOLD);
  336. }
  337. bool mtk_bat_allow_backlight_enable(void)
  338. {
  339. int bat_vol = 0;
  340. #if defined(SWCHR_POWER_PATH)
  341. bat_vol = get_i_sense_volt(1);
  342. #else
  343. bat_vol = get_bat_sense_volt(1);
  344. #endif
  345. if (bat_vol > (BATTERY_LOWVOL_THRESOLD + 150))
  346. return true;
  347. return false;
  348. }
  349. void mt65xx_bat_init(void)
  350. {
  351. kal_int32 bat_vol;
  352. #if defined(SWCHR_POWER_PATH) || defined(MTK_PUMP_EXPRESS_PLUS_SUPPORT)
  353. kal_int32 chr_volt;
  354. kal_int32 rc = 0;
  355. #endif
  356. // Low Battery Safety Booting
  357. #if defined(SWCHR_POWER_PATH)
  358. bat_vol = get_i_sense_volt(1);
  359. #else
  360. bat_vol = get_bat_sense_volt(1);
  361. #endif
  362. //pchr_turn_on_charging(KAL_TRUE);
  363. dprintf(INFO, "[mt65xx_bat_init] check VBAT=%d mV with %d mV\n", bat_vol, BATTERY_LOWVOL_THRESOLD);
  364. /* Get charger interface */
  365. #ifdef MTK_CHARGER_INTERFACE
  366. mtk_charger_init();
  367. primary_mchr = mtk_charger_get_by_name("primary_charger");
  368. if (!primary_mchr)
  369. dprintf(CRITICAL, "%s: get primary charger failed\n", __func__);
  370. #endif
  371. #if defined(MTK_PUMP_EXPRESS_PLUS_SUPPORT) || defined(MTK_PUMP_EXPRESS_PLUS_20_SUPPORT)
  372. /*Try to reset PE+ adapter once abnormal voltage is found*/
  373. chr_volt = get_charger_volt(1);
  374. while (chr_volt > V_CHARGER_MAX) {
  375. dprintf(CRITICAL, "[mt65xx_bat_init] PE+ adpater should be reset to 5V now\n");
  376. pumpex_reset_adapter_enble(1);
  377. mdelay(250);
  378. pumpex_reset_adapter_enble(0);
  379. chr_volt = get_charger_volt(1);
  380. rc++;
  381. if (rc == 3)
  382. break;
  383. }
  384. #endif
  385. if (g_boot_mode == KERNEL_POWER_OFF_CHARGING_BOOT && (pmic_get_register_value(MT6351_PMIC_PWRKEY_DEB)==0) ) {
  386. dprintf(CRITICAL, "[mt65xx_bat_init] KPOC+PWRKEY => change boot mode\n");
  387. g_boot_reason_change = true;
  388. }
  389. rtc_boot_check(false);
  390. #ifndef MTK_DISABLE_POWER_ON_OFF_VOLTAGE_LIMITATION
  391. #ifndef MTK_BATLOWV_NO_PANEL_ON_EARLY
  392. if (bat_vol < BATTERY_LOWVOL_THRESOLD)
  393. #else
  394. if (is_low_battery(bat_vol))
  395. #endif
  396. {
  397. if (g_boot_mode == KERNEL_POWER_OFF_CHARGING_BOOT && upmu_is_chr_det() == KAL_TRUE) {
  398. dprintf(CRITICAL, "[%s] Kernel Low Battery Power Off Charging Mode\n", __func__);
  399. g_boot_mode = LOW_POWER_OFF_CHARGING_BOOT;
  400. check_bat_protect_status();
  401. } else {
  402. dprintf(CRITICAL, "[BATTERY] battery voltage(%dmV) <= CLV ! Can not Boot Linux Kernel !! \n\r",bat_vol);
  403. #ifndef NO_POWER_OFF
  404. mt6575_power_off();
  405. #endif
  406. while (1) {
  407. dprintf(CRITICAL, "If you see the log, please check with RTC power off API\n\r");
  408. }
  409. }
  410. }
  411. #endif
  412. #if defined(SWCHR_POWER_PATH)
  413. chr_volt = get_charger_volt(1);
  414. if (chr_volt > V_CHARGER_MAX) {
  415. dprintf(CRITICAL, "Charger Over Voltage:%d\n, power off...", chr_volt);
  416. mt6575_power_off();
  417. }
  418. #endif
  419. #if defined(DLPT_FEATURE_SUPPORT)
  420. fgauge_initialization(NULL);
  421. if (g_boot_mode != META_BOOT && g_boot_mode != FACTORY_BOOT && g_boot_mode != ATE_FACTORY_BOOT) {
  422. pmic_set_register_value(PMIC_BATON_TDET_EN, 1);
  423. pmic_set_register_value(PMIC_RG_BATON_EN, 1);
  424. if (pmic_get_register_value(PMIC_RGS_BATON_UNDET) == 1) {
  425. dprintf(CRITICAL, "[BATTERY] No battry plug-in. Power Off.");
  426. mt6575_power_off();
  427. }
  428. }
  429. pchr_turn_on_charging(KAL_FALSE);
  430. /* disable SW charger power path */
  431. switch_charger_power_path_enable(KAL_FALSE);
  432. mdelay(50);
  433. get_dlpt_imix_r();
  434. /* after get imix, re-enable SW charger power path */
  435. switch_charger_power_path_enable(KAL_TRUE);
  436. mdelay(50);
  437. check_bat_protect_status();
  438. if (is_charging == 1) {
  439. pchr_turn_on_charging(KAL_TRUE);
  440. dprintf(CRITICAL, "turn on charging \n\r");
  441. }
  442. #endif //#if defined(DLPT_FEATURE_SUPPORT)
  443. return;
  444. }
  445. #if defined(DLPT_FEATURE_SUPPORT)
  446. int imix_r=170;
  447. kal_int32 chip_diff_trim_value_4_0 = 0;
  448. kal_int32 chip_diff_trim_value = 0; // unit = 0.1
  449. #define UNIT_FGCURRENT (158122) // 158.122 uA
  450. /* battery meter parameter */
  451. #define CHANGE_TRACKING_POINT
  452. #define CUST_TRACKING_POINT 1
  453. #define CUST_R_SENSE 68
  454. #define CUST_HW_CC 0
  455. #define AGING_TUNING_VALUE 103
  456. #define CUST_R_FG_OFFSET 0
  457. #define OCV_BOARD_COMPESATE 0 //mV
  458. #define R_FG_BOARD_BASE 1000
  459. #define R_FG_BOARD_SLOPE 1000 //slope
  460. #define CAR_TUNE_VALUE 86 //1.00
  461. /* HW Fuel gague */
  462. #define CURRENT_DETECT_R_FG 10 //1mA
  463. #define MinErrorOffset 1000
  464. #define FG_VBAT_AVERAGE_SIZE 18
  465. #define R_FG_VALUE 10 // mOhm, base is 20
  466. kal_bool g_fg_is_charging = 0;
  467. kal_uint32 ptim_bat_vol=0;
  468. kal_int32 ptim_R_curr=0;
  469. extern kal_uint32 upmu_get_reg_value(kal_uint32 reg);
  470. void get_hw_chip_diff_trim_value(void)
  471. {
  472. #if 1
  473. kal_int32 reg_val = 0;
  474. reg_val = upmu_get_reg_value(0xCB8);
  475. chip_diff_trim_value_4_0 = (reg_val>>7)&0x001F;//chip_diff_trim_value_4_0 = (reg_val>>10)&0x001F;
  476. dprintf(CRITICAL,"[Chip_Trim] Reg[0xCB8]=0x%x, chip_diff_trim_value_4_0=%d\n", reg_val, chip_diff_trim_value_4_0);
  477. #else
  478. dprintf(CRITICAL,"[Chip_Trim] need check reg number\n");
  479. #endif
  480. switch (chip_diff_trim_value_4_0) {
  481. case 0:
  482. chip_diff_trim_value = 1000;
  483. break;
  484. case 1:
  485. chip_diff_trim_value = 1005;
  486. break;
  487. case 2:
  488. chip_diff_trim_value = 1010;
  489. break;
  490. case 3:
  491. chip_diff_trim_value = 1015;
  492. break;
  493. case 4:
  494. chip_diff_trim_value = 1020;
  495. break;
  496. case 5:
  497. chip_diff_trim_value = 1025;
  498. break;
  499. case 6:
  500. chip_diff_trim_value = 1030;
  501. break;
  502. case 7:
  503. chip_diff_trim_value = 1036;
  504. break;
  505. case 8:
  506. chip_diff_trim_value = 1041;
  507. break;
  508. case 9:
  509. chip_diff_trim_value = 1047;
  510. break;
  511. case 10:
  512. chip_diff_trim_value = 1052;
  513. break;
  514. case 11:
  515. chip_diff_trim_value = 1058;
  516. break;
  517. case 12:
  518. chip_diff_trim_value = 1063;
  519. break;
  520. case 13:
  521. chip_diff_trim_value = 1069;
  522. break;
  523. case 14:
  524. chip_diff_trim_value = 1075;
  525. break;
  526. case 15:
  527. chip_diff_trim_value = 1081;
  528. break;
  529. case 31:
  530. chip_diff_trim_value = 995;
  531. break;
  532. case 30:
  533. chip_diff_trim_value = 990;
  534. break;
  535. case 29:
  536. chip_diff_trim_value = 985;
  537. break;
  538. case 28:
  539. chip_diff_trim_value = 980;
  540. break;
  541. case 27:
  542. chip_diff_trim_value = 975;
  543. break;
  544. case 26:
  545. chip_diff_trim_value = 970;
  546. break;
  547. case 25:
  548. chip_diff_trim_value = 966;
  549. break;
  550. case 24:
  551. chip_diff_trim_value = 961;
  552. break;
  553. case 23:
  554. chip_diff_trim_value = 956;
  555. break;
  556. case 22:
  557. chip_diff_trim_value = 952;
  558. break;
  559. case 21:
  560. chip_diff_trim_value = 947;
  561. break;
  562. case 20:
  563. chip_diff_trim_value = 943;
  564. break;
  565. case 19:
  566. chip_diff_trim_value = 938;
  567. break;
  568. case 18:
  569. chip_diff_trim_value = 934;
  570. break;
  571. case 17:
  572. chip_diff_trim_value = 930;
  573. break;
  574. default:
  575. dprintf(CRITICAL, "[Chip_Trim] Invalid value(%d)\n", chip_diff_trim_value_4_0);
  576. break;
  577. }
  578. dprintf(CRITICAL, "[Chip_Trim] chip_diff_trim_value=%d\n", chip_diff_trim_value);
  579. }
  580. static kal_uint32 fg_get_data_ready_status(void)
  581. {
  582. kal_uint32 ret=0;
  583. kal_uint32 temp_val=0;
  584. ret=pmic_read_interface(MT6351_FGADC_CON0, &temp_val, 0xFFFF, 0x0);
  585. dprintf(CRITICAL, "[fg_get_data_ready_status] Reg[0x%x]=0x%x\r\n", MT6351_FGADC_CON0, temp_val);
  586. temp_val = (temp_val & (MT6351_PMIC_FG_LATCHDATA_ST_MASK << MT6351_PMIC_FG_LATCHDATA_ST_SHIFT)) >> MT6351_PMIC_FG_LATCHDATA_ST_SHIFT;
  587. return temp_val;
  588. }
  589. kal_int32 use_chip_trim_value(kal_int32 not_trim_val)
  590. {
  591. kal_int32 ret_val=0;
  592. ret_val=((not_trim_val*chip_diff_trim_value)/1000);
  593. dprintf(CRITICAL, "[use_chip_trim_value] %d -> %d\n", not_trim_val, ret_val);
  594. return ret_val;
  595. }
  596. void fgauge_read_current(void *data)
  597. {
  598. kal_uint16 uvalue16 = 0;
  599. kal_int32 dvalue = 0;
  600. int m = 0;
  601. uint64_t Temp_Value = 0;
  602. kal_int32 Current_Compensate_Value=0;
  603. kal_uint32 ret = 0;
  604. // HW Init
  605. //(1) i2c_write (0x60, 0xC8, 0x01); // Enable VA2
  606. //(2) i2c_write (0x61, 0x15, 0x00); // Enable FGADC clock for digital
  607. //(3) i2c_write (0x61, 0x69, 0x28); // Set current mode, auto-calibration mode and 32KHz clock source
  608. //(4) i2c_write (0x61, 0x69, 0x29); // Enable FGADC
  609. //Read HW Raw Data
  610. //(1) Set READ command
  611. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0200, 0xFF00, 0x0);
  612. //(2) Keep i2c read when status = 1 (0x06)
  613. m=0;
  614. while ( fg_get_data_ready_status() == 0 ) {
  615. m++;
  616. if (m>1000) {
  617. dprintf(CRITICAL, "[fgauge_read_current] fg_get_data_ready_status timeout 1 !\r\n");
  618. break;
  619. }
  620. }
  621. //(3) Read FG_CURRENT_OUT[15:08]
  622. //(4) Read FG_CURRENT_OUT[07:00]
  623. uvalue16 = pmic_get_register_value(MT6351_PMIC_FG_CURRENT_OUT); //mt6325_upmu_get_fg_current_out();
  624. dprintf(CRITICAL, "[fgauge_read_current] : FG_CURRENT = %x\r\n", uvalue16);
  625. //(5) (Read other data)
  626. //(6) Clear status to 0
  627. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0800, 0xFF00, 0x0);
  628. //(7) Keep i2c read when status = 0 (0x08)
  629. //while ( fg_get_sw_clear_status() != 0 )
  630. m=0;
  631. while ( fg_get_data_ready_status() != 0 ) {
  632. m++;
  633. if (m>1000) {
  634. dprintf(CRITICAL, "[fgauge_read_current] fg_get_data_ready_status timeout 2 !\r\n");
  635. break;
  636. }
  637. }
  638. //(8) Recover original settings
  639. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0000, 0xFF00, 0x0);
  640. //calculate the real world data
  641. dvalue = (kal_uint32) uvalue16;
  642. if ( dvalue == 0 ) {
  643. Temp_Value = (uint64_t) dvalue;
  644. g_fg_is_charging = KAL_FALSE;
  645. } else if ( dvalue > 32767 ) { // > 0x8000
  646. Temp_Value = (uint64_t)(dvalue - 65535);
  647. Temp_Value = Temp_Value - (Temp_Value*2);
  648. g_fg_is_charging = KAL_FALSE;
  649. } else {
  650. Temp_Value = (uint64_t) dvalue;
  651. g_fg_is_charging = KAL_TRUE;
  652. }
  653. Temp_Value = Temp_Value * UNIT_FGCURRENT;
  654. //do_div(Temp_Value, 100000);
  655. Temp_Value=Temp_Value/100000;
  656. dvalue = (kal_uint32)Temp_Value;
  657. if ( g_fg_is_charging == KAL_TRUE ) {
  658. dprintf(CRITICAL, "[fgauge_read_current] current(charging) = %d mA\r\n", dvalue);
  659. } else {
  660. dprintf(CRITICAL, "[fgauge_read_current] current(discharging) = %d mA\r\n", dvalue);
  661. }
  662. // Auto adjust value
  663. if (R_FG_VALUE != 20) {
  664. dprintf(CRITICAL, "[fgauge_read_current] Auto adjust value due to the Rfg is %d\n Ori current=%d, ", R_FG_VALUE, dvalue);
  665. dvalue = (dvalue*20)/R_FG_VALUE;
  666. dprintf(CRITICAL, "[fgauge_read_current] new current=%d\n", dvalue);
  667. }
  668. // K current
  669. if (R_FG_BOARD_SLOPE != R_FG_BOARD_BASE) {
  670. dvalue = ( (dvalue*R_FG_BOARD_BASE) + (R_FG_BOARD_SLOPE/2) ) / R_FG_BOARD_SLOPE;
  671. }
  672. // current compensate
  673. if (g_fg_is_charging == KAL_TRUE) {
  674. dvalue = dvalue + Current_Compensate_Value;
  675. } else {
  676. dvalue = dvalue - Current_Compensate_Value;
  677. }
  678. dprintf(CRITICAL, "[fgauge_read_current] ori current=%d\n", dvalue);
  679. dvalue = ((dvalue*CAR_TUNE_VALUE)/100);
  680. dvalue = use_chip_trim_value(dvalue);
  681. dprintf(CRITICAL, "[fgauge_read_current] final current=%d (ratio=%d)\n", dvalue, CAR_TUNE_VALUE);
  682. *(kal_int32*)(data) = dvalue;
  683. return;
  684. }
  685. void fgauge_read_IM_current(void *data)
  686. {
  687. kal_uint16 uvalue16 = 0;
  688. kal_int32 dvalue = 0;
  689. int m = 0;
  690. uint64_t Temp_Value = 0;
  691. kal_int32 Current_Compensate_Value=0;
  692. kal_uint32 ret = 0;
  693. uvalue16 = pmic_get_register_value(MT6351_PMIC_FG_R_CURR);
  694. dprintf(CRITICAL, "[fgauge_read_IM_current] : FG_CURRENT = %x\r\n", uvalue16);
  695. //calculate the real world data
  696. dvalue = (kal_uint32) uvalue16;
  697. if ( dvalue == 0 ) {
  698. Temp_Value = (uint64_t) dvalue;
  699. g_fg_is_charging = KAL_FALSE;
  700. } else if ( dvalue > 32767 ) { // > 0x8000
  701. Temp_Value = (uint64_t)(dvalue - 65535);
  702. Temp_Value = Temp_Value - (Temp_Value*2);
  703. g_fg_is_charging = KAL_FALSE;
  704. } else {
  705. Temp_Value = (uint64_t) dvalue;
  706. g_fg_is_charging = KAL_TRUE;
  707. }
  708. Temp_Value = Temp_Value * UNIT_FGCURRENT;
  709. //do_div(Temp_Value, 100000);
  710. Temp_Value=Temp_Value/100000;
  711. dvalue = (kal_uint32)Temp_Value;
  712. if ( g_fg_is_charging == KAL_TRUE ) {
  713. dprintf(CRITICAL, "[fgauge_read_IM_current] current(charging) = %d mA\r\n", dvalue);
  714. } else {
  715. dprintf(CRITICAL, "[fgauge_read_IM_current] current(discharging) = %d mA\r\n", dvalue);
  716. }
  717. // Auto adjust value
  718. if (R_FG_VALUE != 20) {
  719. dprintf(CRITICAL, "[fgauge_read_IM_current] Auto adjust value due to the Rfg is %d\n Ori current=%d, ", R_FG_VALUE, dvalue);
  720. dvalue = (dvalue*20)/R_FG_VALUE;
  721. dprintf(CRITICAL, "[fgauge_read_IM_current] new current=%d\n", dvalue);
  722. }
  723. // K current
  724. if (R_FG_BOARD_SLOPE != R_FG_BOARD_BASE) {
  725. dvalue = ( (dvalue*R_FG_BOARD_BASE) + (R_FG_BOARD_SLOPE/2) ) / R_FG_BOARD_SLOPE;
  726. }
  727. // current compensate
  728. if (g_fg_is_charging == KAL_TRUE) {
  729. dvalue = dvalue + Current_Compensate_Value;
  730. } else {
  731. dvalue = dvalue - Current_Compensate_Value;
  732. }
  733. dprintf(CRITICAL, "[fgauge_read_IM_current] ori current=%d\n", dvalue);
  734. dvalue = ((dvalue*CAR_TUNE_VALUE)/100);
  735. dvalue = use_chip_trim_value(dvalue);
  736. dprintf(CRITICAL,"[fgauge_read_IM_current] final current=%d (ratio=%d)\n", dvalue, CAR_TUNE_VALUE);
  737. *(kal_int32*)(data) = dvalue;
  738. return;
  739. }
  740. void fgauge_initialization(void *data)
  741. {
  742. kal_uint32 ret=0;
  743. kal_int32 current_temp = 0;
  744. int m = 0;
  745. get_hw_chip_diff_trim_value();
  746. // 1. HW initialization
  747. //FGADC clock is 32768Hz from RTC
  748. //Enable FGADC in current mode at 32768Hz with auto-calibration
  749. //(1) Enable VA2
  750. //(2) Enable FGADC clock for digital
  751. pmic_set_register_value(MT6351_PMIC_RG_FGADC_ANA_CK_PDN,0);// mt6325_upmu_set_rg_fgadc_ana_ck_pdn(0);
  752. pmic_set_register_value(MT6351_PMIC_RG_FGADC_DIG_CK_PDN,0);// mt6325_upmu_set_rg_fgadc_dig_ck_pdn(0);
  753. //(3) Set current mode, auto-calibration mode and 32KHz clock source
  754. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0028, 0x00FF, 0x0);
  755. //(4) Enable FGADC
  756. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x0029, 0x00FF, 0x0);
  757. //reset HW FG
  758. ret=pmic_config_interface(MT6351_FGADC_CON0, 0x7100, 0xFF00, 0x0);
  759. dprintf(CRITICAL,"******** [fgauge_initialization] reset HW FG!\n" );
  760. //set FG_OSR
  761. ret=pmic_config_interface(MT6351_FGADC_CON11, 0x8, 0xF, 0x0);
  762. dprintf(CRITICAL, "[fgauge_initialization] Reg[0x%x]=0x%x\n",MT6351_FGADC_CON11, upmu_get_reg_value(MT6351_FGADC_CON11));
  763. //make sure init finish
  764. m = 0;
  765. while (current_temp == 0) {
  766. fgauge_read_current(&current_temp);
  767. m++;
  768. if (m>1000) {
  769. dprintf(CRITICAL, "[fgauge_initialization] timeout!\r\n");
  770. break;
  771. }
  772. }
  773. dprintf(CRITICAL, "******** [fgauge_initialization] Done!\n" );
  774. return ;
  775. }
  776. void do_ptim(void)
  777. {
  778. kal_uint32 i;
  779. kal_uint32 vbat_reg;
  780. //PMICLOG("[do_ptim] start \n");
  781. //pmic_auxadc_lock();
  782. //pmic_set_register_value(PMIC_RG_AUXADC_RST,1);
  783. //pmic_set_register_value(PMIC_RG_AUXADC_RST,0);
  784. upmu_set_reg_value(0x0eac,0x0006);
  785. pmic_set_register_value(MT6351_PMIC_AUXADC_IMP_AUTORPT_PRD,6);
  786. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN,0);
  787. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN_HWEN,0);
  788. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_CK_PDN_HWEN,0);
  789. pmic_set_register_value(MT6351_PMIC_RG_AUXADC_CK_PDN,0);
  790. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,1);
  791. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,1);
  792. //restore to initial state
  793. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,0);
  794. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,0);
  795. //set issue interrupt
  796. //pmic_set_register_value(MT6351_PMIC_RG_INT_EN_AUXADC_IMP,1);
  797. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_CHSEL,0);
  798. pmic_set_register_value(MT6351_PMIC_AUXADC_IMP_AUTORPT_EN,1);
  799. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_CNT,3);
  800. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_MODE,1);
  801. // MT6351_PMICLOG("[do_ptim] end %d %d \n",pmic_get_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN),pmic_get_register_value(MT6351_PMIC_RG_AUXADC_SMPS_CK_PDN_HWEN));
  802. while (pmic_get_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_STATUS)==0) {
  803. //MT6351_PMICLOG("[do_ptim] MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_STATUS= %d \n",pmic_get_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_STATUS));
  804. mdelay(1);
  805. }
  806. //disable
  807. pmic_set_register_value(MT6351_PMIC_AUXADC_IMP_AUTORPT_EN,0);//typo
  808. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_MODE,0);
  809. //clear irq
  810. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,1);
  811. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,1);
  812. pmic_set_register_value(MT6351_PMIC_AUXADC_CLR_IMP_CNT_STOP,0);
  813. pmic_set_register_value(MT6351_PMIC_AUXADC_IMPEDANCE_IRQ_CLR,0);
  814. //MT6351_PMICLOG("[do_ptim2] 0xee8=0x%x 0x2c6=0x%x\n", upmu_get_reg_value(0xee8),upmu_get_reg_value(0x2c6));
  815. //pmic_set_register_value(MT6351_PMIC_RG_INT_STATUS_AUXADC_IMP,1);//write 1 to clear !
  816. //pmic_set_register_value(MT6351_PMIC_RG_INT_EN_AUXADC_IMP,0);
  817. vbat_reg=pmic_get_register_value(MT6351_PMIC_AUXADC_ADC_OUT_IMP_AVG);
  818. ptim_bat_vol=(vbat_reg*3*18000)/32768;
  819. fgauge_read_IM_current((void *)&ptim_R_curr);
  820. }
  821. void enable_dummy_load(kal_uint32 en)
  822. {
  823. kal_uint32 reg;
  824. if (en==1) {
  825. /*1. disable isink pdn */
  826. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK3_CK_PDN, 0);
  827. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK2_CK_PDN, 0);
  828. /*
  829. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK1_CK_PDN, 0);
  830. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK0_CK_PDN, 0);
  831. */
  832. pmic_set_register_value(MT6351_PMIC_RG_DRV_32K_CK_PDN, 0);
  833. /*1. disable isink pdn */
  834. pmic_set_register_value(MT6351_PMIC_RG_DRV_CHRIND_CK_PDN, 0);
  835. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK7_CK_PDN, 0);
  836. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK6_CK_PDN, 0);
  837. /*
  838. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK5_CK_PDN, 0);
  839. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK4_CK_PDN, 0);
  840. */
  841. /* enable isink step */
  842. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_STEP, 0x7);
  843. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_STEP, 0x7);
  844. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_STEP, 0x7);
  845. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_STEP, 0x7);
  846. /*enable isink */
  847. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_BIAS_EN, 0x1);
  848. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_BIAS_EN, 0x1);
  849. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_BIAS_EN, 0x1);
  850. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_BIAS_EN, 0x1);
  851. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP7_EN, 0x1);
  852. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP6_EN, 0x1);
  853. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP3_EN, 0x1);
  854. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP2_EN, 0x1);
  855. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_EN, 0x1);
  856. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_EN, 0x1);
  857. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_EN, 0x1);
  858. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_EN, 0x1);
  859. /*PMICLOG("[enable dummy load]\n"); */
  860. pmic_read_interface(0x23a, &reg, 0xffff, 0);
  861. dprintf(INFO, "[isink 2 [0x23a]=0x%x \n", reg);
  862. pmic_read_interface(0x258, &reg, 0xffff, 0);
  863. dprintf(INFO, "[isink 2 [0x258]=0x%x \n", reg);
  864. pmic_read_interface(0x83c, &reg, 0xffff, 0);
  865. dprintf(INFO, "[isink 2 [0x83c]=0x%x \n", reg);
  866. pmic_read_interface(0x83e, &reg, 0xffff, 0);
  867. dprintf(INFO, "[isink 3 [0x83e]=0x%x] \n", reg);
  868. pmic_read_interface(0x840, &reg, 0xffff, 0);
  869. dprintf(INFO, "[isink 6 [0x840]=0x%x] \n", reg);
  870. pmic_read_interface(0x842, &reg, 0xffff, 0);
  871. dprintf(INFO, "[isink 7 [0x842]=0x%x] \n", reg);
  872. pmic_read_interface(0x848, &reg, 0xffff, 0);
  873. dprintf(INFO, "[isink 7 [0x848]=0x%x] \n", reg);
  874. pmic_read_interface(0x844, &reg, 0xffff, 0);
  875. dprintf(INFO, "[isink 7 [0x844]=0x%x] \n", reg);
  876. } else {
  877. /*upmu_set_reg_value(0x828,0x0cc0); */
  878. #if MT6328
  879. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_EN, 0);
  880. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_EN, 0);
  881. #endif
  882. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_EN, 0);
  883. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_EN, 0);
  884. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_EN, 0);
  885. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_EN, 0);
  886. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP7_EN, 0);
  887. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP6_EN, 0);
  888. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP3_EN, 0);
  889. pmic_set_register_value(MT6351_PMIC_ISINK_CHOP2_EN, 0);
  890. pmic_set_register_value(MT6351_PMIC_ISINK_CH7_BIAS_EN, 0);
  891. pmic_set_register_value(MT6351_PMIC_ISINK_CH6_BIAS_EN, 0);
  892. pmic_set_register_value(MT6351_PMIC_ISINK_CH3_BIAS_EN, 0);
  893. pmic_set_register_value(MT6351_PMIC_ISINK_CH2_BIAS_EN, 0);
  894. /*1. enable isink pdn */
  895. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK3_CK_PDN, 0x1);
  896. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK2_CK_PDN, 0x1);
  897. pmic_set_register_value(MT6351_PMIC_RG_DRV_32K_CK_PDN, 0x1);
  898. /*1. enable isink pdn */
  899. pmic_set_register_value(MT6351_PMIC_RG_DRV_CHRIND_CK_PDN, 0x1);
  900. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK7_CK_PDN, 0x1);
  901. pmic_set_register_value(MT6351_PMIC_RG_DRV_ISINK6_CK_PDN, 0x1);
  902. /*pmic_set_register_value(PMIC_RG_VIBR_EN,0); */
  903. /*PMICLOG("[disable dummy load]\n"); */
  904. }
  905. }
  906. int get_rac_val(void)
  907. {
  908. int volt_1=0;
  909. int volt_2=0;
  910. int curr_1=0;
  911. int curr_2=0;
  912. int rac_cal=0;
  913. int ret=0;
  914. kal_bool retry_state = KAL_FALSE;
  915. int retry_count=0;
  916. do {
  917. //adc and fg--------------------------------------------------------
  918. do_ptim();
  919. dprintf(INFO, "[1,Trigger ADC PTIM mode] volt1=%d, curr_1=%d\n", ptim_bat_vol, ptim_R_curr);
  920. volt_1=ptim_bat_vol;
  921. curr_1=ptim_R_curr;
  922. dprintf(INFO, "[2,enable dummy load]");
  923. enable_dummy_load(1);
  924. /* debug to measure bat volt & Isense */
  925. /* pmic_set_register_value(MT6351_PMIC_RG_VIBR_EN, 0x1); */
  926. mdelay(1);
  927. //Wait --------------------------------------------------------------
  928. //adc and fg--------------------------------------------------------
  929. do_ptim();
  930. dprintf(INFO, "[3,Trigger ADC PTIM mode again]0717 volt2=%d, curr_2=%d\n", ptim_bat_vol, ptim_R_curr);
  931. volt_2=ptim_bat_vol;
  932. curr_2=ptim_R_curr;
  933. //Disable dummy load-------------------------------------------------
  934. enable_dummy_load(0);
  935. /* debug to measure bat volt & Isense */
  936. /*pmic_set_register_value(MT6351_PMIC_RG_VIBR_EN, 0); */
  937. //Calculate Rac------------------------------------------------------
  938. if ( (curr_2-curr_1) >= 700 && (curr_2-curr_1) <= 1200 && (volt_1-volt_2)>=80 ) { //40.0mA
  939. rac_cal=((volt_1-volt_2)*1000)/(curr_2-curr_1); //m-ohm
  940. if (rac_cal<0) {
  941. ret = (rac_cal-(rac_cal*2))*1;
  942. } else {
  943. ret = rac_cal*1;
  944. }
  945. } else {
  946. ret=-1;
  947. dprintf(CRITICAL, "[4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA\n");
  948. }
  949. dprintf(INFO, "[5,Calculate Rac] volt_1=%d,volt_2=%d,curr_1=%d,curr_2=%d,rac_cal=%d,ret=%d,retry_count=%d\n",
  950. volt_1,volt_2,curr_1,curr_2,rac_cal,ret,retry_count);
  951. dprintf(CRITICAL, "[6,Calculate Rac *] %d,%d,%d,%d,%d,%d,%d\n",
  952. volt_1,volt_2,curr_1,curr_2,rac_cal,ret,retry_count);
  953. //------------------------
  954. retry_count++;
  955. if ((retry_count < 3) && (ret == -1)) retry_state = KAL_TRUE;
  956. else retry_state = KAL_FALSE;
  957. } while (retry_state == KAL_TRUE);
  958. return ret;
  959. }
  960. void get_dlpt_imix_r(void)
  961. {
  962. int rac_val[5],rac_val_avg=0,rac_val_sum=0;
  963. int volt[5],curr[5],volt_avg=0,curr_avg=0;
  964. int imix;
  965. int i;
  966. int validcnt=0;
  967. int min=1000,max=0;
  968. for (i=0; i<5; i++) {
  969. rac_val[i]=get_rac_val();
  970. if (rac_val[i]<=min && rac_val[i]!=-1)
  971. min=rac_val[i];
  972. if (rac_val[i]>=max)
  973. max=rac_val[i];
  974. if (rac_val[i]!=-1) {
  975. rac_val_sum+=rac_val[i];
  976. validcnt++;
  977. }
  978. }
  979. if (validcnt>=4) {
  980. rac_val_sum=rac_val_sum-min-max;
  981. imix_r=rac_val_sum/(validcnt-2);
  982. } else if (validcnt!=0) {
  983. imix_r=rac_val_sum/validcnt;
  984. }
  985. dprintf(CRITICAL, "[dlpt_R] %d,%d,%d,%d,%d [%d:%d:%d]%d\n",rac_val[0],rac_val[1],rac_val[2],rac_val[3],rac_val[4],min,max,validcnt,imix_r);
  986. return;
  987. }
  988. #endif //#if defined(DLPT_FEATURE_SUPPORT)
  989. #else
  990. #include <platform/mt_typedefs.h>
  991. #include <platform/mt_reg_base.h>
  992. #include <printf.h>
  993. int imix_r=170;
  994. void mt65xx_bat_init(void)
  995. {
  996. dprintf(CRITICAL, "[BATTERY] Skip mt65xx_bat_init !!\n\r");
  997. dprintf(CRITICAL, "[BATTERY] If you want to enable power off charging, \n\r");
  998. dprintf(CRITICAL, "[BATTERY] Please #define CFG_POWER_CHARGING!!\n\r");
  999. }
  1000. int get_bat_volt(int times)
  1001. {
  1002. int bat_vol;
  1003. #if defined(SWCHR_POWER_PATH)
  1004. bat_vol = get_i_sense_volt(times);
  1005. #else
  1006. bat_vol = get_bat_sense_volt(times);
  1007. #endif
  1008. return bat_vol;
  1009. }
  1010. #endif