primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. //#include<linux/timer.h>
  44. #define DDP_LK_BOOT
  45. #ifndef HZ
  46. #define HZ 100
  47. #endif
  48. #ifdef DDP_LK_BOOT
  49. typedef void * cmdqRecHandle;
  50. #endif
  51. #define ALIGN_TO(x, n) \
  52. (((x) + ((n) - 1)) & ~((n) - 1))
  53. int primary_display_use_cmdq = CMDQ_DISABLE;
  54. int primary_display_use_m4u = 1;
  55. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  56. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  57. static UINT32 disp_fb_pages = 3; ///double buffer
  58. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  59. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  60. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  61. typedef struct _disp_dfo_item {
  62. char name[32];
  63. int value;
  64. } disp_dfo_item_t;
  65. static disp_dfo_item_t disp_dfo_setting[] = {
  66. {"LCM_FAKE_WIDTH", 0},
  67. {"LCM_FAKE_HEIGHT", 0},
  68. {"DISP_DEBUG_SWITCH", 0}
  69. };
  70. typedef struct {
  71. int state;
  72. int need_trigger_overlay;
  73. DISP_PRIMARY_PATH_MODE mode;
  74. unsigned int last_vsync_tick;
  75. #ifndef DDP_LK_BOOT
  76. struct mutex lock;
  77. #endif
  78. disp_lcm_handle * plcm;
  79. cmdqRecHandle cmdq_handle_config;
  80. cmdqRecHandle cmdq_handle_trigger;
  81. disp_path_handle dpmgr_handle;
  82. disp_path_handle ovl2mem_path_handle;
  83. } display_primary_path_context;
  84. #define pgc _get_context()
  85. static display_primary_path_context* _get_context(void)
  86. {
  87. static int is_context_inited = 0;
  88. static display_primary_path_context g_context;
  89. if (!is_context_inited) {
  90. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  91. is_context_inited = 1;
  92. }
  93. return &g_context;
  94. }
  95. static void _primary_path_lock(void)
  96. {
  97. #ifndef DDP_LK_BOOT
  98. disp_sw_mutex_lock(&(pgc->lock));
  99. #endif
  100. }
  101. static void _primary_path_unlock(void)
  102. {
  103. #ifndef DDP_LK_BOOT
  104. disp_sw_mutex_unlock(&(pgc->lock));
  105. #endif
  106. }
  107. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  108. {
  109. if (plcm == NULL) {
  110. DISPERR("plcm is null\n");
  111. return DISP_MODULE_UNKNOWN;
  112. }
  113. if (plcm->params->type == LCM_TYPE_DSI) {
  114. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  115. return DISP_MODULE_DSI0;
  116. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  117. return DISP_MODULE_DSI1;
  118. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  119. return DISP_MODULE_DSIDUAL;
  120. } else {
  121. return DISP_MODULE_DSI0;
  122. }
  123. } else if (plcm->params->type == LCM_TYPE_DPI) {
  124. return DISP_MODULE_DPI;
  125. } else {
  126. DISPERR("can't find primary path dst module\n");
  127. return DISP_MODULE_UNKNOWN;
  128. }
  129. }
  130. static int _build_path_direct_link(void)
  131. {
  132. int ret = 0;
  133. DISP_MODULE_ENUM dst_module = 0;
  134. DISPFUNC();
  135. pgc->mode = DIRECT_LINK_MODE;
  136. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  137. if (pgc->dpmgr_handle) {
  138. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", pgc->dpmgr_handle);
  139. } else {
  140. DISPCHECK("dpmgr create path FAIL\n");
  141. return -1;
  142. }
  143. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  144. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  145. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  146. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  147. return ret;
  148. }
  149. static int _build_path_decouple(void)
  150. {
  151. return 0;
  152. }
  153. static int _build_path_single_layer(void)
  154. {
  155. return 0;
  156. }
  157. static int _build_path_debug_rdma1_dsi0(void)
  158. {
  159. int ret = 0;
  160. DISP_MODULE_ENUM dst_module = 0;
  161. DISPFUNC();
  162. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  163. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  164. if (pgc->dpmgr_handle) {
  165. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", pgc->dpmgr_handle);
  166. } else {
  167. DISPCHECK("dpmgr create path FAIL\n");
  168. return -1;
  169. }
  170. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  171. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  172. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  173. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  174. return ret;
  175. }
  176. static void _build_cmdq_trigger_loop(void)
  177. {
  178. #ifndef DDP_LK_BOOT
  179. int ret = 0;
  180. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  181. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  182. cmdqRecReset(pgc->cmdq_handle_trigger);
  183. if (primary_display_is_video_mode()) {
  184. // wait and clear stream_done
  185. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  186. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  187. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  188. } else {
  189. // only in DSI Command mode we need to wait these
  190. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  191. // no internal te on fpga now.
  192. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  193. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  194. // block config threads, we'll about to update frame
  195. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  196. // only in DSI command mode we need to enable mutex explicitly
  197. // WRITE mutex enable
  198. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  199. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  200. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  201. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  202. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  203. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  204. // polling DSI idle
  205. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  206. // polling wdma frame done
  207. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  208. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  209. /*********************/
  210. /***build cmdq finished***/
  211. /*********************/
  212. // TODO:
  213. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  214. // RUN forever!!!!
  215. BUG_ON(ret < 0);
  216. }
  217. #endif
  218. }
  219. static void _start_cmdq_trigger_loop(void)
  220. {
  221. #ifndef DDP_LK_BOOT
  222. int ret = 0;
  223. // this should be called only once because trigger loop will nevet stop
  224. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  225. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  226. #endif
  227. }
  228. static void _set_cmdq_config_handle_dirty(void)
  229. {
  230. #ifndef DDP_LK_BOOT
  231. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  232. cmdqRecFlush(pgc->cmdq_handle_config);
  233. #endif
  234. }
  235. static void _reset_cmdq_config_handle(void)
  236. {
  237. #ifndef DDP_LK_BOOT
  238. cmdqRecReset(pgc->cmdq_handle_config);
  239. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  240. #endif
  241. }
  242. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  243. {
  244. if (src && dst) {
  245. dst->inputFormat = src->fmt;
  246. dst->address = src->addr;
  247. dst->width = src->src_w;
  248. dst->height = src->src_h;
  249. dst->pitch = src->src_pitch;
  250. return 0;
  251. } else {
  252. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", src, dst);
  253. return -1;
  254. }
  255. }
  256. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  257. {
  258. if (src && dst) {
  259. dst->layer = src->layer;
  260. dst->layer_en = src->layer_en;
  261. dst->fmt = src->fmt;
  262. dst->addr = src->addr;
  263. dst->vaddr = src->vaddr;
  264. dst->src_x = src->src_x;
  265. dst->src_y = src->src_y;
  266. dst->src_w = src->src_w;
  267. dst->src_h = src->src_h;
  268. dst->src_pitch = src->src_pitch;
  269. dst->dst_x = src->dst_x;
  270. dst->dst_y = src->dst_y;
  271. dst->dst_w = src->dst_w;
  272. dst->dst_h = src->dst_h;
  273. dst->keyEn = src->keyEn;
  274. dst->key = src->key;
  275. dst->aen = src->aen;
  276. dst->alpha = src->alpha;
  277. dst->isDirty = src->isDirty;
  278. dst->buff_idx = src->buff_idx;
  279. dst->identity = src->identity;
  280. dst->connected_type = src->connected_type;
  281. dst->security = src->security;
  282. return 0;
  283. } else {
  284. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", src, dst);
  285. return -1;
  286. }
  287. }
  288. void _dump_lcm_info_by_video_printf(void)
  289. {
  290. int i = 0;
  291. LCM_DRIVER *l = NULL;
  292. LCM_PARAMS *p = NULL;
  293. disp_lcm_handle *plcm = pgc->plcm;
  294. if (plcm == NULL) {
  295. DISPERR("plcm is null\n");
  296. return;
  297. }
  298. l = plcm->drv;
  299. p = plcm->params;
  300. if (l && p) {
  301. video_printf("[LCM], name: %s\n", l->name);
  302. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  303. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  304. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  305. switch (p->lcm_if) {
  306. case LCM_INTERFACE_DSI0:
  307. video_printf("[LCM] interface: DSI0\n");
  308. break;
  309. case LCM_INTERFACE_DSI1:
  310. video_printf("[LCM] interface: DSI1\n");
  311. break;
  312. case LCM_INTERFACE_DPI0:
  313. video_printf("[LCM] interface: DPI0\n");
  314. break;
  315. case LCM_INTERFACE_DPI1:
  316. video_printf("[LCM] interface: DPI1\n");
  317. break;
  318. case LCM_INTERFACE_DBI0:
  319. video_printf("[LCM] interface: DBI0\n");
  320. break;
  321. default:
  322. video_printf("[LCM] interface: unknown\n");
  323. break;
  324. }
  325. switch (p->type) {
  326. case LCM_TYPE_DBI:
  327. video_printf("[LCM] Type: DBI\n");
  328. break;
  329. case LCM_TYPE_DSI:
  330. video_printf("[LCM] Type: DSI\n");
  331. break;
  332. case LCM_TYPE_DPI:
  333. video_printf("[LCM] Type: DPI\n");
  334. break;
  335. default:
  336. video_printf("[LCM] TYPE: unknown\n");
  337. break;
  338. }
  339. if (p->type == LCM_TYPE_DSI) {
  340. switch (p->dsi.mode) {
  341. case CMD_MODE:
  342. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  343. break;
  344. case SYNC_PULSE_VDO_MODE:
  345. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  346. break;
  347. case SYNC_EVENT_VDO_MODE:
  348. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  349. break;
  350. case BURST_VDO_MODE:
  351. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  352. break;
  353. default:
  354. video_printf("[LCM] DSI Mode: Unknown\n");
  355. break;
  356. }
  357. }
  358. if (p->type == LCM_TYPE_DSI) {
  359. video_printf("[LCM] LANE_NUM: %d,data_format: %d,vertical_sync_active: %d\n",p->dsi.LANE_NUM,p->dsi.data_format);
  360. #ifdef MY_TODO
  361. #error
  362. #endif
  363. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  364. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  365. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  366. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  367. }
  368. }
  369. return;
  370. }
  371. unsigned int mt_disp_parse_dfo_setting(void)
  372. {
  373. unsigned int i, j=0 ;
  374. char tmp[11];
  375. char *buffer = NULL;
  376. char *ptr = NULL;
  377. buffer = (char *)get_env("DFO");
  378. DISPMSG("env buffer = %s\n", buffer);
  379. if (buffer != NULL) {
  380. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  381. j = 0;
  382. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  383. ptr = strstr(buffer, disp_dfo_setting[i].name);
  384. if (ptr == NULL) continue;
  385. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  386. do {} while ((*ptr++) != ',');
  387. do {tmp[j++] = *ptr++;}
  388. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  389. disp_dfo_setting[i].value = atoi((const char*)tmp);
  390. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  391. }
  392. } else {
  393. DISPMSG("env buffer = NULL\n");
  394. }
  395. return 0;
  396. }
  397. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  398. {
  399. char *disp_name;
  400. int disp_value;
  401. unsigned int i = 0;
  402. if (string == NULL)
  403. return -1;
  404. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  405. disp_name = disp_dfo_setting[i].name;
  406. disp_value = disp_dfo_setting[i].value;
  407. if (!strcmp(disp_name, string)) {
  408. *value = disp_value;
  409. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  410. return 0;
  411. }
  412. }
  413. return 0;
  414. }
  415. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  416. int primary_display_is_lcm_connected(void)
  417. {
  418. return pgc->plcm->is_connected;
  419. }
  420. const char* primary_display_get_lcm_name(void)
  421. {
  422. return disp_lcm_get_name(pgc->plcm);
  423. }
  424. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  425. {
  426. if (pgc->plcm) {
  427. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  428. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  429. // otherwise we will have a panic in lk(root cause unknown).
  430. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  431. DISPERR("Invalid resolution: %dx%d\n", width, height);
  432. return -1;
  433. }
  434. if (primary_display_is_video_mode()) {
  435. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  436. return -1;
  437. }
  438. pgc->plcm->params->width = width;
  439. pgc->plcm->params->height = height;
  440. return 0;
  441. } else {
  442. return -1;
  443. }
  444. }
  445. int primary_display_init(char *lcm_name)
  446. {
  447. DISPFUNC();
  448. DISP_STATUS ret = DISP_STATUS_OK;
  449. DISP_MODULE_ENUM dst_module = 0;
  450. unsigned int lcm_fake_width = 0;
  451. unsigned int lcm_fake_height = 0;
  452. LCM_PARAMS *lcm_param = NULL;
  453. LCM_INTERFACE_ID lcm_id = LCM_INTERFACE_NOTDEFINED;
  454. dpmgr_init();
  455. #ifndef DDP_LK_BOOT
  456. mutex_init(&(pgc->lock));
  457. #endif
  458. _primary_path_lock();
  459. if (pgc->plcm == NULL)
  460. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  461. if (pgc->plcm == NULL) {
  462. DISPCHECK("disp_lcm_probe returns null\n");
  463. ret = DISP_STATUS_ERROR;
  464. goto done;
  465. } else {
  466. DISPCHECK("disp_lcm_probe SUCCESS\n");
  467. }
  468. lcm_param = disp_lcm_get_params(pgc->plcm);
  469. if (lcm_param == NULL) {
  470. DISPERR("get lcm params FAILED\n");
  471. ret = DISP_STATUS_ERROR;
  472. goto done;
  473. }
  474. if (primary_display_mode == DIRECT_LINK_MODE) {
  475. _build_path_direct_link();
  476. DISPCHECK("primary display is DIRECT LINK MODE\n");
  477. } else if (primary_display_mode == DECOUPLE_MODE) {
  478. _build_path_decouple();
  479. DISPCHECK("primary display is DECOUPLE MODE\n");
  480. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  481. _build_path_single_layer();
  482. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  483. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  484. _build_path_debug_rdma1_dsi0();
  485. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  486. } else {
  487. DISPCHECK("primary display mode is WRONG\n");
  488. }
  489. _build_cmdq_trigger_loop();
  490. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  491. _start_cmdq_trigger_loop();
  492. DISPCHECK("primary display START cmdq trigger loop finished\n");
  493. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  494. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  495. disp_ddp_path_config data_config;
  496. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  497. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  498. data_config.dst_w = disp_lcm_width(pgc->plcm);
  499. data_config.dst_h = disp_lcm_height(pgc->plcm);
  500. if (lcm_param->type == LCM_TYPE_DSI) {
  501. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  502. data_config.lcm_bpp = 24;
  503. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  504. data_config.lcm_bpp = 16;
  505. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  506. data_config.lcm_bpp = 18;
  507. } else if (lcm_param->type == LCM_TYPE_DPI) {
  508. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  509. data_config.lcm_bpp = 24;
  510. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  511. data_config.lcm_bpp = 16;
  512. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  513. data_config.lcm_bpp = 18;
  514. }
  515. data_config.dst_dirty = 1;
  516. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  517. ret = disp_lcm_init(pgc->plcm);
  518. if (primary_display_is_video_mode()) {
  519. if (lcm_param->dsi.lfr_enable == 1) {
  520. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  521. } else {
  522. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  523. }
  524. } else {
  525. }
  526. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  527. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  528. pgc->state = 1;
  529. done:
  530. _primary_path_unlock();
  531. return ret;
  532. }
  533. // register rdma done event
  534. int primary_display_wait_for_idle(void)
  535. {
  536. DISP_STATUS ret = DISP_STATUS_OK;
  537. DISPFUNC();
  538. _primary_path_lock();
  539. done:
  540. _primary_path_unlock();
  541. return ret;
  542. }
  543. int primary_display_wait_for_dump(void)
  544. {
  545. return 0;
  546. }
  547. static long int get_current_time_us(void)
  548. {
  549. return get_timer(0);
  550. }
  551. int priamry_display_wait_for_vsync(void)
  552. {
  553. int ret = 0;
  554. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  555. if (ret == -2) {
  556. DISPCHECK("vsync for primary display path not enabled yet\n");
  557. return -1;
  558. }
  559. // pgc->last_vsync_tick = get_current_time_us();
  560. pgc->last_vsync_tick = 0;
  561. return 0;
  562. }
  563. int primary_display_suspend(void)
  564. {
  565. DISP_STATUS ret = DISP_STATUS_OK;
  566. DISPFUNC();
  567. _primary_path_lock();
  568. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  569. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  570. #ifndef DDP_LK_BOOT
  571. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  572. #endif
  573. disp_path_clock_off("Primary Display Path");
  574. pgc->state = 0;
  575. done:
  576. _primary_path_unlock();
  577. return ret;
  578. }
  579. int primary_display_resume(void)
  580. {
  581. DISP_STATUS ret = DISP_STATUS_OK;
  582. DISPFUNC();
  583. _primary_path_lock();
  584. disp_path_clock_on("Primary Display Path");
  585. pgc->state = 1;
  586. done:
  587. _primary_path_unlock();
  588. return ret;
  589. }
  590. int primary_display_is_alive(void)
  591. {
  592. unsigned int temp = 0;
  593. DISPFUNC();
  594. _primary_path_lock();
  595. temp = pgc->state;
  596. _primary_path_unlock();
  597. return temp;
  598. }
  599. int primary_display_is_sleepd(void)
  600. {
  601. unsigned int temp = 0;
  602. DISPFUNC();
  603. _primary_path_lock();
  604. temp = !pgc->state;
  605. _primary_path_unlock();
  606. return temp;
  607. }
  608. #ifdef MTK_ROUND_CORNER_SUPPORT
  609. int round_corner_Bpp = 4;
  610. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  611. {
  612. if (pgc->plcm == NULL) {
  613. return NULL;
  614. }
  615. if (pgc->plcm->params) {
  616. return &(pgc->plcm->params->round_corner_params);
  617. } else {
  618. DISPERR("lcm_params is null!\n");
  619. return NULL;
  620. }
  621. }
  622. int disp_get_round_corner_size(void)
  623. {
  624. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  625. int pitch = DISP_GetScreenWidth();
  626. int size = 0;
  627. if (corner_params)
  628. size = corner_params->h * pitch * 2 * round_corner_Bpp;
  629. else
  630. DISPERR("corner_params is null!\n");
  631. return size;
  632. }
  633. int disp_get_round_corner_Bpp(void)
  634. {
  635. return round_corner_Bpp;
  636. }
  637. #endif
  638. int primary_display_get_width(void)
  639. {
  640. if (pgc->plcm == NULL) {
  641. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  642. DISPDBG("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  643. if (pgc->plcm == NULL)
  644. return 0;
  645. }
  646. if (pgc->plcm->params) {
  647. return pgc->plcm->params->width;
  648. } else {
  649. DISPERR("lcm_params is null!\n");
  650. return 0;
  651. }
  652. }
  653. int primary_display_get_height(void)
  654. {
  655. if (pgc->plcm == NULL) {
  656. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  657. DISPDBG("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  658. if (pgc->plcm == NULL)
  659. return 0;
  660. }
  661. if (pgc->plcm->params) {
  662. return pgc->plcm->params->height;
  663. } else {
  664. DISPERR("lcm_params is null!\n");
  665. return 0;
  666. }
  667. }
  668. int primary_display_get_bpp(void)
  669. {
  670. return 32;
  671. }
  672. int primary_display_get_info(void *dispif_info)
  673. {
  674. #if 0
  675. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  676. switch (pgc->lcm_param->type) {
  677. case LCM_TYPE_DBI: {
  678. dispif_info->displayType = DISPIF_TYPE_DBI;
  679. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  680. dispif_info->isHwVsyncAvailable = 1;
  681. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  682. break;
  683. }
  684. case LCM_TYPE_DPI: {
  685. dispif_info->displayType = DISPIF_TYPE_DPI0;
  686. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  687. dispif_info->isHwVsyncAvailable = 1;
  688. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  689. break;
  690. }
  691. case LCM_TYPE_DSI: {
  692. dispif_info->displayType = DISPIF_TYPE_DSI0;
  693. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  694. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  695. dispif_info->isHwVsyncAvailable = 1;
  696. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  697. } else {
  698. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  699. dispif_info->isHwVsyncAvailable = 1;
  700. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  701. }
  702. break;
  703. }
  704. default:
  705. break;
  706. }
  707. #ifdef MY_TODO
  708. #error
  709. if (disp_if_drv->get_panel_color_format()) {
  710. switch (disp_if_drv->get_panel_color_format()) {
  711. case PANEL_COLOR_FORMAT_RGB565:
  712. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  713. case PANEL_COLOR_FORMAT_RGB666:
  714. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  715. case PANEL_COLOR_FORMAT_RGB888:
  716. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  717. default:
  718. break;
  719. }
  720. }
  721. #endif
  722. dispif_info->displayWidth = primary_display_get_width();
  723. dispif_info->displayHeight = primary_display_get_height();
  724. #ifdef MY_TODO
  725. #error
  726. dispif_info->vsyncFPS = lcd_fps;
  727. #endif
  728. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  729. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  730. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  731. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  732. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  733. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  734. } else {
  735. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  736. }
  737. dispif_info->isConnected = 1;
  738. #ifdef MY_TODO
  739. #error
  740. {
  741. LCM_PARAMS lcm_params_temp;
  742. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  743. if (lcm_drv) {
  744. lcm_drv->get_params(&lcm_params_temp);
  745. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  746. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  747. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  748. } else {
  749. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  750. }
  751. }
  752. #endif
  753. #endif
  754. return 0;
  755. }
  756. int primary_display_get_pages(void)
  757. {
  758. return 3;
  759. }
  760. int primary_display_config_output()
  761. {
  762. return 0;
  763. }
  764. int primary_display_diagnose(void)
  765. {
  766. int ret = 0;
  767. dpmgr_check_status(pgc->dpmgr_handle);
  768. return ret;
  769. }
  770. int primary_display_trigger(int blocking)
  771. {
  772. int ret = 0;
  773. DISPFUNC();
  774. int x=0, y=0;
  775. int width = 0, height =0;
  776. x = disp_lcm_x(pgc->plcm);
  777. y = disp_lcm_y(pgc->plcm);
  778. width = disp_lcm_width(pgc->plcm);
  779. height = disp_lcm_height(pgc->plcm);
  780. _primary_path_lock();
  781. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  782. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  783. if (primary_display_is_video_mode()) {
  784. _primary_path_unlock();
  785. return 0;
  786. }
  787. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  788. }
  789. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  790. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  791. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  792. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  793. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  794. }
  795. //_set_cmdq_config_handle_dirty();
  796. //_reset_cmdq_config_handle();
  797. //if(blocking)
  798. {
  799. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  800. }
  801. } else if (pgc->mode == DECOUPLE_MODE) {
  802. DISPCHECK("trigger mode: DECOUPLE\n");
  803. if (pgc->need_trigger_overlay) {
  804. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  805. if (blocking) {
  806. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  807. }
  808. } else {
  809. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  810. // this request of trigger should be called by AAL or ovl2mem done event
  811. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  812. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  813. }
  814. _set_cmdq_config_handle_dirty();
  815. _reset_cmdq_config_handle();
  816. if (blocking) {
  817. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  818. }
  819. }
  820. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  821. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  822. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  823. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  824. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  825. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  826. }
  827. if (blocking) {
  828. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  829. }
  830. } else {
  831. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  832. }
  833. _primary_path_unlock();
  834. //primary_display_diagnose();
  835. return ret;
  836. }
  837. int primary_display_config_input(disp_input_config* input)
  838. {
  839. int ret = 0;
  840. int i=0;
  841. int layer =0;
  842. DISPFUNC();
  843. disp_ddp_path_config data_config;
  844. // all dirty should be cleared in dpmgr_path_get_last_config()
  845. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  846. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  847. data_config.dst_dirty = 0;
  848. data_config.ovl_dirty = 0;
  849. data_config.rdma_dirty = 0;
  850. data_config.wdma_dirty = 0;
  851. _primary_path_lock();
  852. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  853. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  854. if (primary_display_is_video_mode()) {
  855. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  856. }
  857. }
  858. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  859. data_config.ovl_dirty = 1;
  860. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  861. // this is used for decouple mode, to indicate whether we need to trigger ovl
  862. pgc->need_trigger_overlay = 1;
  863. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  864. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  865. data_config.rdma_dirty= 1;
  866. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  867. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  868. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  869. data_config.rdma_dirty= 1;
  870. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  871. // TODO: should use wait_event_timeout_or_idle
  872. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  873. }
  874. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  875. } else {
  876. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  877. }
  878. _primary_path_unlock();
  879. return ret;
  880. }
  881. int primary_display_is_video_mode(void)
  882. {
  883. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  884. return disp_lcm_is_video_mode(pgc->plcm);
  885. }
  886. int primary_display_get_vsync_interval(void)
  887. {
  888. int ret = 0;
  889. unsigned int time0 = 0;
  890. unsigned int time1 = 0;
  891. unsigned int lcd_time = 0;
  892. pgc->plcm->is_connected = false;
  893. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  894. if (ret <= 0)
  895. goto fail;
  896. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  897. if (ret <= 0)
  898. goto fail;
  899. // because we are polling irq status, so the first event should be ignored
  900. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  901. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  902. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  903. if (ret <= 0)
  904. goto fail;
  905. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  906. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  907. if (ret > 0) {
  908. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  909. } else
  910. goto fail;
  911. lcd_time = (time1 - time0)/2;
  912. pgc->plcm->is_connected = true;
  913. if (0 != lcd_time)
  914. return (100000000/lcd_time);
  915. else
  916. return (6000);
  917. fail:
  918. DISPERR("wait event fail\n");
  919. return 0;
  920. }
  921. int primary_display_setbacklight(unsigned int level)
  922. {
  923. DISPMSG("lk %s level=%d\n",__func__,level);
  924. int ret=0;
  925. if (pgc->dpmgr_handle == NULL) {
  926. DISPCHECK("lk set backlight early!\n");
  927. return 0;
  928. }
  929. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  930. DISPCHECK("primary display path is busy\n");
  931. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  932. DISPCHECK("wait frame done ret:%d\n", ret);
  933. }
  934. disp_lcm_set_backlight(pgc->plcm,level);
  935. return 0;
  936. }
  937. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  938. /***********************/
  939. /*****Legacy DISP API*****/
  940. /***********************/
  941. UINT32 DISP_GetScreenWidth(void)
  942. {
  943. return primary_display_get_width();
  944. }
  945. UINT32 DISP_GetScreenHeight(void)
  946. {
  947. return primary_display_get_height();
  948. }
  949. UINT32 DISP_GetActiveHeight(void)
  950. {
  951. if (pgc->plcm == NULL) {
  952. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  953. DISPERR("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  954. if (pgc->plcm == NULL)return 0;
  955. }
  956. if (pgc->plcm->params) {
  957. return pgc->plcm->params->physical_height;
  958. } else {
  959. DISPERR("lcm_params is null!\n");
  960. return 0;
  961. }
  962. }
  963. UINT32 DISP_GetActiveWidth(void)
  964. {
  965. if (pgc->plcm == NULL) {
  966. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  967. DISPERR("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  968. if (pgc->plcm == NULL)return 0;
  969. }
  970. if (pgc->plcm->params) {
  971. return pgc->plcm->params->physical_width;
  972. } else {
  973. DISPERR("lcm_params is null!\n");
  974. return 0;
  975. }
  976. }
  977. int primary_display_capture_framebuffer(unsigned int *pbuf)
  978. {
  979. return 0;
  980. }
  981. UINT32 DISP_GetPanelBPP(void)
  982. {
  983. #if 0
  984. PANEL_COLOR_FORMAT fmt;
  985. disp_drv_init_context();
  986. if (disp_if_drv->get_panel_color_format == NULL) {
  987. return DISP_STATUS_NOT_IMPLEMENTED;
  988. }
  989. fmt = disp_if_drv->get_panel_color_format();
  990. switch (fmt) {
  991. case PANEL_COLOR_FORMAT_RGB332:
  992. return 8;
  993. case PANEL_COLOR_FORMAT_RGB444:
  994. return 12;
  995. case PANEL_COLOR_FORMAT_RGB565:
  996. return 16;
  997. case PANEL_COLOR_FORMAT_RGB666:
  998. return 18;
  999. case PANEL_COLOR_FORMAT_RGB888:
  1000. return 24;
  1001. default:
  1002. return 0;
  1003. }
  1004. #endif
  1005. return 0;
  1006. }
  1007. UINT32 DISP_GetScreenBpp(void)
  1008. {
  1009. return disp_fb_bpp;
  1010. }
  1011. UINT32 DISP_GetPages(void)
  1012. {
  1013. return disp_fb_pages; // Double Buffers
  1014. }
  1015. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1016. #define DAL_BPP (2)
  1017. #define DAL_WIDTH (DISP_GetScreenWidth())
  1018. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1019. UINT32 DAL_GetLayerSize(void)
  1020. {
  1021. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1022. }
  1023. UINT32 DISP_GetFBRamSize(void)
  1024. {
  1025. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1026. }
  1027. unsigned int DISP_GetVRamSize(void)
  1028. {
  1029. static UINT32 vramSize = 0;
  1030. unsigned int fb_ram_size =0;
  1031. //FB RAM(n blocks)+(Assert layer size)
  1032. if (0 == vramSize) {
  1033. vramSize = DISP_GetFBRamSize();
  1034. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1035. fb_ram_size = vramSize;
  1036. vramSize += DAL_GetLayerSize();
  1037. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1038. #ifdef MTK_ROUND_CORNER_SUPPORT
  1039. fb_ram_size = vramSize;
  1040. vramSize += disp_get_round_corner_size();
  1041. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1042. #endif
  1043. #if 0
  1044. if (g_is_64bit_kernel) {
  1045. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1046. } else {
  1047. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1048. }
  1049. #else
  1050. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1051. #endif
  1052. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1053. }
  1054. return vramSize;
  1055. }