primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. //#include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. #include <video.h>
  44. //#include<linux/timer.h>
  45. #define DDP_LK_BOOT
  46. #ifndef HZ
  47. #define HZ 100
  48. #endif
  49. #ifdef DDP_LK_BOOT
  50. typedef void * cmdqRecHandle;
  51. #endif
  52. #define ALIGN_TO(x, n) \
  53. (((x) + ((n) - 1)) & ~((n) - 1))
  54. int primary_display_use_cmdq = CMDQ_DISABLE;
  55. int primary_display_use_m4u = 0;
  56. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  57. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  58. static UINT32 disp_fb_pages = 3; ///double buffer
  59. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  60. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  61. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  62. typedef struct _disp_dfo_item {
  63. char name[32];
  64. int value;
  65. } disp_dfo_item_t;
  66. static disp_dfo_item_t disp_dfo_setting[] = {
  67. {"LCM_FAKE_WIDTH", 0},
  68. {"LCM_FAKE_HEIGHT", 0},
  69. {"DISP_DEBUG_SWITCH", 0}
  70. };
  71. typedef struct {
  72. int state;
  73. int need_trigger_overlay;
  74. DISP_PRIMARY_PATH_MODE mode;
  75. unsigned int last_vsync_tick;
  76. #ifndef DDP_LK_BOOT
  77. struct mutex lock;
  78. #endif
  79. disp_lcm_handle * plcm;
  80. cmdqRecHandle cmdq_handle_config;
  81. cmdqRecHandle cmdq_handle_trigger;
  82. disp_path_handle dpmgr_handle;
  83. disp_path_handle ovl2mem_path_handle;
  84. } display_primary_path_context;
  85. #define pgc _get_context()
  86. static display_primary_path_context* _get_context(void)
  87. {
  88. static int is_context_inited = 0;
  89. static display_primary_path_context g_context;
  90. if (!is_context_inited) {
  91. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  92. is_context_inited = 1;
  93. }
  94. return &g_context;
  95. }
  96. static void _primary_path_lock(void)
  97. {
  98. #ifndef DDP_LK_BOOT
  99. disp_sw_mutex_lock(&(pgc->lock));
  100. #endif
  101. }
  102. static void _primary_path_unlock(void)
  103. {
  104. #ifndef DDP_LK_BOOT
  105. disp_sw_mutex_unlock(&(pgc->lock));
  106. #endif
  107. }
  108. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  109. {
  110. if (plcm == NULL) {
  111. DISPERR("plcm is null\n");
  112. return DISP_MODULE_UNKNOWN;
  113. }
  114. if (plcm->params->type == LCM_TYPE_DSI) {
  115. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  116. return DISP_MODULE_DSI0;
  117. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  118. return DISP_MODULE_DSI1;
  119. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  120. return DISP_MODULE_DSIDUAL;
  121. } else {
  122. return DISP_MODULE_DSI0;
  123. }
  124. } else if (plcm->params->type == LCM_TYPE_DPI) {
  125. return DISP_MODULE_DPI;
  126. } else {
  127. DISPERR("can't find primary path dst module\n");
  128. return DISP_MODULE_UNKNOWN;
  129. }
  130. }
  131. static int _build_path_direct_link(void)
  132. {
  133. int ret = 0;
  134. DISP_MODULE_ENUM dst_module = 0;
  135. DISPFUNC();
  136. pgc->mode = DIRECT_LINK_MODE;
  137. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  138. if (pgc->dpmgr_handle) {
  139. DISPCHECK("dpmgr create path SUCCESS(0x%p)\n", pgc->dpmgr_handle);
  140. } else {
  141. DISPCHECK("dpmgr create path FAIL\n");
  142. return -1;
  143. }
  144. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  145. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  146. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  147. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  148. return ret;
  149. }
  150. static int _build_path_decouple(void)
  151. {
  152. return 0;
  153. }
  154. static int _build_path_single_layer(void)
  155. {
  156. return 0;
  157. }
  158. static int _build_path_debug_rdma1_dsi0(void)
  159. {
  160. int ret = 0;
  161. DISP_MODULE_ENUM dst_module = 0;
  162. DISPFUNC();
  163. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  164. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  165. if (pgc->dpmgr_handle) {
  166. DISPCHECK("dpmgr create path SUCCESS(0x%p)\n", pgc->dpmgr_handle);
  167. } else {
  168. DISPCHECK("dpmgr create path FAIL\n");
  169. return -1;
  170. }
  171. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  172. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  173. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  174. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  175. return ret;
  176. }
  177. static void _build_cmdq_trigger_loop(void)
  178. {
  179. #ifndef DDP_LK_BOOT
  180. int ret = 0;
  181. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  182. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  183. cmdqRecReset(pgc->cmdq_handle_trigger);
  184. if (primary_display_is_video_mode()) {
  185. // wait and clear stream_done
  186. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  187. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  188. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  189. } else {
  190. // only in DSI Command mode we need to wait these
  191. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  192. // no internal te on fpga now.
  193. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  194. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  195. // block config threads, we'll about to update frame
  196. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  197. // only in DSI command mode we need to enable mutex explicitly
  198. // WRITE mutex enable
  199. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  200. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  201. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  202. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  203. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  204. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  205. // polling DSI idle
  206. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  207. // polling wdma frame done
  208. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  209. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  210. /*********************/
  211. /***build cmdq finished***/
  212. /*********************/
  213. // TODO:
  214. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  215. // RUN forever!!!!
  216. BUG_ON(ret < 0);
  217. }
  218. #endif
  219. }
  220. static void _start_cmdq_trigger_loop(void)
  221. {
  222. #ifndef DDP_LK_BOOT
  223. int ret = 0;
  224. // this should be called only once because trigger loop will nevet stop
  225. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  226. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  227. #endif
  228. }
  229. static void _set_cmdq_config_handle_dirty(void)
  230. {
  231. #ifndef DDP_LK_BOOT
  232. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  233. cmdqRecFlush(pgc->cmdq_handle_config);
  234. #endif
  235. }
  236. static void _reset_cmdq_config_handle(void)
  237. {
  238. #ifndef DDP_LK_BOOT
  239. cmdqRecReset(pgc->cmdq_handle_config);
  240. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  241. #endif
  242. }
  243. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  244. {
  245. if (src && dst) {
  246. dst->inputFormat = src->fmt;
  247. dst->address = src->addr;
  248. dst->width = src->src_w;
  249. dst->height = src->src_h;
  250. dst->pitch = src->src_pitch;
  251. return 0;
  252. } else {
  253. DISPERR("src(0x%p) or dst(0x%p) is null\n", src, dst);
  254. return -1;
  255. }
  256. }
  257. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  258. {
  259. if (src && dst) {
  260. dst->layer = src->layer;
  261. dst->layer_en = src->layer_en;
  262. dst->fmt = src->fmt;
  263. dst->addr = src->addr;
  264. dst->vaddr = src->vaddr;
  265. dst->src_x = src->src_x;
  266. dst->src_y = src->src_y;
  267. dst->src_w = src->src_w;
  268. dst->src_h = src->src_h;
  269. dst->src_pitch = src->src_pitch;
  270. dst->dst_x = src->dst_x;
  271. dst->dst_y = src->dst_y;
  272. dst->dst_w = src->dst_w;
  273. dst->dst_h = src->dst_h;
  274. dst->keyEn = src->keyEn;
  275. dst->key = src->key;
  276. dst->aen = src->aen;
  277. dst->alpha = src->alpha;
  278. dst->isDirty = src->isDirty;
  279. dst->buff_idx = src->buff_idx;
  280. dst->identity = src->identity;
  281. dst->connected_type = src->connected_type;
  282. dst->security = src->security;
  283. return 0;
  284. } else {
  285. DISPERR("src(0x%p) or dst(0x%p) is null\n", src, dst);
  286. return -1;
  287. }
  288. }
  289. void _dump_lcm_info_by_video_printf(void)
  290. {
  291. //int i = 0;
  292. LCM_DRIVER *l = NULL;
  293. LCM_PARAMS *p = NULL;
  294. disp_lcm_handle *plcm = pgc->plcm;
  295. if (plcm == NULL) {
  296. DISPERR("plcm is null\n");
  297. return;
  298. }
  299. l = plcm->drv;
  300. p = plcm->params;
  301. if (l && p) {
  302. video_printf("[LCM], name: %s\n", l->name);
  303. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  304. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  305. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  306. switch (p->lcm_if) {
  307. case LCM_INTERFACE_DSI0:
  308. video_printf("[LCM] interface: DSI0\n");
  309. break;
  310. case LCM_INTERFACE_DSI1:
  311. video_printf("[LCM] interface: DSI1\n");
  312. break;
  313. case LCM_INTERFACE_DPI0:
  314. video_printf("[LCM] interface: DPI0\n");
  315. break;
  316. case LCM_INTERFACE_DPI1:
  317. video_printf("[LCM] interface: DPI1\n");
  318. break;
  319. case LCM_INTERFACE_DBI0:
  320. video_printf("[LCM] interface: DBI0\n");
  321. break;
  322. default:
  323. video_printf("[LCM] interface: unknown\n");
  324. break;
  325. }
  326. switch (p->type) {
  327. case LCM_TYPE_DBI:
  328. video_printf("[LCM] Type: DBI\n");
  329. break;
  330. case LCM_TYPE_DSI:
  331. video_printf("[LCM] Type: DSI\n");
  332. break;
  333. case LCM_TYPE_DPI:
  334. video_printf("[LCM] Type: DPI\n");
  335. break;
  336. default:
  337. video_printf("[LCM] TYPE: unknown\n");
  338. break;
  339. }
  340. if (p->type == LCM_TYPE_DSI) {
  341. switch (p->dsi.mode) {
  342. case CMD_MODE:
  343. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  344. break;
  345. case SYNC_PULSE_VDO_MODE:
  346. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  347. break;
  348. case SYNC_EVENT_VDO_MODE:
  349. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  350. break;
  351. case BURST_VDO_MODE:
  352. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  353. break;
  354. default:
  355. video_printf("[LCM] DSI Mode: Unknown\n");
  356. break;
  357. }
  358. }
  359. if (p->type == LCM_TYPE_DSI) {
  360. video_printf("[LCM] LANE_NUM: %d,data_format: %d,"
  361. " vertical_sync_active: %d\n",
  362. p->dsi.LANE_NUM,
  363. p->dsi.data_format.format,
  364. p->dsi.vertical_sync_active);
  365. #ifdef MY_TODO
  366. #error
  367. #endif
  368. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d,"
  369. "hact: %d, hbp: %d, hfp: %d, hblank: %d\n",
  370. p->dsi.vertical_sync_active,
  371. p->dsi.vertical_backporch,
  372. p->dsi.vertical_frontporch,
  373. p->dsi.vertical_active_line,
  374. p->dsi.horizontal_sync_active,
  375. p->dsi.horizontal_backporch,
  376. p->dsi.horizontal_frontporch,
  377. p->dsi.horizontal_blanking_pixel);
  378. video_printf("[LCM] pll_select: %d, pll_div1: %d,"
  379. " pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",
  380. p->dsi.pll_select,
  381. p->dsi.pll_div1,
  382. p->dsi.pll_div2,
  383. p->dsi.fbk_div,
  384. p->dsi.fbk_sel,
  385. p->dsi.rg_bir);
  386. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d,"
  387. " dsi_clock: %d, ssc_range: %d, ssc_disable: %d,"
  388. " compatibility_for_nvk: %d, cont_clock: %d\n",
  389. p->dsi.rg_bic,
  390. p->dsi.rg_bp,
  391. p->dsi.PLL_CLOCK,
  392. p->dsi.dsi_clock,
  393. p->dsi.ssc_range,
  394. p->dsi.ssc_disable,
  395. p->dsi.compatibility_for_nvk,
  396. p->dsi.cont_clock);
  397. video_printf("[LCM] lcm_ext_te_enable: %d,"
  398. " noncont_clock: %d, noncont_clock_period: %d\n",
  399. p->dsi.lcm_ext_te_enable,
  400. p->dsi.noncont_clock,
  401. p->dsi.noncont_clock_period);
  402. }
  403. }
  404. return;
  405. }
  406. unsigned int mt_disp_parse_dfo_setting(void)
  407. {
  408. unsigned int i, j=0 ;
  409. char tmp[11];
  410. char *buffer = NULL;
  411. char *ptr = NULL;
  412. buffer = (char *)get_env("DFO");
  413. DISPMSG("env buffer = %s\n", buffer);
  414. if (buffer != NULL) {
  415. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  416. j = 0;
  417. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  418. ptr = strstr(buffer, disp_dfo_setting[i].name);
  419. if (ptr == NULL) continue;
  420. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  421. do {} while ((*ptr++) != ',');
  422. do {tmp[j++] = *ptr++;}
  423. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  424. disp_dfo_setting[i].value = atoi((const char*)tmp);
  425. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  426. }
  427. } else {
  428. DISPMSG("env buffer = NULL\n");
  429. }
  430. return 0;
  431. }
  432. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  433. {
  434. char *disp_name;
  435. int disp_value;
  436. unsigned int i = 0;
  437. if (string == NULL)
  438. return -1;
  439. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  440. disp_name = disp_dfo_setting[i].name;
  441. disp_value = disp_dfo_setting[i].value;
  442. if (!strcmp(disp_name, string)) {
  443. *value = disp_value;
  444. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  445. return 0;
  446. }
  447. }
  448. return 0;
  449. }
  450. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  451. int primary_display_is_lcm_connected(void)
  452. {
  453. return pgc->plcm->is_connected;
  454. }
  455. const char* primary_display_get_lcm_name(void)
  456. {
  457. return disp_lcm_get_name(pgc->plcm);
  458. }
  459. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  460. {
  461. if (pgc->plcm) {
  462. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  463. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  464. // otherwise we will have a panic in lk(root cause unknown).
  465. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  466. DISPERR("Invalid resolution: %dx%d\n", width, height);
  467. return -1;
  468. }
  469. if (primary_display_is_video_mode()) {
  470. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  471. return -1;
  472. }
  473. pgc->plcm->params->width = width;
  474. pgc->plcm->params->height = height;
  475. return 0;
  476. } else {
  477. return -1;
  478. }
  479. }
  480. int primary_display_init(char *lcm_name)
  481. {
  482. DISPFUNC();
  483. DISP_STATUS ret = DISP_STATUS_OK;
  484. //DISP_MODULE_ENUM dst_module = 0;
  485. //unsigned int lcm_fake_width = 0;
  486. //unsigned int lcm_fake_height = 0;
  487. LCM_PARAMS *lcm_param = NULL;
  488. //LCM_INTERFACE_ID lcm_id = LCM_INTERFACE_NOTDEFINED;
  489. dpmgr_init();
  490. #ifndef DDP_LK_BOOT
  491. mutex_init(&(pgc->lock));
  492. #endif
  493. _primary_path_lock();
  494. if (pgc->plcm == NULL)
  495. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  496. if (pgc->plcm == NULL) {
  497. DISPCHECK("disp_lcm_probe returns null\n");
  498. ret = DISP_STATUS_ERROR;
  499. goto done;
  500. } else {
  501. DISPCHECK("disp_lcm_probe SUCCESS\n");
  502. }
  503. lcm_param = disp_lcm_get_params(pgc->plcm);
  504. if (lcm_param == NULL) {
  505. DISPERR("get lcm params FAILED\n");
  506. ret = DISP_STATUS_ERROR;
  507. goto done;
  508. }
  509. if (primary_display_mode == DIRECT_LINK_MODE) {
  510. _build_path_direct_link();
  511. DISPCHECK("primary display is DIRECT LINK MODE\n");
  512. } else if (primary_display_mode == DECOUPLE_MODE) {
  513. _build_path_decouple();
  514. DISPCHECK("primary display is DECOUPLE MODE\n");
  515. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  516. _build_path_single_layer();
  517. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  518. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  519. _build_path_debug_rdma1_dsi0();
  520. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  521. } else {
  522. DISPCHECK("primary display mode is WRONG\n");
  523. }
  524. _build_cmdq_trigger_loop();
  525. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  526. _start_cmdq_trigger_loop();
  527. DISPCHECK("primary display START cmdq trigger loop finished\n");
  528. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  529. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  530. disp_ddp_path_config data_config;
  531. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  532. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  533. data_config.dst_w = disp_lcm_width(pgc->plcm);
  534. data_config.dst_h = disp_lcm_height(pgc->plcm);
  535. if (lcm_param->type == LCM_TYPE_DSI) {
  536. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  537. data_config.lcm_bpp = 24;
  538. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  539. data_config.lcm_bpp = 16;
  540. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  541. data_config.lcm_bpp = 18;
  542. } else if (lcm_param->type == LCM_TYPE_DPI) {
  543. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  544. data_config.lcm_bpp = 24;
  545. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  546. data_config.lcm_bpp = 16;
  547. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  548. data_config.lcm_bpp = 18;
  549. }
  550. data_config.dst_dirty = 1;
  551. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  552. ret = disp_lcm_init(pgc->plcm);
  553. if (primary_display_is_video_mode()) {
  554. if (lcm_param->dsi.lfr_enable == 1) {
  555. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  556. } else {
  557. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  558. }
  559. } else {
  560. }
  561. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  562. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  563. pgc->state = 1;
  564. done:
  565. _primary_path_unlock();
  566. return ret;
  567. }
  568. // register rdma done event
  569. int primary_display_wait_for_idle(void)
  570. {
  571. DISP_STATUS ret = DISP_STATUS_OK;
  572. DISPFUNC();
  573. _primary_path_lock();
  574. _primary_path_unlock();
  575. return ret;
  576. }
  577. int primary_display_wait_for_dump(void)
  578. {
  579. return 0;
  580. }
  581. static long int get_current_time_us(void)
  582. {
  583. return get_timer(0);
  584. }
  585. int priamry_display_wait_for_vsync(void)
  586. {
  587. int ret = 0;
  588. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  589. if (ret == -2) {
  590. DISPCHECK("vsync for primary display path not enabled yet\n");
  591. return -1;
  592. }
  593. // pgc->last_vsync_tick = get_current_time_us();
  594. pgc->last_vsync_tick = 0;
  595. return 0;
  596. }
  597. int primary_display_suspend(void)
  598. {
  599. DISP_STATUS ret = DISP_STATUS_OK;
  600. DISPFUNC();
  601. _primary_path_lock();
  602. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  603. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  604. #ifndef DDP_LK_BOOT
  605. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  606. #endif
  607. //disp_path_clock_off("Primary Display Path");
  608. pgc->state = 0;
  609. //done:
  610. _primary_path_unlock();
  611. return ret;
  612. }
  613. int primary_display_resume(void)
  614. {
  615. DISP_STATUS ret = DISP_STATUS_OK;
  616. DISPFUNC();
  617. _primary_path_lock();
  618. //disp_path_clock_on("Primary Display Path");
  619. pgc->state = 1;
  620. //done:
  621. _primary_path_unlock();
  622. return ret;
  623. }
  624. int primary_display_is_alive(void)
  625. {
  626. unsigned int temp = 0;
  627. DISPFUNC();
  628. _primary_path_lock();
  629. temp = pgc->state;
  630. _primary_path_unlock();
  631. return temp;
  632. }
  633. int primary_display_is_sleepd(void)
  634. {
  635. unsigned int temp = 0;
  636. DISPFUNC();
  637. _primary_path_lock();
  638. temp = !pgc->state;
  639. _primary_path_unlock();
  640. return temp;
  641. }
  642. #ifdef MTK_ROUND_CORNER_SUPPORT
  643. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  644. {
  645. if (pgc->plcm == NULL) {
  646. return NULL;
  647. }
  648. if (pgc->plcm->params) {
  649. return &(pgc->plcm->params->round_corner_params);
  650. } else {
  651. DISPERR("lcm_params is null!\n");
  652. return NULL;
  653. }
  654. }
  655. int disp_get_round_corner_size(void)
  656. {
  657. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  658. int pitch = DISP_GetScreenWidth();
  659. int size = 0;
  660. if (corner_params->round_corner_en) {
  661. if (corner_params)
  662. size = corner_params->h * pitch * 2 * 2;
  663. else
  664. DISPERR("corner_params is null!\n");
  665. }
  666. return size;
  667. }
  668. #endif
  669. int primary_display_get_width(void)
  670. {
  671. if (pgc->plcm == NULL) {
  672. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  673. DISPDBG("lcm handle is null, after probe:0x%p\n",pgc->plcm);
  674. if (pgc->plcm == NULL)
  675. return 0;
  676. }
  677. if (pgc->plcm->params) {
  678. return pgc->plcm->params->width;
  679. } else {
  680. DISPERR("lcm_params is null!\n");
  681. return 0;
  682. }
  683. }
  684. int primary_display_get_height(void)
  685. {
  686. if (pgc->plcm == NULL) {
  687. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  688. DISPDBG("lcm handle is null, after probe:0x%p\n",pgc->plcm);
  689. if (pgc->plcm == NULL)
  690. return 0;
  691. }
  692. if (pgc->plcm->params) {
  693. return pgc->plcm->params->height;
  694. } else {
  695. DISPERR("lcm_params is null!\n");
  696. return 0;
  697. }
  698. }
  699. int primary_display_get_bpp(void)
  700. {
  701. return 32;
  702. }
  703. int primary_display_get_info(void *dispif_info)
  704. {
  705. #if 0
  706. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  707. switch (pgc->lcm_param->type) {
  708. case LCM_TYPE_DBI: {
  709. dispif_info->displayType = DISPIF_TYPE_DBI;
  710. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  711. dispif_info->isHwVsyncAvailable = 1;
  712. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  713. break;
  714. }
  715. case LCM_TYPE_DPI: {
  716. dispif_info->displayType = DISPIF_TYPE_DPI0;
  717. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  718. dispif_info->isHwVsyncAvailable = 1;
  719. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  720. break;
  721. }
  722. case LCM_TYPE_DSI: {
  723. dispif_info->displayType = DISPIF_TYPE_DSI0;
  724. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  725. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  726. dispif_info->isHwVsyncAvailable = 1;
  727. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  728. } else {
  729. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  730. dispif_info->isHwVsyncAvailable = 1;
  731. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  732. }
  733. break;
  734. }
  735. default:
  736. break;
  737. }
  738. #ifdef MY_TODO
  739. #error
  740. if (disp_if_drv->get_panel_color_format()) {
  741. switch (disp_if_drv->get_panel_color_format()) {
  742. case PANEL_COLOR_FORMAT_RGB565:
  743. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  744. case PANEL_COLOR_FORMAT_RGB666:
  745. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  746. case PANEL_COLOR_FORMAT_RGB888:
  747. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  748. default:
  749. break;
  750. }
  751. }
  752. #endif
  753. dispif_info->displayWidth = primary_display_get_width();
  754. dispif_info->displayHeight = primary_display_get_height();
  755. #ifdef MY_TODO
  756. #error
  757. dispif_info->vsyncFPS = lcd_fps;
  758. #endif
  759. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  760. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  761. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  762. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  763. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  764. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  765. } else {
  766. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  767. }
  768. dispif_info->isConnected = 1;
  769. #ifdef MY_TODO
  770. #error
  771. {
  772. LCM_PARAMS lcm_params_temp;
  773. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  774. if (lcm_drv) {
  775. lcm_drv->get_params(&lcm_params_temp);
  776. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  777. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  778. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  779. } else {
  780. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  781. }
  782. }
  783. #endif
  784. #endif
  785. return 0;
  786. }
  787. int primary_display_get_pages(void)
  788. {
  789. return 3;
  790. }
  791. int primary_display_config_output()
  792. {
  793. return 0;
  794. }
  795. int primary_display_diagnose(void)
  796. {
  797. int ret = 0;
  798. dpmgr_check_status(pgc->dpmgr_handle);
  799. return ret;
  800. }
  801. int primary_display_trigger(int blocking)
  802. {
  803. int ret = 0;
  804. DISPFUNC();
  805. int x=0, y=0;
  806. int width = 0, height =0;
  807. x = disp_lcm_x(pgc->plcm);
  808. y = disp_lcm_y(pgc->plcm);
  809. width = disp_lcm_width(pgc->plcm);
  810. height = disp_lcm_height(pgc->plcm);
  811. _primary_path_lock();
  812. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  813. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  814. if (primary_display_is_video_mode()) {
  815. _primary_path_unlock();
  816. return 0;
  817. }
  818. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  819. }
  820. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  821. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  822. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  823. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  824. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  825. }
  826. //_set_cmdq_config_handle_dirty();
  827. //_reset_cmdq_config_handle();
  828. //if(blocking)
  829. {
  830. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  831. }
  832. } else if (pgc->mode == DECOUPLE_MODE) {
  833. DISPCHECK("trigger mode: DECOUPLE\n");
  834. if (pgc->need_trigger_overlay) {
  835. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  836. if (blocking) {
  837. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  838. }
  839. } else {
  840. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  841. // this request of trigger should be called by AAL or ovl2mem done event
  842. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  843. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  844. }
  845. _set_cmdq_config_handle_dirty();
  846. _reset_cmdq_config_handle();
  847. if (blocking) {
  848. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  849. }
  850. }
  851. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  852. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  853. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  854. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  855. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  856. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  857. }
  858. if (blocking) {
  859. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  860. }
  861. } else {
  862. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  863. }
  864. _primary_path_unlock();
  865. //primary_display_diagnose();
  866. return ret;
  867. }
  868. int primary_display_config_input(disp_input_config* input)
  869. {
  870. int ret = 0;
  871. //int i=0;
  872. //int layer =0;
  873. DISPFUNC();
  874. disp_ddp_path_config data_config;
  875. // all dirty should be cleared in dpmgr_path_get_last_config()
  876. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  877. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  878. data_config.dst_dirty = 0;
  879. data_config.ovl_dirty = 0;
  880. data_config.rdma_dirty = 0;
  881. data_config.wdma_dirty = 0;
  882. _primary_path_lock();
  883. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  884. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  885. if (primary_display_is_video_mode()) {
  886. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  887. }
  888. }
  889. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  890. data_config.ovl_dirty = 1;
  891. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  892. // this is used for decouple mode, to indicate whether we need to trigger ovl
  893. pgc->need_trigger_overlay = 1;
  894. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  895. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  896. data_config.rdma_dirty= 1;
  897. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  898. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  899. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  900. data_config.rdma_dirty= 1;
  901. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  902. // TODO: should use wait_event_timeout_or_idle
  903. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  904. }
  905. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  906. } else {
  907. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  908. }
  909. _primary_path_unlock();
  910. return ret;
  911. }
  912. int primary_display_is_video_mode(void)
  913. {
  914. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  915. return disp_lcm_is_video_mode(pgc->plcm);
  916. }
  917. int primary_display_get_vsync_interval(void)
  918. {
  919. int ret = 0;
  920. unsigned int time0 = 0;
  921. unsigned int time1 = 0;
  922. unsigned int lcd_time = 0;
  923. pgc->plcm->is_connected = false;
  924. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  925. if (ret <= 0)
  926. goto fail;
  927. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  928. if (ret <= 0)
  929. goto fail;
  930. // because we are polling irq status, so the first event should be ignored
  931. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  932. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  933. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  934. if (ret <= 0)
  935. goto fail;
  936. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  937. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  938. if (ret > 0) {
  939. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  940. } else
  941. goto fail;
  942. lcd_time = (time1 - time0)/2;
  943. pgc->plcm->is_connected = true;
  944. if (0 != lcd_time)
  945. return (100000000/lcd_time);
  946. else
  947. return (6000);
  948. fail:
  949. DISPERR("wait event fail\n");
  950. return 0;
  951. }
  952. int primary_display_setbacklight(unsigned int level)
  953. {
  954. DISPMSG("lk %s level=%d\n",__func__,level);
  955. int ret=0;
  956. if (pgc->dpmgr_handle == NULL) {
  957. DISPCHECK("lk set backlight early!\n");
  958. return 0;
  959. }
  960. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  961. DISPCHECK("primary display path is busy\n");
  962. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  963. DISPCHECK("wait frame done ret:%d\n", ret);
  964. }
  965. disp_lcm_set_backlight(pgc->plcm,level);
  966. return 0;
  967. }
  968. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  969. /***********************/
  970. /*****Legacy DISP API*****/
  971. /***********************/
  972. UINT32 DISP_GetScreenWidth(void)
  973. {
  974. return primary_display_get_width();
  975. }
  976. UINT32 DISP_GetScreenHeight(void)
  977. {
  978. return primary_display_get_height();
  979. }
  980. UINT32 DISP_GetActiveHeight(void)
  981. {
  982. if (pgc->plcm == NULL) {
  983. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  984. DISPERR("lcm handle is null, after probe:0x%p\n",pgc->plcm);
  985. if (pgc->plcm == NULL)return 0;
  986. }
  987. if (pgc->plcm->params) {
  988. return pgc->plcm->params->physical_height;
  989. } else {
  990. DISPERR("lcm_params is null!\n");
  991. return 0;
  992. }
  993. }
  994. UINT32 DISP_GetActiveWidth(void)
  995. {
  996. if (pgc->plcm == NULL) {
  997. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  998. DISPERR("lcm handle is null, after probe:0x%p\n",pgc->plcm);
  999. if (pgc->plcm == NULL)return 0;
  1000. }
  1001. if (pgc->plcm->params) {
  1002. return pgc->plcm->params->physical_width;
  1003. } else {
  1004. DISPERR("lcm_params is null!\n");
  1005. return 0;
  1006. }
  1007. }
  1008. int primary_display_capture_framebuffer(unsigned int *pbuf)
  1009. {
  1010. return 0;
  1011. }
  1012. UINT32 DISP_GetPanelBPP(void)
  1013. {
  1014. #if 0
  1015. PANEL_COLOR_FORMAT fmt;
  1016. disp_drv_init_context();
  1017. if (disp_if_drv->get_panel_color_format == NULL) {
  1018. return DISP_STATUS_NOT_IMPLEMENTED;
  1019. }
  1020. fmt = disp_if_drv->get_panel_color_format();
  1021. switch (fmt) {
  1022. case PANEL_COLOR_FORMAT_RGB332:
  1023. return 8;
  1024. case PANEL_COLOR_FORMAT_RGB444:
  1025. return 12;
  1026. case PANEL_COLOR_FORMAT_RGB565:
  1027. return 16;
  1028. case PANEL_COLOR_FORMAT_RGB666:
  1029. return 18;
  1030. case PANEL_COLOR_FORMAT_RGB888:
  1031. return 24;
  1032. default:
  1033. return 0;
  1034. }
  1035. #endif
  1036. return 0;
  1037. }
  1038. UINT32 DISP_GetScreenBpp(void)
  1039. {
  1040. return disp_fb_bpp;
  1041. }
  1042. UINT32 DISP_GetPages(void)
  1043. {
  1044. return disp_fb_pages; // Double Buffers
  1045. }
  1046. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1047. #define DAL_BPP (2)
  1048. #define DAL_WIDTH (DISP_GetScreenWidth())
  1049. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1050. UINT32 DAL_GetLayerSize(void)
  1051. {
  1052. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1053. }
  1054. UINT32 DISP_GetFBRamSize(void)
  1055. {
  1056. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1057. }
  1058. unsigned int DISP_GetVRamSize(void)
  1059. {
  1060. static UINT32 vramSize = 0;
  1061. unsigned int fb_ram_size =0;
  1062. //FB RAM(n blocks)+(Assert layer size)
  1063. if (0 == vramSize) {
  1064. vramSize = DISP_GetFBRamSize();
  1065. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1066. fb_ram_size = vramSize;
  1067. vramSize += DAL_GetLayerSize();
  1068. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1069. #ifdef MTK_ROUND_CORNER_SUPPORT
  1070. fb_ram_size = vramSize;
  1071. vramSize += disp_get_round_corner_size();
  1072. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1073. #endif
  1074. #if 0
  1075. if (g_is_64bit_kernel) {
  1076. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1077. } else {
  1078. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1079. }
  1080. #else
  1081. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1082. #endif
  1083. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1084. }
  1085. return vramSize;
  1086. }