mtk-lk/platform/mt6771/include/platform/ddp_reg.h

/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
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* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
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*
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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*/

#ifndef _DDP_REG_H_
#define _DDP_REG_H_

#include <platform/mt_typedefs.h>
#include <platform/sync_write.h>

#include <platform/mt_reg_base.h>

typedef void * cmdqRecHandle;


//TDODO: get base reg addr from system header
#define DISP_INDEX_OFFSET (DISP_OVL0_2L_BASE - OVL0_BASE) /* used by ovl */
#define DISP_RDMA_INDEX_OFFSET (DISP_RDMA1_BASE - DISP_RDMA0_BASE) /* used by rdma */

#define DISPSYS_OVL0_BASE               OVL0_BASE
#define DISPSYS_WDMA0_BASE              DISP_WDMA0_BASE
#define DISPSYS_RDMA0_BASE              DISP_RDMA0_BASE
#define DISPSYS_COLOR0_BASE             COLOR0_BASE
#define DISPSYS_AAL0_BASE               DISP_AAL0_BASE
#define DISPSYS_GAMMA0_BASE             DISP_GAMMA0_BASE
#define DISPSYS_SPLIT0_BASE             DISP_SPLIT0_BASE
#define DISPSYS_DSI0_BASE               DSI0_BASE
#define DISPSYS_DITHER0_BASE            DITHER0_BASE
#define DISPSYS_DSI1_BASE               DSI1_BASE
#define DISPSYS_PWM0_BASE               DISP_PWM0_BASE
#define DISPSYS_PWM1_BASE               (0)
#define DISPSYS_MUTEX_BASE              MM_MUTEX_BASE
#define DISPSYS_SMI_LARB0_BASE          SMI_LARB0_BASE
//#define DISPSYS_SMI_LARB1_BASE          SMI_LARB1_BASE
#define DISPSYS_SMI_COMMON_BASE         SMI_COMMON_BASE
#define DISPSYS_CCORR0_BASE             CCORR0_BASE
#define DISPSYS_DPI_BASE				DPI_BASE
#define DISPSYS_MIPITX0_BASE			MIPI_TX0_BASE
#define DISPSYS_MIPITX1_BASE			MIPI_TX1_BASE
#define DISPSYS_CONFIG_BASE				MMSYS_CONFIG_BASE

// ---------------------------------------------------------------------------
//  Type Casting
// ---------------------------------------------------------------------------

#define AS_INT32(x)     (*(INT32 *)(x))
#define AS_INT16(x)     (*(INT16 *)(x))
#define AS_INT8(x)      (*(INT8  *)(x))

#define AS_UINT32(x)    (*(UINT32 *)(x))
#define AS_UINT16(x)    (*(UINT16 *)(x))
#define AS_UINT8(x)     (*(UINT8  *)(x))


// ---------------------------------------------------------------------------
//  Register Manipulations
// ---------------------------------------------------------------------------
/*
#define READ_REGISTER_UINT32(reg) \
    (*(volatile UINT32 * const)(reg))

#define WRITE_REGISTER_UINT32(reg, val) \
    (*(volatile UINT32 * const)(reg)) = (val)

#define READ_REGISTER_UINT16(reg) \
    (*(volatile UINT16 * const)(reg))

#define WRITE_REGISTER_UINT16(reg, val) \
    (*(volatile UINT16 * const)(reg)) = (val)

#define READ_REGISTER_UINT8(reg) \
    (*(volatile UINT8 * const)(reg))

#define WRITE_REGISTER_UINT8(reg, val) \
    (*(volatile UINT8 * const)(reg)) = (val)
*/

// ---------------------------------------------------------------------------
//  Register Field Access
// ---------------------------------------------------------------------------

#define REG_FLD(width, shift) \
	((unsigned int)((((width) & 0xFF) << 16) | ((shift) & 0xFF)))

#define REG_FLD_MSB_LSB(msb, lsb) REG_FLD((msb) - (lsb) + 1, (lsb))

#define REG_FLD_WIDTH(field) \
	((unsigned int)(((field) >> 16) & 0xFF))

#define REG_FLD_SHIFT(field) \
	((unsigned int)((field) & 0xFF))

#define REG_FLD_MASK(field) \
	((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) << REG_FLD_SHIFT(field))

#define REG_FLD_VAL(field, val) \
	(((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))

#define REG_FLD_VAL_GET(field, regval) \
	(((regval) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field))


#define DISP_REG_GET(reg32) (*(volatile unsigned int*)(reg32))
#define DISP_REG_GET_FIELD(field, reg32) ((*(volatile unsigned int*)(reg32) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field))

/* polling register until masked bit is 1 */
#define DDP_REG_POLLING(reg32, mask) \
	do { \
		while (!((DISP_REG_GET(reg32))&mask))\
			; \
	} while (0)

/* Polling register until masked bit is 0 */
#define DDP_REG_POLLING_NEG(reg32, mask) \
	do { \
		while ((DISP_REG_GET(reg32))&mask)\
			; \
	} while (0)

#define DISP_CPU_REG_SET(reg32, val) mt_reg_sync_writel(val, (volatile unsigned int*)(reg32))
#define DISP_CPU_REG_SET_FIELD(field, reg32, val)  \
    do {                                \
           mt_reg_sync_writel( (*(volatile unsigned int*)(reg32) & ~REG_FLD_MASK(field))|REG_FLD_VAL((field), (val)), reg32);  \
    } while (0)

#define DISP_REG_MASK(handle, reg32, val, mask)     \
        do { \
            mt_reg_sync_writel((unsigned int)(INREG32(reg32)&~(mask))|(val),(volatile unsigned long*)(reg32) );\
        } while (0)

#define DISP_REG_SET(handle,reg32, val) \
        do { \
            mt_reg_sync_writel(val, (volatile unsigned int*)(reg32));\
        } while (0)


#define DISP_REG_SET_FIELD(handle,field, reg32, val)  \
        do {  \
             mt_reg_sync_writel( (*(volatile unsigned int*)(reg32) & ~REG_FLD_MASK(field))|REG_FLD_VAL((field), (val)), reg32);  \
        } while (0)

#define DISP_REG_CMDQ_POLLING(handle, reg32, val, mask) \
	do { \
		while ((DISP_REG_GET(reg32) & (mask)) != ((val) & (mask)))\
			; \
	} while (0)


#include <platform/ddp_reg_mmsys.h>
#include <platform/ddp_reg_mutex.h>
#include <platform/ddp_reg_ovl.h>
#include <platform/ddp_reg_dsi.h>
#include <platform/ddp_reg_mipi.h>
#include <platform/ddp_reg_dma.h>
#include <platform/ddp_reg_pq.h>

#endif