primary_display.c 34 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276
  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. //#include<linux/timer.h>
  44. #define DDP_LK_BOOT
  45. #ifndef HZ
  46. #define HZ 100
  47. #endif
  48. #ifdef DDP_LK_BOOT
  49. typedef void * cmdqRecHandle;
  50. #endif
  51. #define ALIGN_TO(x, n) \
  52. (((x) + ((n) - 1)) & ~((n) - 1))
  53. int primary_display_use_cmdq = CMDQ_DISABLE;
  54. int primary_display_use_m4u = 0;
  55. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  56. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  57. static UINT32 disp_fb_pages = 3; ///double buffer
  58. static UINT32 display_init;
  59. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  60. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  61. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  62. typedef struct _disp_dfo_item {
  63. char name[32];
  64. int value;
  65. } disp_dfo_item_t;
  66. static disp_dfo_item_t disp_dfo_setting[] = {
  67. {"LCM_FAKE_WIDTH", 0},
  68. {"LCM_FAKE_HEIGHT", 0},
  69. {"DISP_DEBUG_SWITCH", 0}
  70. };
  71. typedef struct {
  72. int state;
  73. int need_trigger_overlay;
  74. DISP_PRIMARY_PATH_MODE mode;
  75. unsigned int last_vsync_tick;
  76. #ifndef DDP_LK_BOOT
  77. struct mutex lock;
  78. #endif
  79. disp_lcm_handle * plcm;
  80. cmdqRecHandle cmdq_handle_config;
  81. cmdqRecHandle cmdq_handle_trigger;
  82. disp_path_handle dpmgr_handle;
  83. disp_path_handle ovl2mem_path_handle;
  84. } display_primary_path_context;
  85. #define pgc _get_context()
  86. static display_primary_path_context* _get_context(void)
  87. {
  88. static int is_context_inited = 0;
  89. static display_primary_path_context g_context;
  90. if (!is_context_inited) {
  91. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  92. is_context_inited = 1;
  93. }
  94. return &g_context;
  95. }
  96. static void _primary_path_lock(void)
  97. {
  98. #ifndef DDP_LK_BOOT
  99. disp_sw_mutex_lock(&(pgc->lock));
  100. #endif
  101. }
  102. static void _primary_path_unlock(void)
  103. {
  104. #ifndef DDP_LK_BOOT
  105. disp_sw_mutex_unlock(&(pgc->lock));
  106. #endif
  107. }
  108. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  109. {
  110. if (plcm == NULL) {
  111. DISPERR("plcm is null\n");
  112. return DISP_MODULE_UNKNOWN;
  113. }
  114. if (plcm->params->type == LCM_TYPE_DSI) {
  115. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  116. return DISP_MODULE_DSI0;
  117. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  118. return DISP_MODULE_DSI1;
  119. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  120. return DISP_MODULE_DSIDUAL;
  121. } else {
  122. return DISP_MODULE_DSI0;
  123. }
  124. } else if (plcm->params->type == LCM_TYPE_DPI) {
  125. return DISP_MODULE_DPI;
  126. } else {
  127. DISPERR("can't find primary path dst module\n");
  128. return DISP_MODULE_UNKNOWN;
  129. }
  130. }
  131. static int _build_path_direct_link(void)
  132. {
  133. int ret = 0;
  134. DISP_MODULE_ENUM dst_module = 0;
  135. DISPFUNC();
  136. pgc->mode = DIRECT_LINK_MODE;
  137. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  138. if (pgc->dpmgr_handle) {
  139. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", pgc->dpmgr_handle);
  140. } else {
  141. DISPCHECK("dpmgr create path FAIL\n");
  142. return -1;
  143. }
  144. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  145. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  146. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  147. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  148. return ret;
  149. }
  150. static int _build_path_decouple(void)
  151. {
  152. return 0;
  153. }
  154. static int _build_path_single_layer(void)
  155. {
  156. return 0;
  157. }
  158. static int _build_path_debug_rdma1_dsi0(void)
  159. {
  160. int ret = 0;
  161. DISP_MODULE_ENUM dst_module = 0;
  162. DISPFUNC();
  163. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  164. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  165. if (pgc->dpmgr_handle) {
  166. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", pgc->dpmgr_handle);
  167. } else {
  168. DISPCHECK("dpmgr create path FAIL\n");
  169. return -1;
  170. }
  171. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  172. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  173. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  174. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  175. return ret;
  176. }
  177. static void _build_cmdq_trigger_loop(void)
  178. {
  179. #ifndef DDP_LK_BOOT
  180. int ret = 0;
  181. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  182. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  183. cmdqRecReset(pgc->cmdq_handle_trigger);
  184. if (primary_display_is_video_mode()) {
  185. // wait and clear stream_done
  186. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  187. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  188. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  189. } else {
  190. // only in DSI Command mode we need to wait these
  191. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  192. // no internal te on fpga now.
  193. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  194. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  195. // block config threads, we'll about to update frame
  196. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  197. // only in DSI command mode we need to enable mutex explicitly
  198. // WRITE mutex enable
  199. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  200. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  201. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  202. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  203. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  204. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  205. // polling DSI idle
  206. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  207. // polling wdma frame done
  208. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  209. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  210. /*********************/
  211. /***build cmdq finished***/
  212. /*********************/
  213. // TODO:
  214. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  215. // RUN forever!!!!
  216. BUG_ON(ret < 0);
  217. }
  218. #endif
  219. }
  220. static void _start_cmdq_trigger_loop(void)
  221. {
  222. #ifndef DDP_LK_BOOT
  223. int ret = 0;
  224. // this should be called only once because trigger loop will nevet stop
  225. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  226. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  227. #endif
  228. }
  229. static void _set_cmdq_config_handle_dirty(void)
  230. {
  231. #ifndef DDP_LK_BOOT
  232. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  233. cmdqRecFlush(pgc->cmdq_handle_config);
  234. #endif
  235. }
  236. static void _reset_cmdq_config_handle(void)
  237. {
  238. #ifndef DDP_LK_BOOT
  239. cmdqRecReset(pgc->cmdq_handle_config);
  240. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  241. #endif
  242. }
  243. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  244. {
  245. if (src && dst) {
  246. dst->inputFormat = src->fmt;
  247. dst->address = src->addr;
  248. dst->width = src->src_w;
  249. dst->height = src->src_h;
  250. dst->pitch = src->src_pitch;
  251. return 0;
  252. } else {
  253. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", src, dst);
  254. return -1;
  255. }
  256. }
  257. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  258. {
  259. if (src && dst) {
  260. dst->layer = src->layer;
  261. dst->layer_en = src->layer_en;
  262. dst->fmt = src->fmt;
  263. dst->addr = src->addr;
  264. dst->vaddr = src->vaddr;
  265. dst->src_x = src->src_x;
  266. dst->src_y = src->src_y;
  267. dst->src_w = src->src_w;
  268. dst->src_h = src->src_h;
  269. dst->src_pitch = src->src_pitch;
  270. dst->dst_x = src->dst_x;
  271. dst->dst_y = src->dst_y;
  272. dst->dst_w = src->dst_w;
  273. dst->dst_h = src->dst_h;
  274. dst->keyEn = src->keyEn;
  275. dst->key = src->key;
  276. dst->aen = src->aen;
  277. dst->alpha = src->alpha;
  278. dst->isDirty = src->isDirty;
  279. dst->buff_idx = src->buff_idx;
  280. dst->identity = src->identity;
  281. dst->connected_type = src->connected_type;
  282. dst->security = src->security;
  283. return 0;
  284. } else {
  285. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", src, dst);
  286. return -1;
  287. }
  288. }
  289. void _dump_lcm_info_by_video_printf(void)
  290. {
  291. int i = 0;
  292. LCM_DRIVER *l = NULL;
  293. LCM_PARAMS *p = NULL;
  294. disp_lcm_handle *plcm = pgc->plcm;
  295. if (plcm == NULL) {
  296. DISPERR("plcm is null\n");
  297. return;
  298. }
  299. l = plcm->drv;
  300. p = plcm->params;
  301. if (l && p) {
  302. video_printf("[LCM], name: %s\n", l->name);
  303. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  304. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  305. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  306. switch (p->lcm_if) {
  307. case LCM_INTERFACE_DSI0:
  308. video_printf("[LCM] interface: DSI0\n");
  309. break;
  310. case LCM_INTERFACE_DSI1:
  311. video_printf("[LCM] interface: DSI1\n");
  312. break;
  313. case LCM_INTERFACE_DPI0:
  314. video_printf("[LCM] interface: DPI0\n");
  315. break;
  316. case LCM_INTERFACE_DPI1:
  317. video_printf("[LCM] interface: DPI1\n");
  318. break;
  319. case LCM_INTERFACE_DBI0:
  320. video_printf("[LCM] interface: DBI0\n");
  321. break;
  322. default:
  323. video_printf("[LCM] interface: unknown\n");
  324. break;
  325. }
  326. switch (p->type) {
  327. case LCM_TYPE_DBI:
  328. video_printf("[LCM] Type: DBI\n");
  329. break;
  330. case LCM_TYPE_DSI:
  331. video_printf("[LCM] Type: DSI\n");
  332. break;
  333. case LCM_TYPE_DPI:
  334. video_printf("[LCM] Type: DPI\n");
  335. break;
  336. default:
  337. video_printf("[LCM] TYPE: unknown\n");
  338. break;
  339. }
  340. if (p->type == LCM_TYPE_DSI) {
  341. switch (p->dsi.mode) {
  342. case CMD_MODE:
  343. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  344. break;
  345. case SYNC_PULSE_VDO_MODE:
  346. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  347. break;
  348. case SYNC_EVENT_VDO_MODE:
  349. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  350. break;
  351. case BURST_VDO_MODE:
  352. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  353. break;
  354. default:
  355. video_printf("[LCM] DSI Mode: Unknown\n");
  356. break;
  357. }
  358. }
  359. if (p->type == LCM_TYPE_DSI) {
  360. video_printf("[LCM] LANE_NUM: %d,data_format: %d,vertical_sync_active: %d\n",
  361. p->dsi.LANE_NUM, p->dsi.data_format.format, p->dsi.vertical_sync_active);
  362. #ifdef MY_TODO
  363. #error
  364. #endif
  365. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",
  366. p->dsi.vertical_sync_active, p->dsi.vertical_backporch, p->dsi.vertical_frontporch,
  367. p->dsi.vertical_active_line, p->dsi.horizontal_sync_active, p->dsi.horizontal_backporch,
  368. p->dsi.horizontal_frontporch, p->dsi.horizontal_blanking_pixel);
  369. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",
  370. p->dsi.pll_select, p->dsi.pll_div1, p->dsi.pll_div2, p->dsi.fbk_div, p->dsi.fbk_sel, p->dsi.rg_bir);
  371. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n",
  372. p->dsi.rg_bic, p->dsi.rg_bp, p->dsi.PLL_CLOCK, p->dsi.dsi_clock, p->dsi.ssc_range, p->dsi.ssc_disable, p->dsi.compatibility_for_nvk, p->dsi.cont_clock);
  373. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n",
  374. p->dsi.lcm_ext_te_enable, p->dsi.noncont_clock, p->dsi.noncont_clock_period);
  375. }
  376. }
  377. return;
  378. }
  379. unsigned int mt_disp_parse_dfo_setting(void)
  380. {
  381. unsigned int i, j=0 ;
  382. char tmp[11];
  383. char *buffer = NULL;
  384. char *ptr = NULL;
  385. buffer = (char *)get_env("DFO");
  386. DISPMSG("env buffer = %s\n", buffer);
  387. if (buffer != NULL) {
  388. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  389. j = 0;
  390. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  391. ptr = strstr(buffer, disp_dfo_setting[i].name);
  392. if (ptr == NULL) continue;
  393. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  394. do {} while ((*ptr++) != ',');
  395. do {tmp[j++] = *ptr++;}
  396. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  397. disp_dfo_setting[i].value = atoi((const char*)tmp);
  398. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  399. }
  400. } else {
  401. DISPMSG("env buffer = NULL\n");
  402. }
  403. return 0;
  404. }
  405. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  406. {
  407. char *disp_name;
  408. int disp_value;
  409. unsigned int i = 0;
  410. if (string == NULL)
  411. return -1;
  412. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  413. disp_name = disp_dfo_setting[i].name;
  414. disp_value = disp_dfo_setting[i].value;
  415. if (!strcmp(disp_name, string)) {
  416. *value = disp_value;
  417. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  418. return 0;
  419. }
  420. }
  421. return 0;
  422. }
  423. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  424. int primary_display_is_lcm_connected(void)
  425. {
  426. return pgc->plcm->is_connected;
  427. }
  428. const char* primary_display_get_lcm_name(void)
  429. {
  430. return disp_lcm_get_name(pgc->plcm);
  431. }
  432. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  433. {
  434. if (pgc->plcm) {
  435. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  436. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  437. // otherwise we will have a panic in lk(root cause unknown).
  438. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  439. DISPERR("Invalid resolution: %dx%d\n", width, height);
  440. return -1;
  441. }
  442. if (primary_display_is_video_mode()) {
  443. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  444. return -1;
  445. }
  446. pgc->plcm->params->width = width;
  447. pgc->plcm->params->height = height;
  448. return 0;
  449. } else {
  450. return -1;
  451. }
  452. }
  453. int primary_display_init(char *lcm_name)
  454. {
  455. DISPFUNC();
  456. DISP_STATUS ret = DISP_STATUS_OK;
  457. DISP_MODULE_ENUM dst_module = 0;
  458. unsigned int lcm_fake_width = 0;
  459. unsigned int lcm_fake_height = 0;
  460. LCM_PARAMS *lcm_param = NULL;
  461. LCM_INTERFACE_ID lcm_id = LCM_INTERFACE_NOTDEFINED;
  462. dpmgr_init();
  463. #ifndef DDP_LK_BOOT
  464. mutex_init(&(pgc->lock));
  465. #endif
  466. _primary_path_lock();
  467. if (pgc->plcm == NULL)
  468. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  469. if (pgc->plcm == NULL) {
  470. DISPCHECK("disp_lcm_probe returns null\n");
  471. ret = DISP_STATUS_ERROR;
  472. goto done;
  473. } else {
  474. DISPCHECK("disp_lcm_probe SUCCESS\n");
  475. }
  476. lcm_param = disp_lcm_get_params(pgc->plcm);
  477. if (lcm_param == NULL) {
  478. DISPERR("get lcm params FAILED\n");
  479. ret = DISP_STATUS_ERROR;
  480. goto done;
  481. }
  482. if (primary_display_mode == DIRECT_LINK_MODE) {
  483. _build_path_direct_link();
  484. DISPCHECK("primary display is DIRECT LINK MODE\n");
  485. } else if (primary_display_mode == DECOUPLE_MODE) {
  486. _build_path_decouple();
  487. DISPCHECK("primary display is DECOUPLE MODE\n");
  488. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  489. _build_path_single_layer();
  490. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  491. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  492. _build_path_debug_rdma1_dsi0();
  493. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  494. } else {
  495. DISPCHECK("primary display mode is WRONG\n");
  496. }
  497. _build_cmdq_trigger_loop();
  498. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  499. _start_cmdq_trigger_loop();
  500. DISPCHECK("primary display START cmdq trigger loop finished\n");
  501. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  502. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  503. disp_ddp_path_config data_config;
  504. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  505. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  506. data_config.dst_w = disp_lcm_width(pgc->plcm);
  507. data_config.dst_h = disp_lcm_height(pgc->plcm);
  508. if (lcm_param->type == LCM_TYPE_DSI) {
  509. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  510. data_config.lcm_bpp = 24;
  511. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  512. data_config.lcm_bpp = 16;
  513. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  514. data_config.lcm_bpp = 18;
  515. } else if (lcm_param->type == LCM_TYPE_DPI) {
  516. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  517. data_config.lcm_bpp = 24;
  518. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  519. data_config.lcm_bpp = 16;
  520. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  521. data_config.lcm_bpp = 18;
  522. }
  523. data_config.dst_dirty = 1;
  524. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  525. ret = disp_lcm_init(pgc->plcm);
  526. if (primary_display_is_video_mode()) {
  527. if (lcm_param->dsi.lfr_enable == 1) {
  528. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  529. } else {
  530. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  531. }
  532. } else {
  533. }
  534. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  535. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  536. pgc->state = 1;
  537. display_init = 1;
  538. done:
  539. _primary_path_unlock();
  540. return ret;
  541. }
  542. // register rdma done event
  543. int primary_display_wait_for_idle(void)
  544. {
  545. DISP_STATUS ret = DISP_STATUS_OK;
  546. DISPFUNC();
  547. _primary_path_lock();
  548. done:
  549. _primary_path_unlock();
  550. return ret;
  551. }
  552. int primary_display_wait_for_dump(void)
  553. {
  554. return 0;
  555. }
  556. static long int get_current_time_us(void)
  557. {
  558. return get_timer(0);
  559. }
  560. int priamry_display_wait_for_vsync(void)
  561. {
  562. int ret = 0;
  563. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  564. if (ret == -2) {
  565. DISPCHECK("vsync for primary display path not enabled yet\n");
  566. return -1;
  567. }
  568. // pgc->last_vsync_tick = get_current_time_us();
  569. pgc->last_vsync_tick = 0;
  570. return 0;
  571. }
  572. int primary_display_suspend(void)
  573. {
  574. DISP_STATUS ret = DISP_STATUS_OK;
  575. if (display_init == 0) {
  576. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  577. return -1;
  578. }
  579. DISPFUNC();
  580. _primary_path_lock();
  581. disp_lcm_suspend(pgc->plcm);
  582. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  583. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  584. #ifndef DDP_LK_BOOT
  585. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  586. #endif
  587. pgc->state = 0;
  588. done:
  589. _primary_path_unlock();
  590. return ret;
  591. }
  592. int primary_display_resume(void)
  593. {
  594. DISP_STATUS ret = DISP_STATUS_OK;
  595. DISPFUNC();
  596. _primary_path_lock();
  597. disp_path_clock_on("Primary Display Path");
  598. pgc->state = 1;
  599. done:
  600. _primary_path_unlock();
  601. return ret;
  602. }
  603. int primary_display_is_alive(void)
  604. {
  605. unsigned int temp = 0;
  606. DISPFUNC();
  607. _primary_path_lock();
  608. temp = pgc->state;
  609. _primary_path_unlock();
  610. return temp;
  611. }
  612. int primary_display_is_sleepd(void)
  613. {
  614. unsigned int temp = 0;
  615. DISPFUNC();
  616. _primary_path_lock();
  617. temp = !pgc->state;
  618. _primary_path_unlock();
  619. return temp;
  620. }
  621. #ifdef MTK_ROUND_CORNER_SUPPORT
  622. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  623. {
  624. if (pgc->plcm == NULL) {
  625. return NULL;
  626. }
  627. if (pgc->plcm->params) {
  628. return &(pgc->plcm->params->round_corner_params);
  629. } else {
  630. DISPERR("lcm_params is null!\n");
  631. return NULL;
  632. }
  633. }
  634. int disp_get_round_corner_size(void)
  635. {
  636. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  637. int pitch = DISP_GetScreenWidth();
  638. int size = 0;
  639. if (corner_params) {
  640. if (corner_params->round_corner_en) {
  641. if (corner_params->full_content)
  642. size = (corner_params->h + corner_params->h_bot) * pitch * 2;
  643. else
  644. size = corner_params->h * pitch * 2 * 2;
  645. } else
  646. DISPERR("corner_params is null!\n");
  647. }
  648. return size;
  649. }
  650. #endif
  651. int primary_display_get_width(void)
  652. {
  653. if (pgc->plcm == NULL) {
  654. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  655. DISPDBG("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  656. if (pgc->plcm == NULL)
  657. return 0;
  658. }
  659. if (pgc->plcm->params) {
  660. return pgc->plcm->params->width;
  661. } else {
  662. DISPERR("lcm_params is null!\n");
  663. return 0;
  664. }
  665. }
  666. int primary_display_get_height(void)
  667. {
  668. if (pgc->plcm == NULL) {
  669. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  670. DISPDBG("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  671. if (pgc->plcm == NULL)
  672. return 0;
  673. }
  674. if (pgc->plcm->params) {
  675. return pgc->plcm->params->height;
  676. } else {
  677. DISPERR("lcm_params is null!\n");
  678. return 0;
  679. }
  680. }
  681. int primary_display_get_bpp(void)
  682. {
  683. return 32;
  684. }
  685. int primary_display_get_info(void *dispif_info)
  686. {
  687. #if 0
  688. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  689. switch (pgc->lcm_param->type) {
  690. case LCM_TYPE_DBI: {
  691. dispif_info->displayType = DISPIF_TYPE_DBI;
  692. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  693. dispif_info->isHwVsyncAvailable = 1;
  694. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  695. break;
  696. }
  697. case LCM_TYPE_DPI: {
  698. dispif_info->displayType = DISPIF_TYPE_DPI0;
  699. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  700. dispif_info->isHwVsyncAvailable = 1;
  701. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  702. break;
  703. }
  704. case LCM_TYPE_DSI: {
  705. dispif_info->displayType = DISPIF_TYPE_DSI0;
  706. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  707. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  708. dispif_info->isHwVsyncAvailable = 1;
  709. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  710. } else {
  711. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  712. dispif_info->isHwVsyncAvailable = 1;
  713. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  714. }
  715. break;
  716. }
  717. default:
  718. break;
  719. }
  720. #ifdef MY_TODO
  721. #error
  722. if (disp_if_drv->get_panel_color_format()) {
  723. switch (disp_if_drv->get_panel_color_format()) {
  724. case PANEL_COLOR_FORMAT_RGB565:
  725. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  726. case PANEL_COLOR_FORMAT_RGB666:
  727. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  728. case PANEL_COLOR_FORMAT_RGB888:
  729. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  730. default:
  731. break;
  732. }
  733. }
  734. #endif
  735. dispif_info->displayWidth = primary_display_get_width();
  736. dispif_info->displayHeight = primary_display_get_height();
  737. #ifdef MY_TODO
  738. #error
  739. dispif_info->vsyncFPS = lcd_fps;
  740. #endif
  741. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  742. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  743. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  744. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  745. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  746. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  747. } else {
  748. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  749. }
  750. dispif_info->isConnected = 1;
  751. #ifdef MY_TODO
  752. #error
  753. {
  754. LCM_PARAMS lcm_params_temp;
  755. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  756. if (lcm_drv) {
  757. lcm_drv->get_params(&lcm_params_temp);
  758. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  759. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  760. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  761. } else {
  762. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  763. }
  764. }
  765. #endif
  766. #endif
  767. return 0;
  768. }
  769. int primary_display_get_pages(void)
  770. {
  771. return 3;
  772. }
  773. int primary_display_config_output()
  774. {
  775. return 0;
  776. }
  777. int primary_display_diagnose(void)
  778. {
  779. int ret = 0;
  780. dpmgr_check_status(pgc->dpmgr_handle);
  781. return ret;
  782. }
  783. int primary_display_trigger(int blocking)
  784. {
  785. int ret = 0;
  786. DISPFUNC();
  787. int x=0, y=0;
  788. int width = 0, height =0;
  789. x = disp_lcm_x(pgc->plcm);
  790. y = disp_lcm_y(pgc->plcm);
  791. width = disp_lcm_width(pgc->plcm);
  792. height = disp_lcm_height(pgc->plcm);
  793. _primary_path_lock();
  794. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  795. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  796. if (primary_display_is_video_mode()) {
  797. _primary_path_unlock();
  798. return 0;
  799. }
  800. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  801. }
  802. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  803. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  804. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  805. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  806. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  807. }
  808. //_set_cmdq_config_handle_dirty();
  809. //_reset_cmdq_config_handle();
  810. //if(blocking)
  811. {
  812. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  813. }
  814. } else if (pgc->mode == DECOUPLE_MODE) {
  815. DISPCHECK("trigger mode: DECOUPLE\n");
  816. if (pgc->need_trigger_overlay) {
  817. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  818. if (blocking) {
  819. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  820. }
  821. } else {
  822. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  823. // this request of trigger should be called by AAL or ovl2mem done event
  824. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  825. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  826. }
  827. _set_cmdq_config_handle_dirty();
  828. _reset_cmdq_config_handle();
  829. if (blocking) {
  830. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  831. }
  832. }
  833. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  834. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  835. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  836. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  837. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  838. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  839. }
  840. if (blocking) {
  841. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  842. }
  843. } else {
  844. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  845. }
  846. _primary_path_unlock();
  847. //primary_display_diagnose();
  848. return ret;
  849. }
  850. int primary_display_config_input(disp_input_config* input)
  851. {
  852. int ret = 0;
  853. int i=0;
  854. int layer =0;
  855. DISPFUNC();
  856. disp_ddp_path_config data_config;
  857. // all dirty should be cleared in dpmgr_path_get_last_config()
  858. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  859. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  860. data_config.dst_dirty = 0;
  861. data_config.ovl_dirty = 0;
  862. data_config.rdma_dirty = 0;
  863. data_config.wdma_dirty = 0;
  864. _primary_path_lock();
  865. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  866. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  867. if (primary_display_is_video_mode()) {
  868. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  869. }
  870. }
  871. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  872. data_config.ovl_dirty = 1;
  873. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  874. // this is used for decouple mode, to indicate whether we need to trigger ovl
  875. pgc->need_trigger_overlay = 1;
  876. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  877. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  878. data_config.rdma_dirty= 1;
  879. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  880. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  881. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  882. data_config.rdma_dirty= 1;
  883. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  884. // TODO: should use wait_event_timeout_or_idle
  885. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  886. }
  887. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  888. } else {
  889. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  890. }
  891. _primary_path_unlock();
  892. return ret;
  893. }
  894. int primary_display_is_video_mode(void)
  895. {
  896. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  897. return disp_lcm_is_video_mode(pgc->plcm);
  898. }
  899. int primary_display_get_vsync_interval(void)
  900. {
  901. int ret = 0;
  902. unsigned int time0 = 0;
  903. unsigned int time1 = 0;
  904. unsigned int lcd_time = 0;
  905. pgc->plcm->is_connected = false;
  906. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  907. if (ret <= 0)
  908. goto fail;
  909. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  910. if (ret <= 0)
  911. goto fail;
  912. // because we are polling irq status, so the first event should be ignored
  913. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  914. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  915. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  916. if (ret <= 0)
  917. goto fail;
  918. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  919. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  920. if (ret > 0) {
  921. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  922. } else
  923. goto fail;
  924. lcd_time = (time1 - time0)/2;
  925. pgc->plcm->is_connected = true;
  926. if (0 != lcd_time)
  927. return (100000000/lcd_time);
  928. else
  929. return (6000);
  930. fail:
  931. DISPERR("wait event fail\n");
  932. return 0;
  933. }
  934. int primary_display_setbacklight(unsigned int level)
  935. {
  936. DISPMSG("lk %s level=%d\n",__func__,level);
  937. int ret=0;
  938. if (pgc->dpmgr_handle == NULL) {
  939. DISPCHECK("lk set backlight early!\n");
  940. return 0;
  941. }
  942. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  943. DISPCHECK("primary display path is busy\n");
  944. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  945. DISPCHECK("wait frame done ret:%d\n", ret);
  946. }
  947. disp_lcm_set_backlight(pgc->plcm,level);
  948. return 0;
  949. }
  950. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  951. /***********************/
  952. /*****Legacy DISP API*****/
  953. /***********************/
  954. UINT32 DISP_GetScreenWidth(void)
  955. {
  956. return primary_display_get_width();
  957. }
  958. UINT32 DISP_GetScreenHeight(void)
  959. {
  960. return primary_display_get_height();
  961. }
  962. UINT32 DISP_GetActiveHeight(void)
  963. {
  964. if (pgc->plcm == NULL) {
  965. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  966. DISPERR("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  967. if (pgc->plcm == NULL)return 0;
  968. }
  969. if (pgc->plcm->params) {
  970. return pgc->plcm->params->physical_height;
  971. } else {
  972. DISPERR("lcm_params is null!\n");
  973. return 0;
  974. }
  975. }
  976. UINT32 DISP_GetActiveWidth(void)
  977. {
  978. if (pgc->plcm == NULL) {
  979. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  980. DISPERR("lcm handle is null, after probe:0x%08x\n",pgc->plcm);
  981. if (pgc->plcm == NULL)return 0;
  982. }
  983. if (pgc->plcm->params) {
  984. return pgc->plcm->params->physical_width;
  985. } else {
  986. DISPERR("lcm_params is null!\n");
  987. return 0;
  988. }
  989. }
  990. int primary_display_capture_framebuffer(unsigned int *pbuf)
  991. {
  992. return 0;
  993. }
  994. UINT32 DISP_GetPanelBPP(void)
  995. {
  996. #if 0
  997. PANEL_COLOR_FORMAT fmt;
  998. disp_drv_init_context();
  999. if (disp_if_drv->get_panel_color_format == NULL) {
  1000. return DISP_STATUS_NOT_IMPLEMENTED;
  1001. }
  1002. fmt = disp_if_drv->get_panel_color_format();
  1003. switch (fmt) {
  1004. case PANEL_COLOR_FORMAT_RGB332:
  1005. return 8;
  1006. case PANEL_COLOR_FORMAT_RGB444:
  1007. return 12;
  1008. case PANEL_COLOR_FORMAT_RGB565:
  1009. return 16;
  1010. case PANEL_COLOR_FORMAT_RGB666:
  1011. return 18;
  1012. case PANEL_COLOR_FORMAT_RGB888:
  1013. return 24;
  1014. default:
  1015. return 0;
  1016. }
  1017. #endif
  1018. return 0;
  1019. }
  1020. UINT32 DISP_GetScreenBpp(void)
  1021. {
  1022. return disp_fb_bpp;
  1023. }
  1024. UINT32 DISP_GetPages(void)
  1025. {
  1026. return disp_fb_pages; // Double Buffers
  1027. }
  1028. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1029. #define DAL_BPP (2)
  1030. #define DAL_WIDTH (DISP_GetScreenWidth())
  1031. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1032. UINT32 DAL_GetLayerSize(void)
  1033. {
  1034. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1035. }
  1036. UINT32 DISP_GetFBRamSize(void)
  1037. {
  1038. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1039. }
  1040. unsigned int DISP_GetVRamSize(void)
  1041. {
  1042. static UINT32 vramSize = 0;
  1043. unsigned int fb_ram_size =0;
  1044. //FB RAM(n blocks)+(Assert layer size)
  1045. if (0 == vramSize) {
  1046. vramSize = DISP_GetFBRamSize();
  1047. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1048. fb_ram_size = vramSize;
  1049. vramSize += DAL_GetLayerSize();
  1050. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1051. #ifdef MTK_ROUND_CORNER_SUPPORT
  1052. fb_ram_size = vramSize;
  1053. vramSize += disp_get_round_corner_size();
  1054. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1055. #endif
  1056. #if 0
  1057. if (g_is_64bit_kernel) {
  1058. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1059. } else {
  1060. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1061. }
  1062. #else
  1063. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1064. #endif
  1065. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1066. }
  1067. return vramSize;
  1068. }