mt_rtc.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368
  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <debug.h>
  32. #include <platform/mt_typedefs.h>
  33. #include <platform/mt_rtc.h>
  34. #include <platform/boot_mode.h>
  35. #include <platform/mt_pmic_wrap_init.h>
  36. #include <target/board.h>
  37. #include <platform/mtk_wdt.h>
  38. #include <platform/mt_rtc_hw.h>
  39. #define DBG_RTC_C(x...) dprintf(CRITICAL, x)
  40. #define DBG_RTC_I(x...) dprintf(INFO, x)
  41. #define DBG_RTC_S(x...) dprintf(SPEW, x)
  42. extern BOOT_ARGUMENT *g_boot_arg;
  43. static U16 RTC_Read(U16 addr)
  44. {
  45. U32 rdata=0;
  46. pwrap_read((U32)addr, &rdata);
  47. return (U16)rdata;
  48. }
  49. static void RTC_Write(U16 addr, U16 data)
  50. {
  51. pwrap_write((U32)addr, (U32)data);
  52. }
  53. #define rtc_busy_wait() \
  54. do { \
  55. while (RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY); \
  56. } while (0)
  57. static unsigned long rtc_mktime(int yea, int mth, int dom, int hou, int min, int sec)
  58. {
  59. unsigned long d1, d2, d3;
  60. mth -= 2;
  61. if (mth <= 0) {
  62. mth += 12;
  63. yea -= 1;
  64. }
  65. d1 = (yea - 1) * 365 + (yea / 4 - yea / 100 + yea / 400);
  66. d2 = (367 * mth / 12 - 30) + 59;
  67. d3 = d1 + d2 + (dom - 1) - 719162;
  68. return ((d3 * 24 + hou) * 60 + min) * 60 + sec;
  69. }
  70. static void rtc_write_trigger(void)
  71. {
  72. RTC_Write(RTC_WRTGR, 1);
  73. rtc_busy_wait();
  74. }
  75. void rtc_writeif_unlock(void)
  76. {
  77. RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1);
  78. rtc_write_trigger();
  79. RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2);
  80. rtc_write_trigger();
  81. }
  82. void rtc_writeif_lock(void)
  83. {
  84. RTC_Write(RTC_PROT, 0);
  85. rtc_write_trigger();
  86. }
  87. static void rtc_xosc_write(U16 val)
  88. {
  89. RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
  90. mdelay(1);
  91. RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
  92. mdelay(1);
  93. RTC_Write(RTC_OSC32CON, val);
  94. mdelay(1);
  95. }
  96. void rtc_enable_k_eosc(void)
  97. {
  98. pmic_config_interface(PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR, 1, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT);
  99. pmic_config_interface(PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR, 1, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT);
  100. pmic_config_interface(PMIC_RG_RTC_EOSC32_CK_PDN_ADDR, 0, PMIC_RG_RTC_EOSC32_CK_PDN_MASK, PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
  101. /* If cali eosc every second, needing to add the following configuration, default period is 8 sec */
  102. /* pmic_config_interface(PMIC_EOSC_CALI_TD_ADDR, 0x3, PMIC_EOSC_CALI_TD_MASK, PMIC_EOSC_CALI_TD_SHIFT); */
  103. RTC_Write(RTC_BBPU, RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  104. rtc_write_trigger();
  105. /* Enable K EOSC mode for normal power off and then plug out battery */
  106. RTC_Write(RTC_AL_YEA, ((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1)) | RTC_K_EOSC_RSV_2);
  107. rtc_write_trigger();
  108. RTC_Write(RTC_BBPU, RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  109. rtc_write_trigger();
  110. rtc_xosc_write(RTC_Read(RTC_OSC32CON) | RTC_EMBCK_SRC_SEL);
  111. DBG_RTC_I("[RTC] k_eosc bbpu = 0x%x, con = 0x%x, osc32con = 0x%x, sec = 0x%x, yea = 0x%x\n", RTC_Read(RTC_BBPU), RTC_Read(RTC_CON), RTC_Read(RTC_OSC32CON), RTC_Read(RTC_AL_SEC), RTC_Read(RTC_AL_YEA));
  112. }
  113. void rtc_disable_2sec_reboot(void)
  114. {
  115. U16 reboot;
  116. reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) & ~RTC_BBPU_AUTO_PDN_SEL;
  117. RTC_Write(RTC_AL_SEC, reboot);
  118. rtc_write_trigger();
  119. }
  120. void rtc_bbpu_power_down(void)
  121. {
  122. U16 bbpu;
  123. rtc_disable_2sec_reboot();
  124. rtc_enable_k_eosc();
  125. bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN;
  126. rtc_writeif_unlock();
  127. RTC_Write(RTC_BBPU, bbpu);
  128. rtc_write_trigger();
  129. pmic_power_hold(0);
  130. }
  131. U16 rtc_rdwr_uart_bits(U16 *val)
  132. {
  133. U16 pdn2;
  134. if (val) {
  135. pdn2 = RTC_Read(RTC_PDN2) & ~RTC_PDN2_UART_MASK;
  136. pdn2 |= (*val & (RTC_PDN2_UART_MASK >> RTC_PDN2_UART_SHIFT)) << RTC_PDN2_UART_SHIFT;
  137. RTC_Write(RTC_PDN2, pdn2);
  138. rtc_write_trigger();
  139. }
  140. return (RTC_Read(RTC_PDN2) & RTC_PDN2_UART_MASK) >> RTC_PDN2_UART_SHIFT;
  141. }
  142. bool rtc_reset_bbpu_alarm_status(void)
  143. {
  144. u16 bbpu;
  145. ulong begin = get_timer(0);
  146. bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN | RTC_BBPU_RESET_ALARM;
  147. RTC_Write(RTC_BBPU, bbpu);
  148. rtc_write_trigger();
  149. while ((RTC_Read(RTC_BBPU) & RTC_BBPU_RESET_ALARM))
  150. {
  151. if (get_timer(begin) > 500)
  152. {
  153. DBG_RTC_I("%s time out\n", __func__);
  154. return false;
  155. }
  156. }
  157. return true;
  158. }
  159. bool rtc_boot_check(bool can_alarm_boot)
  160. {
  161. U16 irqsta, pdn1, pdn2, spar0, spar1;
  162. irqsta = RTC_Read(RTC_IRQ_STA); /* read clear */
  163. pdn1 = RTC_Read(RTC_PDN1);
  164. pdn2 = RTC_Read(RTC_PDN2);
  165. spar0 = RTC_Read(RTC_SPAR0);
  166. spar1 = RTC_Read(RTC_SPAR1);
  167. /*printf("irqsta = 0x%x, pdn1 = 0x%x, pdn2 = 0x%x, spar0 = 0x%x, spar1 = 0x%x\n",
  168. irqsta, pdn1, pdn2, spar0, spar1);*/
  169. if (irqsta & RTC_IRQ_STA_AL) {
  170. rtc_reset_bbpu_alarm_status();
  171. if (pdn1 & RTC_PDN1_PWRON_TIME) { /* power-on time is available */
  172. U16 now_sec, now_min, now_hou, now_dom, now_mth, now_yea;
  173. U16 irqen, sec, min, hou, dom, mth, yea;
  174. unsigned long now_time, time;
  175. now_sec = RTC_Read(RTC_TC_SEC);
  176. now_min = RTC_Read(RTC_TC_MIN);
  177. now_hou = RTC_Read(RTC_TC_HOU);
  178. now_dom = RTC_Read(RTC_TC_DOM);
  179. now_mth = RTC_Read(RTC_TC_MTH) & RTC_TC_MTH_MASK;
  180. now_yea = RTC_Read(RTC_TC_YEA) + RTC_MIN_YEAR;
  181. if (RTC_Read(RTC_TC_SEC) < now_sec) { /* SEC has carried */
  182. now_sec = RTC_Read(RTC_TC_SEC);
  183. now_min = RTC_Read(RTC_TC_MIN);
  184. now_hou = RTC_Read(RTC_TC_HOU);
  185. now_dom = RTC_Read(RTC_TC_DOM);
  186. now_mth = RTC_Read(RTC_TC_MTH) & RTC_TC_MTH_MASK;
  187. now_yea = RTC_Read(RTC_TC_YEA) + RTC_MIN_YEAR;
  188. }
  189. sec = ((spar0 & RTC_SPAR0_PWRON_SEC_MASK) >> RTC_SPAR0_PWRON_SEC_SHIFT);
  190. min = ((spar1 & RTC_SPAR1_PWRON_MIN_MASK) >> RTC_SPAR1_PWRON_MIN_SHIFT);
  191. hou = ((spar1 & RTC_SPAR1_PWRON_HOU_MASK) >> RTC_SPAR1_PWRON_HOU_SHIFT);
  192. dom = ((spar1 & RTC_SPAR1_PWRON_DOM_MASK) >> RTC_SPAR1_PWRON_DOM_SHIFT);
  193. mth = ((pdn2 & RTC_PDN2_PWRON_MTH_MASK) >> RTC_PDN2_PWRON_MTH_SHIFT);
  194. yea = ((pdn2 & RTC_PDN2_PWRON_YEA_MASK) >> RTC_PDN2_PWRON_YEA_SHIFT) + RTC_MIN_YEAR;
  195. now_time = rtc_mktime(now_yea, now_mth, now_dom, now_hou, now_min, now_sec);
  196. time = rtc_mktime(yea, mth, dom, hou, min, sec);
  197. DBG_RTC_I("now = %d/%d/%d %d:%d:%d (%lu)\n",
  198. now_yea, now_mth, now_dom, now_hou, now_min, now_sec, now_time);
  199. DBG_RTC_I("power-on = %d/%d/%d %d:%d:%d (%lu)\n",
  200. yea, mth, dom, hou, min, sec, time);
  201. if (now_time >= time - 1 && now_time <= time + 4) { /* power on */
  202. pdn1 &= ~(RTC_PDN1_PWRON_TIME | RTC_PDN1_FAC_RESET | RTC_PDN1_BYPASS_PWR);
  203. RTC_Write(RTC_PDN1, pdn1);
  204. RTC_Write(RTC_PDN2, pdn2 | RTC_PDN2_PWRON_ALARM);
  205. rtc_write_trigger();
  206. if (can_alarm_boot &&
  207. !(pdn2 & RTC_PDN2_PWRON_LOGO)) { /* no logo means ALARM_BOOT */
  208. g_boot_mode = ALARM_BOOT;
  209. }
  210. return true;
  211. } else if (now_time < time) { /* set power-on alarm */
  212. RTC_Write(RTC_AL_YEA, (RTC_Read(RTC_AL_YEA) & ~(RTC_AL_YEA_MASK)) | ((yea - RTC_MIN_YEAR) & RTC_AL_YEA_MASK));
  213. RTC_Write(RTC_AL_MTH, (RTC_Read(RTC_AL_MTH)&RTC_NEW_SPARE3)|mth);
  214. RTC_Write(RTC_AL_DOM, (RTC_Read(RTC_AL_DOM)&RTC_NEW_SPARE1)|dom);
  215. RTC_Write(RTC_AL_HOU, (RTC_Read(RTC_AL_HOU)&RTC_AL_HOU_FG_MASK)|hou);
  216. RTC_Write(RTC_AL_MIN, min);
  217. RTC_Write(RTC_AL_SEC, (RTC_Read(RTC_AL_SEC) & (~RTC_AL_SEC_MASK)) | (sec & RTC_AL_SEC_MASK));
  218. RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW); /* mask DOW */
  219. rtc_write_trigger();
  220. irqen = RTC_Read(RTC_IRQ_EN) | RTC_IRQ_EN_ONESHOT_AL;
  221. RTC_Write(RTC_IRQ_EN, irqen);
  222. rtc_write_trigger();
  223. }
  224. }
  225. }
  226. if ((pdn1 & RTC_PDN1_RECOVERY_MASK) == RTC_PDN1_FAC_RESET) { /* factory data reset */
  227. RTC_Write(RTC_PDN1, pdn1 & ~RTC_PDN1_FAC_RESET);
  228. rtc_write_trigger();
  229. DBG_RTC_I("%s:factory data reset\n", __func__);
  230. return true;
  231. }
  232. if (pdn1 & RTC_PDN1_BYPASS_PWR) { /* bypass power key detection */
  233. RTC_Write(RTC_PDN1, pdn1 & ~RTC_PDN1_BYPASS_PWR);
  234. rtc_write_trigger();
  235. DBG_RTC_I("%s:bypass power key detection, boot_reason=%d\n", __func__, g_boot_arg->boot_reason);
  236. return true;
  237. }
  238. return false;
  239. }
  240. void Set_Clr_RTC_PDN1_bit13(bool flag)
  241. {
  242. U16 pdn1;
  243. rtc_writeif_unlock();
  244. //use PDN1 bit13 for LK
  245. pdn1 = RTC_Read(RTC_PDN1);
  246. if (flag==true)
  247. pdn1 = pdn1 | RTC_PDN1_FAST_BOOT;
  248. else if (flag==false)
  249. pdn1 = pdn1 & ~RTC_PDN1_FAST_BOOT;
  250. RTC_Write(RTC_PDN1, pdn1);
  251. rtc_write_trigger();
  252. }
  253. bool Check_RTC_PDN1_bit13(void)
  254. {
  255. U16 pdn1;
  256. pdn1 = RTC_Read(RTC_PDN1);
  257. if (pdn1 & RTC_PDN1_FAST_BOOT)
  258. return true;
  259. else
  260. return false;
  261. }
  262. bool Check_RTC_Recovery_Mode(void)
  263. {
  264. U16 pdn1;
  265. pdn1 = RTC_Read(RTC_PDN1);
  266. if ( (pdn1 & RTC_PDN1_RECOVERY_MASK)==RTC_PDN1_FAC_RESET )
  267. return true;
  268. else
  269. return false;
  270. }
  271. #if 1
  272. bool rtc_2sec_boot_check(void)
  273. {
  274. int boot_reason;
  275. if (g_boot_arg->maggic_number == BOOT_ARGUMENT_MAGIC) {
  276. boot_reason = g_boot_arg->boot_reason;
  277. if (boot_reason == BR_2SEC_REBOOT)
  278. return true;
  279. }
  280. return false;
  281. }
  282. #endif
  283. void Set_RTC_Recovery_Mode(bool flag)
  284. {
  285. U16 pdn1;
  286. rtc_writeif_unlock();
  287. pdn1 = RTC_Read(RTC_PDN1);
  288. if (flag==true)
  289. pdn1 = pdn1 | RTC_PDN1_FAC_RESET;
  290. else if (flag==false)
  291. pdn1 = pdn1 & ~RTC_PDN1_FAC_RESET;
  292. RTC_Write(RTC_PDN1, pdn1);
  293. rtc_write_trigger();
  294. DBG_RTC_I("Set_RTC_Fastboot_Mode\n");
  295. }
  296. static void rtc_get_tick(struct rtc_time *tm)
  297. {
  298. tm->tm_sec = RTC_Read(RTC_TC_SEC);
  299. tm->tm_min = RTC_Read(RTC_TC_MIN);
  300. tm->tm_hour = RTC_Read(RTC_TC_HOU);
  301. tm->tm_mday = RTC_Read(RTC_TC_DOM);
  302. tm->tm_mon = RTC_Read(RTC_TC_MTH) & RTC_TC_MTH_MASK;
  303. tm->tm_year = RTC_Read(RTC_TC_YEA);
  304. }
  305. void rtc_get_time(struct rtc_time *tm) {
  306. rtc_get_tick(tm);
  307. if (RTC_Read(RTC_TC_SEC) < tm->tm_sec) { /* SEC has carried */
  308. rtc_get_tick(tm);
  309. }
  310. tm->tm_year += RTC_MIN_YEAR;
  311. }