mtk-lk/platform/mt6779/ufs_aio_platform.c

/* Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein
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 */
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 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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 */

#include "ufs_aio_cfg.h"
#include "ufs_aio_platform.h"
#include "ufs_aio_hcd.h"
#include "ufs_aio_utils.h"
#if defined(MTK_UFS_DRV_DA)
#include <dev/irq/irq.h>        /* for MT_UFS_IRQ_ID */
#elif defined(MTK_UFS_DRV_LK)
#include <platform/mt_irq.h>
#endif
#ifdef MTK_UFS_DRV_PRELOADER
#include "pal_log.h"

#ifdef UFS_CFG_HQA_MODE
void ufs_aio_hqa_mode(void)
{
	pal_log_info("[UFS] ------- HQA or MPHY Debugging Mode ------");
}
#endif
#endif
//-------------------------------------------------------------------------
/** Round_Operation
 *  Round operation of A/B
 *  @param  A
 *  @param  B
 *  @retval round(A/B)
 */
//-------------------------------------------------------------------------
static unsigned int ufs_round(unsigned int A, unsigned int B)
{
    unsigned int temp;

    if (B == 0)
    {
        return 0xffffffff;
    }

    temp = A/B;

    if ((A-temp*B) >= ((temp+1)*B-A))
    {
        return (temp+1);
    }
    else
    {
        return temp;
    }
}

int ufs_aio_init_mphy(struct ufs_hba *hba)
{
	unsigned int N;
	unsigned int reg = 0;
	unsigned int temp = 0;

	/*
	Support t12 UFS TX Deemphasis by Software.
	RG_MP_TX_RDN_TRIM_CODE		0x11FA9000  ,  Bit [12:8]
	RG_MP_TX0_DRV_MASTER_3P5DB	0x11FA9008  ,  Bit [4:0]
	RG_MP_TX0_DRV_SLAVE_3P5DB	0x11FA9008  ,  Bit [7:5]
	RG_MP_TX0_DRV_MASTER_6DB	0x11FA9008  ,  Bit [12:8]
	RG_MP_TX0_DRV_SLAVE_6DB	0x11FA9008  ,  Bit [15:13]
	*/

	/* N = RG_MP_TX0_RDN_TRIM_CODE<12:8> + 9 */
	reg = readl(0x11fa9000);
	N = ((reg & (0x00001F00)) >> 8) + 9;

	/* RG_MP_TX0_DRV_MASTER_3P5DB = round(N*(5/6)) - 9 */
	temp = ufs_round(N*5, 6) - 9;
	reg = temp & 0x0000001F;

	/* RG_MP_TX0_DRV_SLAVE_3P5DB = N - round(N*(5/6)) - 3 */
	temp = N - ufs_round(N*5, 6) - 3;
	reg |= ((temp << 5) & 0x000000E0);

	/* RG_MP_TX0_DRV_MASTER_6DB = round(N*(3/4)) - 9 */
	temp = ufs_round(N*3, 4) - 9;
	reg |= ((temp << 8) & 0x00001F00);

	/* RG_MP_TX0_DRV_SLAVE_6DB = N - round(N*(3/4)) - 3 */
	temp = N - ufs_round(N*3, 4) - 3;
	reg |= ((temp << 13) & 0x0000E000);

	writel(((readl(0x11fa9008) & 0xFFFF0000) | reg), 0x11fa9008);

	return 0;
}

#if defined(MTK_UFS_DRV_DA) || defined(MTK_UFS_DRV_LK)
int ufs_get_irq_id(void)
{
	return MT_UFS_IRQ_ID;
}
#endif