ddp_misc.c 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209
  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #define LOG_TAG "MISC"
  32. #include <platform/ddp_reg.h>
  33. #include <platform/ddp_misc.h>
  34. #include <platform/ddp_log.h>
  35. #include <debug.h>
  36. void ddp_bypass_color(int idx, unsigned int width, unsigned int height, void * handle)
  37. {
  38. DDPDBG("bypass color\n");
  39. DISP_REG_SET(NULL,DISP_COLOR_CFG_MAIN, 1<<7); //bypass color engine
  40. DISP_REG_SET(NULL,DISP_COLOR_INTERNAL_IP_WIDTH, width); //bypass color engine
  41. DISP_REG_SET(NULL,DISP_COLOR_INTERNAL_IP_HEIGHT, height); //bypass color engine
  42. DISP_REG_SET(NULL,DISP_COLOR_START, 0x1); // start
  43. }
  44. void ddp_bypass_ccorr(unsigned int width, unsigned int height, void * handle)
  45. {
  46. DDPDBG("bypass ccorr\n");
  47. DISP_REG_MASK(NULL,DISP_REG_CCORR_CFG, 1, 1);
  48. DISP_REG_SET(NULL,DISP_REG_CCORR_SIZE, (width<<16)|height); //bypass color engine
  49. DISP_REG_SET(NULL,DISP_REG_CCORR_EN, 1);
  50. }
  51. void ddp_bypass_aal(unsigned int width, unsigned int height, void * handle)
  52. {
  53. DDPDBG("bypass aal\n");
  54. DISP_REG_SET_FIELD(handle,CFG_FLD_RELAY_MODE, DISP_AAL_CFG, 0x1); //relay_mode
  55. DISP_REG_SET(NULL,DISP_AAL_SIZE, (width<<16)|height); //bypass color engine
  56. DISP_REG_SET(handle,DISP_AAL_EN, 0x1); //bypass mode
  57. DISP_REG_SET(NULL,DISP_AAL_OUTPUT_SIZE, (width<<16)|height); //set output size
  58. }
  59. void ddp_bypass_gamma(unsigned int width, unsigned int height, void * handle)
  60. {
  61. DDPDBG("bypass gamma\n");
  62. DISP_REG_MASK(NULL,DISP_REG_GAMMA_CFG, 1, 1);
  63. DISP_REG_SET(NULL,DISP_REG_GAMMA_SIZE, (width<<16)|height); //bypass color engine
  64. DISP_REG_SET(handle,DISP_REG_GAMMA_EN, 0x1); //bypass mode
  65. }
  66. static int config_color(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  67. {
  68. int color_idx;
  69. if (module == DISP_MODULE_COLOR0)
  70. color_idx = 0;
  71. else
  72. color_idx = 1;
  73. DDPDBG("config color dirty = %d\n", pConfig->dst_dirty);
  74. if (!pConfig->dst_dirty) {
  75. return 0;
  76. }
  77. ddp_bypass_color(color_idx,pConfig->dst_w, pConfig->dst_h,cmdq);
  78. return 0;
  79. }
  80. static int config_ccorr(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  81. {
  82. DDPDBG("config ccorr dirty = %d\n", pConfig->dst_dirty);
  83. if (!pConfig->dst_dirty) {
  84. return 0;
  85. }
  86. ddp_bypass_ccorr(pConfig->dst_w, pConfig->dst_h,cmdq);
  87. return 0;
  88. }
  89. static int config_aal(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  90. {
  91. DDPDBG("config aal dirty = %d\n", pConfig->dst_dirty);
  92. if (!pConfig->dst_dirty) {
  93. return 0;
  94. }
  95. ddp_bypass_aal(pConfig->dst_w, pConfig->dst_h,cmdq);
  96. return 0;
  97. }
  98. static int config_gamma(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  99. {
  100. DDPDBG("config gamma dirty = %d\n", pConfig->dst_dirty);
  101. if (!pConfig->dst_dirty) {
  102. return 0;
  103. }
  104. ddp_bypass_gamma(pConfig->dst_w, pConfig->dst_h,cmdq);
  105. return 0;
  106. }
  107. static int clock_on(DISP_MODULE_ENUM module,void * handle)
  108. {
  109. ddp_enable_module_clock(module);
  110. return 0;
  111. }
  112. static int clock_off(DISP_MODULE_ENUM module,void * handle)
  113. {
  114. ddp_disable_module_clock(module);
  115. return 0;
  116. }
  117. ///////////////////////////////////////////////////////////
  118. // color
  119. DDP_MODULE_DRIVER ddp_driver_color = {
  120. .init = clock_on,
  121. .deinit = clock_off,
  122. .config = config_color,
  123. .start = NULL,
  124. .trigger = NULL,
  125. .stop = NULL,
  126. .reset = NULL,
  127. .power_on = clock_on,
  128. .power_off = clock_off,
  129. .is_idle = NULL,
  130. .is_busy = NULL,
  131. .dump_info = NULL,
  132. .bypass = NULL,
  133. .build_cmdq = NULL,
  134. .set_lcm_utils = NULL,
  135. };
  136. // ccorr
  137. DDP_MODULE_DRIVER ddp_driver_ccorr = {
  138. .init = clock_on,
  139. .deinit = clock_off,
  140. .config = config_ccorr,
  141. .start = NULL,
  142. .trigger = NULL,
  143. .stop = NULL,
  144. .reset = NULL,
  145. .power_on = clock_on,
  146. .power_off = clock_off,
  147. .is_idle = NULL,
  148. .is_busy = NULL,
  149. .dump_info = NULL,
  150. .bypass = NULL,
  151. .build_cmdq = NULL,
  152. .set_lcm_utils = NULL,
  153. };
  154. // aal
  155. DDP_MODULE_DRIVER ddp_driver_aal = {
  156. .init = clock_on,
  157. .deinit = clock_off,
  158. .config = config_aal,
  159. .start = NULL,
  160. .trigger = NULL,
  161. .stop = NULL,
  162. .reset = NULL,
  163. .power_on = clock_on,
  164. .power_off = clock_off,
  165. .is_idle = NULL,
  166. .is_busy = NULL,
  167. .dump_info = NULL,
  168. .bypass = NULL,
  169. .build_cmdq = NULL,
  170. .set_lcm_utils = NULL,
  171. };
  172. // gamma
  173. DDP_MODULE_DRIVER ddp_driver_gamma = {
  174. .init = clock_on,
  175. .deinit = clock_off,
  176. .config = config_gamma,
  177. .start = NULL,
  178. .trigger = NULL,
  179. .stop = NULL,
  180. .reset = NULL,
  181. .power_on = clock_on,
  182. .power_off = clock_off,
  183. .is_idle = NULL,
  184. .is_busy = NULL,
  185. .dump_info = NULL,
  186. .bypass = NULL,
  187. .build_cmdq = NULL,
  188. .set_lcm_utils = NULL,
  189. };