ccci_ld_md_ass.c 29 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <sys/types.h>
  32. #include <stdint.h>
  33. #include <platform/partition.h>
  34. #include <platform/mt_typedefs.h>
  35. #include <platform/boot_mode.h>
  36. #include <platform/mt_reg_base.h>
  37. #include <platform/errno.h>
  38. #include <printf.h>
  39. #include <string.h>
  40. #include <malloc.h>
  41. #include <libfdt.h>
  42. #include <platform/mt_gpt.h>
  43. #include <debug.h>
  44. #include "ccci_ld_md_core.h"
  45. #include "ccci_ld_md_errno.h"
  46. #define MODULE_NAME "LK_LD_MD"
  47. /*==============================================================================*/
  48. /* region |idx | bits | AP | MD1 | MDHW */
  49. /* md1_rom(dsp_rom)| 0 | 3:0 | f | f | f */
  50. /* md1_mcurw_hwro | 1 | 7:4 | f | f | f */
  51. /* md1_mcuro_hwrw | 2 |11:8 | f | f | f */
  52. /* md1_mcurw_hwrw | 3 |15:12 | f | f | f */
  53. /* md1_rw | 4 |19:16 | f | f | f */
  54. static void parse_mem_layout_attr_v5_hdr(struct md_check_header_v5 *hdr, struct image_section_desc tbl[])
  55. {
  56. unsigned int i, j;
  57. unsigned int region_attr_merged, shift_num, tmp;
  58. for (i = 0; i < 8; i++) {
  59. region_attr_merged = 0;
  60. for (j = 0; j < 4; j++) {
  61. shift_num = i<<2;/* equal *4 */
  62. tmp = (hdr->domain_attr[j]&(0x0000000F<<shift_num))>>shift_num;
  63. region_attr_merged |= (tmp<<(j*4));
  64. }
  65. tbl[i].mpu_attr = region_attr_merged;
  66. tbl[i].offset = hdr->region_info[i].region_offset;
  67. tbl[i].size = hdr->region_info[i].region_size;
  68. tbl[i].relate_idx = 0;
  69. tbl[i].ext_flag = 0;
  70. }
  71. /* Mark for end */
  72. tbl[i].offset = 0;
  73. tbl[i].size = 0;
  74. }
  75. static void parse_mem_layout_attr_v6_hdr(struct md_check_header_v6 *hdr, struct image_section_desc tbl[])
  76. {
  77. unsigned int i, j;
  78. unsigned int region_attr_merged, shift_num, tmp;
  79. for (i = 0; i < 8; i++) {
  80. region_attr_merged = 0;
  81. for (j = 0; j < 4; j++) {
  82. shift_num = i<<2;/* equal *4 */
  83. tmp = (hdr->domain_attr[j]&(0x0000000FU<<shift_num))>>shift_num;
  84. region_attr_merged |= (tmp<<(j*4));
  85. }
  86. tbl[i].mpu_attr = region_attr_merged;
  87. tbl[i].offset = hdr->region_info[i].region_offset;
  88. tbl[i].size = hdr->region_info[i].region_size;
  89. tbl[i].relate_idx = 0;
  90. tbl[i].ext_flag = 0;
  91. }
  92. /* Mark for end */
  93. tbl[i].offset = 0;
  94. tbl[i].size = 0;
  95. }
  96. static void *ccci_get_md_header(void *tail_addr, int *header_ver)
  97. {
  98. int size;
  99. void *header_addr = NULL;
  100. LD_DBG_LOG("ccci_get_md_header tail_addr[%p]\n", tail_addr);
  101. if (!tail_addr)
  102. return NULL;
  103. size = *((unsigned int *)(tail_addr - 4));
  104. LD_DBG_LOG("ccci_get_md_header check headr v1(%d), v3(%d), v5(%d), v6(%d) curr(%d)\n",
  105. sizeof(struct md_check_header_v1), sizeof(struct md_check_header_v3),
  106. sizeof(struct md_check_header_v5), sizeof(struct md_check_header_v6), size);
  107. if (size == sizeof(struct md_check_header_v1)) {
  108. header_addr = tail_addr - sizeof(struct md_check_header_v1);
  109. if (header_ver)
  110. *header_ver = 1;
  111. } else if (size == sizeof(struct md_check_header_v3)) {
  112. header_addr = tail_addr - sizeof(struct md_check_header_v3);
  113. if (header_ver)
  114. *header_ver = 3;
  115. } else if (size == sizeof(struct md_check_header_v5)) {
  116. header_addr = tail_addr - sizeof(struct md_check_header_v5);
  117. if (header_ver)
  118. *header_ver = 5;
  119. } else if (size == sizeof(struct md_check_header_v6)) {
  120. header_addr = tail_addr - sizeof(struct md_check_header_v6);
  121. if (header_ver)
  122. *header_ver = 6;
  123. }
  124. return header_addr;
  125. }
  126. static int ccci_get_max_chk_hdr_size(void)
  127. {
  128. int max = (int)sizeof(struct md_check_header_v5);
  129. int size = (int)sizeof(struct md_check_header_v4);
  130. if (max < size)
  131. max = size;
  132. size = (int)sizeof(struct md_check_header_v3);
  133. if (max < size)
  134. max = size;
  135. size = (int)sizeof(struct md_check_header_v1);
  136. if (max < size)
  137. max = size;
  138. size = (int)sizeof(struct md_check_header_v6);
  139. if (max < size)
  140. max = size;
  141. return max;
  142. }
  143. static int get_chk_hdr_size_by_ver(int ver)
  144. {
  145. switch (ver) {
  146. case 5:
  147. return (int)sizeof(struct md_check_header_v5);
  148. case 6:
  149. return (int)sizeof(struct md_check_header_v6);
  150. case 1:
  151. return (int)sizeof(struct md_check_header_v1);
  152. case 4:
  153. return (int)sizeof(struct md_check_header_v4);
  154. case 3:
  155. return (int)sizeof(struct md_check_header_v3);
  156. default:
  157. return 0;
  158. }
  159. return 0;
  160. }
  161. static int ccci_md_header_dump(void *header_addr, int ver)
  162. {
  163. #ifdef LD_IMG_DUMP_LOG_EN
  164. //int size;
  165. struct md_check_header_v1 *v1_hdr;
  166. struct md_check_header_v3 *v3_hdr;
  167. struct md_check_header_v5 *v5_hdr;
  168. struct md_check_header_v6 *v6_hdr;
  169. int i;
  170. if (!header_addr)
  171. return -LD_ERR_NULL_PTR;
  172. switch (ver) {
  173. case 1:
  174. /* parsing md check header */
  175. v1_hdr = (struct md_check_header_v1 *)header_addr;
  176. LD_DBG_LOG("===== Dump v1 md header =====\n");
  177. LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v1_hdr->common.check_header);
  178. LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v1_hdr->common.header_verno);
  179. LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v1_hdr->common.product_ver);
  180. LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v1_hdr->common.image_type);
  181. LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v1_hdr->common.mem_size);
  182. LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v1_hdr->common.md_img_size);
  183. LD_DBG_LOG("[%s] MD IMG - ap_md_smem_size: 0x%08X\n", MODULE_NAME, v1_hdr->ap_md_smem_size);
  184. LD_DBG_LOG("=============================\n");
  185. break;
  186. case 3: /* V3 */
  187. case 4:
  188. /* parsing md check header */
  189. v3_hdr = (struct md_check_header_v3 *)header_addr;
  190. LD_DBG_LOG("===== Dump v3 md header =====\n");
  191. LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v3_hdr->common.check_header);
  192. LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v3_hdr->common.header_verno);
  193. LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v3_hdr->common.product_ver);
  194. LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v3_hdr->common.image_type);
  195. LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v3_hdr->common.mem_size);
  196. LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v3_hdr->common.md_img_size);
  197. LD_DBG_LOG("[%s] MD IMG - dsp offset : 0x%08X\n", MODULE_NAME, v3_hdr->dsp_img_offset);
  198. LD_DBG_LOG("[%s] MD IMG - dsp size : 0x%08X\n", MODULE_NAME, v3_hdr->dsp_img_size);
  199. LD_DBG_LOG("[%s] MD IMG - rpc_sec_mem_addr : 0x%08X\n", MODULE_NAME, v3_hdr->rpc_sec_mem_addr);
  200. LD_DBG_LOG("=============================\n");
  201. break;
  202. case 5:
  203. /* parsing md check header */
  204. v5_hdr = (struct md_check_header_v5 *)header_addr;
  205. LD_DBG_LOG("===== Dump v5 md header =====\n");
  206. LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v5_hdr->common.check_header);
  207. LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v5_hdr->common.header_verno);
  208. LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v5_hdr->common.product_ver);
  209. LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v5_hdr->common.image_type);
  210. LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v5_hdr->common.mem_size);
  211. LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v5_hdr->common.md_img_size);
  212. LD_DBG_LOG("[%s] MD IMG - dsp offset : 0x%08X\n", MODULE_NAME, v5_hdr->dsp_img_offset);
  213. LD_DBG_LOG("[%s] MD IMG - dsp size : 0x%08X\n", MODULE_NAME, v5_hdr->dsp_img_size);
  214. LD_DBG_LOG("[%s] MD IMG - rpc_sec_mem_addr : 0x%08X\n", MODULE_NAME, v5_hdr->rpc_sec_mem_addr);
  215. LD_DBG_LOG("[%s] MD IMG - armv7 offset : 0x%08X\n", MODULE_NAME, v5_hdr->arm7_img_offset);
  216. LD_DBG_LOG("[%s] MD IMG - armv7 size : 0x%08X\n", MODULE_NAME, v5_hdr->arm7_img_size);
  217. LD_DBG_LOG("[%s] MD IMG - region num : 0x%08X\n", MODULE_NAME, v5_hdr->region_num);
  218. LD_DBG_LOG("[%s] MD IMG - ap_md_smem_size: 0x%08X\n", MODULE_NAME, v5_hdr->ap_md_smem_size);
  219. LD_DBG_LOG("[%s] MD IMG - md_md_smem_size: 0x%08X\n", MODULE_NAME, v5_hdr->md_to_md_smem_size);
  220. for (i = 0; i < 8; i++) {
  221. LD_DBG_LOG("[%s] MD IMG - region[%d] off : 0x%08X\n", MODULE_NAME, i,
  222. v5_hdr->region_info[i].region_offset);
  223. LD_DBG_LOG("[%s] MD IMG - region[%d] size: 0x%08X\n", MODULE_NAME, i,
  224. v5_hdr->region_info[i].region_size);
  225. }
  226. for (i = 0; i < 4; i++) {
  227. LD_DBG_LOG("[%s] MD IMG - domain_attr[%d] : 0x%08X\n", MODULE_NAME, i,
  228. v5_hdr->domain_attr[i]);
  229. }
  230. for (i = 0; i < MAX_PADDING_NUM_V5_HDR; i++) {
  231. LD_DBG_LOG("[%s] MD IMG - padding info[%d] offset: 0x%08X\n", MODULE_NAME, i,
  232. v5_hdr->padding_blk[i].start_offset);
  233. LD_DBG_LOG("[%s] MD IMG - padding info[%d] size: 0x%08X\n", MODULE_NAME, i,
  234. v5_hdr->padding_blk[i].length);
  235. }
  236. LD_DBG_LOG("=============================\n");
  237. break;
  238. case 6:
  239. /* parsing md check header */
  240. v6_hdr = (struct md_check_header_v6 *)header_addr;
  241. LD_DBG_LOG("===== Dump v6 md header =====\n");
  242. LD_DBG_LOG("[%s] MD IMG - Magic : %s\n" , MODULE_NAME, v6_hdr->common.check_header);
  243. LD_DBG_LOG("[%s] MD IMG - header_verno : 0x%08X\n", MODULE_NAME, v6_hdr->common.header_verno);
  244. LD_DBG_LOG("[%s] MD IMG - product_ver : 0x%08X\n", MODULE_NAME, v6_hdr->common.product_ver);
  245. LD_DBG_LOG("[%s] MD IMG - image_type : 0x%08X\n", MODULE_NAME, v6_hdr->common.image_type);
  246. LD_DBG_LOG("[%s] MD IMG - mem_size : 0x%08X\n", MODULE_NAME, v6_hdr->common.mem_size);
  247. LD_DBG_LOG("[%s] MD IMG - md_img_size : 0x%08X\n", MODULE_NAME, v6_hdr->common.md_img_size);
  248. LD_DBG_LOG("[%s] MD IMG - dsp offset : 0x%08X\n", MODULE_NAME, v6_hdr->dsp_img_offset);
  249. LD_DBG_LOG("[%s] MD IMG - dsp size : 0x%08X\n", MODULE_NAME, v6_hdr->dsp_img_size);
  250. LD_DBG_LOG("[%s] MD IMG - rpc_sec_mem_addr : 0x%08X\n", MODULE_NAME, v6_hdr->rpc_sec_mem_addr);
  251. LD_DBG_LOG("[%s] MD IMG - armv7 offset : 0x%08X\n", MODULE_NAME, v6_hdr->arm7_img_offset);
  252. LD_DBG_LOG("[%s] MD IMG - armv7 size : 0x%08X\n", MODULE_NAME, v6_hdr->arm7_img_size);
  253. LD_DBG_LOG("[%s] MD IMG - region num : 0x%08X\n", MODULE_NAME, v6_hdr->region_num);
  254. LD_DBG_LOG("[%s] MD IMG - ap_md_smem_size: 0x%08X\n", MODULE_NAME, v6_hdr->ap_md_smem_size);
  255. LD_DBG_LOG("[%s] MD IMG - md_md_smem_size: 0x%08X\n", MODULE_NAME, v6_hdr->md_to_md_smem_size);
  256. LD_DBG_LOG("[%s] MD IMG - amms_pos_size : 0x%08X\n", MODULE_NAME, v6_hdr->amms_pos_size);
  257. for (i = 0; i < 8; i++) {
  258. LD_DBG_LOG("[%s] MD IMG - region[%d] off : 0x%08X\n", MODULE_NAME, i,
  259. v6_hdr->region_info[i].region_offset);
  260. LD_DBG_LOG("[%s] MD IMG - region[%d] size: 0x%08X\n", MODULE_NAME, i,
  261. v6_hdr->region_info[i].region_size);
  262. }
  263. for (i = 0; i < 4; i++) {
  264. LD_DBG_LOG("[%s] MD IMG - domain_attr[%d] : 0x%08X\n", MODULE_NAME, i,
  265. v6_hdr->domain_attr[i]);
  266. }
  267. for (i = 0; i < MAX_PADDING_NUM_V6_HDR; i++) {
  268. LD_DBG_LOG("[%s] MD IMG - padding info[%d] offset: 0x%08X\n", MODULE_NAME, i,
  269. v6_hdr->padding_blk[i].start_offset);
  270. LD_DBG_LOG("[%s] MD IMG - padding info[%d] size: 0x%08X\n", MODULE_NAME, i,
  271. v6_hdr->padding_blk[i].length);
  272. }
  273. LD_DBG_LOG("[%s] MD IMG - drdi offset : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_offset);
  274. LD_DBG_LOG("[%s] MD IMG - drdi size : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_size);
  275. LD_DBG_LOG("[%s] Runtime - drdi rt offset : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_rt_offset);
  276. LD_DBG_LOG("[%s] Runtime - drdi rt size : 0x%08X\n", MODULE_NAME, v6_hdr->drdi_rt_size);
  277. LD_DBG_LOG("=============================\n");
  278. break;
  279. default:
  280. break;
  281. }
  282. #endif
  283. return 0;
  284. }
  285. int verify_main_img_check_header(modem_info_t *info)
  286. {
  287. struct md_check_header_comm *common_hdr;
  288. int md_hdr_ver;
  289. char md_str[16];
  290. int ret;
  291. /* Parse check header */
  292. common_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, &md_hdr_ver);
  293. if (common_hdr == NULL) {
  294. ALWAYS_LOG("parse check header fail\n");
  295. ret = -LD_ERR_GET_COM_CHK_HDR_FAIL;
  296. goto _Hdr_Verity_Exit;
  297. }
  298. if (strncmp((char const *)common_hdr->check_header, "CHECK_HEADER", 12)) {
  299. ALWAYS_LOG("invald md check header str[%s]\n", common_hdr->check_header);
  300. ret = -LD_ERR_CHK_HDR_PATTERN;
  301. goto _Hdr_Verity_Exit;
  302. }
  303. /* Dump header info */
  304. ccci_md_header_dump(common_hdr, md_hdr_ver);
  305. /* Post to platform */
  306. ccci_hal_post_hdr_info((void*)common_hdr, md_hdr_ver, (int)info->md_id);
  307. if (info->resv_mem_size < common_hdr->mem_size) {
  308. ALWAYS_LOG("Reserved memory not enough, resv:%d, require:%d\n",
  309. (int)info->resv_mem_size, (int)common_hdr->mem_size);
  310. ret = -LD_ERR_RESERVE_MEM_NOT_ENOUGH;
  311. goto _Hdr_Verity_Exit;
  312. }
  313. info->resv_mem_size = common_hdr->mem_size;
  314. info->ro_rw_size = common_hdr->md_img_size;
  315. info->md_type = common_hdr->image_type;
  316. if (info->md_id < MD1_DSP) {
  317. /* Inssert image size and check header info to arguments array for kernel */
  318. snprintf(md_str, 16, "md%dimg", info->md_id + 1);
  319. if (insert_ccci_tag_inf(md_str, (char*)&info->ro_rw_size, sizeof(unsigned int)) < 0)
  320. ALWAYS_LOG("insert %s fail\n", md_str);
  321. /* Inssert image size and check header info to arguments array for kernel */
  322. snprintf(md_str, 16, "md%d_chk", info->md_id + 1);
  323. if (insert_ccci_tag_inf(md_str, (char*)common_hdr, get_chk_hdr_size_by_ver(md_hdr_ver)) < 0)
  324. ALWAYS_LOG("insert %s fail\n", md_str);
  325. }
  326. ccci_update_md_version(info->md_id, common_hdr->build_ver);
  327. return 0;
  328. _Hdr_Verity_Exit:
  329. return ret;
  330. }
  331. /***************************************************************************************************
  332. ****************************************************************************************************
  333. ** Sub section:
  334. ** Download image list part: normal load and dummy AP
  335. ** MD1 default using v5 header; MD3 default using v1 header
  336. ****************************************************************************************************
  337. ***************************************************************************************************/
  338. static download_info_t *find_ptr_at_img_list(download_info_t img_list[], int img_type)
  339. {
  340. download_info_t *curr = img_list;
  341. while (curr->img_type != 0) {
  342. if (curr->img_type == img_type)
  343. return curr;
  344. curr++;
  345. }
  346. return NULL;
  347. }
  348. /* --- Assistant function for MD check header v5 --- */
  349. int ass_func_for_v5_normal_img(void *load_info, void *data)
  350. {
  351. modem_info_t *info = (modem_info_t *)load_info;
  352. download_info_t *ld_list = (download_info_t *)data;
  353. struct md_check_header_v5 *chk_hdr;
  354. download_info_t *curr;
  355. unsigned char *md_resv_mem_addr = NULL;
  356. struct image_section_desc *tbl;
  357. int mpu_num_for_padding;
  358. int ret;
  359. /* region: 8; padding:3; mark for end:1 total: 12(=8+3+1) */
  360. tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*12);
  361. if (tbl == NULL)
  362. return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
  363. /* find start addr for check header */
  364. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  365. if (chk_hdr == NULL) {
  366. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  367. goto _free_alloc_mem;
  368. }
  369. /* Get md main image addr at memory */
  370. curr = find_ptr_at_img_list(ld_list, main_img);
  371. if (curr == NULL) {
  372. ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
  373. goto _free_alloc_mem;
  374. } else
  375. md_resv_mem_addr = curr->mem_addr;
  376. /* Get dsp image addr at memory and size */
  377. curr = find_ptr_at_img_list(ld_list, dsp_img);
  378. if (curr == NULL) {
  379. ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
  380. goto _free_alloc_mem;
  381. } else {
  382. curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
  383. curr->img_size = chk_hdr->dsp_img_size;
  384. }
  385. /* Get armv7 image addr at memory and size */
  386. curr = find_ptr_at_img_list(ld_list, armv7_img);
  387. if (curr == NULL) {
  388. ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
  389. goto _free_alloc_mem;
  390. } else {
  391. curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset;
  392. curr->img_size = chk_hdr->arm7_img_size;
  393. }
  394. parse_mem_layout_attr_v5_hdr(chk_hdr, tbl);
  395. mpu_num_for_padding = ccci_hal_get_mpu_num_for_padding_mem();
  396. if (mpu_num_for_padding >= 1)
  397. retrieve_free_padding_mem_v5_hdr((modem_info_t *)load_info, tbl, chk_hdr, mpu_num_for_padding);
  398. ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
  399. if (ret < 0)
  400. goto _free_alloc_mem;
  401. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  402. _free_alloc_mem:
  403. if (tbl)
  404. free(tbl);
  405. return ret;
  406. }
  407. int ass_func_for_v6_normal_img(void *load_info, void *data)
  408. {
  409. modem_info_t *info = (modem_info_t *)load_info;
  410. download_info_t *ld_list = (download_info_t *)data;
  411. struct md_check_header_v6 *chk_hdr;
  412. download_info_t *curr;
  413. unsigned char *md_resv_mem_addr = NULL;
  414. struct image_section_desc *tbl;
  415. int mpu_num_for_padding;
  416. int i, ret;
  417. /* region: 8; padding:8; mark for end:1 total: 17(=8+8+1) */
  418. tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*17);
  419. if (tbl == NULL)
  420. return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
  421. for (i = 0; i < 17; i++)
  422. tbl[i].ext_flag = 0;
  423. /* find start addr for check header */
  424. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  425. if (chk_hdr == NULL) {
  426. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  427. goto _free_alloc_mem;
  428. }
  429. /* Get md main image addr at memory */
  430. curr = find_ptr_at_img_list(ld_list, main_img);
  431. if (curr == NULL) {
  432. ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
  433. goto _free_alloc_mem;
  434. } else
  435. md_resv_mem_addr = curr->mem_addr;
  436. /* Get dsp image addr at memory and size */
  437. curr = find_ptr_at_img_list(ld_list, dsp_img);
  438. if (curr == NULL) {
  439. ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
  440. goto _free_alloc_mem;
  441. } else {
  442. curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
  443. if (curr->ass_func)
  444. curr->img_size = DSP_IMG_MAX_SIZE; /* it will be overwriten after loading */
  445. else
  446. curr->img_size = chk_hdr->dsp_img_size;
  447. }
  448. /* Get armv7 image addr at memory and size */
  449. curr = find_ptr_at_img_list(ld_list, armv7_img);
  450. if (curr == NULL) {
  451. ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
  452. goto _free_alloc_mem;
  453. } else {
  454. curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset;
  455. curr->img_size = chk_hdr->arm7_img_size;
  456. }
  457. /* Get drdi image addr at memory and size */
  458. curr = find_ptr_at_img_list(ld_list, drdi_img);
  459. if (curr == NULL) {
  460. ret = -LD_ERR_ASS_FIND_DRDI_INF_FAIL;
  461. goto _free_alloc_mem;
  462. } else {
  463. /* Note here, just for MD R3 BM script compatible workaround,
  464. for final solution, rt_xxx check should be removed */
  465. if ((chk_hdr->drdi_rt_offset != 0) && (chk_hdr->drdi_rt_size != 0)) {
  466. curr->mem_addr = md_resv_mem_addr + chk_hdr->drdi_offset;
  467. curr->img_size = chk_hdr->drdi_size;
  468. }
  469. }
  470. parse_mem_layout_attr_v6_hdr(chk_hdr, tbl);
  471. mpu_num_for_padding = ccci_hal_get_mpu_num_for_padding_mem();
  472. if (mpu_num_for_padding >= 1)
  473. retrieve_free_padding_mem_v6_hdr((modem_info_t *)load_info, tbl, chk_hdr, mpu_num_for_padding);
  474. ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
  475. if (ret < 0)
  476. goto _free_alloc_mem;
  477. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  478. _free_alloc_mem:
  479. if (tbl)
  480. free(tbl);
  481. return ret;
  482. }
  483. int ass_func_for_v1_normal_img(void *load_info, void *data)
  484. {
  485. modem_info_t *info = (modem_info_t *)load_info;
  486. struct md_check_header_v1 *chk_hdr;
  487. struct image_section_desc *tbl;
  488. int ret;
  489. /* region: 2; mark for end:1 total: 3(=2+1) */
  490. tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*3);
  491. if (tbl == NULL)
  492. return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
  493. /* find start addr for check header */
  494. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  495. if (chk_hdr == NULL) {
  496. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  497. goto _free_alloc_mem;
  498. }
  499. /* Configure mpu info */
  500. /* RO part */
  501. tbl[0].mpu_attr = 0xFFFFFFFF;
  502. tbl[0].offset = 0;
  503. tbl[0].size = chk_hdr->common.md_img_size;
  504. tbl[0].relate_idx = 0;
  505. tbl[0].ext_flag = 0;
  506. /* RW part */
  507. tbl[1].mpu_attr = 0xFFFFFFFF;
  508. tbl[1].offset = tbl[0].offset + tbl[0].size;
  509. tbl[1].size = chk_hdr->common.mem_size - chk_hdr->common.md_img_size;
  510. tbl[1].relate_idx = 0;
  511. tbl[1].ext_flag = 0;
  512. /* Mark for end */
  513. tbl[2].mpu_attr = 0xFFFFFFFF;
  514. tbl[2].offset = 0;
  515. tbl[2].size = 0;
  516. tbl[2].relate_idx = 0;
  517. tbl[2].ext_flag = 0;
  518. ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
  519. if (ret < 0)
  520. goto _free_alloc_mem;
  521. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  522. _free_alloc_mem:
  523. if (tbl)
  524. free(tbl);
  525. return ret;
  526. }
  527. int ass_func_for_v1_r8_normal_img(void *load_info, void *data)
  528. {
  529. modem_info_t *info = (modem_info_t *)load_info;
  530. struct md_check_header_v1 *chk_hdr;
  531. struct image_section_desc *tbl;
  532. int ret;
  533. /* region: 2; mark for end:1 total: 3(=2+1) */
  534. tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*3);
  535. if (tbl == NULL)
  536. return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
  537. /* find start addr for check header */
  538. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  539. if (chk_hdr == NULL) {
  540. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  541. goto _free_alloc_mem;
  542. }
  543. /* Configure mpu info */
  544. /* RO part */
  545. tbl[0].mpu_attr = 0xFFFFFFFF;
  546. tbl[0].offset = 0;
  547. tbl[0].size = chk_hdr->common.md_img_size;
  548. tbl[0].size = (tbl[0].size + 0xFFFF)&(~0xFFFF);
  549. tbl[0].relate_idx = 0;
  550. tbl[0].ext_flag = 0;
  551. /* RW part */
  552. tbl[1].mpu_attr = 0xFFFFFFFF;
  553. tbl[1].offset = tbl[0].offset + tbl[0].size;
  554. tbl[1].size = chk_hdr->common.mem_size - tbl[0].size;
  555. tbl[1].relate_idx = 0;
  556. tbl[1].ext_flag = 0;
  557. /* Mark for end */
  558. tbl[2].mpu_attr = 0xFFFFFFFF;
  559. tbl[2].offset = 0;
  560. tbl[2].size = 0;
  561. tbl[2].relate_idx = 0;
  562. tbl[2].ext_flag = 0;
  563. ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
  564. if (ret < 0)
  565. goto _free_alloc_mem;
  566. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  567. _free_alloc_mem:
  568. if (tbl)
  569. free(tbl);
  570. return ret;
  571. }
  572. /* --- Assistant function for DSP check header v3 --- */
  573. int ass_func_for_dsp_normal_img(void *load_info, void *data)
  574. {
  575. modem_info_t *info = (modem_info_t *)load_info;
  576. struct md_check_header_v3 *chk_hdr;
  577. struct image_section_desc *tbl;
  578. int ret;
  579. /* region: 8; padding:3; mark for end:1 total: 12(=8+3+1) */
  580. tbl = (struct image_section_desc *)malloc(sizeof(struct image_section_desc)*12);
  581. if (tbl == NULL)
  582. return -LD_ERR_ASS_FUNC_ALLOC_MEM_FAIL;
  583. /* find start addr for check header */
  584. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  585. if (chk_hdr == NULL) {
  586. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  587. goto _free_alloc_mem;
  588. }
  589. /* Configure mpu info */
  590. /* RO part */
  591. tbl[0].mpu_attr = 0xFFFFFFFF;
  592. /*dsp base addr = md base addr + DSP offset, so RO offset should be 0*/
  593. tbl[0].offset = 0;
  594. tbl[0].size = chk_hdr->common.md_img_size; /*DSP RO size = dsp img + padding*/
  595. /*64K align*/
  596. tbl[0].size = ((tbl[0].size + 0xFFFF)&(~0xFFFF));
  597. tbl[0].relate_idx = 0;
  598. tbl[0].ext_flag = 0;
  599. /* RW part */
  600. tbl[1].mpu_attr = 0xFFFFFFFF;
  601. tbl[1].offset = tbl[0].offset + tbl[0].size;
  602. tbl[1].size = chk_hdr->common.mem_size - tbl[0].size;
  603. tbl[1].relate_idx = 0;
  604. tbl[1].ext_flag = 0;
  605. /* Mark for end */
  606. tbl[3].mpu_attr = 0xFFFFFFFF;
  607. tbl[3].offset = 0;
  608. tbl[3].size = 0;
  609. tbl[3].relate_idx = 0;
  610. tbl[3].ext_flag = 0;
  611. ret = ccci_hal_send_mpu_info_to_platorm(load_info, tbl);
  612. if (ret < 0)
  613. goto _free_alloc_mem;
  614. _free_alloc_mem:
  615. if (tbl)
  616. free(tbl);
  617. return ret;
  618. }
  619. int ass_func_for_v5_md_only_img(void *load_info, void *data)
  620. {
  621. modem_info_t *info = (modem_info_t *)load_info;
  622. download_info_t *ld_list = (download_info_t *)data;
  623. struct md_check_header_v5 *chk_hdr;
  624. download_info_t *curr;
  625. unsigned char *md_resv_mem_addr = NULL;
  626. int ret;
  627. /* find start addr for check header */
  628. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  629. if (chk_hdr == NULL) {
  630. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  631. goto _exit;
  632. }
  633. /* Get md main image(MD only/HVT) addr at memory */
  634. curr = find_ptr_at_img_list(ld_list, main_img);
  635. if (curr == NULL) {
  636. ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
  637. goto _exit;
  638. } else
  639. md_resv_mem_addr = curr->mem_addr;
  640. /* Get dsp image addr at memory and size */
  641. curr = find_ptr_at_img_list(ld_list, dsp_img);
  642. if (curr == NULL) {
  643. ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
  644. goto _exit;
  645. } else {
  646. curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
  647. curr->img_size = chk_hdr->dsp_img_size;
  648. }
  649. /* Get armv7 image addr at memory and size */
  650. curr = find_ptr_at_img_list(ld_list, armv7_img);
  651. if (curr == NULL) {
  652. ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
  653. goto _exit;
  654. } else {
  655. curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset; /* using arm7 section as ramdisk */
  656. curr->img_size = chk_hdr->arm7_img_size;
  657. }
  658. /* Get ramdisk image addr at memory and size */
  659. curr = find_ptr_at_img_list(ld_list, ramdisk_img);
  660. if (curr == NULL) {
  661. ret = -LD_ERR_ASS_FIND_RAMDISK_INF_FAIL;
  662. goto _exit;
  663. } else {
  664. curr->mem_addr = md_resv_mem_addr + chk_hdr->ramdisk_offset;
  665. curr->img_size = chk_hdr->ramdisk_size;
  666. }
  667. /* Get l1_core image addr at memory and size */
  668. curr = find_ptr_at_img_list(ld_list, l1_core_img);
  669. if (curr == NULL) {
  670. ret = -LD_ERR_ASS_FIND_L1CORE_INF_FAIL;
  671. goto _exit;
  672. } else {
  673. curr->mem_addr = md_resv_mem_addr + chk_hdr->region_info[7].region_offset; /* using padding[1] section as l1core */
  674. curr->img_size = chk_hdr->region_info[7].region_size;
  675. }
  676. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  677. _exit:
  678. return ret;
  679. }
  680. int ass_func_for_v6_md_only_img(void *load_info, void *data)
  681. {
  682. modem_info_t *info = (modem_info_t *)load_info;
  683. download_info_t *ld_list = (download_info_t *)data;
  684. struct md_check_header_v6 *chk_hdr;
  685. download_info_t *curr;
  686. unsigned char *md_resv_mem_addr = NULL;
  687. int ret;
  688. /* find start addr for check header */
  689. chk_hdr = ccci_get_md_header((unsigned char*)((unsigned long)info->base_addr) + info->load_size, NULL);
  690. if (chk_hdr == NULL) {
  691. ret = -LD_ERR_ASS_FUNC_GET_CHK_HDR_FAIL;
  692. goto _exit;
  693. }
  694. /* Get md main image(MD only/HVT) addr at memory */
  695. curr = find_ptr_at_img_list(ld_list, main_img);
  696. if (curr == NULL) {
  697. ret = -LD_ERR_ASS_FIND_MAIN_INF_FAIL;
  698. goto _exit;
  699. } else
  700. md_resv_mem_addr = curr->mem_addr;
  701. /* Get dsp image addr at memory and size */
  702. curr = find_ptr_at_img_list(ld_list, dsp_img);
  703. if (curr == NULL) {
  704. ret = -LD_ERR_ASS_FIND_DSP_INF_FAIL;
  705. goto _exit;
  706. } else {
  707. curr->mem_addr = md_resv_mem_addr + chk_hdr->dsp_img_offset;
  708. curr->img_size = chk_hdr->dsp_img_size;
  709. }
  710. /* Get armv7 image addr at memory and size */
  711. curr = find_ptr_at_img_list(ld_list, armv7_img);
  712. if (curr == NULL) {
  713. ret = -LD_ERR_ASS_FIND_ARMV7_INF_FAIL;
  714. goto _exit;
  715. } else {
  716. curr->mem_addr = md_resv_mem_addr + chk_hdr->arm7_img_offset; /* using arm7 section as ramdisk */
  717. curr->img_size = chk_hdr->arm7_img_size;
  718. }
  719. /* Get ramdisk image addr at memory and size */
  720. curr = find_ptr_at_img_list(ld_list, ramdisk_img);
  721. if (curr == NULL) {
  722. ret = -LD_ERR_ASS_FIND_RAMDISK_INF_FAIL;
  723. goto _exit;
  724. } else {
  725. curr->mem_addr = md_resv_mem_addr + chk_hdr->ramdisk_offset;
  726. curr->img_size = chk_hdr->ramdisk_size;
  727. }
  728. /* Get l1_core image addr at memory and size */
  729. curr = find_ptr_at_img_list(ld_list, l1_core_img);
  730. if (curr == NULL) {
  731. ret = -LD_ERR_ASS_FIND_L1CORE_INF_FAIL;
  732. goto _exit;
  733. } else {
  734. curr->mem_addr = md_resv_mem_addr + chk_hdr->region_info[7].region_offset; /* using padding[1] section as l1core */
  735. curr->img_size = chk_hdr->region_info[7].region_size;
  736. }
  737. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  738. _exit:
  739. return ret;
  740. }
  741. int ass_func_for_v1_md_only_img(void *load_info, void *data)
  742. {
  743. int ret;
  744. ret = ccci_hal_apply_hw_remap_for_md_ro_rw(load_info);
  745. return ret;
  746. }