mtk-lk/platform/common/power/mt6370_pmu_charger.h

/* Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein
 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
 * Without the prior written permission of MediaTek inc. and/or its licensors,
 * any reproduction, modification, use or disclosure of MediaTek Software,
 * and information contained herein, in whole or in part, shall be strictly prohibited.
 */

/* MediaTek Inc. (C) 2015. All rights reserved.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 *
 * The following software/firmware and/or related documentation ("MediaTek Software")
 * have been modified by MediaTek Inc. All revisions are subject to any receiver\'s
 * applicable license agreements with MediaTek Inc.
 */

#ifndef __MT6370_PMU_CHARGER_H
#define __MT6370_PMU_CHARGER_H

#include <bits.h>

#ifdef MTK_MT6370_PMU_CHARGER_SUPPORT
int mt6370_chg_probe(void);
#else
static inline int mt6370_chg_probe(void)
{
	return 0;
}
#endif

#define MT6370_SLAVE_ADDR		(0x34)
#define RT5081_VENDOR_ID		(0x80)
#define MT6370_VENDOR_ID		(0xE0)
#define MT6371_VENDOR_ID		(0xF0)
#define MT6372_VENDOR_ID		(0x90)
#define MT6372C_VENDOR_ID		(0xB0)

/* core control */
#define MT6370_PMU_REG_DEVINFO		(0x00)
#define MT6370_PMU_REG_CORECTRL1	(0x01)
#define MT6370_PMU_REG_CORECTRL2	(0x02)
#define MT6370_PMU_REG_RSTPASCODE1	(0x03)
#define MT6370_PMU_REG_RSTPASCODE2	(0x04)
#define MT6370_PMU_REG_HIDDENPASCODE1	(0x07)
#define MT6370_PMU_REG_HIDDENPASCODE2	(0x08)
#define MT6370_PMU_REG_HIDDENPASCODE3	(0x09)
#define MT6370_PMU_REG_HIDDENPASCODE4	(0x0A)

/* charger control */
#define MT6370_PMU_REG_CHGCTRL1		(0x11)
#define MT6370_PMU_REG_CHGCTRL2		(0x12)
#define MT6370_PMU_REG_CHGCTRL3		(0x13)
#define MT6370_PMU_REG_CHGCTRL4		(0x14)
#define MT6370_PMU_REG_CHGCTRL5		(0x15)
#define MT6370_PMU_REG_CHGCTRL6		(0x16)
#define MT6370_PMU_REG_CHGCTRL7		(0x17)
#define MT6370_PMU_REG_CHGCTRL8		(0x18)
#define MT6370_PMU_REG_CHGCTRL9		(0x19)
#define MT6370_PMU_REG_CHGCTRL10	(0x1A)
#define MT6370_PMU_REG_CHGCTRL11	(0x1B)
#define MT6370_PMU_REG_CHGCTRL12	(0x1C)
#define MT6370_PMU_REG_CHGCTRL13	(0x1D)
#define MT6370_PMU_REG_CHGCTRL14	(0x1E)
#define MT6370_PMU_REG_CHGCTRL15	(0x1F)
#define MT6370_PMU_REG_CHGCTRL16	(0x20)
#define MT6370_PMU_REG_CHGADC		(0x21)
#define MT6370_PMU_REG_DEVICETYPE	(0x22)
#define MT6370_PMU_REG_QCCTRL1		(0x23)
#define MT6370_PMU_REG_QCCTRL2		(0x24)
#define MT6370_PMU_REG_QC3P0CTRL1	(0x25)
#define MT6370_PMU_REG_QC3P0CTRL2	(0x26)
#define MT6370_PMU_REG_USBSTATUS1	(0x27)
#define MT6370_PMU_REG_QCSTATUS1	(0x28)
#define MT6370_PMU_REG_QCSTATUS2	(0x29)
#define MT6370_PMU_REG_CHGPUMP		(0x2A)
#define MT6370_PMU_REG_CHGCTRL17	(0x2B)
#define MT6370_PMU_REG_CHGCTRL18	(0x2C)
#define MT6370_PMU_REG_CHGDIRCHG1	(0x2D)
#define MT6370_PMU_REG_CHGDIRCHG2	(0x2E)
#define MT6370_PMU_REG_CHGDIRCHG3	(0x2F)
#define MT6370_PMU_REG_CHGHIDDENCTRL6	(0x35)
#define MT6370_PMU_REG_CHGHIDDENCTRL7	(0x36)
#define MT6370_PMU_REG_CHGHIDDENCTRL8	(0x37)
#define MT6370_PMU_REG_CHGHIDDENCTRL9	(0x38)
#define MT6370_PMU_REG_CHGHIDDENCTRL15	(0x3E)
#define MT6370_PMU_REG_CHGSTAT		(0x4A)
#define MT6370_PMU_REG_CHGNTC		(0x4B)
#define MT6370_PMU_REG_ADCDATAH		(0x4C)
#define MT6370_PMU_REG_ADCDATAL		(0x4D)
#define MT6370_PMU_REG_CHGCTRL19	(0x60)
#define MT6370_PMU_REG_OVPCTRL		(0x61)
/* status event */
#define MT6370_PMU_REG_CHGSTAT1		(0xD0)
#define MT6370_PMU_REG_CHGSTAT2		(0xD1)
#define MT6370_PMU_REG_CHGSTAT3		(0xD2)
#define MT6370_PMU_REG_CHGSTAT4		(0xD3)
#define MT6370_PMU_REG_CHGSTAT5		(0xD4)
#define MT6370_PMU_REG_CHGSTAT6		(0xD5)
#define MT6370_PMU_REG_QCSTAT		(0xD6)
#define MT6370_PMU_REG_DICHGSTAT	(0xD7)
#define MT6370_PMU_REG_OVPCTRLSTAT	(0xD8)
/* test mode related register */
#define MT6370_PMU_REG_TM_PAS_CODE1	(0xF0)
#define MT6370_PMU_REG_TM_INF		(0xF4)
#define MT6370_PMU_REG_BANK_REG		(0xFF)
#define MT6370_TM_REG_ICC_1A		(0x19)
#define MT6370_TM_REG_TM_INF		(0x41)

/* Parameter */
/* mA */
#define MT6370_ICHG_MIN			100
#define MT6370_ICHG_MAX			5000
#define MT6370_ICHG_STEP		100

/* mA */
#define MT6370_IEOC_MIN			100
#define MT6370_IEOC_MAX			850
#define MT6370_IEOC_STEP		50

/* mV */
#define MT6370_MIVR_MIN			3900
#define MT6370_MIVR_MAX			13400
#define MT6370_MIVR_STEP		100

/* mA */
#define MT6370_AICR_MIN			100
#define MT6370_AICR_MAX			3250
#define MT6370_AICR_STEP		50

/* mV */
#define MT6370_BAT_VOREG_MIN		3900
#define MT6370_BAT_VOREG_MAX		4710
#define MT6370_BAT_VOREG_STEP		10

/* mV */
#define MT6370_BOOST_VOREG_MIN		4425
#define MT6370_BOOST_VOREG_MAX		5825
#define MT6370_BOOST_VOREG_STEP		25

/* mV */
#define MT6370_VPREC_MIN		2000
#define MT6370_VPREC_MAX		3500
#define MT6370_VPREC_STEP		100

/* mA */
#define MT6370_IPREC_MIN		100
#define MT6370_IPREC_MAX		850
#define MT6370_IPREC_STEP		50

/* mV */
#define MT6370_VRECHG_MIN		100
#define MT6370_VRECHG_MAX		400
#define MT6370_VRECHG_STEP		100

/* Watchdog fast-charge timer */
/* hour */
#define MT6370_WT_FC_MIN		4
#define MT6370_WT_FC_MAX		20
#define MT6370_WT_FC_STEP		2

/* IR compensation */
/* mohm */
#define MT6370_IRCMP_RES_MIN		0
#define MT6370_IRCMP_RES_MAX		175
#define MT6370_IRCMP_RES_STEP		25

/* IR compensation maximum voltage clamp */
/* mV */
#define MT6370_IRCMP_VCLAMP_MIN		0
#define MT6370_IRCMP_VCLAMP_MAX		224
#define MT6370_IRCMP_VCLAMP_STEP	32

/* PE+20 voltage */
/* mV */
#define MT6370_PEP20_VOLT_MIN		5500
#define MT6370_PEP20_VOLT_MAX		20000
#define MT6370_PEP20_VOLT_STEP		500

/* AICL VTH */
/* mV */
#define MT6370_AICL_VTH_MIN		4100
#define MT6370_AICL_VTH_MAX		4800
#define MT6370_AICL_VTH_STEP		100

/* VBUSOV LVL */
#define MT6370_DC_VBUSOV_LVL_MIN	3900
#define MT6370_DC_VBUSOV_LVL_MAX	7000
#define MT6370_DC_VBUSOV_LVL_STEP	100

/* IBUSOC LVL */
#define MT6370_DC_IBUSOC_LVL_MIN	4000
#define MT6370_DC_IBUSOC_LVL_MAX	6500
#define MT6370_DC_IBUSOC_LVL_STEP	500

/* ADC unit/offset */
#define MT6370_ADC_UNIT_VBUS_DIV5	25 /* mV */
#define MT6370_ADC_UNIT_VBUS_DIV2	10 /* mV */
#define MT6370_ADC_UNIT_VSYS		5  /* mV */
#define MT6370_ADC_UNIT_VBAT		5  /* mV */
#define MT6370_ADC_UNIT_TS_BAT		25 /* 0.01% */
#define MT6370_ADC_UNIT_IBUS		50 /* mA */
#define MT6370_ADC_UNIT_IBAT		50 /* mA */
#define MT6370_ADC_UNIT_CHG_VDDP	5  /* mV */
#define MT6370_ADC_UNIT_TEMP_JC		2  /* degree */

#define MT6370_ADC_OFFSET_VBUS_DIV5	0 /* mV */
#define MT6370_ADC_OFFSET_VBUS_DIV2	0 /* mV */
#define MT6370_ADC_OFFSET_VSYS		0 /* mV */
#define MT6370_ADC_OFFSET_VBAT		0 /* mV */
#define MT6370_ADC_OFFSET_TS_BAT	0 /* % */
#define MT6370_ADC_OFFSET_IBUS		0 /* mA */
#define MT6370_ADC_OFFSET_IBAT		0 /* mA */
#define MT6370_ADC_OFFSET_CHG_VDDP	0 /* mV */
#define MT6370_ADC_OFFSET_TEMP_JC	(-40)  /* degree */

/* ========== CHG_CTRL1 0x11 ============ */
#define MT6370_SHIFT_OPA_MODE		0
#define MT6370_SHIFT_HZ_EN		2

#define MT6370_MASK_OPA_MODE		BIT(MT6370_SHIFT_OPA_MODE)
#define MT6370_MASK_HZ_EN		BIT(MT6370_SHIFT_HZ_EN)

/* ========== CHG_CTRL2 0x12 ============ */
#define MT6370_SHIFT_CHG_EN		0
#define MT6370_SHIFT_CFO_EN		1
#define MT6370_SHIFT_IINLMTSEL		2
#define MT6370_SHIFT_TE_EN		4
#define MT6370_SHIFT_BYPASS_MODE	5

#define MT6370_MASK_CHG_EN		BIT(MT6370_SHIFT_CHG_EN)
#define MT6370_MASK_CFO_EN		BIT(MT6370_SHIFT_CFO_EN)
#define MT6370_MASK_IINLMTSEL		0x0C
#define MT6370_MASK_TE_EN		BIT(MT6370_SHIFT_TE_EN)
#define MT6370_MASK_BYPASS_MODE		BIT(MT6370_SHIFT_BYPASS_MODE)

/* ========== CHG_CTRL3 0x13 ============ */
#define MT6370_SHIFT_AICR		2
#define MT6370_SHIFT_AICR_EN		1
#define MT6370_SHIFT_ILIM_EN		0

#define MT6370_MASK_AICR		0xFC
#define MT6370_MASK_AICR_EN		BIT(MT6370_SHIFT_AICR_EN)
#define MT6370_MASK_ILIM_EN		BIT(MT6370_SHIFT_ILIM_EN)

/* ========== CHG_CTRL4 0x14 ============ */
#define MT6370_SHIFT_BAT_VOREG		1

#define MT6370_MASK_BAT_VOREG		0xFE

/* ========== CHG_CTRL5 0x15 ============ */
#define MT6370_SHIFT_BOOST_VOREG	2

#define MT6370_MASK_BOOST_VOREG		0xFC

/* ========== CHG_CTRL6 0x16 ============ */
#define MT6370_SHIFT_MIVR		1
#define MT6370_SHIFT_MIVR_EN		0

#define MT6370_MASK_MIVR		0xFE
#define MT6370_MASK_MIVR_EN		BIT(MT6370_SHIFT_MIVR_EN)

/* ========== CHG_CTRL7 0x17 ============ */
#define MT6370_SHIFT_ICHG		2

#define MT6370_MASK_ICHG		0xFC

/* ========== CHG_CTRL8 0x18 ============ */
#define MT6370_SHIFT_VPREC		4
#define MT6370_SHIFT_IPREC		0

#define MT6370_MASK_VPREC		0xF0
#define MT6370_MASK_IPREC		0x0F

/* ========== CHG_CTRL9 0x19 ============ */
#define MT6370_SHIFT_IEOC		4

#define MT6370_MASK_IEOC		0xF0

/* ========== CHG_CTRL10 0x1A ============ */
#define MT6370_SHIFT_BOOST_OC		0

#define MT6370_MASK_BOOST_OC		0x07

/* ========== CHG_CTRL11 0x1B ============ */
#define MT6370_SHIFT_VRECHG		0

#define MT6370_MASK_VRECHG		0x03

/* ========== CHG_CTRL12 0x1C ============ */
#define MT6370_SHIFT_TMR_EN		1
#define MT6370_SHIFT_WT_FC		5

#define MT6370_MASK_TMR_EN		BIT(MT6370_SHIFT_TMR_EN)
#define MT6370_MASK_WT_FC		0xE0

/* ========== CHG_CTRL13 0x1D ============ */
#define MT6370_SHIFT_WDT_EN		7

#define MT6370_MASK_WDT_EN		BIT(MT6370_SHIFT_WDT_EN)

/* ========== CHG_CTRL14 0x1E ============ */
#define MT6370_SHIFT_AICL_MEAS		7
#define MT6370_SHIFT_AICL_VTH		0

#define MT6370_MASK_AICL_MEAS		BIT(MT6370_SHIFT_AICL_MEAS)
#define MT6370_MASK_AICL_VTH		0x07

/* ========== CHG_CTRL16 0x20 ============ */
#define MT6370_SHIFT_JEITA_EN		4

#define MT6370_MASK_JEITA_EN		BIT(MT6370_SHIFT_JEITA_EN)

/* ========== CHG_ADC 0x21 ============ */
#define MT6370_SHIFT_ADC_IN_SEL		4
#define MT6370_SHIFT_ADC_START		0

#define MT6370_MASK_ADC_IN_SEL		0xF0
#define MT6370_MASK_ADC_START		BIT(MT6370_SHIFT_ADC_START)

/* ========== CHG_DEVICETYPE 0x22 ============ */
#define MT6370_SHIFT_USBCHGEN		7
#define MT6370_SHIFT_DCPSTD		2
#define MT6370_SHIFT_CDP		1
#define MT6370_SHIFT_SDP		0

#define MT6370_MASK_USBCHGEN		BIT(MT6370_SHIFT_USBCHGEN)
#define MT6370_MASK_DCPSTD		BIT(MT6370_SHIFT_DCPSTD)
#define MT6370_MASK_CDP			BIT(MT6370_SHIFT_CDP)
#define MT6370_MASK_SDP			BIT(MT6370_SHIFT_SDP)

/* ========== QCCTRL2 0x24 ============ */
#define MT6370_SHIFT_EN_DCP		1

#define MT6370_MASK_EN_DCP		BIT(MT6370_SHIFT_EN_DCP)

/* ========== CHG_PUMP 0x2A ============ */
#define MT6370_SHIFT_VG_LVL_SEL		1
#define MT6370_SHIFT_VG_EN		0

#define MT6370_MASK_VG_LVL_SEL		BIT(MT6370_SHIFT_VG_LVL_SEL)
#define MT6370_MASK_VG_EN		BIT(MT6370_SHIFT_VG_EN)

/* ========== CHG_CTRL17 0x2B ============ */
#define MT6370_SHIFT_PUMPX_EN		7
#define MT6370_SHIFT_PUMPX_20_10	6
#define MT6370_SHIFT_PUMPX_UP_DN	5
#define MT6370_SHIFT_PUMPX_DEC		0

#define MT6370_MASK_PUMPX_EN		BIT(MT6370_SHIFT_PUMPX_EN)
#define MT6370_MASK_PUMPX_20_10		BIT(MT6370_SHIFT_PUMPX_20_10)
#define MT6370_MASK_PUMPX_UP_DN		BIT(MT6370_SHIFT_PUMPX_UP_DN)
#define MT6370_MASK_PUMPX_DEC		0x1F

/* ========== CHG_CTRL18 0x2C ============ */
#define MT6370_SHIFT_IRCMP_RES		3
#define MT6370_SHIFT_IRCMP_VCLAMP	0

#define MT6370_MASK_IRCMP_RES		0x38
#define MT6370_MASK_IRCMP_VCLAMP	0x07

/* ========== CHG_DIRCHG1 0x2D ============ */
#define MT6370_SHIFT_DC_VBATOV_EN	6
#define MT6370_SHIFT_DC_VBATOV_LVL	4
#define MT6370_SHIFT_DC_IBUSOC_EN	3
#define MT6370_SHIFT_DC_IBUSOC_LVL	0

#define MT6370_MASK_DC_VBATOV_EN	BIT(MT6370_SHIFT_DC_VBATOV_EN)
#define MT6370_MASK_DC_VBATOV_LVL	0x30
#define MT6370_MASK_DC_IBUSOC_EN	BIT(MT6370_SHIFT_DC_IBUSOC_EN)
#define MT6370_MASK_DC_IBUSOC_LVL	0x07

/* ========== CHG_DIRCHG1 0x2E ============ */
#define MT6370_SHIFT_DC_WDT		4

#define MT6370_MASK_DC_WDT		0x70

/* ========== CHG_DIRCHG2 0x2F ============ */
#define MT6370_SHIFT_DC_VBUSOV_EN	7
#define MT6370_SHIFT_DC_VBUSOV_LVL	2

#define MT6370_MASK_DC_VBUSOV_EN	BIT(MT6370_SHIFT_DC_VBUSOV_EN)
#define MT6370_MASK_DC_VBUSOV_LVL	0x7C

/* ========== CHG_HIDDEN_CTRL9 0x38 ============ */
#define MT6370_SHIFT_EN_PSK		7

#define MT6370_MASK_EN_PSK		BIT(MT6370_SHIFT_EN_PSK)

/* ========== CHG_STAT 0x4A ============ */
#define MT6370_SHIFT_ADC_STAT		0
#define MT6370_SHIFT_CHG_STAT		6

#define MT6370_MASK_ADC_STAT		BIT(MT6370_SHIFT_ADC_STAT)
#define MT6370_MASK_CHG_STAT		0xC0

/* ========== CHG_IRQ5 0xC4 ============ */
#define MT6370_SHIFT_CHG_IEOCI		7
#define MT6370_SHIFT_CHG_TERMI		6
#define MT6370_SHIFT_CHG_RECHGI		5
#define MT6370_SHIFT_CHG_SSFINISHI	4
#define MT6370_SHIFT_CHG_WDTMRI		3
#define MT6370_SHIFT_CHGDET_DONEI	2
#define MT6370_SHIFT_CHG_ICHGMEASI	1
#define MT6370_SHIFT_CHG_AICLMEASI	0

#define MT6370_MASK_CHG_IEOCI		BIT(MT6370_SHIFT_CHG_IEOCI)
#define MT6370_MASK_CHG_TERMI		BIT(MT6370_SHIFT_CHG_TERMI)
#define MT6370_MASK_CHG_RECHGI		BIT(MT6370_SHIFT_CHG_RECHGI)
#define MT6370_MASK_CHG_SSFINISHI	BIT(MT6370_SHIFT_CHG_SSFINISHI)
#define MT6370_MASK_CHG_WDTMRI		BIT(MT6370_SHIFT_CHG_WDTMRI)
#define MT6370_MASK_CHGDET_DONEI	BIT(MT6370_SHIFT_CHGDET_DONEI)
#define MT6370_MASK_CHG_ICHGMEASI	BIT(MT6370_SHIFT_CHG_ICHGMEASI)
#define MT6370_MASK_CHG_AICLMEASI	BIT(MT6370_SHIFT_CHG_AICLMEASI)

/* ========== CHG_IRQ6 0xC5 ============ */
#define MT6370_SHIFT_BST_OLPI		7
#define MT6370_SHIFT_BST_MIDOVI		6
#define MT6370_SHIFT_BST_BATUVI		5
#define MT6370_SHIFT_PUMPX_DONEI	1
#define MT6370_SHIFT_ADC_DONEI		0

#define MT6370_MASK_BST_OLPI		BIT(MT6370_SHIFT_BST_OLPI)
#define MT6370_MASK_BST_MIDOVI		BIT(MT6370_SHIFT_BST_MIDOVI)
#define MT6370_MASK_BST_BATUVI		BIT(MT6370_SHIFT_BST_BATUVI)
#define MT6370_MASK_PUMPX_DONEI		BIT(MT6370_SHIFT_PUMPX_DONEI)
#define MT6370_MASK_ADC_DONEI		BIT(MT6370_SHIFT_ADC_DONEI)

/* ========== DPDM_IRQ 0xC6 ============ */
#define MT6370_SHIFT_DCDTI		7
#define MT6370_SHIFT_CHGDETI		6
#define MT6370_SHIFT_HVDCPDET		5
#define MT6370_SHIFT_DETACHI		1
#define MT6370_SHIFT_ATTACHI		0

#define MT6370_MASK_DCDTI		BIT(MT6370_SHIFT_DCDTI)
#define MT6370_MASK_CHGDETI		BIT(MT6370_SHIFT_CHGDETI)
#define MT6370_MASK_HVDCPDET		BIT(MT6370_SHIFT_HVDCPDET)
#define MT6370_MASK_DETACHI		BIT(MT6370_SHIFT_DETACHI)
#define MT6370_MASK_ATTACHI		BIT(MT6370_SHIFT_ATTACHI)

/* ========== CHG_STAT1 0xD0 ============ */
#define MT6370_SHIFT_PWR_RDY_STAT	7
#define MT6370_SHIFT_MIVR_STAT		6
#define MT6370_SHIFT_AICR_STAT		5
#define MT6370_SHIFT_TREG_STAT		4
#define MT6370_SHIFT_DIRCHG_ON_STAT	0

#define MT6370_MASK_PWR_RDY_STAT	BIT(MT6370_SHIFT_PWR_RDY_STAT)
#define MT6370_MASK_MIVR_STAT		BIT(MT6370_SHIFT_MIVR_STAT)
#define MT6370_MASK_AICR_STAT		BIT(MT6370_SHIFT_AICR_STAT)
#define MT6370_MASK_TREG_STAT		BIT(MT6370_SHIFT_TREG_STAT)
#define MT6370_MASK_DIRCHG_ON_STAT	BIT(MT6370_SHIFT_DIRCHG_ON_STAT)

/* ========== CHG_STAT2 0xD1 ============ */
#define MT6370_SHIFT_CHG_VBUSOV_STAT	7

#define MT6370_MASK_CHG_VBUSOV_STAT	BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)

/* ========== CHG_STAT4 0xD3 ============ */
#define MT6370_SHIFT_CHG_TMRI_STAT	3

#define MT6370_MASK_CHG_TMRI_STAT	BIT(MT6370_SHIFT_CHG_TMRI_STAT)

/* ========== CHG_STAT5 0xD4 ============ */
#define MT6370_SHIFT_CHG_IEOCI_STAT	7

#define MT6370_MASK_CHG_IEOCI_STAT	BIT(MT6370_SHIFT_CHG_IEOCI_STAT)

/* ========== DPDM_STAT 0xD6 ============ */
#define MT6370_SHIFT_DCDTI_STAT		7

#define MT6370_MASK_DCDTI_STAT		BIT(MT6370_SHIFT_DCDTI_STAT)

/* ========== OVPCTRL_STAT 0xD8 ============ */
#define MT6370_SHIFT_OVPCTRL_UVP_D_STAT	4

#define MT6370_MASK_OVPCTRL_UVP_D_STAT	BIT(MT6370_SHIFT_OVPCTRL_UVP_D_STAT)

/* ========== CHG_MASK1 0xE0 ============ */
#define MT6370_SHIFT_CHG_MIVRM		6
#define MT6370_MASK_CHG_MIVRM		BIT(MT6370_SHIFT_CHG_MIVRM)

/* ========== CHG_MASK5 0xE4 ============ */
#define MT6370_SHIFT_CHG_IEOCM		7
#define MT6370_SHIFT_CHG_TERMM		6
#define MT6370_SHIFT_CHG_RECHGM		5
#define MT6370_SHIFT_CHG_SSFINISHM	4
#define MT6370_SHIFT_CHG_WDTMRM		3
#define MT6370_SHIFT_CHGDET_DONEM	2
#define MT6370_SHIFT_CHG_ICHGMEASM	1
#define MT6370_SHIFT_CHG_AICLMEASM	0

#define MT6370_MASK_CHG_IEOCM		BIT(MT6370_SHIFT_CHG_IEOCM)
#define MT6370_MASK_CHG_TERMM		BIT(MT6370_SHIFT_CHG_TERMM)
#define MT6370_MASK_CHG_RECHGM		BIT(MT6370_SHIFT_CHG_RECHGM)
#define MT6370_MASK_CHG_SSFINISHM	BIT(MT6370_SHIFT_CHG_SSFINISHM)
#define MT6370_MASK_CHG_WDTMRM		BIT(MT6370_SHIFT_CHG_WDTMRM)
#define MT6370_MASK_CHGDET_DONEM	BIT(MT6370_SHIFT_CHGDET_DONEM)
#define MT6370_MASK_CHG_ICHGMEASM	BIT(MT6370_SHIFT_CHG_ICHGMEASM)
#define MT6370_MASK_CHG_AICLMEASM	BIT(MT6370_SHIFT_CHG_AICLMEASM)

/* ========== CHG_MASK6 0xE5 ============ */
#define MT6370_SHIFT_BST_OLPM		7
#define MT6370_SHIFT_BST_MIDOVM		6
#define MT6370_SHIFT_BST_BATUVM		5
#define MT6370_SHIFT_PUMPX_DONEM	1
#define MT6370_SHIFT_ADC_DONEM		0

#define MT6370_MASK_BST_OLPM		BIT(MT6370_SHIFT_BST_OLPM)
#define MT6370_MASK_BST_MIDOVM		BIT(MT6370_SHIFT_BST_MIDOVM)
#define MT6370_MASK_BST_BATUVM		BIT(MT6370_SHIFT_BST_BATUVM)
#define MT6370_MASK_PUMPX_DONEM		BIT(MT6370_SHIFT_PUMPX_DONEM)
#define MT6370_MASK_ADC_DONEM		BIT(MT6370_SHIFT_ADC_DONEM)

/* ========== PMU_TM_INF 0xF4 ============ */
#define MT6370_SHIFT_PMU_ID		6

#define MT6370_MASK_PMU_ID		BIT(MT6370_SHIFT_PMU_ID)

/* ========== BANK_REG 0xFF ============ */
#define MT6370_PMU_BANK_REG		0x00
#define MT6370_TM_BANK_REG		0x69

/* ========== TM_INF 0x41 ============ */
#define MT6370_SHIFT_TM_ID		7

#define MT6370_MASK_TM_ID		BIT(MT6370_SHIFT_TM_ID)

#endif /* __MT6370_PMU_CHARGER_H */