mtk-lk/platform/mt6580/upmu_common.c

#include <platform/mt_pmic.h>
#include <printf.h>

void pmic_lock(void)
{
}

void pmic_unlock(void)
{
}

const PMU_FLAG_TABLE_ENTRY pmu_flags_table[]=
{
  {PMIC_RG_VCDT_HV_EN, MT6350_PMIC_RG_VCDT_HV_EN_ADDR, MT6350_PMIC_RG_VCDT_HV_EN_MASK, MT6350_PMIC_RG_VCDT_HV_EN_SHIFT},
  {PMIC_RGS_CHR_LDO_DET, MT6350_PMIC_RGS_CHR_LDO_DET_ADDR, MT6350_PMIC_RGS_CHR_LDO_DET_MASK, MT6350_PMIC_RGS_CHR_LDO_DET_SHIFT},
  {PMIC_RG_PCHR_AUTOMODE, MT6350_PMIC_RG_PCHR_AUTOMODE_ADDR, MT6350_PMIC_RG_PCHR_AUTOMODE_MASK, MT6350_PMIC_RG_PCHR_AUTOMODE_SHIFT},
  {PMIC_RG_CSDAC_EN, MT6350_PMIC_RG_CSDAC_EN_ADDR, MT6350_PMIC_RG_CSDAC_EN_MASK, MT6350_PMIC_RG_CSDAC_EN_SHIFT},
  {PMIC_RG_CHR_EN, MT6350_PMIC_RG_CHR_EN_ADDR, MT6350_PMIC_RG_CHR_EN_MASK, MT6350_PMIC_RG_CHR_EN_SHIFT},
  {PMIC_RGS_CHRDET, MT6350_PMIC_RGS_CHRDET_ADDR, MT6350_PMIC_RGS_CHRDET_MASK, MT6350_PMIC_RGS_CHRDET_SHIFT},
  {PMIC_RGS_VCDT_LV_DET, MT6350_PMIC_RGS_VCDT_LV_DET_ADDR, MT6350_PMIC_RGS_VCDT_LV_DET_MASK, MT6350_PMIC_RGS_VCDT_LV_DET_SHIFT},
  {PMIC_RGS_VCDT_HV_DET, MT6350_PMIC_RGS_VCDT_HV_DET_ADDR, MT6350_PMIC_RGS_VCDT_HV_DET_MASK, MT6350_PMIC_RGS_VCDT_HV_DET_SHIFT},
  {PMIC_RG_VCDT_LV_VTH, MT6350_PMIC_RG_VCDT_LV_VTH_ADDR, MT6350_PMIC_RG_VCDT_LV_VTH_MASK, MT6350_PMIC_RG_VCDT_LV_VTH_SHIFT},
  {PMIC_RG_VCDT_HV_VTH, MT6350_PMIC_RG_VCDT_HV_VTH_ADDR, MT6350_PMIC_RG_VCDT_HV_VTH_MASK, MT6350_PMIC_RG_VCDT_HV_VTH_SHIFT},
  {PMIC_RG_VBAT_CV_EN, MT6350_PMIC_RG_VBAT_CV_EN_ADDR, MT6350_PMIC_RG_VBAT_CV_EN_MASK, MT6350_PMIC_RG_VBAT_CV_EN_SHIFT},
  {PMIC_RG_VBAT_CC_EN, MT6350_PMIC_RG_VBAT_CC_EN_ADDR, MT6350_PMIC_RG_VBAT_CC_EN_MASK, MT6350_PMIC_RG_VBAT_CC_EN_SHIFT},
  {PMIC_RG_CS_EN, MT6350_PMIC_RG_CS_EN_ADDR, MT6350_PMIC_RG_CS_EN_MASK, MT6350_PMIC_RG_CS_EN_SHIFT},
  {PMIC_RGS_CS_DET, MT6350_PMIC_RGS_CS_DET_ADDR, MT6350_PMIC_RGS_CS_DET_MASK, MT6350_PMIC_RGS_CS_DET_SHIFT},
  {PMIC_RGS_VBAT_CV_DET, MT6350_PMIC_RGS_VBAT_CV_DET_ADDR, MT6350_PMIC_RGS_VBAT_CV_DET_MASK, MT6350_PMIC_RGS_VBAT_CV_DET_SHIFT},
  {PMIC_RGS_VBAT_CC_DET, MT6350_PMIC_RGS_VBAT_CC_DET_ADDR, MT6350_PMIC_RGS_VBAT_CC_DET_MASK, MT6350_PMIC_RGS_VBAT_CC_DET_SHIFT},
  {PMIC_RG_VBAT_CV_VTH, MT6350_PMIC_RG_VBAT_CV_VTH_ADDR, MT6350_PMIC_RG_VBAT_CV_VTH_MASK, MT6350_PMIC_RG_VBAT_CV_VTH_SHIFT},
  {PMIC_RG_VBAT_CC_VTH, MT6350_PMIC_RG_VBAT_CC_VTH_ADDR, MT6350_PMIC_RG_VBAT_CC_VTH_MASK, MT6350_PMIC_RG_VBAT_CC_VTH_SHIFT},
  {PMIC_RG_CS_VTH, MT6350_PMIC_RG_CS_VTH_ADDR, MT6350_PMIC_RG_CS_VTH_MASK, MT6350_PMIC_RG_CS_VTH_SHIFT},
  {PMIC_RG_PCHR_TOHTC, MT6350_PMIC_RG_PCHR_TOHTC_ADDR, MT6350_PMIC_RG_PCHR_TOHTC_MASK, MT6350_PMIC_RG_PCHR_TOHTC_SHIFT},
  {PMIC_RG_PCHR_TOLTC, MT6350_PMIC_RG_PCHR_TOLTC_ADDR, MT6350_PMIC_RG_PCHR_TOLTC_MASK, MT6350_PMIC_RG_PCHR_TOLTC_SHIFT},
  {PMIC_RG_VBAT_OV_EN, MT6350_PMIC_RG_VBAT_OV_EN_ADDR, MT6350_PMIC_RG_VBAT_OV_EN_MASK, MT6350_PMIC_RG_VBAT_OV_EN_SHIFT},
  {PMIC_RG_VBAT_OV_VTH, MT6350_PMIC_RG_VBAT_OV_VTH_ADDR, MT6350_PMIC_RG_VBAT_OV_VTH_MASK, MT6350_PMIC_RG_VBAT_OV_VTH_SHIFT},
  {PMIC_RG_VBAT_OV_DEG, MT6350_PMIC_RG_VBAT_OV_DEG_ADDR, MT6350_PMIC_RG_VBAT_OV_DEG_MASK, MT6350_PMIC_RG_VBAT_OV_DEG_SHIFT},
  {PMIC_RGS_VBAT_OV_DET, MT6350_PMIC_RGS_VBAT_OV_DET_ADDR, MT6350_PMIC_RGS_VBAT_OV_DET_MASK, MT6350_PMIC_RGS_VBAT_OV_DET_SHIFT},
  {PMIC_RG_BATON_EN, MT6350_PMIC_RG_BATON_EN_ADDR, MT6350_PMIC_RG_BATON_EN_MASK, MT6350_PMIC_RG_BATON_EN_SHIFT},
  {PMIC_RG_BATON_HT_EN, MT6350_PMIC_RG_BATON_HT_EN_ADDR, MT6350_PMIC_RG_BATON_HT_EN_MASK, MT6350_PMIC_RG_BATON_HT_EN_SHIFT},
  {PMIC_BATON_TDET_EN, MT6350_PMIC_BATON_TDET_EN_ADDR, MT6350_PMIC_BATON_TDET_EN_MASK, MT6350_PMIC_BATON_TDET_EN_SHIFT},
  {PMIC_RG_BATON_HT_TRIM, MT6350_PMIC_RG_BATON_HT_TRIM_ADDR, MT6350_PMIC_RG_BATON_HT_TRIM_MASK, MT6350_PMIC_RG_BATON_HT_TRIM_SHIFT},
  {PMIC_RG_BATON_HT_TRIM_SET, MT6350_PMIC_RG_BATON_HT_TRIM_SET_ADDR, MT6350_PMIC_RG_BATON_HT_TRIM_SET_MASK, MT6350_PMIC_RG_BATON_HT_TRIM_SET_SHIFT},
  {PMIC_RGS_BATON_UNDET, MT6350_PMIC_RGS_BATON_UNDET_ADDR, MT6350_PMIC_RGS_BATON_UNDET_MASK, MT6350_PMIC_RGS_BATON_UNDET_SHIFT},
  {PMIC_RG_CSDAC_DATA, MT6350_PMIC_RG_CSDAC_DATA_ADDR, MT6350_PMIC_RG_CSDAC_DATA_MASK, MT6350_PMIC_RG_CSDAC_DATA_SHIFT},
  {PMIC_RG_FRC_CSVTH_USBDL, MT6350_PMIC_RG_FRC_CSVTH_USBDL_ADDR, MT6350_PMIC_RG_FRC_CSVTH_USBDL_MASK, MT6350_PMIC_RG_FRC_CSVTH_USBDL_SHIFT},
  {PMIC_RGS_PCHR_FLAG_OUT, MT6350_PMIC_RGS_PCHR_FLAG_OUT_ADDR, MT6350_PMIC_RGS_PCHR_FLAG_OUT_MASK, MT6350_PMIC_RGS_PCHR_FLAG_OUT_SHIFT},
  {PMIC_RG_PCHR_FLAG_EN, MT6350_PMIC_RG_PCHR_FLAG_EN_ADDR, MT6350_PMIC_RG_PCHR_FLAG_EN_MASK, MT6350_PMIC_RG_PCHR_FLAG_EN_SHIFT},
  {PMIC_RG_OTG_BVALID_EN, MT6350_PMIC_RG_OTG_BVALID_EN_ADDR, MT6350_PMIC_RG_OTG_BVALID_EN_MASK, MT6350_PMIC_RG_OTG_BVALID_EN_SHIFT},
  {PMIC_RGS_OTG_BVALID_DET, MT6350_PMIC_RGS_OTG_BVALID_DET_ADDR, MT6350_PMIC_RGS_OTG_BVALID_DET_MASK, MT6350_PMIC_RGS_OTG_BVALID_DET_SHIFT},
  {PMIC_RG_PCHR_FLAG_SEL, MT6350_PMIC_RG_PCHR_FLAG_SEL_ADDR, MT6350_PMIC_RG_PCHR_FLAG_SEL_MASK, MT6350_PMIC_RG_PCHR_FLAG_SEL_SHIFT},
  {PMIC_RG_PCHR_TESTMODE, MT6350_PMIC_RG_PCHR_TESTMODE_ADDR, MT6350_PMIC_RG_PCHR_TESTMODE_MASK, MT6350_PMIC_RG_PCHR_TESTMODE_SHIFT},
  {PMIC_RG_CSDAC_TESTMODE, MT6350_PMIC_RG_CSDAC_TESTMODE_ADDR, MT6350_PMIC_RG_CSDAC_TESTMODE_MASK, MT6350_PMIC_RG_CSDAC_TESTMODE_SHIFT},
  {PMIC_RG_PCHR_RST, MT6350_PMIC_RG_PCHR_RST_ADDR, MT6350_PMIC_RG_PCHR_RST_MASK, MT6350_PMIC_RG_PCHR_RST_SHIFT},
  {PMIC_RG_PCHR_FT_CTRL, MT6350_PMIC_RG_PCHR_FT_CTRL_ADDR, MT6350_PMIC_RG_PCHR_FT_CTRL_MASK, MT6350_PMIC_RG_PCHR_FT_CTRL_SHIFT},
  {PMIC_RG_CHRWDT_TD, MT6350_PMIC_RG_CHRWDT_TD_ADDR, MT6350_PMIC_RG_CHRWDT_TD_MASK, MT6350_PMIC_RG_CHRWDT_TD_SHIFT},
  {PMIC_RG_CHRWDT_EN, MT6350_PMIC_RG_CHRWDT_EN_ADDR, MT6350_PMIC_RG_CHRWDT_EN_MASK, MT6350_PMIC_RG_CHRWDT_EN_SHIFT},
  {PMIC_RG_CHRWDT_WR, MT6350_PMIC_RG_CHRWDT_WR_ADDR, MT6350_PMIC_RG_CHRWDT_WR_MASK, MT6350_PMIC_RG_CHRWDT_WR_SHIFT},
  {PMIC_RG_PCHR_RV, MT6350_PMIC_RG_PCHR_RV_ADDR, MT6350_PMIC_RG_PCHR_RV_MASK, MT6350_PMIC_RG_PCHR_RV_SHIFT},
  {PMIC_RG_CHRWDT_INT_EN, MT6350_PMIC_RG_CHRWDT_INT_EN_ADDR, MT6350_PMIC_RG_CHRWDT_INT_EN_MASK, MT6350_PMIC_RG_CHRWDT_INT_EN_SHIFT},
  {PMIC_RG_CHRWDT_FLAG_WR, MT6350_PMIC_RG_CHRWDT_FLAG_WR_ADDR, MT6350_PMIC_RG_CHRWDT_FLAG_WR_MASK, MT6350_PMIC_RG_CHRWDT_FLAG_WR_SHIFT},
  {PMIC_RGS_CHRWDT_OUT, MT6350_PMIC_RGS_CHRWDT_OUT_ADDR, MT6350_PMIC_RGS_CHRWDT_OUT_MASK, MT6350_PMIC_RGS_CHRWDT_OUT_SHIFT},
  {PMIC_RG_UVLO_VTHL, MT6350_PMIC_RG_UVLO_VTHL_ADDR, MT6350_PMIC_RG_UVLO_VTHL_MASK, MT6350_PMIC_RG_UVLO_VTHL_SHIFT},
  {PMIC_RG_USBDL_RST, MT6350_PMIC_RG_USBDL_RST_ADDR, MT6350_PMIC_RG_USBDL_RST_MASK, MT6350_PMIC_RG_USBDL_RST_SHIFT},
  {PMIC_RG_USBDL_SET, MT6350_PMIC_RG_USBDL_SET_ADDR, MT6350_PMIC_RG_USBDL_SET_MASK, MT6350_PMIC_RG_USBDL_SET_SHIFT},
  {PMIC_ADCIN_VSEN_MUX_EN, MT6350_PMIC_ADCIN_VSEN_MUX_EN_ADDR, MT6350_PMIC_ADCIN_VSEN_MUX_EN_MASK, MT6350_PMIC_ADCIN_VSEN_MUX_EN_SHIFT},
  {PMIC_RG_ADCIN_VSEN_EXT_BATON_EN, MT6350_PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_ADDR, MT6350_PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK, MT6350_PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT},
  {PMIC_ADCIN_VBAT_EN, MT6350_PMIC_ADCIN_VBAT_EN_ADDR, MT6350_PMIC_ADCIN_VBAT_EN_MASK, MT6350_PMIC_ADCIN_VBAT_EN_SHIFT},
  {PMIC_ADCIN_VSEN_EN, MT6350_PMIC_ADCIN_VSEN_EN_ADDR, MT6350_PMIC_ADCIN_VSEN_EN_MASK, MT6350_PMIC_ADCIN_VSEN_EN_SHIFT},
  {PMIC_ADCIN_VCHR_EN, MT6350_PMIC_ADCIN_VCHR_EN_ADDR, MT6350_PMIC_ADCIN_VCHR_EN_MASK, MT6350_PMIC_ADCIN_VCHR_EN_SHIFT},
  {PMIC_RG_BGR_RSEL, MT6350_PMIC_RG_BGR_RSEL_ADDR, MT6350_PMIC_RG_BGR_RSEL_MASK, MT6350_PMIC_RG_BGR_RSEL_SHIFT},
  {PMIC_RG_BGR_UNCHOP_PH, MT6350_PMIC_RG_BGR_UNCHOP_PH_ADDR, MT6350_PMIC_RG_BGR_UNCHOP_PH_MASK, MT6350_PMIC_RG_BGR_UNCHOP_PH_SHIFT},
  {PMIC_RG_BGR_UNCHOP, MT6350_PMIC_RG_BGR_UNCHOP_ADDR, MT6350_PMIC_RG_BGR_UNCHOP_MASK, MT6350_PMIC_RG_BGR_UNCHOP_SHIFT},
  {PMIC_RG_BC11_BB_CTRL, MT6350_PMIC_RG_BC11_BB_CTRL_ADDR, MT6350_PMIC_RG_BC11_BB_CTRL_MASK, MT6350_PMIC_RG_BC11_BB_CTRL_SHIFT},
  {PMIC_RG_BC11_RST, MT6350_PMIC_RG_BC11_RST_ADDR, MT6350_PMIC_RG_BC11_RST_MASK, MT6350_PMIC_RG_BC11_RST_SHIFT},
  {PMIC_RG_BC11_VSRC_EN, MT6350_PMIC_RG_BC11_VSRC_EN_ADDR, MT6350_PMIC_RG_BC11_VSRC_EN_MASK, MT6350_PMIC_RG_BC11_VSRC_EN_SHIFT},
  {PMIC_RGS_BC11_CMP_OUT, MT6350_PMIC_RGS_BC11_CMP_OUT_ADDR, MT6350_PMIC_RGS_BC11_CMP_OUT_MASK, MT6350_PMIC_RGS_BC11_CMP_OUT_SHIFT},
  {PMIC_RG_BC11_VREF_VTH, MT6350_PMIC_RG_BC11_VREF_VTH_ADDR, MT6350_PMIC_RG_BC11_VREF_VTH_MASK, MT6350_PMIC_RG_BC11_VREF_VTH_SHIFT},
  {PMIC_RG_BC11_CMP_EN, MT6350_PMIC_RG_BC11_CMP_EN_ADDR, MT6350_PMIC_RG_BC11_CMP_EN_MASK, MT6350_PMIC_RG_BC11_CMP_EN_SHIFT},
  {PMIC_RG_BC11_IPD_EN, MT6350_PMIC_RG_BC11_IPD_EN_ADDR, MT6350_PMIC_RG_BC11_IPD_EN_MASK, MT6350_PMIC_RG_BC11_IPD_EN_SHIFT},
  {PMIC_RG_BC11_IPU_EN, MT6350_PMIC_RG_BC11_IPU_EN_ADDR, MT6350_PMIC_RG_BC11_IPU_EN_MASK, MT6350_PMIC_RG_BC11_IPU_EN_SHIFT},
  {PMIC_RG_BC11_BIAS_EN, MT6350_PMIC_RG_BC11_BIAS_EN_ADDR, MT6350_PMIC_RG_BC11_BIAS_EN_MASK, MT6350_PMIC_RG_BC11_BIAS_EN_SHIFT},
  {PMIC_RG_CSDAC_STP_INC, MT6350_PMIC_RG_CSDAC_STP_INC_ADDR, MT6350_PMIC_RG_CSDAC_STP_INC_MASK, MT6350_PMIC_RG_CSDAC_STP_INC_SHIFT},
  {PMIC_RG_CSDAC_STP_DEC, MT6350_PMIC_RG_CSDAC_STP_DEC_ADDR, MT6350_PMIC_RG_CSDAC_STP_DEC_MASK, MT6350_PMIC_RG_CSDAC_STP_DEC_SHIFT},
  {PMIC_RG_CSDAC_DLY, MT6350_PMIC_RG_CSDAC_DLY_ADDR, MT6350_PMIC_RG_CSDAC_DLY_MASK, MT6350_PMIC_RG_CSDAC_DLY_SHIFT},
  {PMIC_RG_CSDAC_STP, MT6350_PMIC_RG_CSDAC_STP_ADDR, MT6350_PMIC_RG_CSDAC_STP_MASK, MT6350_PMIC_RG_CSDAC_STP_SHIFT},
  {PMIC_RG_LOW_ICH_DB, MT6350_PMIC_RG_LOW_ICH_DB_ADDR, MT6350_PMIC_RG_LOW_ICH_DB_MASK, MT6350_PMIC_RG_LOW_ICH_DB_SHIFT},
  {PMIC_RG_CHRIND_ON, MT6350_PMIC_RG_CHRIND_ON_ADDR, MT6350_PMIC_RG_CHRIND_ON_MASK, MT6350_PMIC_RG_CHRIND_ON_SHIFT},
  {PMIC_RG_CHRIND_DIMMING, MT6350_PMIC_RG_CHRIND_DIMMING_ADDR, MT6350_PMIC_RG_CHRIND_DIMMING_MASK, MT6350_PMIC_RG_CHRIND_DIMMING_SHIFT},
  {PMIC_RG_CV_MODE, MT6350_PMIC_RG_CV_MODE_ADDR, MT6350_PMIC_RG_CV_MODE_MASK, MT6350_PMIC_RG_CV_MODE_SHIFT},
  {PMIC_RG_VCDT_MODE, MT6350_PMIC_RG_VCDT_MODE_ADDR, MT6350_PMIC_RG_VCDT_MODE_MASK, MT6350_PMIC_RG_VCDT_MODE_SHIFT},
  {PMIC_RG_CSDAC_MODE, MT6350_PMIC_RG_CSDAC_MODE_ADDR, MT6350_PMIC_RG_CSDAC_MODE_MASK, MT6350_PMIC_RG_CSDAC_MODE_SHIFT},
  {PMIC_RG_TRACKING_EN, MT6350_PMIC_RG_TRACKING_EN_ADDR, MT6350_PMIC_RG_TRACKING_EN_MASK, MT6350_PMIC_RG_TRACKING_EN_SHIFT},
  {PMIC_RG_HWCV_EN, MT6350_PMIC_RG_HWCV_EN_ADDR, MT6350_PMIC_RG_HWCV_EN_MASK, MT6350_PMIC_RG_HWCV_EN_SHIFT},
  {PMIC_RG_ULC_DET_EN, MT6350_PMIC_RG_ULC_DET_EN_ADDR, MT6350_PMIC_RG_ULC_DET_EN_MASK, MT6350_PMIC_RG_ULC_DET_EN_SHIFT},
  {PMIC_RG_BGR_TRIM_EN, MT6350_PMIC_RG_BGR_TRIM_EN_ADDR, MT6350_PMIC_RG_BGR_TRIM_EN_MASK, MT6350_PMIC_RG_BGR_TRIM_EN_SHIFT},
  {PMIC_RG_ICHRG_TRIM, MT6350_PMIC_RG_ICHRG_TRIM_ADDR, MT6350_PMIC_RG_ICHRG_TRIM_MASK, MT6350_PMIC_RG_ICHRG_TRIM_SHIFT},
  {PMIC_RG_BGR_TRIM, MT6350_PMIC_RG_BGR_TRIM_ADDR, MT6350_PMIC_RG_BGR_TRIM_MASK, MT6350_PMIC_RG_BGR_TRIM_SHIFT},
  {PMIC_RG_OVP_TRIM, MT6350_PMIC_RG_OVP_TRIM_ADDR, MT6350_PMIC_RG_OVP_TRIM_MASK, MT6350_PMIC_RG_OVP_TRIM_SHIFT},
  {PMIC_RG_CHR_OSC_TRIM, MT6350_PMIC_RG_CHR_OSC_TRIM_ADDR, MT6350_PMIC_RG_CHR_OSC_TRIM_MASK, MT6350_PMIC_RG_CHR_OSC_TRIM_SHIFT},
  {PMIC_QI_BGR_EXT_BUF_EN, MT6350_PMIC_QI_BGR_EXT_BUF_EN_ADDR, MT6350_PMIC_QI_BGR_EXT_BUF_EN_MASK, MT6350_PMIC_QI_BGR_EXT_BUF_EN_SHIFT},
  {PMIC_RG_BGR_TEST_EN, MT6350_PMIC_RG_BGR_TEST_EN_ADDR, MT6350_PMIC_RG_BGR_TEST_EN_MASK, MT6350_PMIC_RG_BGR_TEST_EN_SHIFT},
  {PMIC_RG_BGR_TEST_RSTB, MT6350_PMIC_RG_BGR_TEST_RSTB_ADDR, MT6350_PMIC_RG_BGR_TEST_RSTB_MASK, MT6350_PMIC_RG_BGR_TEST_RSTB_SHIFT},
  {PMIC_RG_DAC_USBDL_MAX, MT6350_PMIC_RG_DAC_USBDL_MAX_ADDR, MT6350_PMIC_RG_DAC_USBDL_MAX_MASK, MT6350_PMIC_RG_DAC_USBDL_MAX_SHIFT},
  {PMIC_RG_PCHR_RSV, MT6350_PMIC_RG_PCHR_RSV_ADDR, MT6350_PMIC_RG_PCHR_RSV_MASK, MT6350_PMIC_RG_PCHR_RSV_SHIFT},
  {PMIC_THR_DET_DIS, MT6350_PMIC_THR_DET_DIS_ADDR, MT6350_PMIC_THR_DET_DIS_MASK, MT6350_PMIC_THR_DET_DIS_SHIFT},
  {PMIC_RG_THR_TMODE, MT6350_PMIC_RG_THR_TMODE_ADDR, MT6350_PMIC_RG_THR_TMODE_MASK, MT6350_PMIC_RG_THR_TMODE_SHIFT},
  {PMIC_RG_THR_TEMP_SEL, MT6350_PMIC_RG_THR_TEMP_SEL_ADDR, MT6350_PMIC_RG_THR_TEMP_SEL_MASK, MT6350_PMIC_RG_THR_TEMP_SEL_SHIFT},
  {PMIC_RG_STRUP_THR_SEL, MT6350_PMIC_RG_STRUP_THR_SEL_ADDR, MT6350_PMIC_RG_STRUP_THR_SEL_MASK, MT6350_PMIC_RG_STRUP_THR_SEL_SHIFT},
  {PMIC_THR_HWPDN_EN, MT6350_PMIC_THR_HWPDN_EN_ADDR, MT6350_PMIC_THR_HWPDN_EN_MASK, MT6350_PMIC_THR_HWPDN_EN_SHIFT},
  {PMIC_RG_THRDET_SEL, MT6350_PMIC_RG_THRDET_SEL_ADDR, MT6350_PMIC_RG_THRDET_SEL_MASK, MT6350_PMIC_RG_THRDET_SEL_SHIFT},
  {PMIC_RG_STRUP_IREF_TRIM, MT6350_PMIC_RG_STRUP_IREF_TRIM_ADDR, MT6350_PMIC_RG_STRUP_IREF_TRIM_MASK, MT6350_PMIC_RG_STRUP_IREF_TRIM_SHIFT},
  {PMIC_RG_USBDL_EN, MT6350_PMIC_RG_USBDL_EN_ADDR, MT6350_PMIC_RG_USBDL_EN_MASK, MT6350_PMIC_RG_USBDL_EN_SHIFT},
  {PMIC_RG_FCHR_KEYDET_EN, MT6350_PMIC_RG_FCHR_KEYDET_EN_ADDR, MT6350_PMIC_RG_FCHR_KEYDET_EN_MASK, MT6350_PMIC_RG_FCHR_KEYDET_EN_SHIFT},
  {PMIC_RG_FCHR_PU_EN, MT6350_PMIC_RG_FCHR_PU_EN_ADDR, MT6350_PMIC_RG_FCHR_PU_EN_MASK, MT6350_PMIC_RG_FCHR_PU_EN_SHIFT},
  {PMIC_RG_EN_DRVSEL, MT6350_PMIC_RG_EN_DRVSEL_ADDR, MT6350_PMIC_RG_EN_DRVSEL_MASK, MT6350_PMIC_RG_EN_DRVSEL_SHIFT},
  {PMIC_RG_RST_DRVSEL, MT6350_PMIC_RG_RST_DRVSEL_ADDR, MT6350_PMIC_RG_RST_DRVSEL_MASK, MT6350_PMIC_RG_RST_DRVSEL_SHIFT},
  {PMIC_RG_VREF_BG, MT6350_PMIC_RG_VREF_BG_ADDR, MT6350_PMIC_RG_VREF_BG_MASK, MT6350_PMIC_RG_VREF_BG_SHIFT},
  {PMIC_RG_PMU_RSV, MT6350_PMIC_RG_PMU_RSV_ADDR, MT6350_PMIC_RG_PMU_RSV_MASK, MT6350_PMIC_RG_PMU_RSV_SHIFT},
  {PMIC_THR_TEST, MT6350_PMIC_THR_TEST_ADDR, MT6350_PMIC_THR_TEST_MASK, MT6350_PMIC_THR_TEST_SHIFT},
  {PMIC_PMU_THR_DEB, MT6350_PMIC_PMU_THR_DEB_ADDR, MT6350_PMIC_PMU_THR_DEB_MASK, MT6350_PMIC_PMU_THR_DEB_SHIFT},
  {PMIC_PMU_THR_STATUS, MT6350_PMIC_PMU_THR_STATUS_ADDR, MT6350_PMIC_PMU_THR_STATUS_MASK, MT6350_PMIC_PMU_THR_STATUS_SHIFT},
  {PMIC_DDUVLO_DEB_EN, MT6350_PMIC_DDUVLO_DEB_EN_ADDR, MT6350_PMIC_DDUVLO_DEB_EN_MASK, MT6350_PMIC_DDUVLO_DEB_EN_SHIFT},
  {PMIC_PWRBB_DEB_EN, MT6350_PMIC_PWRBB_DEB_EN_ADDR, MT6350_PMIC_PWRBB_DEB_EN_MASK, MT6350_PMIC_PWRBB_DEB_EN_SHIFT},
  {PMIC_STRUP_OSC_EN, MT6350_PMIC_STRUP_OSC_EN_ADDR, MT6350_PMIC_STRUP_OSC_EN_MASK, MT6350_PMIC_STRUP_OSC_EN_SHIFT},
  {PMIC_STRUP_OSC_EN_SEL, MT6350_PMIC_STRUP_OSC_EN_SEL_ADDR, MT6350_PMIC_STRUP_OSC_EN_SEL_MASK, MT6350_PMIC_STRUP_OSC_EN_SEL_SHIFT},
  {PMIC_STRUP_FT_CTRL, MT6350_PMIC_STRUP_FT_CTRL_ADDR, MT6350_PMIC_STRUP_FT_CTRL_MASK, MT6350_PMIC_STRUP_FT_CTRL_SHIFT},
  {PMIC_STRUP_PWRON_FORCE, MT6350_PMIC_STRUP_PWRON_FORCE_ADDR, MT6350_PMIC_STRUP_PWRON_FORCE_MASK, MT6350_PMIC_STRUP_PWRON_FORCE_SHIFT},
  {PMIC_BIAS_GEN_EN_FORCE, MT6350_PMIC_BIAS_GEN_EN_FORCE_ADDR, MT6350_PMIC_BIAS_GEN_EN_FORCE_MASK, MT6350_PMIC_BIAS_GEN_EN_FORCE_SHIFT},
  {PMIC_STRUP_PWRON, MT6350_PMIC_STRUP_PWRON_ADDR, MT6350_PMIC_STRUP_PWRON_MASK, MT6350_PMIC_STRUP_PWRON_SHIFT},
  {PMIC_STRUP_PWRON_SEL, MT6350_PMIC_STRUP_PWRON_SEL_ADDR, MT6350_PMIC_STRUP_PWRON_SEL_MASK, MT6350_PMIC_STRUP_PWRON_SEL_SHIFT},
  {PMIC_BIAS_GEN_EN, MT6350_PMIC_BIAS_GEN_EN_ADDR, MT6350_PMIC_BIAS_GEN_EN_MASK, MT6350_PMIC_BIAS_GEN_EN_SHIFT},
  {PMIC_BIAS_GEN_EN_SEL, MT6350_PMIC_BIAS_GEN_EN_SEL_ADDR, MT6350_PMIC_BIAS_GEN_EN_SEL_MASK, MT6350_PMIC_BIAS_GEN_EN_SEL_SHIFT},
  {PMIC_RTC_XOSC32_ENB_SW, MT6350_PMIC_RTC_XOSC32_ENB_SW_ADDR, MT6350_PMIC_RTC_XOSC32_ENB_SW_MASK, MT6350_PMIC_RTC_XOSC32_ENB_SW_SHIFT},
  {PMIC_RTC_XOSC32_ENB_SEL, MT6350_PMIC_RTC_XOSC32_ENB_SEL_ADDR, MT6350_PMIC_RTC_XOSC32_ENB_SEL_MASK, MT6350_PMIC_RTC_XOSC32_ENB_SEL_SHIFT},
  {PMIC_STRUP_DIG_IO_PG_FORCE, MT6350_PMIC_STRUP_DIG_IO_PG_FORCE_ADDR, MT6350_PMIC_STRUP_DIG_IO_PG_FORCE_MASK, MT6350_PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT},
  {PMIC_VPROC_PG_ENB, MT6350_PMIC_VPROC_PG_ENB_ADDR, MT6350_PMIC_VPROC_PG_ENB_MASK, MT6350_PMIC_VPROC_PG_ENB_SHIFT},
  {PMIC_VSYS_PG_ENB, MT6350_PMIC_VSYS_PG_ENB_ADDR, MT6350_PMIC_VSYS_PG_ENB_MASK, MT6350_PMIC_VSYS_PG_ENB_SHIFT},
  {PMIC_VM_PG_ENB, MT6350_PMIC_VM_PG_ENB_ADDR, MT6350_PMIC_VM_PG_ENB_MASK, MT6350_PMIC_VM_PG_ENB_SHIFT},
  {PMIC_VIO18_PG_ENB, MT6350_PMIC_VIO18_PG_ENB_ADDR, MT6350_PMIC_VIO18_PG_ENB_MASK, MT6350_PMIC_VIO18_PG_ENB_SHIFT},
  {PMIC_VTCXO_PG_ENB, MT6350_PMIC_VTCXO_PG_ENB_ADDR, MT6350_PMIC_VTCXO_PG_ENB_MASK, MT6350_PMIC_VTCXO_PG_ENB_SHIFT},
  {PMIC_VA_PG_ENB, MT6350_PMIC_VA_PG_ENB_ADDR, MT6350_PMIC_VA_PG_ENB_MASK, MT6350_PMIC_VA_PG_ENB_SHIFT},
  {PMIC_VIO28_PG_ENB, MT6350_PMIC_VIO28_PG_ENB_ADDR, MT6350_PMIC_VIO28_PG_ENB_MASK, MT6350_PMIC_VIO28_PG_ENB_SHIFT},
  {PMIC_VGP2_PG_ENB, MT6350_PMIC_VGP2_PG_ENB_ADDR, MT6350_PMIC_VGP2_PG_ENB_MASK, MT6350_PMIC_VGP2_PG_ENB_SHIFT},
  {PMIC_VPROC_PG_H2L_EN, MT6350_PMIC_VPROC_PG_H2L_EN_ADDR, MT6350_PMIC_VPROC_PG_H2L_EN_MASK, MT6350_PMIC_VPROC_PG_H2L_EN_SHIFT},
  {PMIC_VSYS_PG_H2L_EN, MT6350_PMIC_VSYS_PG_H2L_EN_ADDR, MT6350_PMIC_VSYS_PG_H2L_EN_MASK, MT6350_PMIC_VSYS_PG_H2L_EN_SHIFT},
  {PMIC_STRUP_CON6_RSV0, MT6350_PMIC_STRUP_CON6_RSV0_ADDR, MT6350_PMIC_STRUP_CON6_RSV0_MASK, MT6350_PMIC_STRUP_CON6_RSV0_SHIFT},
  {PMIC_CLR_JUST_RST, MT6350_PMIC_CLR_JUST_RST_ADDR, MT6350_PMIC_CLR_JUST_RST_MASK, MT6350_PMIC_CLR_JUST_RST_SHIFT},
  {PMIC_UVLO_L2H_DEB_EN, MT6350_PMIC_UVLO_L2H_DEB_EN_ADDR, MT6350_PMIC_UVLO_L2H_DEB_EN_MASK, MT6350_PMIC_UVLO_L2H_DEB_EN_SHIFT},
  {PMIC_JUST_PWRKEY_RST, MT6350_PMIC_JUST_PWRKEY_RST_ADDR, MT6350_PMIC_JUST_PWRKEY_RST_MASK, MT6350_PMIC_JUST_PWRKEY_RST_SHIFT},
  {PMIC_QI_OSC_EN, MT6350_PMIC_QI_OSC_EN_ADDR, MT6350_PMIC_QI_OSC_EN_MASK, MT6350_PMIC_QI_OSC_EN_SHIFT},
  {PMIC_STRUP_EXT_PMIC_EN, MT6350_PMIC_STRUP_EXT_PMIC_EN_ADDR, MT6350_PMIC_STRUP_EXT_PMIC_EN_MASK, MT6350_PMIC_STRUP_EXT_PMIC_EN_SHIFT},
  {PMIC_STRUP_EXT_PMIC_SEL, MT6350_PMIC_STRUP_EXT_PMIC_SEL_ADDR, MT6350_PMIC_STRUP_EXT_PMIC_SEL_MASK, MT6350_PMIC_STRUP_EXT_PMIC_SEL_SHIFT},
  {PMIC_STRUP_CON8_RSV0, MT6350_PMIC_STRUP_CON8_RSV0_ADDR, MT6350_PMIC_STRUP_CON8_RSV0_MASK, MT6350_PMIC_STRUP_CON8_RSV0_SHIFT},
  {PMIC_QI_EXT_PMIC_EN, MT6350_PMIC_QI_EXT_PMIC_EN_ADDR, MT6350_PMIC_QI_EXT_PMIC_EN_MASK, MT6350_PMIC_QI_EXT_PMIC_EN_SHIFT},
  {PMIC_STRUP_AUXADC_START_SW, MT6350_PMIC_STRUP_AUXADC_START_SW_ADDR, MT6350_PMIC_STRUP_AUXADC_START_SW_MASK, MT6350_PMIC_STRUP_AUXADC_START_SW_SHIFT},
  {PMIC_STRUP_AUXADC_RSTB_SW, MT6350_PMIC_STRUP_AUXADC_RSTB_SW_ADDR, MT6350_PMIC_STRUP_AUXADC_RSTB_SW_MASK, MT6350_PMIC_STRUP_AUXADC_RSTB_SW_SHIFT},
  {PMIC_STRUP_AUXADC_START_SEL, MT6350_PMIC_STRUP_AUXADC_START_SEL_ADDR, MT6350_PMIC_STRUP_AUXADC_START_SEL_MASK, MT6350_PMIC_STRUP_AUXADC_START_SEL_SHIFT},
  {PMIC_STRUP_AUXADC_RSTB_SEL, MT6350_PMIC_STRUP_AUXADC_RSTB_SEL_ADDR, MT6350_PMIC_STRUP_AUXADC_RSTB_SEL_MASK, MT6350_PMIC_STRUP_AUXADC_RSTB_SEL_SHIFT},
  {PMIC_STRUP_PWROFF_SEQ_EN, MT6350_PMIC_STRUP_PWROFF_SEQ_EN_ADDR, MT6350_PMIC_STRUP_PWROFF_SEQ_EN_MASK, MT6350_PMIC_STRUP_PWROFF_SEQ_EN_SHIFT},
  {PMIC_STRUP_PWROFF_PREOFF_EN, MT6350_PMIC_STRUP_PWROFF_PREOFF_EN_ADDR, MT6350_PMIC_STRUP_PWROFF_PREOFF_EN_MASK, MT6350_PMIC_STRUP_PWROFF_PREOFF_EN_SHIFT},
  {PMIC_SPK_EN_L, MT6350_PMIC_SPK_EN_L_ADDR, MT6350_PMIC_SPK_EN_L_MASK, MT6350_PMIC_SPK_EN_L_SHIFT},
  {PMIC_SPKMODE_L, MT6350_PMIC_SPKMODE_L_ADDR, MT6350_PMIC_SPKMODE_L_MASK, MT6350_PMIC_SPKMODE_L_SHIFT},
  {PMIC_SPK_TRIM_EN_L, MT6350_PMIC_SPK_TRIM_EN_L_ADDR, MT6350_PMIC_SPK_TRIM_EN_L_MASK, MT6350_PMIC_SPK_TRIM_EN_L_SHIFT},
  {PMIC_SPK_OC_SHDN_DL, MT6350_PMIC_SPK_OC_SHDN_DL_ADDR, MT6350_PMIC_SPK_OC_SHDN_DL_MASK, MT6350_PMIC_SPK_OC_SHDN_DL_SHIFT},
  {PMIC_SPK_THER_SHDN_L_EN, MT6350_PMIC_SPK_THER_SHDN_L_EN_ADDR, MT6350_PMIC_SPK_THER_SHDN_L_EN_MASK, MT6350_PMIC_SPK_THER_SHDN_L_EN_SHIFT},
  {PMIC_RG_SPK_GAINL, MT6350_PMIC_RG_SPK_GAINL_ADDR, MT6350_PMIC_RG_SPK_GAINL_MASK, MT6350_PMIC_RG_SPK_GAINL_SHIFT},
  {PMIC_DA_SPK_OFFSET_L, MT6350_PMIC_DA_SPK_OFFSET_L_ADDR, MT6350_PMIC_DA_SPK_OFFSET_L_MASK, MT6350_PMIC_DA_SPK_OFFSET_L_SHIFT},
  {PMIC_DA_SPK_LEAD_DGLH_L, MT6350_PMIC_DA_SPK_LEAD_DGLH_L_ADDR, MT6350_PMIC_DA_SPK_LEAD_DGLH_L_MASK, MT6350_PMIC_DA_SPK_LEAD_DGLH_L_SHIFT},
  {PMIC_NI_SPK_LEAD_L, MT6350_PMIC_NI_SPK_LEAD_L_ADDR, MT6350_PMIC_NI_SPK_LEAD_L_MASK, MT6350_PMIC_NI_SPK_LEAD_L_SHIFT},
  {PMIC_SPK_OFFSET_L_OV, MT6350_PMIC_SPK_OFFSET_L_OV_ADDR, MT6350_PMIC_SPK_OFFSET_L_OV_MASK, MT6350_PMIC_SPK_OFFSET_L_OV_SHIFT},
  {PMIC_SPK_OFFSET_L_SW, MT6350_PMIC_SPK_OFFSET_L_SW_ADDR, MT6350_PMIC_SPK_OFFSET_L_SW_MASK, MT6350_PMIC_SPK_OFFSET_L_SW_SHIFT},
  {PMIC_SPK_LEAD_L_SW, MT6350_PMIC_SPK_LEAD_L_SW_ADDR, MT6350_PMIC_SPK_LEAD_L_SW_MASK, MT6350_PMIC_SPK_LEAD_L_SW_SHIFT},
  {PMIC_SPK_OFFSET_L_MODE, MT6350_PMIC_SPK_OFFSET_L_MODE_ADDR, MT6350_PMIC_SPK_OFFSET_L_MODE_MASK, MT6350_PMIC_SPK_OFFSET_L_MODE_SHIFT},
  {PMIC_SPK_TRIM_DONE_L, MT6350_PMIC_SPK_TRIM_DONE_L_ADDR, MT6350_PMIC_SPK_TRIM_DONE_L_MASK, MT6350_PMIC_SPK_TRIM_DONE_L_SHIFT},
  {PMIC_RG_SPK_INTG_RST_L, MT6350_PMIC_RG_SPK_INTG_RST_L_ADDR, MT6350_PMIC_RG_SPK_INTG_RST_L_MASK, MT6350_PMIC_RG_SPK_INTG_RST_L_SHIFT},
  {PMIC_RG_SPK_FORCE_EN_L, MT6350_PMIC_RG_SPK_FORCE_EN_L_ADDR, MT6350_PMIC_RG_SPK_FORCE_EN_L_MASK, MT6350_PMIC_RG_SPK_FORCE_EN_L_SHIFT},
  {PMIC_RG_SPK_SLEW_L, MT6350_PMIC_RG_SPK_SLEW_L_ADDR, MT6350_PMIC_RG_SPK_SLEW_L_MASK, MT6350_PMIC_RG_SPK_SLEW_L_SHIFT},
  {PMIC_RG_SPKAB_OBIAS_L, MT6350_PMIC_RG_SPKAB_OBIAS_L_ADDR, MT6350_PMIC_RG_SPKAB_OBIAS_L_MASK, MT6350_PMIC_RG_SPKAB_OBIAS_L_SHIFT},
  {PMIC_RG_SPKRCV_EN_L, MT6350_PMIC_RG_SPKRCV_EN_L_ADDR, MT6350_PMIC_RG_SPKRCV_EN_L_MASK, MT6350_PMIC_RG_SPKRCV_EN_L_SHIFT},
  {PMIC_RG_SPK_DRC_EN_L, MT6350_PMIC_RG_SPK_DRC_EN_L_ADDR, MT6350_PMIC_RG_SPK_DRC_EN_L_MASK, MT6350_PMIC_RG_SPK_DRC_EN_L_SHIFT},
  {PMIC_RG_SPK_TEST_EN_L, MT6350_PMIC_RG_SPK_TEST_EN_L_ADDR, MT6350_PMIC_RG_SPK_TEST_EN_L_MASK, MT6350_PMIC_RG_SPK_TEST_EN_L_SHIFT},
  {PMIC_RG_SPKAB_OC_EN_L, MT6350_PMIC_RG_SPKAB_OC_EN_L_ADDR, MT6350_PMIC_RG_SPKAB_OC_EN_L_MASK, MT6350_PMIC_RG_SPKAB_OC_EN_L_SHIFT},
  {PMIC_RG_SPK_OC_EN_L, MT6350_PMIC_RG_SPK_OC_EN_L_ADDR, MT6350_PMIC_RG_SPK_OC_EN_L_MASK, MT6350_PMIC_RG_SPK_OC_EN_L_SHIFT},
  {PMIC_SPK_TRIM_WND, MT6350_PMIC_SPK_TRIM_WND_ADDR, MT6350_PMIC_SPK_TRIM_WND_MASK, MT6350_PMIC_SPK_TRIM_WND_SHIFT},
  {PMIC_SPK_TRIM_THD, MT6350_PMIC_SPK_TRIM_THD_ADDR, MT6350_PMIC_SPK_TRIM_THD_MASK, MT6350_PMIC_SPK_TRIM_THD_SHIFT},
  {PMIC_SPK_OC_WND, MT6350_PMIC_SPK_OC_WND_ADDR, MT6350_PMIC_SPK_OC_WND_MASK, MT6350_PMIC_SPK_OC_WND_SHIFT},
  {PMIC_SPK_OC_THD, MT6350_PMIC_SPK_OC_THD_ADDR, MT6350_PMIC_SPK_OC_THD_MASK, MT6350_PMIC_SPK_OC_THD_SHIFT},
  {PMIC_SPK_D_OC_L_DEG, MT6350_PMIC_SPK_D_OC_L_DEG_ADDR, MT6350_PMIC_SPK_D_OC_L_DEG_MASK, MT6350_PMIC_SPK_D_OC_L_DEG_SHIFT},
  {PMIC_SPK_AB_OC_L_DEG, MT6350_PMIC_SPK_AB_OC_L_DEG_ADDR, MT6350_PMIC_SPK_AB_OC_L_DEG_MASK, MT6350_PMIC_SPK_AB_OC_L_DEG_SHIFT},
  {PMIC_SPK_TD1, MT6350_PMIC_SPK_TD1_ADDR, MT6350_PMIC_SPK_TD1_MASK, MT6350_PMIC_SPK_TD1_SHIFT},
  {PMIC_SPK_TD2, MT6350_PMIC_SPK_TD2_ADDR, MT6350_PMIC_SPK_TD2_MASK, MT6350_PMIC_SPK_TD2_SHIFT},
  {PMIC_SPK_TD3, MT6350_PMIC_SPK_TD3_ADDR, MT6350_PMIC_SPK_TD3_MASK, MT6350_PMIC_SPK_TD3_SHIFT},
  {PMIC_SPK_TRIM_DIV, MT6350_PMIC_SPK_TRIM_DIV_ADDR, MT6350_PMIC_SPK_TRIM_DIV_MASK, MT6350_PMIC_SPK_TRIM_DIV_SHIFT},
  {PMIC_RG_BTL_SET, MT6350_PMIC_RG_BTL_SET_ADDR, MT6350_PMIC_RG_BTL_SET_MASK, MT6350_PMIC_RG_BTL_SET_SHIFT},
  {PMIC_RG_SPK_IBIAS_SEL, MT6350_PMIC_RG_SPK_IBIAS_SEL_ADDR, MT6350_PMIC_RG_SPK_IBIAS_SEL_MASK, MT6350_PMIC_RG_SPK_IBIAS_SEL_SHIFT},
  {PMIC_RG_SPK_CCODE, MT6350_PMIC_RG_SPK_CCODE_ADDR, MT6350_PMIC_RG_SPK_CCODE_MASK, MT6350_PMIC_RG_SPK_CCODE_SHIFT},
  {PMIC_RG_SPK_EN_VIEW_VCM, MT6350_PMIC_RG_SPK_EN_VIEW_VCM_ADDR, MT6350_PMIC_RG_SPK_EN_VIEW_VCM_MASK, MT6350_PMIC_RG_SPK_EN_VIEW_VCM_SHIFT},
  {PMIC_RG_SPK_EN_VIEW_CLK, MT6350_PMIC_RG_SPK_EN_VIEW_CLK_ADDR, MT6350_PMIC_RG_SPK_EN_VIEW_CLK_MASK, MT6350_PMIC_RG_SPK_EN_VIEW_CLK_SHIFT},
  {PMIC_RG_SPK_VCM_SEL, MT6350_PMIC_RG_SPK_VCM_SEL_ADDR, MT6350_PMIC_RG_SPK_VCM_SEL_MASK, MT6350_PMIC_RG_SPK_VCM_SEL_SHIFT},
  {PMIC_RG_SPK_VCM_IBSEL, MT6350_PMIC_RG_SPK_VCM_IBSEL_ADDR, MT6350_PMIC_RG_SPK_VCM_IBSEL_MASK, MT6350_PMIC_RG_SPK_VCM_IBSEL_SHIFT},
  {PMIC_RG_SPK_FBRC_EN, MT6350_PMIC_RG_SPK_FBRC_EN_ADDR, MT6350_PMIC_RG_SPK_FBRC_EN_MASK, MT6350_PMIC_RG_SPK_FBRC_EN_SHIFT},
  {PMIC_RG_SPKAB_OVDRV, MT6350_PMIC_RG_SPKAB_OVDRV_ADDR, MT6350_PMIC_RG_SPKAB_OVDRV_MASK, MT6350_PMIC_RG_SPKAB_OVDRV_SHIFT},
  {PMIC_RG_SPK_OCTH_D, MT6350_PMIC_RG_SPK_OCTH_D_ADDR, MT6350_PMIC_RG_SPK_OCTH_D_MASK, MT6350_PMIC_RG_SPK_OCTH_D_SHIFT},
  {PMIC_RG_SPK_RSV, MT6350_PMIC_RG_SPK_RSV_ADDR, MT6350_PMIC_RG_SPK_RSV_MASK, MT6350_PMIC_RG_SPK_RSV_SHIFT},
  {PMIC_RG_SPKPGA_GAIN, MT6350_PMIC_RG_SPKPGA_GAIN_ADDR, MT6350_PMIC_RG_SPKPGA_GAIN_MASK, MT6350_PMIC_RG_SPKPGA_GAIN_SHIFT},
  {PMIC_SPK_RSV0, MT6350_PMIC_SPK_RSV0_ADDR, MT6350_PMIC_SPK_RSV0_MASK, MT6350_PMIC_SPK_RSV0_SHIFT},
  {PMIC_SPK_VCM_FAST_EN, MT6350_PMIC_SPK_VCM_FAST_EN_ADDR, MT6350_PMIC_SPK_VCM_FAST_EN_MASK, MT6350_PMIC_SPK_VCM_FAST_EN_SHIFT},
  {PMIC_SPK_TEST_MODE0, MT6350_PMIC_SPK_TEST_MODE0_ADDR, MT6350_PMIC_SPK_TEST_MODE0_MASK, MT6350_PMIC_SPK_TEST_MODE0_SHIFT},
  {PMIC_SPK_TEST_MODE1, MT6350_PMIC_SPK_TEST_MODE1_ADDR, MT6350_PMIC_SPK_TEST_MODE1_MASK, MT6350_PMIC_SPK_TEST_MODE1_SHIFT},
  {PMIC_RG_SPK_ISENSE_REFSEL, MT6350_PMIC_RG_SPK_ISENSE_REFSEL_ADDR, MT6350_PMIC_RG_SPK_ISENSE_REFSEL_MASK, MT6350_PMIC_RG_SPK_ISENSE_REFSEL_SHIFT},
  {PMIC_RG_SPK_ISENSE_GAINSEL, MT6350_PMIC_RG_SPK_ISENSE_GAINSEL_ADDR, MT6350_PMIC_RG_SPK_ISENSE_GAINSEL_MASK, MT6350_PMIC_RG_SPK_ISENSE_GAINSEL_SHIFT},
  {PMIC_RG_ISENSE_PD_RESET, MT6350_PMIC_RG_ISENSE_PD_RESET_ADDR, MT6350_PMIC_RG_ISENSE_PD_RESET_MASK, MT6350_PMIC_RG_ISENSE_PD_RESET_SHIFT},
  {PMIC_RG_SPK_ISENSE_EN, MT6350_PMIC_RG_SPK_ISENSE_EN_ADDR, MT6350_PMIC_RG_SPK_ISENSE_EN_MASK, MT6350_PMIC_RG_SPK_ISENSE_EN_SHIFT},
  {PMIC_RG_SPK_ISENSE_TEST_EN, MT6350_PMIC_RG_SPK_ISENSE_TEST_EN_ADDR, MT6350_PMIC_RG_SPK_ISENSE_TEST_EN_MASK, MT6350_PMIC_RG_SPK_ISENSE_TEST_EN_SHIFT},
  {PMIC_SPK_TD_WAIT, MT6350_PMIC_SPK_TD_WAIT_ADDR, MT6350_PMIC_SPK_TD_WAIT_MASK, MT6350_PMIC_SPK_TD_WAIT_SHIFT},
  {PMIC_SPK_TD_DONE, MT6350_PMIC_SPK_TD_DONE_ADDR, MT6350_PMIC_SPK_TD_DONE_MASK, MT6350_PMIC_SPK_TD_DONE_SHIFT},
  {PMIC_SPK_EN_MODE, MT6350_PMIC_SPK_EN_MODE_ADDR, MT6350_PMIC_SPK_EN_MODE_MASK, MT6350_PMIC_SPK_EN_MODE_SHIFT},
  {PMIC_SPK_VCM_FAST_SW, MT6350_PMIC_SPK_VCM_FAST_SW_ADDR, MT6350_PMIC_SPK_VCM_FAST_SW_MASK, MT6350_PMIC_SPK_VCM_FAST_SW_SHIFT},
  {PMIC_SPK_RST_L_SW, MT6350_PMIC_SPK_RST_L_SW_ADDR, MT6350_PMIC_SPK_RST_L_SW_MASK, MT6350_PMIC_SPK_RST_L_SW_SHIFT},
  {PMIC_SPKMODE_L_SW, MT6350_PMIC_SPKMODE_L_SW_ADDR, MT6350_PMIC_SPKMODE_L_SW_MASK, MT6350_PMIC_SPKMODE_L_SW_SHIFT},
  {PMIC_SPK_DEPOP_EN_L_SW, MT6350_PMIC_SPK_DEPOP_EN_L_SW_ADDR, MT6350_PMIC_SPK_DEPOP_EN_L_SW_MASK, MT6350_PMIC_SPK_DEPOP_EN_L_SW_SHIFT},
  {PMIC_SPK_EN_L_SW, MT6350_PMIC_SPK_EN_L_SW_ADDR, MT6350_PMIC_SPK_EN_L_SW_MASK, MT6350_PMIC_SPK_EN_L_SW_SHIFT},
  {PMIC_SPK_OUTSTG_EN_L_SW, MT6350_PMIC_SPK_OUTSTG_EN_L_SW_ADDR, MT6350_PMIC_SPK_OUTSTG_EN_L_SW_MASK, MT6350_PMIC_SPK_OUTSTG_EN_L_SW_SHIFT},
  {PMIC_SPK_TRIM_EN_L_SW, MT6350_PMIC_SPK_TRIM_EN_L_SW_ADDR, MT6350_PMIC_SPK_TRIM_EN_L_SW_MASK, MT6350_PMIC_SPK_TRIM_EN_L_SW_SHIFT},
  {PMIC_SPK_TRIM_STOP_L_SW, MT6350_PMIC_SPK_TRIM_STOP_L_SW_ADDR, MT6350_PMIC_SPK_TRIM_STOP_L_SW_MASK, MT6350_PMIC_SPK_TRIM_STOP_L_SW_SHIFT},
  {PMIC_CID, MT6350_PMIC_CID_ADDR, MT6350_PMIC_CID_MASK, MT6350_PMIC_CID_SHIFT},
  {PMIC_RG_CLKSQ_EN_AUD, MT6350_PMIC_RG_CLKSQ_EN_AUD_ADDR, MT6350_PMIC_RG_CLKSQ_EN_AUD_MASK, MT6350_PMIC_RG_CLKSQ_EN_AUD_SHIFT},
  {PMIC_RG_CLKSQ_EN_AUX, MT6350_PMIC_RG_CLKSQ_EN_AUX_ADDR, MT6350_PMIC_RG_CLKSQ_EN_AUX_MASK, MT6350_PMIC_RG_CLKSQ_EN_AUX_SHIFT},
  {PMIC_RG_CLKSQ_EN_FQR, MT6350_PMIC_RG_CLKSQ_EN_FQR_ADDR, MT6350_PMIC_RG_CLKSQ_EN_FQR_MASK, MT6350_PMIC_RG_CLKSQ_EN_FQR_SHIFT},
  {PMIC_RG_STRUP_75K_CK_PDN, MT6350_PMIC_RG_STRUP_75K_CK_PDN_ADDR, MT6350_PMIC_RG_STRUP_75K_CK_PDN_MASK, MT6350_PMIC_RG_STRUP_75K_CK_PDN_SHIFT},
  {PMIC_RG_STRUP_32K_CK_PDN, MT6350_PMIC_RG_STRUP_32K_CK_PDN_ADDR, MT6350_PMIC_RG_STRUP_32K_CK_PDN_MASK, MT6350_PMIC_RG_STRUP_32K_CK_PDN_SHIFT},
  {PMIC_RG_RTC_75K_DIV4_CK_PDN, MT6350_PMIC_RG_RTC_75K_DIV4_CK_PDN_ADDR, MT6350_PMIC_RG_RTC_75K_DIV4_CK_PDN_MASK, MT6350_PMIC_RG_RTC_75K_DIV4_CK_PDN_SHIFT},
  {PMIC_RG_RTC_75K_CK_PDN, MT6350_PMIC_RG_RTC_75K_CK_PDN_ADDR, MT6350_PMIC_RG_RTC_75K_CK_PDN_MASK, MT6350_PMIC_RG_RTC_75K_CK_PDN_SHIFT},
  {PMIC_RG_RTC_32K_CK_PDN, MT6350_PMIC_RG_RTC_32K_CK_PDN_ADDR, MT6350_PMIC_RG_RTC_32K_CK_PDN_MASK, MT6350_PMIC_RG_RTC_32K_CK_PDN_SHIFT},
  {PMIC_RG_PCHR_32K_CK_PDN, MT6350_PMIC_RG_PCHR_32K_CK_PDN_ADDR, MT6350_PMIC_RG_PCHR_32K_CK_PDN_MASK, MT6350_PMIC_RG_PCHR_32K_CK_PDN_SHIFT},
  {PMIC_RG_LDOSTB_1M_CK_PDN, MT6350_PMIC_RG_LDOSTB_1M_CK_PDN_ADDR, MT6350_PMIC_RG_LDOSTB_1M_CK_PDN_MASK, MT6350_PMIC_RG_LDOSTB_1M_CK_PDN_SHIFT},
  {PMIC_RG_INTRP_CK_PDN, MT6350_PMIC_RG_INTRP_CK_PDN_ADDR, MT6350_PMIC_RG_INTRP_CK_PDN_MASK, MT6350_PMIC_RG_INTRP_CK_PDN_SHIFT},
  {PMIC_RG_DRV_32K_CK_PDN, MT6350_PMIC_RG_DRV_32K_CK_PDN_ADDR, MT6350_PMIC_RG_DRV_32K_CK_PDN_MASK, MT6350_PMIC_RG_DRV_32K_CK_PDN_SHIFT},
  {PMIC_RG_BUCK_1M_CK_PDN, MT6350_PMIC_RG_BUCK_1M_CK_PDN_ADDR, MT6350_PMIC_RG_BUCK_1M_CK_PDN_MASK, MT6350_PMIC_RG_BUCK_1M_CK_PDN_SHIFT},
  {PMIC_RG_BUCK_CK_PDN, MT6350_PMIC_RG_BUCK_CK_PDN_ADDR, MT6350_PMIC_RG_BUCK_CK_PDN_MASK, MT6350_PMIC_RG_BUCK_CK_PDN_SHIFT},
  {PMIC_RG_BUCK_ANA_CK_PDN, MT6350_PMIC_RG_BUCK_ANA_CK_PDN_ADDR, MT6350_PMIC_RG_BUCK_ANA_CK_PDN_MASK, MT6350_PMIC_RG_BUCK_ANA_CK_PDN_SHIFT},
  {PMIC_RG_BUCK32K_PDN, MT6350_PMIC_RG_BUCK32K_PDN_ADDR, MT6350_PMIC_RG_BUCK32K_PDN_MASK, MT6350_PMIC_RG_BUCK32K_PDN_SHIFT},
  {PMIC_TOP_CKPDN0_SET, MT6350_PMIC_TOP_CKPDN0_SET_ADDR, MT6350_PMIC_TOP_CKPDN0_SET_MASK, MT6350_PMIC_TOP_CKPDN0_SET_SHIFT},
  {PMIC_TOP_CKPDN0_CLR, MT6350_PMIC_TOP_CKPDN0_CLR_ADDR, MT6350_PMIC_TOP_CKPDN0_CLR_MASK, MT6350_PMIC_TOP_CKPDN0_CLR_SHIFT},
  {PMIC_RG_STRUP_6M_PDN, MT6350_PMIC_RG_STRUP_6M_PDN_ADDR, MT6350_PMIC_RG_STRUP_6M_PDN_MASK, MT6350_PMIC_RG_STRUP_6M_PDN_SHIFT},
  {PMIC_RG_SPK_PWM_DIV_PDN, MT6350_PMIC_RG_SPK_PWM_DIV_PDN_ADDR, MT6350_PMIC_RG_SPK_PWM_DIV_PDN_MASK, MT6350_PMIC_RG_SPK_PWM_DIV_PDN_SHIFT},
  {PMIC_RG_SPK_DIV_PDN, MT6350_PMIC_RG_SPK_DIV_PDN_ADDR, MT6350_PMIC_RG_SPK_DIV_PDN_MASK, MT6350_PMIC_RG_SPK_DIV_PDN_SHIFT},
  {PMIC_RG_SPK_CK_PDN, MT6350_PMIC_RG_SPK_CK_PDN_ADDR, MT6350_PMIC_RG_SPK_CK_PDN_MASK, MT6350_PMIC_RG_SPK_CK_PDN_SHIFT},
  {PMIC_RG_PWMOC_CK_PDN, MT6350_PMIC_RG_PWMOC_CK_PDN_ADDR, MT6350_PMIC_RG_PWMOC_CK_PDN_MASK, MT6350_PMIC_RG_PWMOC_CK_PDN_SHIFT},
  {PMIC_RG_FQMTR_PDN, MT6350_PMIC_RG_FQMTR_PDN_ADDR, MT6350_PMIC_RG_FQMTR_PDN_MASK, MT6350_PMIC_RG_FQMTR_PDN_SHIFT},
  {PMIC_RG_DRV_2M_CK_PDN, MT6350_PMIC_RG_DRV_2M_CK_PDN_ADDR, MT6350_PMIC_RG_DRV_2M_CK_PDN_MASK, MT6350_PMIC_RG_DRV_2M_CK_PDN_SHIFT},
  {PMIC_RG_DRV_1M_CK_PDN, MT6350_PMIC_RG_DRV_1M_CK_PDN_ADDR, MT6350_PMIC_RG_DRV_1M_CK_PDN_MASK, MT6350_PMIC_RG_DRV_1M_CK_PDN_SHIFT},
  {PMIC_RG_AUD_26M_PDN, MT6350_PMIC_RG_AUD_26M_PDN_ADDR, MT6350_PMIC_RG_AUD_26M_PDN_MASK, MT6350_PMIC_RG_AUD_26M_PDN_SHIFT},
  {PMIC_RG_ACCDET_CK_PDN, MT6350_PMIC_RG_ACCDET_CK_PDN_ADDR, MT6350_PMIC_RG_ACCDET_CK_PDN_MASK, MT6350_PMIC_RG_ACCDET_CK_PDN_SHIFT},
  {PMIC_RG_RTC_MCLK_PDN, MT6350_PMIC_RG_RTC_MCLK_PDN_ADDR, MT6350_PMIC_RG_RTC_MCLK_PDN_MASK, MT6350_PMIC_RG_RTC_MCLK_PDN_SHIFT},
  {PMIC_RG_SMPS_CK_DIV_PDN, MT6350_PMIC_RG_SMPS_CK_DIV_PDN_ADDR, MT6350_PMIC_RG_SMPS_CK_DIV_PDN_MASK, MT6350_PMIC_RG_SMPS_CK_DIV_PDN_SHIFT},
  {PMIC_RG_EFUSE_CK_PDN, MT6350_PMIC_RG_EFUSE_CK_PDN_ADDR, MT6350_PMIC_RG_EFUSE_CK_PDN_MASK, MT6350_PMIC_RG_EFUSE_CK_PDN_SHIFT},
  {PMIC_RG_RTC32K_1V8_PDN, MT6350_PMIC_RG_RTC32K_1V8_PDN_ADDR, MT6350_PMIC_RG_RTC32K_1V8_PDN_MASK, MT6350_PMIC_RG_RTC32K_1V8_PDN_SHIFT},
  {PMIC_RG_CLKSQ_EN_AUX_MD, MT6350_PMIC_RG_CLKSQ_EN_AUX_MD_ADDR, MT6350_PMIC_RG_CLKSQ_EN_AUX_MD_MASK, MT6350_PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT},
  {PMIC_RG_AUXADC_SDM_CK_WAKE_PDN, MT6350_PMIC_RG_AUXADC_SDM_CK_WAKE_PDN_ADDR, MT6350_PMIC_RG_AUXADC_SDM_CK_WAKE_PDN_MASK, MT6350_PMIC_RG_AUXADC_SDM_CK_WAKE_PDN_SHIFT},
  {PMIC_TOP_CKPDN1_SET, MT6350_PMIC_TOP_CKPDN1_SET_ADDR, MT6350_PMIC_TOP_CKPDN1_SET_MASK, MT6350_PMIC_TOP_CKPDN1_SET_SHIFT},
  {PMIC_TOP_CKPDN1_CLR, MT6350_PMIC_TOP_CKPDN1_CLR_ADDR, MT6350_PMIC_TOP_CKPDN1_CLR_MASK, MT6350_PMIC_TOP_CKPDN1_CLR_SHIFT},
  {PMIC_RG_ISINK0_CK_PDN, MT6350_PMIC_RG_ISINK0_CK_PDN_ADDR, MT6350_PMIC_RG_ISINK0_CK_PDN_MASK, MT6350_PMIC_RG_ISINK0_CK_PDN_SHIFT},
  {PMIC_RG_ISINK1_CK_PDN, MT6350_PMIC_RG_ISINK1_CK_PDN_ADDR, MT6350_PMIC_RG_ISINK1_CK_PDN_MASK, MT6350_PMIC_RG_ISINK1_CK_PDN_SHIFT},
  {PMIC_RG_ISINK2_CK_PDN, MT6350_PMIC_RG_ISINK2_CK_PDN_ADDR, MT6350_PMIC_RG_ISINK2_CK_PDN_MASK, MT6350_PMIC_RG_ISINK2_CK_PDN_SHIFT},
  {PMIC_RG_ISINK3_CK_PDN, MT6350_PMIC_RG_ISINK3_CK_PDN_ADDR, MT6350_PMIC_RG_ISINK3_CK_PDN_MASK, MT6350_PMIC_RG_ISINK3_CK_PDN_SHIFT},
  {PMIC_RG_AUXADC_SDM_CK_PDN, MT6350_PMIC_RG_AUXADC_SDM_CK_PDN_ADDR, MT6350_PMIC_RG_AUXADC_SDM_CK_PDN_MASK, MT6350_PMIC_RG_AUXADC_SDM_CK_PDN_SHIFT},
  {PMIC_RG_AUXADC_CTL_CK_PDN, MT6350_PMIC_RG_AUXADC_CTL_CK_PDN_ADDR, MT6350_PMIC_RG_AUXADC_CTL_CK_PDN_MASK, MT6350_PMIC_RG_AUXADC_CTL_CK_PDN_SHIFT},
  {PMIC_RG_AUXADC_32K_CK_PDN, MT6350_PMIC_RG_AUXADC_32K_CK_PDN_ADDR, MT6350_PMIC_RG_AUXADC_32K_CK_PDN_MASK, MT6350_PMIC_RG_AUXADC_32K_CK_PDN_SHIFT},
  {PMIC_RG_AUD26M_DIV4_CK_PDN, MT6350_PMIC_RG_AUD26M_DIV4_CK_PDN_ADDR, MT6350_PMIC_RG_AUD26M_DIV4_CK_PDN_MASK, MT6350_PMIC_RG_AUD26M_DIV4_CK_PDN_SHIFT},
  {PMIC_TOP_CKPDN2_SET, MT6350_PMIC_TOP_CKPDN2_SET_ADDR, MT6350_PMIC_TOP_CKPDN2_SET_MASK, MT6350_PMIC_TOP_CKPDN2_SET_SHIFT},
  {PMIC_TOP_CKPDN2_CLR, MT6350_PMIC_TOP_CKPDN2_CLR_ADDR, MT6350_PMIC_TOP_CKPDN2_CLR_MASK, MT6350_PMIC_TOP_CKPDN2_CLR_SHIFT},
  {PMIC_RG_EFUSE_MAN_RST, MT6350_PMIC_RG_EFUSE_MAN_RST_ADDR, MT6350_PMIC_RG_EFUSE_MAN_RST_MASK, MT6350_PMIC_RG_EFUSE_MAN_RST_SHIFT},
  {PMIC_RG_AUXADC_RST, MT6350_PMIC_RG_AUXADC_RST_ADDR, MT6350_PMIC_RG_AUXADC_RST_MASK, MT6350_PMIC_RG_AUXADC_RST_SHIFT},
  {PMIC_RG_AUDIO_RST, MT6350_PMIC_RG_AUDIO_RST_ADDR, MT6350_PMIC_RG_AUDIO_RST_MASK, MT6350_PMIC_RG_AUDIO_RST_SHIFT},
  {PMIC_RG_ACCDET_RST, MT6350_PMIC_RG_ACCDET_RST_ADDR, MT6350_PMIC_RG_ACCDET_RST_MASK, MT6350_PMIC_RG_ACCDET_RST_SHIFT},
  {PMIC_RG_SPK_RST, MT6350_PMIC_RG_SPK_RST_ADDR, MT6350_PMIC_RG_SPK_RST_MASK, MT6350_PMIC_RG_SPK_RST_SHIFT},
  {PMIC_RG_DRIVER_RST, MT6350_PMIC_RG_DRIVER_RST_ADDR, MT6350_PMIC_RG_DRIVER_RST_MASK, MT6350_PMIC_RG_DRIVER_RST_SHIFT},
  {PMIC_RG_RTC_RST, MT6350_PMIC_RG_RTC_RST_ADDR, MT6350_PMIC_RG_RTC_RST_MASK, MT6350_PMIC_RG_RTC_RST_SHIFT},
  {PMIC_RG_FQMTR_RST, MT6350_PMIC_RG_FQMTR_RST_ADDR, MT6350_PMIC_RG_FQMTR_RST_MASK, MT6350_PMIC_RG_FQMTR_RST_SHIFT},
  {PMIC_RG_TOP_RST_CON_RSV_15_9, MT6350_PMIC_RG_TOP_RST_CON_RSV_15_9_ADDR, MT6350_PMIC_RG_TOP_RST_CON_RSV_15_9_MASK, MT6350_PMIC_RG_TOP_RST_CON_RSV_15_9_SHIFT},
  {PMIC_TOP_RST_CON_SET, MT6350_PMIC_TOP_RST_CON_SET_ADDR, MT6350_PMIC_TOP_RST_CON_SET_MASK, MT6350_PMIC_TOP_RST_CON_SET_SHIFT},
  {PMIC_TOP_RST_CON_CLR, MT6350_PMIC_TOP_RST_CON_CLR_ADDR, MT6350_PMIC_TOP_RST_CON_CLR_MASK, MT6350_PMIC_TOP_RST_CON_CLR_SHIFT},
  {PMIC_RG_AP_RST_DIS, MT6350_PMIC_RG_AP_RST_DIS_ADDR, MT6350_PMIC_RG_AP_RST_DIS_MASK, MT6350_PMIC_RG_AP_RST_DIS_SHIFT},
  {PMIC_RG_SYSRSTB_EN, MT6350_PMIC_RG_SYSRSTB_EN_ADDR, MT6350_PMIC_RG_SYSRSTB_EN_MASK, MT6350_PMIC_RG_SYSRSTB_EN_SHIFT},
  {PMIC_RG_STRUP_MAN_RST_EN, MT6350_PMIC_RG_STRUP_MAN_RST_EN_ADDR, MT6350_PMIC_RG_STRUP_MAN_RST_EN_MASK, MT6350_PMIC_RG_STRUP_MAN_RST_EN_SHIFT},
  {PMIC_RG_NEWLDO_RSTB_EN, MT6350_PMIC_RG_NEWLDO_RSTB_EN_ADDR, MT6350_PMIC_RG_NEWLDO_RSTB_EN_MASK, MT6350_PMIC_RG_NEWLDO_RSTB_EN_SHIFT},
  {PMIC_RG_RST_PART_SEL, MT6350_PMIC_RG_RST_PART_SEL_ADDR, MT6350_PMIC_RG_RST_PART_SEL_MASK, MT6350_PMIC_RG_RST_PART_SEL_SHIFT},
  {PMIC_RG_HOMEKEY_RST_EN, MT6350_PMIC_RG_HOMEKEY_RST_EN_ADDR, MT6350_PMIC_RG_HOMEKEY_RST_EN_MASK, MT6350_PMIC_RG_HOMEKEY_RST_EN_SHIFT},
  {PMIC_RG_PWRKEY_RST_EN, MT6350_PMIC_RG_PWRKEY_RST_EN_ADDR, MT6350_PMIC_RG_PWRKEY_RST_EN_MASK, MT6350_PMIC_RG_PWRKEY_RST_EN_SHIFT},
  {PMIC_RG_PWRRST_TMR_DIS, MT6350_PMIC_RG_PWRRST_TMR_DIS_ADDR, MT6350_PMIC_RG_PWRRST_TMR_DIS_MASK, MT6350_PMIC_RG_PWRRST_TMR_DIS_SHIFT},
  {PMIC_RG_PWRKEY_RST_TD, MT6350_PMIC_RG_PWRKEY_RST_TD_ADDR, MT6350_PMIC_RG_PWRKEY_RST_TD_MASK, MT6350_PMIC_RG_PWRKEY_RST_TD_SHIFT},
  {PMIC_TOP_RST_MISC_SET, MT6350_PMIC_TOP_RST_MISC_SET_ADDR, MT6350_PMIC_TOP_RST_MISC_SET_MASK, MT6350_PMIC_TOP_RST_MISC_SET_SHIFT},
  {PMIC_TOP_RST_MISC_CLR, MT6350_PMIC_TOP_RST_MISC_CLR_ADDR, MT6350_PMIC_TOP_RST_MISC_CLR_MASK, MT6350_PMIC_TOP_RST_MISC_CLR_SHIFT},
  {PMIC_RG_SRCLKEN_EN, MT6350_PMIC_RG_SRCLKEN_EN_ADDR, MT6350_PMIC_RG_SRCLKEN_EN_MASK, MT6350_PMIC_RG_SRCLKEN_EN_SHIFT},
  {PMIC_RG_OSC_SEL, MT6350_PMIC_RG_OSC_SEL_ADDR, MT6350_PMIC_RG_OSC_SEL_MASK, MT6350_PMIC_RG_OSC_SEL_SHIFT},
  {PMIC_RG_AUXADC_SDM_SEL_HW_MODE, MT6350_PMIC_RG_AUXADC_SDM_SEL_HW_MODE_ADDR, MT6350_PMIC_RG_AUXADC_SDM_SEL_HW_MODE_MASK, MT6350_PMIC_RG_AUXADC_SDM_SEL_HW_MODE_SHIFT},
  {PMIC_RG_SRCLKEN_HW_MODE, MT6350_PMIC_RG_SRCLKEN_HW_MODE_ADDR, MT6350_PMIC_RG_SRCLKEN_HW_MODE_MASK, MT6350_PMIC_RG_SRCLKEN_HW_MODE_SHIFT},
  {PMIC_RG_OSC_HW_MODE, MT6350_PMIC_RG_OSC_HW_MODE_ADDR, MT6350_PMIC_RG_OSC_HW_MODE_MASK, MT6350_PMIC_RG_OSC_HW_MODE_SHIFT},
  {PMIC_RG_OSC_HW_SRC_SEL, MT6350_PMIC_RG_OSC_HW_SRC_SEL_ADDR, MT6350_PMIC_RG_OSC_HW_SRC_SEL_MASK, MT6350_PMIC_RG_OSC_HW_SRC_SEL_SHIFT},
  {PMIC_RG_AUXADC_SDM_CK_HW_MODE, MT6350_PMIC_RG_AUXADC_SDM_CK_HW_MODE_ADDR, MT6350_PMIC_RG_AUXADC_SDM_CK_HW_MODE_MASK, MT6350_PMIC_RG_AUXADC_SDM_CK_HW_MODE_SHIFT},
  {PMIC_RG_SMPS_AUTOFF_DIS, MT6350_PMIC_RG_SMPS_AUTOFF_DIS_ADDR, MT6350_PMIC_RG_SMPS_AUTOFF_DIS_MASK, MT6350_PMIC_RG_SMPS_AUTOFF_DIS_SHIFT},
  {PMIC_RG_BUCK_1M_AUTOFF_DIS, MT6350_PMIC_RG_BUCK_1M_AUTOFF_DIS_ADDR, MT6350_PMIC_RG_BUCK_1M_AUTOFF_DIS_MASK, MT6350_PMIC_RG_BUCK_1M_AUTOFF_DIS_SHIFT},
  {PMIC_RG_BUCK_ANA_AUTOFF_DIS, MT6350_PMIC_RG_BUCK_ANA_AUTOFF_DIS_ADDR, MT6350_PMIC_RG_BUCK_ANA_AUTOFF_DIS_MASK, MT6350_PMIC_RG_BUCK_ANA_AUTOFF_DIS_SHIFT},
  {PMIC_TOP_CKCON0_SET, MT6350_PMIC_TOP_CKCON0_SET_ADDR, MT6350_PMIC_TOP_CKCON0_SET_MASK, MT6350_PMIC_TOP_CKCON0_SET_SHIFT},
  {PMIC_TOP_CKCON0_CLR, MT6350_PMIC_TOP_CKCON0_CLR_ADDR, MT6350_PMIC_TOP_CKCON0_CLR_MASK, MT6350_PMIC_TOP_CKCON0_CLR_SHIFT},
  {PMIC_RG_REGCK_SEL, MT6350_PMIC_RG_REGCK_SEL_ADDR, MT6350_PMIC_RG_REGCK_SEL_MASK, MT6350_PMIC_RG_REGCK_SEL_SHIFT},
  {PMIC_RG_SPK_PWM_DIV_SEL, MT6350_PMIC_RG_SPK_PWM_DIV_SEL_ADDR, MT6350_PMIC_RG_SPK_PWM_DIV_SEL_MASK, MT6350_PMIC_RG_SPK_PWM_DIV_SEL_SHIFT},
  {PMIC_RG_SPK_DIV_SEL, MT6350_PMIC_RG_SPK_DIV_SEL_ADDR, MT6350_PMIC_RG_SPK_DIV_SEL_MASK, MT6350_PMIC_RG_SPK_DIV_SEL_SHIFT},
  {PMIC_RG_FQMTR_CKSEL, MT6350_PMIC_RG_FQMTR_CKSEL_ADDR, MT6350_PMIC_RG_FQMTR_CKSEL_MASK, MT6350_PMIC_RG_FQMTR_CKSEL_SHIFT},
  {PMIC_RG_ACCDET_CKSEL, MT6350_PMIC_RG_ACCDET_CKSEL_ADDR, MT6350_PMIC_RG_ACCDET_CKSEL_MASK, MT6350_PMIC_RG_ACCDET_CKSEL_SHIFT},
  {PMIC_RG_ISINK0_CK_SEL, MT6350_PMIC_RG_ISINK0_CK_SEL_ADDR, MT6350_PMIC_RG_ISINK0_CK_SEL_MASK, MT6350_PMIC_RG_ISINK0_CK_SEL_SHIFT},
  {PMIC_RG_ISINK1_CK_SEL, MT6350_PMIC_RG_ISINK1_CK_SEL_ADDR, MT6350_PMIC_RG_ISINK1_CK_SEL_MASK, MT6350_PMIC_RG_ISINK1_CK_SEL_SHIFT},
  {PMIC_RG_ISINK2_CK_SEL, MT6350_PMIC_RG_ISINK2_CK_SEL_ADDR, MT6350_PMIC_RG_ISINK2_CK_SEL_MASK, MT6350_PMIC_RG_ISINK2_CK_SEL_SHIFT},
  {PMIC_RG_ISINK3_CK_SEL, MT6350_PMIC_RG_ISINK3_CK_SEL_ADDR, MT6350_PMIC_RG_ISINK3_CK_SEL_MASK, MT6350_PMIC_RG_ISINK3_CK_SEL_SHIFT},
  {PMIC_RG_AUXADC_SDM_CK_SEL, MT6350_PMIC_RG_AUXADC_SDM_CK_SEL_ADDR, MT6350_PMIC_RG_AUXADC_SDM_CK_SEL_MASK, MT6350_PMIC_RG_AUXADC_SDM_CK_SEL_SHIFT},
  {PMIC_RG_AUDIO_CK_SEL, MT6350_PMIC_RG_AUDIO_CK_SEL_ADDR, MT6350_PMIC_RG_AUDIO_CK_SEL_MASK, MT6350_PMIC_RG_AUDIO_CK_SEL_SHIFT},
  {PMIC_TOP_CKCON1_SET, MT6350_PMIC_TOP_CKCON1_SET_ADDR, MT6350_PMIC_TOP_CKCON1_SET_MASK, MT6350_PMIC_TOP_CKCON1_SET_SHIFT},
  {PMIC_TOP_CKCON1_CLR, MT6350_PMIC_TOP_CKCON1_CLR_ADDR, MT6350_PMIC_TOP_CKCON1_CLR_MASK, MT6350_PMIC_TOP_CKCON1_CLR_SHIFT},
  {PMIC_RG_RTC32K_TST_DIS, MT6350_PMIC_RG_RTC32K_TST_DIS_ADDR, MT6350_PMIC_RG_RTC32K_TST_DIS_MASK, MT6350_PMIC_RG_RTC32K_TST_DIS_SHIFT},
  {PMIC_RG_SPK_TST_DIS, MT6350_PMIC_RG_SPK_TST_DIS_ADDR, MT6350_PMIC_RG_SPK_TST_DIS_MASK, MT6350_PMIC_RG_SPK_TST_DIS_SHIFT},
  {PMIC_RG_SMPS_TST_DIS, MT6350_PMIC_RG_SMPS_TST_DIS_ADDR, MT6350_PMIC_RG_SMPS_TST_DIS_MASK, MT6350_PMIC_RG_SMPS_TST_DIS_SHIFT},
  {PMIC_RG_PMU75K_TST_DIS, MT6350_PMIC_RG_PMU75K_TST_DIS_ADDR, MT6350_PMIC_RG_PMU75K_TST_DIS_MASK, MT6350_PMIC_RG_PMU75K_TST_DIS_SHIFT},
  {PMIC_RG_AUD26M_TST_DIS, MT6350_PMIC_RG_AUD26M_TST_DIS_ADDR, MT6350_PMIC_RG_AUD26M_TST_DIS_MASK, MT6350_PMIC_RG_AUD26M_TST_DIS_SHIFT},
  {PMIC_RG_SPK_TSTSEL, MT6350_PMIC_RG_SPK_TSTSEL_ADDR, MT6350_PMIC_RG_SPK_TSTSEL_MASK, MT6350_PMIC_RG_SPK_TSTSEL_SHIFT},
  {PMIC_RG_SMPS_TSTSEL, MT6350_PMIC_RG_SMPS_TSTSEL_ADDR, MT6350_PMIC_RG_SMPS_TSTSEL_MASK, MT6350_PMIC_RG_SMPS_TSTSEL_SHIFT},
  {PMIC_RG_RTC32K_TSTSEL, MT6350_PMIC_RG_RTC32K_TSTSEL_ADDR, MT6350_PMIC_RG_RTC32K_TSTSEL_MASK, MT6350_PMIC_RG_RTC32K_TSTSEL_SHIFT},
  {PMIC_RG_PMU75K_TSTSEL, MT6350_PMIC_RG_PMU75K_TSTSEL_ADDR, MT6350_PMIC_RG_PMU75K_TSTSEL_MASK, MT6350_PMIC_RG_PMU75K_TSTSEL_SHIFT},
  {PMIC_RG_AUD26M_TSTSEL, MT6350_PMIC_RG_AUD26M_TSTSEL_ADDR, MT6350_PMIC_RG_AUD26M_TSTSEL_MASK, MT6350_PMIC_RG_AUD26M_TSTSEL_SHIFT},
  {PMIC_RG_RTCDET_TSTSEL, MT6350_PMIC_RG_RTCDET_TSTSEL_ADDR, MT6350_PMIC_RG_RTCDET_TSTSEL_MASK, MT6350_PMIC_RG_RTCDET_TSTSEL_SHIFT},
  {PMIC_RG_PWMOC_TSTSEL, MT6350_PMIC_RG_PWMOC_TSTSEL_ADDR, MT6350_PMIC_RG_PWMOC_TSTSEL_MASK, MT6350_PMIC_RG_PWMOC_TSTSEL_SHIFT},
  {PMIC_RG_LDOSTB_TSTSEL, MT6350_PMIC_RG_LDOSTB_TSTSEL_ADDR, MT6350_PMIC_RG_LDOSTB_TSTSEL_MASK, MT6350_PMIC_RG_LDOSTB_TSTSEL_SHIFT},
  {PMIC_RG_ISINK_TSTSEL, MT6350_PMIC_RG_ISINK_TSTSEL_ADDR, MT6350_PMIC_RG_ISINK_TSTSEL_MASK, MT6350_PMIC_RG_ISINK_TSTSEL_SHIFT},
  {PMIC_RG_FQMTR_TSTSEL, MT6350_PMIC_RG_FQMTR_TSTSEL_ADDR, MT6350_PMIC_RG_FQMTR_TSTSEL_MASK, MT6350_PMIC_RG_FQMTR_TSTSEL_SHIFT},
  {PMIC_RG_CLASSD_TSTSEL, MT6350_PMIC_RG_CLASSD_TSTSEL_ADDR, MT6350_PMIC_RG_CLASSD_TSTSEL_MASK, MT6350_PMIC_RG_CLASSD_TSTSEL_SHIFT},
  {PMIC_RG_AUXADC_SDM_TSTSEL, MT6350_PMIC_RG_AUXADC_SDM_TSTSEL_ADDR, MT6350_PMIC_RG_AUXADC_SDM_TSTSEL_MASK, MT6350_PMIC_RG_AUXADC_SDM_TSTSEL_SHIFT},
  {PMIC_RG_AUD26M_DIV4_TSTSEL, MT6350_PMIC_RG_AUD26M_DIV4_TSTSEL_ADDR, MT6350_PMIC_RG_AUD26M_DIV4_TSTSEL_MASK, MT6350_PMIC_RG_AUD26M_DIV4_TSTSEL_SHIFT},
  {PMIC_RG_AUDIF_TSTSEL, MT6350_PMIC_RG_AUDIF_TSTSEL_ADDR, MT6350_PMIC_RG_AUDIF_TSTSEL_MASK, MT6350_PMIC_RG_AUDIF_TSTSEL_SHIFT},
  {PMIC_RG_BGR_TEST_CK_SEL, MT6350_PMIC_RG_BGR_TEST_CK_SEL_ADDR, MT6350_PMIC_RG_BGR_TEST_CK_SEL_MASK, MT6350_PMIC_RG_BGR_TEST_CK_SEL_SHIFT},
  {PMIC_RG_PCHR_TEST_CK_SEL, MT6350_PMIC_RG_PCHR_TEST_CK_SEL_ADDR, MT6350_PMIC_RG_PCHR_TEST_CK_SEL_MASK, MT6350_PMIC_RG_PCHR_TEST_CK_SEL_SHIFT},
  {PMIC_RG_STRUP_75K_26M_SEL, MT6350_PMIC_RG_STRUP_75K_26M_SEL_ADDR, MT6350_PMIC_RG_STRUP_75K_26M_SEL_MASK, MT6350_PMIC_RG_STRUP_75K_26M_SEL_SHIFT},
  {PMIC_RG_BGR_TESTMODE, MT6350_PMIC_RG_BGR_TESTMODE_ADDR, MT6350_PMIC_RG_BGR_TESTMODE_MASK, MT6350_PMIC_RG_BGR_TESTMODE_SHIFT},
  {PMIC_RG_TOP_CKTST2_RSV_15_8, MT6350_PMIC_RG_TOP_CKTST2_RSV_15_8_ADDR, MT6350_PMIC_RG_TOP_CKTST2_RSV_15_8_MASK, MT6350_PMIC_RG_TOP_CKTST2_RSV_15_8_SHIFT},
  {PMIC_TEST_OUT, MT6350_PMIC_TEST_OUT_ADDR, MT6350_PMIC_TEST_OUT_MASK, MT6350_PMIC_TEST_OUT_SHIFT},
  {PMIC_RG_MON_FLAG_SEL, MT6350_PMIC_RG_MON_FLAG_SEL_ADDR, MT6350_PMIC_RG_MON_FLAG_SEL_MASK, MT6350_PMIC_RG_MON_FLAG_SEL_SHIFT},
  {PMIC_RG_MON_GRP_SEL, MT6350_PMIC_RG_MON_GRP_SEL_ADDR, MT6350_PMIC_RG_MON_GRP_SEL_MASK, MT6350_PMIC_RG_MON_GRP_SEL_SHIFT},
  {PMIC_RG_TEST_DRIVER, MT6350_PMIC_RG_TEST_DRIVER_ADDR, MT6350_PMIC_RG_TEST_DRIVER_MASK, MT6350_PMIC_RG_TEST_DRIVER_SHIFT},
  {PMIC_RG_TEST_CLASSD, MT6350_PMIC_RG_TEST_CLASSD_ADDR, MT6350_PMIC_RG_TEST_CLASSD_MASK, MT6350_PMIC_RG_TEST_CLASSD_SHIFT},
  {PMIC_RG_TEST_AUD, MT6350_PMIC_RG_TEST_AUD_ADDR, MT6350_PMIC_RG_TEST_AUD_MASK, MT6350_PMIC_RG_TEST_AUD_SHIFT},
  {PMIC_RG_TEST_AUXADC, MT6350_PMIC_RG_TEST_AUXADC_ADDR, MT6350_PMIC_RG_TEST_AUXADC_MASK, MT6350_PMIC_RG_TEST_AUXADC_SHIFT},
  {PMIC_RG_NANDTREE_MODE, MT6350_PMIC_RG_NANDTREE_MODE_ADDR, MT6350_PMIC_RG_NANDTREE_MODE_MASK, MT6350_PMIC_RG_NANDTREE_MODE_SHIFT},
  {PMIC_RG_EFUSE_MODE, MT6350_PMIC_RG_EFUSE_MODE_ADDR, MT6350_PMIC_RG_EFUSE_MODE_MASK, MT6350_PMIC_RG_EFUSE_MODE_SHIFT},
  {PMIC_RG_TEST_STRUP, MT6350_PMIC_RG_TEST_STRUP_ADDR, MT6350_PMIC_RG_TEST_STRUP_MASK, MT6350_PMIC_RG_TEST_STRUP_SHIFT},
  {PMIC_RG_TEST_SPK, MT6350_PMIC_RG_TEST_SPK_ADDR, MT6350_PMIC_RG_TEST_SPK_MASK, MT6350_PMIC_RG_TEST_SPK_SHIFT},
  {PMIC_RG_TEST_SPK_PWM, MT6350_PMIC_RG_TEST_SPK_PWM_ADDR, MT6350_PMIC_RG_TEST_SPK_PWM_MASK, MT6350_PMIC_RG_TEST_SPK_PWM_SHIFT},
  {PMIC_EN_STATUS_VPROC, MT6350_PMIC_EN_STATUS_VPROC_ADDR, MT6350_PMIC_EN_STATUS_VPROC_MASK, MT6350_PMIC_EN_STATUS_VPROC_SHIFT},
  {PMIC_EN_STATUS_VSYS, MT6350_PMIC_EN_STATUS_VSYS_ADDR, MT6350_PMIC_EN_STATUS_VSYS_MASK, MT6350_PMIC_EN_STATUS_VSYS_SHIFT},
  {PMIC_EN_STATUS_VPA, MT6350_PMIC_EN_STATUS_VPA_ADDR, MT6350_PMIC_EN_STATUS_VPA_MASK, MT6350_PMIC_EN_STATUS_VPA_SHIFT},
  {PMIC_EN_STATUS_VRTC, MT6350_PMIC_EN_STATUS_VRTC_ADDR, MT6350_PMIC_EN_STATUS_VRTC_MASK, MT6350_PMIC_EN_STATUS_VRTC_SHIFT},
  {PMIC_EN_STATUS_VA, MT6350_PMIC_EN_STATUS_VA_ADDR, MT6350_PMIC_EN_STATUS_VA_MASK, MT6350_PMIC_EN_STATUS_VA_SHIFT},
  {PMIC_EN_STATUS_VCAMA, MT6350_PMIC_EN_STATUS_VCAMA_ADDR, MT6350_PMIC_EN_STATUS_VCAMA_MASK, MT6350_PMIC_EN_STATUS_VCAMA_SHIFT},
  {PMIC_EN_STATUS_VCAMD, MT6350_PMIC_EN_STATUS_VCAMD_ADDR, MT6350_PMIC_EN_STATUS_VCAMD_MASK, MT6350_PMIC_EN_STATUS_VCAMD_SHIFT},
  {PMIC_EN_STATUS_VCAM_AF, MT6350_PMIC_EN_STATUS_VCAM_AF_ADDR, MT6350_PMIC_EN_STATUS_VCAM_AF_MASK, MT6350_PMIC_EN_STATUS_VCAM_AF_SHIFT},
  {PMIC_EN_STATUS_VCAM_IO, MT6350_PMIC_EN_STATUS_VCAM_IO_ADDR, MT6350_PMIC_EN_STATUS_VCAM_IO_MASK, MT6350_PMIC_EN_STATUS_VCAM_IO_SHIFT},
  {PMIC_EN_STATUS_VCN28, MT6350_PMIC_EN_STATUS_VCN28_ADDR, MT6350_PMIC_EN_STATUS_VCN28_MASK, MT6350_PMIC_EN_STATUS_VCN28_SHIFT},
  {PMIC_EN_STATUS_VCN33, MT6350_PMIC_EN_STATUS_VCN33_ADDR, MT6350_PMIC_EN_STATUS_VCN33_MASK, MT6350_PMIC_EN_STATUS_VCN33_SHIFT},
  {PMIC_EN_STATUS_VCN_1V8, MT6350_PMIC_EN_STATUS_VCN_1V8_ADDR, MT6350_PMIC_EN_STATUS_VCN_1V8_MASK, MT6350_PMIC_EN_STATUS_VCN_1V8_SHIFT},
  {PMIC_EN_STATUS_VEMC_3V3, MT6350_PMIC_EN_STATUS_VEMC_3V3_ADDR, MT6350_PMIC_EN_STATUS_VEMC_3V3_MASK, MT6350_PMIC_EN_STATUS_VEMC_3V3_SHIFT},
  {PMIC_EN_STATUS_VGP1, MT6350_PMIC_EN_STATUS_VGP1_ADDR, MT6350_PMIC_EN_STATUS_VGP1_MASK, MT6350_PMIC_EN_STATUS_VGP1_SHIFT},
  {PMIC_EN_STATUS_VGP2, MT6350_PMIC_EN_STATUS_VGP2_ADDR, MT6350_PMIC_EN_STATUS_VGP2_MASK, MT6350_PMIC_EN_STATUS_VGP2_SHIFT},
  {PMIC_EN_STATUS_VGP3, MT6350_PMIC_EN_STATUS_VGP3_ADDR, MT6350_PMIC_EN_STATUS_VGP3_MASK, MT6350_PMIC_EN_STATUS_VGP3_SHIFT},
  {PMIC_EN_STATUS_VIBR, MT6350_PMIC_EN_STATUS_VIBR_ADDR, MT6350_PMIC_EN_STATUS_VIBR_MASK, MT6350_PMIC_EN_STATUS_VIBR_SHIFT},
  {PMIC_EN_STATUS_VIO18, MT6350_PMIC_EN_STATUS_VIO18_ADDR, MT6350_PMIC_EN_STATUS_VIO18_MASK, MT6350_PMIC_EN_STATUS_VIO18_SHIFT},
  {PMIC_EN_STATUS_VIO28, MT6350_PMIC_EN_STATUS_VIO28_ADDR, MT6350_PMIC_EN_STATUS_VIO28_MASK, MT6350_PMIC_EN_STATUS_VIO28_SHIFT},
  {PMIC_EN_STATUS_VM, MT6350_PMIC_EN_STATUS_VM_ADDR, MT6350_PMIC_EN_STATUS_VM_MASK, MT6350_PMIC_EN_STATUS_VM_SHIFT},
  {PMIC_EN_STATUS_VMC, MT6350_PMIC_EN_STATUS_VMC_ADDR, MT6350_PMIC_EN_STATUS_VMC_MASK, MT6350_PMIC_EN_STATUS_VMC_SHIFT},
  {PMIC_EN_STATUS_VMCH, MT6350_PMIC_EN_STATUS_VMCH_ADDR, MT6350_PMIC_EN_STATUS_VMCH_MASK, MT6350_PMIC_EN_STATUS_VMCH_SHIFT},
  {PMIC_EN_STATUS_VRF18, MT6350_PMIC_EN_STATUS_VRF18_ADDR, MT6350_PMIC_EN_STATUS_VRF18_MASK, MT6350_PMIC_EN_STATUS_VRF18_SHIFT},
  {PMIC_EN_STATUS_VSIM1, MT6350_PMIC_EN_STATUS_VSIM1_ADDR, MT6350_PMIC_EN_STATUS_VSIM1_MASK, MT6350_PMIC_EN_STATUS_VSIM1_SHIFT},
  {PMIC_EN_STATUS_VSIM2, MT6350_PMIC_EN_STATUS_VSIM2_ADDR, MT6350_PMIC_EN_STATUS_VSIM2_MASK, MT6350_PMIC_EN_STATUS_VSIM2_SHIFT},
  {PMIC_EN_STATUS_VTCXO, MT6350_PMIC_EN_STATUS_VTCXO_ADDR, MT6350_PMIC_EN_STATUS_VTCXO_MASK, MT6350_PMIC_EN_STATUS_VTCXO_SHIFT},
  {PMIC_EN_STATUS_VUSB, MT6350_PMIC_EN_STATUS_VUSB_ADDR, MT6350_PMIC_EN_STATUS_VUSB_MASK, MT6350_PMIC_EN_STATUS_VUSB_SHIFT},
  {PMIC_OC_STATUS_VPROC, MT6350_PMIC_OC_STATUS_VPROC_ADDR, MT6350_PMIC_OC_STATUS_VPROC_MASK, MT6350_PMIC_OC_STATUS_VPROC_SHIFT},
  {PMIC_OC_STATUS_VSYS, MT6350_PMIC_OC_STATUS_VSYS_ADDR, MT6350_PMIC_OC_STATUS_VSYS_MASK, MT6350_PMIC_OC_STATUS_VSYS_SHIFT},
  {PMIC_OC_STATUS_VPA, MT6350_PMIC_OC_STATUS_VPA_ADDR, MT6350_PMIC_OC_STATUS_VPA_MASK, MT6350_PMIC_OC_STATUS_VPA_SHIFT},
  {PMIC_OC_STATUS_VA, MT6350_PMIC_OC_STATUS_VA_ADDR, MT6350_PMIC_OC_STATUS_VA_MASK, MT6350_PMIC_OC_STATUS_VA_SHIFT},
  {PMIC_OC_STATUS_VCAMA, MT6350_PMIC_OC_STATUS_VCAMA_ADDR, MT6350_PMIC_OC_STATUS_VCAMA_MASK, MT6350_PMIC_OC_STATUS_VCAMA_SHIFT},
  {PMIC_OC_STATUS_VCAMD, MT6350_PMIC_OC_STATUS_VCAMD_ADDR, MT6350_PMIC_OC_STATUS_VCAMD_MASK, MT6350_PMIC_OC_STATUS_VCAMD_SHIFT},
  {PMIC_OC_STATUS_VCAM_AF, MT6350_PMIC_OC_STATUS_VCAM_AF_ADDR, MT6350_PMIC_OC_STATUS_VCAM_AF_MASK, MT6350_PMIC_OC_STATUS_VCAM_AF_SHIFT},
  {PMIC_OC_STATUS_VCAM_IO, MT6350_PMIC_OC_STATUS_VCAM_IO_ADDR, MT6350_PMIC_OC_STATUS_VCAM_IO_MASK, MT6350_PMIC_OC_STATUS_VCAM_IO_SHIFT},
  {PMIC_OC_STATUS_VCN28, MT6350_PMIC_OC_STATUS_VCN28_ADDR, MT6350_PMIC_OC_STATUS_VCN28_MASK, MT6350_PMIC_OC_STATUS_VCN28_SHIFT},
  {PMIC_OC_STATUS_VCN33, MT6350_PMIC_OC_STATUS_VCN33_ADDR, MT6350_PMIC_OC_STATUS_VCN33_MASK, MT6350_PMIC_OC_STATUS_VCN33_SHIFT},
  {PMIC_OC_STATUS_VCN_1V8, MT6350_PMIC_OC_STATUS_VCN_1V8_ADDR, MT6350_PMIC_OC_STATUS_VCN_1V8_MASK, MT6350_PMIC_OC_STATUS_VCN_1V8_SHIFT},
  {PMIC_OC_STATUS_VEMC_3V3, MT6350_PMIC_OC_STATUS_VEMC_3V3_ADDR, MT6350_PMIC_OC_STATUS_VEMC_3V3_MASK, MT6350_PMIC_OC_STATUS_VEMC_3V3_SHIFT},
  {PMIC_OC_STATUS_VGP1, MT6350_PMIC_OC_STATUS_VGP1_ADDR, MT6350_PMIC_OC_STATUS_VGP1_MASK, MT6350_PMIC_OC_STATUS_VGP1_SHIFT},
  {PMIC_OC_STATUS_VGP2, MT6350_PMIC_OC_STATUS_VGP2_ADDR, MT6350_PMIC_OC_STATUS_VGP2_MASK, MT6350_PMIC_OC_STATUS_VGP2_SHIFT},
  {PMIC_OC_STATUS_VGP3, MT6350_PMIC_OC_STATUS_VGP3_ADDR, MT6350_PMIC_OC_STATUS_VGP3_MASK, MT6350_PMIC_OC_STATUS_VGP3_SHIFT},
  {PMIC_OC_STATUS_VIBR, MT6350_PMIC_OC_STATUS_VIBR_ADDR, MT6350_PMIC_OC_STATUS_VIBR_MASK, MT6350_PMIC_OC_STATUS_VIBR_SHIFT},
  {PMIC_OC_STATUS_VIO18, MT6350_PMIC_OC_STATUS_VIO18_ADDR, MT6350_PMIC_OC_STATUS_VIO18_MASK, MT6350_PMIC_OC_STATUS_VIO18_SHIFT},
  {PMIC_OC_STATUS_VIO28, MT6350_PMIC_OC_STATUS_VIO28_ADDR, MT6350_PMIC_OC_STATUS_VIO28_MASK, MT6350_PMIC_OC_STATUS_VIO28_SHIFT},
  {PMIC_OC_STATUS_VM, MT6350_PMIC_OC_STATUS_VM_ADDR, MT6350_PMIC_OC_STATUS_VM_MASK, MT6350_PMIC_OC_STATUS_VM_SHIFT},
  {PMIC_OC_STATUS_VMC, MT6350_PMIC_OC_STATUS_VMC_ADDR, MT6350_PMIC_OC_STATUS_VMC_MASK, MT6350_PMIC_OC_STATUS_VMC_SHIFT},
  {PMIC_OC_STATUS_VMCH, MT6350_PMIC_OC_STATUS_VMCH_ADDR, MT6350_PMIC_OC_STATUS_VMCH_MASK, MT6350_PMIC_OC_STATUS_VMCH_SHIFT},
  {PMIC_OC_STATUS_VRF18, MT6350_PMIC_OC_STATUS_VRF18_ADDR, MT6350_PMIC_OC_STATUS_VRF18_MASK, MT6350_PMIC_OC_STATUS_VRF18_SHIFT},
  {PMIC_OC_STATUS_VSIM1, MT6350_PMIC_OC_STATUS_VSIM1_ADDR, MT6350_PMIC_OC_STATUS_VSIM1_MASK, MT6350_PMIC_OC_STATUS_VSIM1_SHIFT},
  {PMIC_OC_STATUS_VSIM2, MT6350_PMIC_OC_STATUS_VSIM2_ADDR, MT6350_PMIC_OC_STATUS_VSIM2_MASK, MT6350_PMIC_OC_STATUS_VSIM2_SHIFT},
  {PMIC_OC_STATUS_VTCXO, MT6350_PMIC_OC_STATUS_VTCXO_ADDR, MT6350_PMIC_OC_STATUS_VTCXO_MASK, MT6350_PMIC_OC_STATUS_VTCXO_SHIFT},
  {PMIC_OC_STATUS_VUSB, MT6350_PMIC_OC_STATUS_VUSB_ADDR, MT6350_PMIC_OC_STATUS_VUSB_MASK, MT6350_PMIC_OC_STATUS_VUSB_SHIFT},
  {PMIC_NI_SPK_OC_DET_D_L, MT6350_PMIC_NI_SPK_OC_DET_D_L_ADDR, MT6350_PMIC_NI_SPK_OC_DET_D_L_MASK, MT6350_PMIC_NI_SPK_OC_DET_D_L_SHIFT},
  {PMIC_NI_SPK_OC_DET_AB_L, MT6350_PMIC_NI_SPK_OC_DET_AB_L_ADDR, MT6350_PMIC_NI_SPK_OC_DET_AB_L_MASK, MT6350_PMIC_NI_SPK_OC_DET_AB_L_SHIFT},
  {PMIC_VPROC_PG_DEB, MT6350_PMIC_VPROC_PG_DEB_ADDR, MT6350_PMIC_VPROC_PG_DEB_MASK, MT6350_PMIC_VPROC_PG_DEB_SHIFT},
  {PMIC_VSYS_PG_DEB, MT6350_PMIC_VSYS_PG_DEB_ADDR, MT6350_PMIC_VSYS_PG_DEB_MASK, MT6350_PMIC_VSYS_PG_DEB_SHIFT},
  {PMIC_VM_PG_DEB, MT6350_PMIC_VM_PG_DEB_ADDR, MT6350_PMIC_VM_PG_DEB_MASK, MT6350_PMIC_VM_PG_DEB_SHIFT},
  {PMIC_VIO18_PG_DEB, MT6350_PMIC_VIO18_PG_DEB_ADDR, MT6350_PMIC_VIO18_PG_DEB_MASK, MT6350_PMIC_VIO18_PG_DEB_SHIFT},
  {PMIC_VTCXO_PG_DEB, MT6350_PMIC_VTCXO_PG_DEB_ADDR, MT6350_PMIC_VTCXO_PG_DEB_MASK, MT6350_PMIC_VTCXO_PG_DEB_SHIFT},
  {PMIC_VA_PG_DEB, MT6350_PMIC_VA_PG_DEB_ADDR, MT6350_PMIC_VA_PG_DEB_MASK, MT6350_PMIC_VA_PG_DEB_SHIFT},
  {PMIC_VIO28_PG_DEB, MT6350_PMIC_VIO28_PG_DEB_ADDR, MT6350_PMIC_VIO28_PG_DEB_MASK, MT6350_PMIC_VIO28_PG_DEB_SHIFT},
  {PMIC_VGP2_PG_DEB, MT6350_PMIC_VGP2_PG_DEB_ADDR, MT6350_PMIC_VGP2_PG_DEB_MASK, MT6350_PMIC_VGP2_PG_DEB_SHIFT},
  {PMIC_PMU_TEST_MODE_SCAN, MT6350_PMIC_PMU_TEST_MODE_SCAN_ADDR, MT6350_PMIC_PMU_TEST_MODE_SCAN_MASK, MT6350_PMIC_PMU_TEST_MODE_SCAN_SHIFT},
  {PMIC_PWRKEY_DEB, MT6350_PMIC_PWRKEY_DEB_ADDR, MT6350_PMIC_PWRKEY_DEB_MASK, MT6350_PMIC_PWRKEY_DEB_SHIFT},
  {PMIC_FCHRKEY_DEB, MT6350_PMIC_FCHRKEY_DEB_ADDR, MT6350_PMIC_FCHRKEY_DEB_MASK, MT6350_PMIC_FCHRKEY_DEB_SHIFT},
  {PMIC_VBAT_OV, MT6350_PMIC_VBAT_OV_ADDR, MT6350_PMIC_VBAT_OV_MASK, MT6350_PMIC_VBAT_OV_SHIFT},
  {PMIC_PCHR_CHRDET, MT6350_PMIC_PCHR_CHRDET_ADDR, MT6350_PMIC_PCHR_CHRDET_MASK, MT6350_PMIC_PCHR_CHRDET_SHIFT},
  {PMIC_RO_BATON_UNDET, MT6350_PMIC_RO_BATON_UNDET_ADDR, MT6350_PMIC_RO_BATON_UNDET_MASK, MT6350_PMIC_RO_BATON_UNDET_SHIFT},
  {PMIC_RTC_XTAL_DET_DONE, MT6350_PMIC_RTC_XTAL_DET_DONE_ADDR, MT6350_PMIC_RTC_XTAL_DET_DONE_MASK, MT6350_PMIC_RTC_XTAL_DET_DONE_SHIFT},
  {PMIC_XOSC32_ENB_DET, MT6350_PMIC_XOSC32_ENB_DET_ADDR, MT6350_PMIC_XOSC32_ENB_DET_MASK, MT6350_PMIC_XOSC32_ENB_DET_SHIFT},
  {PMIC_RTC_XTAL_DET_RSV, MT6350_PMIC_RTC_XTAL_DET_RSV_ADDR, MT6350_PMIC_RTC_XTAL_DET_RSV_MASK, MT6350_PMIC_RTC_XTAL_DET_RSV_SHIFT},
  {PMIC_RG_SIMAP_TDSEL, MT6350_PMIC_RG_SIMAP_TDSEL_ADDR, MT6350_PMIC_RG_SIMAP_TDSEL_MASK, MT6350_PMIC_RG_SIMAP_TDSEL_SHIFT},
  {PMIC_RG_AUD_TDSEL, MT6350_PMIC_RG_AUD_TDSEL_ADDR, MT6350_PMIC_RG_AUD_TDSEL_MASK, MT6350_PMIC_RG_AUD_TDSEL_SHIFT},
  {PMIC_RG_SPI_TDSEL, MT6350_PMIC_RG_SPI_TDSEL_ADDR, MT6350_PMIC_RG_SPI_TDSEL_MASK, MT6350_PMIC_RG_SPI_TDSEL_SHIFT},
  {PMIC_RG_PMU_TDSEL, MT6350_PMIC_RG_PMU_TDSEL_ADDR, MT6350_PMIC_RG_PMU_TDSEL_MASK, MT6350_PMIC_RG_PMU_TDSEL_SHIFT},
  {PMIC_RG_SIMLS_TDSEL, MT6350_PMIC_RG_SIMLS_TDSEL_ADDR, MT6350_PMIC_RG_SIMLS_TDSEL_MASK, MT6350_PMIC_RG_SIMLS_TDSEL_SHIFT},
  {PMIC_RG_SIMAP_RDSEL, MT6350_PMIC_RG_SIMAP_RDSEL_ADDR, MT6350_PMIC_RG_SIMAP_RDSEL_MASK, MT6350_PMIC_RG_SIMAP_RDSEL_SHIFT},
  {PMIC_RG_AUD_RDSEL, MT6350_PMIC_RG_AUD_RDSEL_ADDR, MT6350_PMIC_RG_AUD_RDSEL_MASK, MT6350_PMIC_RG_AUD_RDSEL_SHIFT},
  {PMIC_RG_SPI_RDSEL, MT6350_PMIC_RG_SPI_RDSEL_ADDR, MT6350_PMIC_RG_SPI_RDSEL_MASK, MT6350_PMIC_RG_SPI_RDSEL_SHIFT},
  {PMIC_RG_PMU_RDSEL, MT6350_PMIC_RG_PMU_RDSEL_ADDR, MT6350_PMIC_RG_PMU_RDSEL_MASK, MT6350_PMIC_RG_PMU_RDSEL_SHIFT},
  {PMIC_RG_SIMLS_RDSEL, MT6350_PMIC_RG_SIMLS_RDSEL_ADDR, MT6350_PMIC_RG_SIMLS_RDSEL_MASK, MT6350_PMIC_RG_SIMLS_RDSEL_SHIFT},
  {PMIC_RG_SMT_SYSRSTB, MT6350_PMIC_RG_SMT_SYSRSTB_ADDR, MT6350_PMIC_RG_SMT_SYSRSTB_MASK, MT6350_PMIC_RG_SMT_SYSRSTB_SHIFT},
  {PMIC_RG_SMT_INT, MT6350_PMIC_RG_SMT_INT_ADDR, MT6350_PMIC_RG_SMT_INT_MASK, MT6350_PMIC_RG_SMT_INT_SHIFT},
  {PMIC_RG_SMT_SRCLKEN, MT6350_PMIC_RG_SMT_SRCLKEN_ADDR, MT6350_PMIC_RG_SMT_SRCLKEN_MASK, MT6350_PMIC_RG_SMT_SRCLKEN_SHIFT},
  {PMIC_RG_SMT_RTC_32K1V8, MT6350_PMIC_RG_SMT_RTC_32K1V8_ADDR, MT6350_PMIC_RG_SMT_RTC_32K1V8_MASK, MT6350_PMIC_RG_SMT_RTC_32K1V8_SHIFT},
  {PMIC_RG_SMT_SPI_CLK, MT6350_PMIC_RG_SMT_SPI_CLK_ADDR, MT6350_PMIC_RG_SMT_SPI_CLK_MASK, MT6350_PMIC_RG_SMT_SPI_CLK_SHIFT},
  {PMIC_RG_SMT_SPI_CSN, MT6350_PMIC_RG_SMT_SPI_CSN_ADDR, MT6350_PMIC_RG_SMT_SPI_CSN_MASK, MT6350_PMIC_RG_SMT_SPI_CSN_SHIFT},
  {PMIC_RG_SMT_SPI_MOSI, MT6350_PMIC_RG_SMT_SPI_MOSI_ADDR, MT6350_PMIC_RG_SMT_SPI_MOSI_MASK, MT6350_PMIC_RG_SMT_SPI_MOSI_SHIFT},
  {PMIC_RG_SMT_SPI_MISO, MT6350_PMIC_RG_SMT_SPI_MISO_ADDR, MT6350_PMIC_RG_SMT_SPI_MISO_MASK, MT6350_PMIC_RG_SMT_SPI_MISO_SHIFT},
  {PMIC_RG_SMT_AUD_CLK, MT6350_PMIC_RG_SMT_AUD_CLK_ADDR, MT6350_PMIC_RG_SMT_AUD_CLK_MASK, MT6350_PMIC_RG_SMT_AUD_CLK_SHIFT},
  {PMIC_RG_SMT_AUD_MOSI, MT6350_PMIC_RG_SMT_AUD_MOSI_ADDR, MT6350_PMIC_RG_SMT_AUD_MOSI_MASK, MT6350_PMIC_RG_SMT_AUD_MOSI_SHIFT},
  {PMIC_RG_SMT_AUD_MISO, MT6350_PMIC_RG_SMT_AUD_MISO_ADDR, MT6350_PMIC_RG_SMT_AUD_MISO_MASK, MT6350_PMIC_RG_SMT_AUD_MISO_SHIFT},
  {PMIC_RG_SMT_SIM1_AP_SCLK, MT6350_PMIC_RG_SMT_SIM1_AP_SCLK_ADDR, MT6350_PMIC_RG_SMT_SIM1_AP_SCLK_MASK, MT6350_PMIC_RG_SMT_SIM1_AP_SCLK_SHIFT},
  {PMIC_RG_SMT_SIM1_AP_SRST, MT6350_PMIC_RG_SMT_SIM1_AP_SRST_ADDR, MT6350_PMIC_RG_SMT_SIM1_AP_SRST_MASK, MT6350_PMIC_RG_SMT_SIM1_AP_SRST_SHIFT},
  {PMIC_RG_SMT_SIMLS1_SCLK, MT6350_PMIC_RG_SMT_SIMLS1_SCLK_ADDR, MT6350_PMIC_RG_SMT_SIMLS1_SCLK_MASK, MT6350_PMIC_RG_SMT_SIMLS1_SCLK_SHIFT},
  {PMIC_RG_SMT_SIMLS1_SRST, MT6350_PMIC_RG_SMT_SIMLS1_SRST_ADDR, MT6350_PMIC_RG_SMT_SIMLS1_SRST_MASK, MT6350_PMIC_RG_SMT_SIMLS1_SRST_SHIFT},
  {PMIC_RG_SMT_SIM2_AP_SCLK, MT6350_PMIC_RG_SMT_SIM2_AP_SCLK_ADDR, MT6350_PMIC_RG_SMT_SIM2_AP_SCLK_MASK, MT6350_PMIC_RG_SMT_SIM2_AP_SCLK_SHIFT},
  {PMIC_RG_SMT_SIM2_AP_SRST, MT6350_PMIC_RG_SMT_SIM2_AP_SRST_ADDR, MT6350_PMIC_RG_SMT_SIM2_AP_SRST_MASK, MT6350_PMIC_RG_SMT_SIM2_AP_SRST_SHIFT},
  {PMIC_RG_SMT_SIMLS2_SCLK, MT6350_PMIC_RG_SMT_SIMLS2_SCLK_ADDR, MT6350_PMIC_RG_SMT_SIMLS2_SCLK_MASK, MT6350_PMIC_RG_SMT_SIMLS2_SCLK_SHIFT},
  {PMIC_RG_SMT_SIMLS2_SRST, MT6350_PMIC_RG_SMT_SIMLS2_SRST_ADDR, MT6350_PMIC_RG_SMT_SIMLS2_SRST_MASK, MT6350_PMIC_RG_SMT_SIMLS2_SRST_SHIFT},
  {PMIC_RG_OCTL_INT, MT6350_PMIC_RG_OCTL_INT_ADDR, MT6350_PMIC_RG_OCTL_INT_MASK, MT6350_PMIC_RG_OCTL_INT_SHIFT},
  {PMIC_RG_OCTL_SRCLKEN, MT6350_PMIC_RG_OCTL_SRCLKEN_ADDR, MT6350_PMIC_RG_OCTL_SRCLKEN_MASK, MT6350_PMIC_RG_OCTL_SRCLKEN_SHIFT},
  {PMIC_RG_OCTL_RTC_32K1V8, MT6350_PMIC_RG_OCTL_RTC_32K1V8_ADDR, MT6350_PMIC_RG_OCTL_RTC_32K1V8_MASK, MT6350_PMIC_RG_OCTL_RTC_32K1V8_SHIFT},
  {PMIC_RG_OCTL_SPI_CLK, MT6350_PMIC_RG_OCTL_SPI_CLK_ADDR, MT6350_PMIC_RG_OCTL_SPI_CLK_MASK, MT6350_PMIC_RG_OCTL_SPI_CLK_SHIFT},
  {PMIC_RG_OCTL_SPI_CSN, MT6350_PMIC_RG_OCTL_SPI_CSN_ADDR, MT6350_PMIC_RG_OCTL_SPI_CSN_MASK, MT6350_PMIC_RG_OCTL_SPI_CSN_SHIFT},
  {PMIC_RG_OCTL_SPI_MOSI, MT6350_PMIC_RG_OCTL_SPI_MOSI_ADDR, MT6350_PMIC_RG_OCTL_SPI_MOSI_MASK, MT6350_PMIC_RG_OCTL_SPI_MOSI_SHIFT},
  {PMIC_RG_OCTL_SPI_MISO, MT6350_PMIC_RG_OCTL_SPI_MISO_ADDR, MT6350_PMIC_RG_OCTL_SPI_MISO_MASK, MT6350_PMIC_RG_OCTL_SPI_MISO_SHIFT},
  {PMIC_RG_OCTL_AUD_CLK, MT6350_PMIC_RG_OCTL_AUD_CLK_ADDR, MT6350_PMIC_RG_OCTL_AUD_CLK_MASK, MT6350_PMIC_RG_OCTL_AUD_CLK_SHIFT},
  {PMIC_RG_OCTL_AUD_MOSI, MT6350_PMIC_RG_OCTL_AUD_MOSI_ADDR, MT6350_PMIC_RG_OCTL_AUD_MOSI_MASK, MT6350_PMIC_RG_OCTL_AUD_MOSI_SHIFT},
  {PMIC_RG_OCTL_AUD_MISO, MT6350_PMIC_RG_OCTL_AUD_MISO_ADDR, MT6350_PMIC_RG_OCTL_AUD_MISO_MASK, MT6350_PMIC_RG_OCTL_AUD_MISO_SHIFT},
  {PMIC_RG_OCTL_SIM1_AP_SCLK, MT6350_PMIC_RG_OCTL_SIM1_AP_SCLK_ADDR, MT6350_PMIC_RG_OCTL_SIM1_AP_SCLK_MASK, MT6350_PMIC_RG_OCTL_SIM1_AP_SCLK_SHIFT},
  {PMIC_RG_OCTL_SIM1_AP_SRST, MT6350_PMIC_RG_OCTL_SIM1_AP_SRST_ADDR, MT6350_PMIC_RG_OCTL_SIM1_AP_SRST_MASK, MT6350_PMIC_RG_OCTL_SIM1_AP_SRST_SHIFT},
  {PMIC_RG_OCTL_SIMLS1_SCLK, MT6350_PMIC_RG_OCTL_SIMLS1_SCLK_ADDR, MT6350_PMIC_RG_OCTL_SIMLS1_SCLK_MASK, MT6350_PMIC_RG_OCTL_SIMLS1_SCLK_SHIFT},
  {PMIC_RG_OCTL_SIMLS1_SRST, MT6350_PMIC_RG_OCTL_SIMLS1_SRST_ADDR, MT6350_PMIC_RG_OCTL_SIMLS1_SRST_MASK, MT6350_PMIC_RG_OCTL_SIMLS1_SRST_SHIFT},
  {PMIC_RG_OCTL_SIM2_AP_SCLK, MT6350_PMIC_RG_OCTL_SIM2_AP_SCLK_ADDR, MT6350_PMIC_RG_OCTL_SIM2_AP_SCLK_MASK, MT6350_PMIC_RG_OCTL_SIM2_AP_SCLK_SHIFT},
  {PMIC_RG_OCTL_SIM2_AP_SRST, MT6350_PMIC_RG_OCTL_SIM2_AP_SRST_ADDR, MT6350_PMIC_RG_OCTL_SIM2_AP_SRST_MASK, MT6350_PMIC_RG_OCTL_SIM2_AP_SRST_SHIFT},
  {PMIC_RG_OCTL_SIMLS2_SCLK, MT6350_PMIC_RG_OCTL_SIMLS2_SCLK_ADDR, MT6350_PMIC_RG_OCTL_SIMLS2_SCLK_MASK, MT6350_PMIC_RG_OCTL_SIMLS2_SCLK_SHIFT},
  {PMIC_RG_OCTL_SIMLS2_SRST, MT6350_PMIC_RG_OCTL_SIMLS2_SRST_ADDR, MT6350_PMIC_RG_OCTL_SIMLS2_SRST_MASK, MT6350_PMIC_RG_OCTL_SIMLS2_SRST_SHIFT},
  {PMIC_RG_SIMLS1_SCLK_CONF, MT6350_PMIC_RG_SIMLS1_SCLK_CONF_ADDR, MT6350_PMIC_RG_SIMLS1_SCLK_CONF_MASK, MT6350_PMIC_RG_SIMLS1_SCLK_CONF_SHIFT},
  {PMIC_RG_SIMLS1_SRST_CONF, MT6350_PMIC_RG_SIMLS1_SRST_CONF_ADDR, MT6350_PMIC_RG_SIMLS1_SRST_CONF_MASK, MT6350_PMIC_RG_SIMLS1_SRST_CONF_SHIFT},
  {PMIC_RG_SIMLS2_SCLK_CONF, MT6350_PMIC_RG_SIMLS2_SCLK_CONF_ADDR, MT6350_PMIC_RG_SIMLS2_SCLK_CONF_MASK, MT6350_PMIC_RG_SIMLS2_SCLK_CONF_SHIFT},
  {PMIC_RG_SIMLS2_SRST_CONF, MT6350_PMIC_RG_SIMLS2_SRST_CONF_ADDR, MT6350_PMIC_RG_SIMLS2_SRST_CONF_MASK, MT6350_PMIC_RG_SIMLS2_SRST_CONF_SHIFT},
  {PMIC_RG_INT_EN_SPKL_AB, MT6350_PMIC_RG_INT_EN_SPKL_AB_ADDR, MT6350_PMIC_RG_INT_EN_SPKL_AB_MASK, MT6350_PMIC_RG_INT_EN_SPKL_AB_SHIFT},
  {PMIC_RG_INT_EN_SPKL, MT6350_PMIC_RG_INT_EN_SPKL_ADDR, MT6350_PMIC_RG_INT_EN_SPKL_MASK, MT6350_PMIC_RG_INT_EN_SPKL_SHIFT},
  {PMIC_RG_INT_EN_BAT_L, MT6350_PMIC_RG_INT_EN_BAT_L_ADDR, MT6350_PMIC_RG_INT_EN_BAT_L_MASK, MT6350_PMIC_RG_INT_EN_BAT_L_SHIFT},
  {PMIC_RG_INT_EN_BAT_H, MT6350_PMIC_RG_INT_EN_BAT_H_ADDR, MT6350_PMIC_RG_INT_EN_BAT_H_MASK, MT6350_PMIC_RG_INT_EN_BAT_H_SHIFT},
  {PMIC_RG_INT_EN_WATCHDOG, MT6350_PMIC_RG_INT_EN_WATCHDOG_ADDR, MT6350_PMIC_RG_INT_EN_WATCHDOG_MASK, MT6350_PMIC_RG_INT_EN_WATCHDOG_SHIFT},
  {PMIC_RG_INT_EN_PWRKEY, MT6350_PMIC_RG_INT_EN_PWRKEY_ADDR, MT6350_PMIC_RG_INT_EN_PWRKEY_MASK, MT6350_PMIC_RG_INT_EN_PWRKEY_SHIFT},
  {PMIC_RG_INT_EN_THR_L, MT6350_PMIC_RG_INT_EN_THR_L_ADDR, MT6350_PMIC_RG_INT_EN_THR_L_MASK, MT6350_PMIC_RG_INT_EN_THR_L_SHIFT},
  {PMIC_RG_INT_EN_THR_H, MT6350_PMIC_RG_INT_EN_THR_H_ADDR, MT6350_PMIC_RG_INT_EN_THR_H_MASK, MT6350_PMIC_RG_INT_EN_THR_H_SHIFT},
  {PMIC_RG_INT_EN_VBATON_UNDET, MT6350_PMIC_RG_INT_EN_VBATON_UNDET_ADDR, MT6350_PMIC_RG_INT_EN_VBATON_UNDET_MASK, MT6350_PMIC_RG_INT_EN_VBATON_UNDET_SHIFT},
  {PMIC_RG_INT_EN_BVALID_DET, MT6350_PMIC_RG_INT_EN_BVALID_DET_ADDR, MT6350_PMIC_RG_INT_EN_BVALID_DET_MASK, MT6350_PMIC_RG_INT_EN_BVALID_DET_SHIFT},
  {PMIC_RG_INT_EN_CHRDET, MT6350_PMIC_RG_INT_EN_CHRDET_ADDR, MT6350_PMIC_RG_INT_EN_CHRDET_MASK, MT6350_PMIC_RG_INT_EN_CHRDET_SHIFT},
  {PMIC_RG_INT_EN_OV, MT6350_PMIC_RG_INT_EN_OV_ADDR, MT6350_PMIC_RG_INT_EN_OV_MASK, MT6350_PMIC_RG_INT_EN_OV_SHIFT},
  {PMIC_INT_CON0_SET, MT6350_PMIC_INT_CON0_SET_ADDR, MT6350_PMIC_INT_CON0_SET_MASK, MT6350_PMIC_INT_CON0_SET_SHIFT},
  {PMIC_INT_CON0_CLR, MT6350_PMIC_INT_CON0_CLR_ADDR, MT6350_PMIC_INT_CON0_CLR_MASK, MT6350_PMIC_INT_CON0_CLR_SHIFT},
  {PMIC_RG_INT_EN_LDO, MT6350_PMIC_RG_INT_EN_LDO_ADDR, MT6350_PMIC_RG_INT_EN_LDO_MASK, MT6350_PMIC_RG_INT_EN_LDO_SHIFT},
  {PMIC_RG_INT_EN_FCHRKEY, MT6350_PMIC_RG_INT_EN_FCHRKEY_ADDR, MT6350_PMIC_RG_INT_EN_FCHRKEY_MASK, MT6350_PMIC_RG_INT_EN_FCHRKEY_SHIFT},
  {PMIC_RG_INT_EN_ACCDET, MT6350_PMIC_RG_INT_EN_ACCDET_ADDR, MT6350_PMIC_RG_INT_EN_ACCDET_MASK, MT6350_PMIC_RG_INT_EN_ACCDET_SHIFT},
  {PMIC_RG_INT_EN_AUDIO, MT6350_PMIC_RG_INT_EN_AUDIO_ADDR, MT6350_PMIC_RG_INT_EN_AUDIO_MASK, MT6350_PMIC_RG_INT_EN_AUDIO_SHIFT},
  {PMIC_RG_INT_EN_RTC, MT6350_PMIC_RG_INT_EN_RTC_ADDR, MT6350_PMIC_RG_INT_EN_RTC_MASK, MT6350_PMIC_RG_INT_EN_RTC_SHIFT},
  {PMIC_RG_INT_EN_VPROC, MT6350_PMIC_RG_INT_EN_VPROC_ADDR, MT6350_PMIC_RG_INT_EN_VPROC_MASK, MT6350_PMIC_RG_INT_EN_VPROC_SHIFT},
  {PMIC_RG_INT_EN_VSYS, MT6350_PMIC_RG_INT_EN_VSYS_ADDR, MT6350_PMIC_RG_INT_EN_VSYS_MASK, MT6350_PMIC_RG_INT_EN_VSYS_SHIFT},
  {PMIC_RG_INT_EN_VPA, MT6350_PMIC_RG_INT_EN_VPA_ADDR, MT6350_PMIC_RG_INT_EN_VPA_MASK, MT6350_PMIC_RG_INT_EN_VPA_SHIFT},
  {PMIC_INT_CON1_SET, MT6350_PMIC_INT_CON1_SET_ADDR, MT6350_PMIC_INT_CON1_SET_MASK, MT6350_PMIC_INT_CON1_SET_SHIFT},
  {PMIC_INT_CON1_CLR, MT6350_PMIC_INT_CON1_CLR_ADDR, MT6350_PMIC_INT_CON1_CLR_MASK, MT6350_PMIC_INT_CON1_CLR_SHIFT},
  {PMIC_POLARITY, MT6350_PMIC_POLARITY_ADDR, MT6350_PMIC_POLARITY_MASK, MT6350_PMIC_POLARITY_SHIFT},
  {PMIC_POLARITY_VBATON_UNDET, MT6350_PMIC_POLARITY_VBATON_UNDET_ADDR, MT6350_PMIC_POLARITY_VBATON_UNDET_MASK, MT6350_PMIC_POLARITY_VBATON_UNDET_SHIFT},
  {PMIC_POLARITY_BVALID_DET, MT6350_PMIC_POLARITY_BVALID_DET_ADDR, MT6350_PMIC_POLARITY_BVALID_DET_MASK, MT6350_PMIC_POLARITY_BVALID_DET_SHIFT},
  {PMIC_RG_FCHRKEY_INT_SEL, MT6350_PMIC_RG_FCHRKEY_INT_SEL_ADDR, MT6350_PMIC_RG_FCHRKEY_INT_SEL_MASK, MT6350_PMIC_RG_FCHRKEY_INT_SEL_SHIFT},
  {PMIC_RG_PWRKEY_INT_SEL, MT6350_PMIC_RG_PWRKEY_INT_SEL_ADDR, MT6350_PMIC_RG_PWRKEY_INT_SEL_MASK, MT6350_PMIC_RG_PWRKEY_INT_SEL_SHIFT},
  {PMIC_IVGEN_EXT_EN, MT6350_PMIC_IVGEN_EXT_EN_ADDR, MT6350_PMIC_IVGEN_EXT_EN_MASK, MT6350_PMIC_IVGEN_EXT_EN_SHIFT},
  {PMIC_INT_MISC_CON_SET, MT6350_PMIC_INT_MISC_CON_SET_ADDR, MT6350_PMIC_INT_MISC_CON_SET_MASK, MT6350_PMIC_INT_MISC_CON_SET_SHIFT},
  {PMIC_INT_MISC_CON_CLR, MT6350_PMIC_INT_MISC_CON_CLR_ADDR, MT6350_PMIC_INT_MISC_CON_CLR_MASK, MT6350_PMIC_INT_MISC_CON_CLR_SHIFT},
  {PMIC_RG_INT_STATUS_SPKL_AB, MT6350_PMIC_RG_INT_STATUS_SPKL_AB_ADDR, MT6350_PMIC_RG_INT_STATUS_SPKL_AB_MASK, MT6350_PMIC_RG_INT_STATUS_SPKL_AB_SHIFT},
  {PMIC_RG_INT_STATUS_SPKL, MT6350_PMIC_RG_INT_STATUS_SPKL_ADDR, MT6350_PMIC_RG_INT_STATUS_SPKL_MASK, MT6350_PMIC_RG_INT_STATUS_SPKL_SHIFT},
  {PMIC_RG_INT_STATUS_BAT_L, MT6350_PMIC_RG_INT_STATUS_BAT_L_ADDR, MT6350_PMIC_RG_INT_STATUS_BAT_L_MASK, MT6350_PMIC_RG_INT_STATUS_BAT_L_SHIFT},
  {PMIC_RG_INT_STATUS_BAT_H, MT6350_PMIC_RG_INT_STATUS_BAT_H_ADDR, MT6350_PMIC_RG_INT_STATUS_BAT_H_MASK, MT6350_PMIC_RG_INT_STATUS_BAT_H_SHIFT},
  {PMIC_RG_INT_STATUS_WATCHDOG, MT6350_PMIC_RG_INT_STATUS_WATCHDOG_ADDR, MT6350_PMIC_RG_INT_STATUS_WATCHDOG_MASK, MT6350_PMIC_RG_INT_STATUS_WATCHDOG_SHIFT},
  {PMIC_RG_INT_STATUS_PWRKEY, MT6350_PMIC_RG_INT_STATUS_PWRKEY_ADDR, MT6350_PMIC_RG_INT_STATUS_PWRKEY_MASK, MT6350_PMIC_RG_INT_STATUS_PWRKEY_SHIFT},
  {PMIC_RG_INT_STATUS_THR_L, MT6350_PMIC_RG_INT_STATUS_THR_L_ADDR, MT6350_PMIC_RG_INT_STATUS_THR_L_MASK, MT6350_PMIC_RG_INT_STATUS_THR_L_SHIFT},
  {PMIC_RG_INT_STATUS_THR_H, MT6350_PMIC_RG_INT_STATUS_THR_H_ADDR, MT6350_PMIC_RG_INT_STATUS_THR_H_MASK, MT6350_PMIC_RG_INT_STATUS_THR_H_SHIFT},
  {PMIC_RG_INT_STATUS_VBATON_UNDET, MT6350_PMIC_RG_INT_STATUS_VBATON_UNDET_ADDR, MT6350_PMIC_RG_INT_STATUS_VBATON_UNDET_MASK, MT6350_PMIC_RG_INT_STATUS_VBATON_UNDET_SHIFT},
  {PMIC_RG_INT_STATUS_BVALID_DET, MT6350_PMIC_RG_INT_STATUS_BVALID_DET_ADDR, MT6350_PMIC_RG_INT_STATUS_BVALID_DET_MASK, MT6350_PMIC_RG_INT_STATUS_BVALID_DET_SHIFT},
  {PMIC_RG_INT_STATUS_CHRDET, MT6350_PMIC_RG_INT_STATUS_CHRDET_ADDR, MT6350_PMIC_RG_INT_STATUS_CHRDET_MASK, MT6350_PMIC_RG_INT_STATUS_CHRDET_SHIFT},
  {PMIC_RG_INT_STATUS_OV, MT6350_PMIC_RG_INT_STATUS_OV_ADDR, MT6350_PMIC_RG_INT_STATUS_OV_MASK, MT6350_PMIC_RG_INT_STATUS_OV_SHIFT},
  {PMIC_RG_INT_STATUS_LDO, MT6350_PMIC_RG_INT_STATUS_LDO_ADDR, MT6350_PMIC_RG_INT_STATUS_LDO_MASK, MT6350_PMIC_RG_INT_STATUS_LDO_SHIFT},
  {PMIC_RG_INT_STATUS_FCHRKEY, MT6350_PMIC_RG_INT_STATUS_FCHRKEY_ADDR, MT6350_PMIC_RG_INT_STATUS_FCHRKEY_MASK, MT6350_PMIC_RG_INT_STATUS_FCHRKEY_SHIFT},
  {PMIC_RG_INT_STATUS_ACCDET, MT6350_PMIC_RG_INT_STATUS_ACCDET_ADDR, MT6350_PMIC_RG_INT_STATUS_ACCDET_MASK, MT6350_PMIC_RG_INT_STATUS_ACCDET_SHIFT},
  {PMIC_RG_INT_STATUS_AUDIO, MT6350_PMIC_RG_INT_STATUS_AUDIO_ADDR, MT6350_PMIC_RG_INT_STATUS_AUDIO_MASK, MT6350_PMIC_RG_INT_STATUS_AUDIO_SHIFT},
  {PMIC_RG_INT_STATUS_RTC, MT6350_PMIC_RG_INT_STATUS_RTC_ADDR, MT6350_PMIC_RG_INT_STATUS_RTC_MASK, MT6350_PMIC_RG_INT_STATUS_RTC_SHIFT},
  {PMIC_RG_INT_STATUS_VPROC, MT6350_PMIC_RG_INT_STATUS_VPROC_ADDR, MT6350_PMIC_RG_INT_STATUS_VPROC_MASK, MT6350_PMIC_RG_INT_STATUS_VPROC_SHIFT},
  {PMIC_RG_INT_STATUS_VSYS, MT6350_PMIC_RG_INT_STATUS_VSYS_ADDR, MT6350_PMIC_RG_INT_STATUS_VSYS_MASK, MT6350_PMIC_RG_INT_STATUS_VSYS_SHIFT},
  {PMIC_RG_INT_STATUS_VPA, MT6350_PMIC_RG_INT_STATUS_VPA_ADDR, MT6350_PMIC_RG_INT_STATUS_VPA_MASK, MT6350_PMIC_RG_INT_STATUS_VPA_SHIFT},
  {PMIC_OC_GEAR_BVALID_DET, MT6350_PMIC_OC_GEAR_BVALID_DET_ADDR, MT6350_PMIC_OC_GEAR_BVALID_DET_MASK, MT6350_PMIC_OC_GEAR_BVALID_DET_SHIFT},
  {PMIC_OC_GEAR_VBATON_UNDET, MT6350_PMIC_OC_GEAR_VBATON_UNDET_ADDR, MT6350_PMIC_OC_GEAR_VBATON_UNDET_MASK, MT6350_PMIC_OC_GEAR_VBATON_UNDET_SHIFT},
  {PMIC_OC_GEAR_LDO, MT6350_PMIC_OC_GEAR_LDO_ADDR, MT6350_PMIC_OC_GEAR_LDO_MASK, MT6350_PMIC_OC_GEAR_LDO_SHIFT},
  {PMIC_VPROC_OC_THD, MT6350_PMIC_VPROC_OC_THD_ADDR, MT6350_PMIC_VPROC_OC_THD_MASK, MT6350_PMIC_VPROC_OC_THD_SHIFT},
  {PMIC_VPROC_OC_WND, MT6350_PMIC_VPROC_OC_WND_ADDR, MT6350_PMIC_VPROC_OC_WND_MASK, MT6350_PMIC_VPROC_OC_WND_SHIFT},
  {PMIC_VPROC_DEG_EN, MT6350_PMIC_VPROC_DEG_EN_ADDR, MT6350_PMIC_VPROC_DEG_EN_MASK, MT6350_PMIC_VPROC_DEG_EN_SHIFT},
  {PMIC_VSYS_OC_THD, MT6350_PMIC_VSYS_OC_THD_ADDR, MT6350_PMIC_VSYS_OC_THD_MASK, MT6350_PMIC_VSYS_OC_THD_SHIFT},
  {PMIC_VSYS_OC_WND, MT6350_PMIC_VSYS_OC_WND_ADDR, MT6350_PMIC_VSYS_OC_WND_MASK, MT6350_PMIC_VSYS_OC_WND_SHIFT},
  {PMIC_VSYS_DEG_EN, MT6350_PMIC_VSYS_DEG_EN_ADDR, MT6350_PMIC_VSYS_DEG_EN_MASK, MT6350_PMIC_VSYS_DEG_EN_SHIFT},
  {PMIC_VPA_OC_THD, MT6350_PMIC_VPA_OC_THD_ADDR, MT6350_PMIC_VPA_OC_THD_MASK, MT6350_PMIC_VPA_OC_THD_SHIFT},
  {PMIC_VPA_OC_WND, MT6350_PMIC_VPA_OC_WND_ADDR, MT6350_PMIC_VPA_OC_WND_MASK, MT6350_PMIC_VPA_OC_WND_SHIFT},
  {PMIC_VPA_DEG_EN, MT6350_PMIC_VPA_DEG_EN_ADDR, MT6350_PMIC_VPA_DEG_EN_MASK, MT6350_PMIC_VPA_DEG_EN_SHIFT},
  {PMIC_FQMTR_TCKSEL, MT6350_PMIC_FQMTR_TCKSEL_ADDR, MT6350_PMIC_FQMTR_TCKSEL_MASK, MT6350_PMIC_FQMTR_TCKSEL_SHIFT},
  {PMIC_FQMTR_BUSY, MT6350_PMIC_FQMTR_BUSY_ADDR, MT6350_PMIC_FQMTR_BUSY_MASK, MT6350_PMIC_FQMTR_BUSY_SHIFT},
  {PMIC_FQMTR_EN, MT6350_PMIC_FQMTR_EN_ADDR, MT6350_PMIC_FQMTR_EN_MASK, MT6350_PMIC_FQMTR_EN_SHIFT},
  {PMIC_FQMTR_WINSET, MT6350_PMIC_FQMTR_WINSET_ADDR, MT6350_PMIC_FQMTR_WINSET_MASK, MT6350_PMIC_FQMTR_WINSET_SHIFT},
  {PMIC_FQMTR_DATA, MT6350_PMIC_FQMTR_DATA_ADDR, MT6350_PMIC_FQMTR_DATA_MASK, MT6350_PMIC_FQMTR_DATA_SHIFT},
  {PMIC_RG_SPI_CON, MT6350_PMIC_RG_SPI_CON_ADDR, MT6350_PMIC_RG_SPI_CON_MASK, MT6350_PMIC_RG_SPI_CON_SHIFT},
  {PMIC_DEW_DIO_EN, MT6350_PMIC_DEW_DIO_EN_ADDR, MT6350_PMIC_DEW_DIO_EN_MASK, MT6350_PMIC_DEW_DIO_EN_SHIFT},
  {PMIC_DEW_READ_TEST, MT6350_PMIC_DEW_READ_TEST_ADDR, MT6350_PMIC_DEW_READ_TEST_MASK, MT6350_PMIC_DEW_READ_TEST_SHIFT},
  {PMIC_DEW_WRITE_TEST, MT6350_PMIC_DEW_WRITE_TEST_ADDR, MT6350_PMIC_DEW_WRITE_TEST_MASK, MT6350_PMIC_DEW_WRITE_TEST_SHIFT},
  {PMIC_DEW_CRC_SWRST, MT6350_PMIC_DEW_CRC_SWRST_ADDR, MT6350_PMIC_DEW_CRC_SWRST_MASK, MT6350_PMIC_DEW_CRC_SWRST_SHIFT},
  {PMIC_DEW_CRC_EN, MT6350_PMIC_DEW_CRC_EN_ADDR, MT6350_PMIC_DEW_CRC_EN_MASK, MT6350_PMIC_DEW_CRC_EN_SHIFT},
  {PMIC_DEW_CRC_VAL, MT6350_PMIC_DEW_CRC_VAL_ADDR, MT6350_PMIC_DEW_CRC_VAL_MASK, MT6350_PMIC_DEW_CRC_VAL_SHIFT},
  {PMIC_DEW_DBG_MON_SEL, MT6350_PMIC_DEW_DBG_MON_SEL_ADDR, MT6350_PMIC_DEW_DBG_MON_SEL_MASK, MT6350_PMIC_DEW_DBG_MON_SEL_SHIFT},
  {PMIC_DEW_CIPHER_KEY_SEL, MT6350_PMIC_DEW_CIPHER_KEY_SEL_ADDR, MT6350_PMIC_DEW_CIPHER_KEY_SEL_MASK, MT6350_PMIC_DEW_CIPHER_KEY_SEL_SHIFT},
  {PMIC_DEW_CIPHER_IV_SEL, MT6350_PMIC_DEW_CIPHER_IV_SEL_ADDR, MT6350_PMIC_DEW_CIPHER_IV_SEL_MASK, MT6350_PMIC_DEW_CIPHER_IV_SEL_SHIFT},
  {PMIC_DEW_CIPHER_EN, MT6350_PMIC_DEW_CIPHER_EN_ADDR, MT6350_PMIC_DEW_CIPHER_EN_MASK, MT6350_PMIC_DEW_CIPHER_EN_SHIFT},
  {PMIC_DEW_CIPHER_RDY, MT6350_PMIC_DEW_CIPHER_RDY_ADDR, MT6350_PMIC_DEW_CIPHER_RDY_MASK, MT6350_PMIC_DEW_CIPHER_RDY_SHIFT},
  {PMIC_DEW_CIPHER_MODE, MT6350_PMIC_DEW_CIPHER_MODE_ADDR, MT6350_PMIC_DEW_CIPHER_MODE_MASK, MT6350_PMIC_DEW_CIPHER_MODE_SHIFT},
  {PMIC_DEW_CIPHER_SWRST, MT6350_PMIC_DEW_CIPHER_SWRST_ADDR, MT6350_PMIC_DEW_CIPHER_SWRST_MASK, MT6350_PMIC_DEW_CIPHER_SWRST_SHIFT},
  {PMIC_DEW_RDDMY_NO, MT6350_PMIC_DEW_RDDMY_NO_ADDR, MT6350_PMIC_DEW_RDDMY_NO_MASK, MT6350_PMIC_DEW_RDDMY_NO_SHIFT},
  {PMIC_DEW_RDATA_DLY_SEL, MT6350_PMIC_DEW_RDATA_DLY_SEL_ADDR, MT6350_PMIC_DEW_RDATA_DLY_SEL_MASK, MT6350_PMIC_DEW_RDATA_DLY_SEL_SHIFT},
  {PMIC_RG_SMPS_TESTMODE_B, MT6350_PMIC_RG_SMPS_TESTMODE_B_ADDR, MT6350_PMIC_RG_SMPS_TESTMODE_B_MASK, MT6350_PMIC_RG_SMPS_TESTMODE_B_SHIFT},
  {PMIC_QI_VPROC_DIG_MON, MT6350_PMIC_QI_VPROC_DIG_MON_ADDR, MT6350_PMIC_QI_VPROC_DIG_MON_MASK, MT6350_PMIC_QI_VPROC_DIG_MON_SHIFT},
  {PMIC_QI_VSYS_DIG_MON, MT6350_PMIC_QI_VSYS_DIG_MON_ADDR, MT6350_PMIC_QI_VSYS_DIG_MON_MASK, MT6350_PMIC_QI_VSYS_DIG_MON_SHIFT},
  {PMIC_VSLEEP_SRC0, MT6350_PMIC_VSLEEP_SRC0_ADDR, MT6350_PMIC_VSLEEP_SRC0_MASK, MT6350_PMIC_VSLEEP_SRC0_SHIFT},
  {PMIC_VSLEEP_SRC1, MT6350_PMIC_VSLEEP_SRC1_ADDR, MT6350_PMIC_VSLEEP_SRC1_MASK, MT6350_PMIC_VSLEEP_SRC1_SHIFT},
  {PMIC_R2R_SRC0, MT6350_PMIC_R2R_SRC0_ADDR, MT6350_PMIC_R2R_SRC0_MASK, MT6350_PMIC_R2R_SRC0_SHIFT},
  {PMIC_R2R_SRC1, MT6350_PMIC_R2R_SRC1_ADDR, MT6350_PMIC_R2R_SRC1_MASK, MT6350_PMIC_R2R_SRC1_SHIFT},
  {PMIC_BUCK_OSC_SEL_SRC0, MT6350_PMIC_BUCK_OSC_SEL_SRC0_ADDR, MT6350_PMIC_BUCK_OSC_SEL_SRC0_MASK, MT6350_PMIC_BUCK_OSC_SEL_SRC0_SHIFT},
  {PMIC_SRCLKEN_DLY_SRC1, MT6350_PMIC_SRCLKEN_DLY_SRC1_ADDR, MT6350_PMIC_SRCLKEN_DLY_SRC1_MASK, MT6350_PMIC_SRCLKEN_DLY_SRC1_SHIFT},
  {PMIC_BUCK_CON5_RSV0, MT6350_PMIC_BUCK_CON5_RSV0_ADDR, MT6350_PMIC_BUCK_CON5_RSV0_MASK, MT6350_PMIC_BUCK_CON5_RSV0_SHIFT},
  {PMIC_RG_VPROC_TRIML, MT6350_PMIC_RG_VPROC_TRIML_ADDR, MT6350_PMIC_RG_VPROC_TRIML_MASK, MT6350_PMIC_RG_VPROC_TRIML_SHIFT},
  {PMIC_RG_VPROC_TRIMH, MT6350_PMIC_RG_VPROC_TRIMH_ADDR, MT6350_PMIC_RG_VPROC_TRIMH_MASK, MT6350_PMIC_RG_VPROC_TRIMH_SHIFT},
  {PMIC_RG_VPROC_CSM, MT6350_PMIC_RG_VPROC_CSM_ADDR, MT6350_PMIC_RG_VPROC_CSM_MASK, MT6350_PMIC_RG_VPROC_CSM_SHIFT},
  {PMIC_RG_VPROC_ZXOS_TRIM, MT6350_PMIC_RG_VPROC_ZXOS_TRIM_ADDR, MT6350_PMIC_RG_VPROC_ZXOS_TRIM_MASK, MT6350_PMIC_RG_VPROC_ZXOS_TRIM_SHIFT},
  {PMIC_RG_VPROC_RZSEL, MT6350_PMIC_RG_VPROC_RZSEL_ADDR, MT6350_PMIC_RG_VPROC_RZSEL_MASK, MT6350_PMIC_RG_VPROC_RZSEL_SHIFT},
  {PMIC_RG_VPROC_CC, MT6350_PMIC_RG_VPROC_CC_ADDR, MT6350_PMIC_RG_VPROC_CC_MASK, MT6350_PMIC_RG_VPROC_CC_SHIFT},
  {PMIC_RG_VPROC_CSR, MT6350_PMIC_RG_VPROC_CSR_ADDR, MT6350_PMIC_RG_VPROC_CSR_MASK, MT6350_PMIC_RG_VPROC_CSR_SHIFT},
  {PMIC_RG_VPROC_CSL, MT6350_PMIC_RG_VPROC_CSL_ADDR, MT6350_PMIC_RG_VPROC_CSL_MASK, MT6350_PMIC_RG_VPROC_CSL_SHIFT},
  {PMIC_RG_VPROC_ZX_OS, MT6350_PMIC_RG_VPROC_ZX_OS_ADDR, MT6350_PMIC_RG_VPROC_ZX_OS_MASK, MT6350_PMIC_RG_VPROC_ZX_OS_SHIFT},
  {PMIC_RG_VPROC_AVP_OS, MT6350_PMIC_RG_VPROC_AVP_OS_ADDR, MT6350_PMIC_RG_VPROC_AVP_OS_MASK, MT6350_PMIC_RG_VPROC_AVP_OS_SHIFT},
  {PMIC_RG_VPROC_AVP_EN, MT6350_PMIC_RG_VPROC_AVP_EN_ADDR, MT6350_PMIC_RG_VPROC_AVP_EN_MASK, MT6350_PMIC_RG_VPROC_AVP_EN_SHIFT},
  {PMIC_RG_VPROC_MODESET, MT6350_PMIC_RG_VPROC_MODESET_ADDR, MT6350_PMIC_RG_VPROC_MODESET_MASK, MT6350_PMIC_RG_VPROC_MODESET_SHIFT},
  {PMIC_RG_VPROC_NDIS_EN, MT6350_PMIC_RG_VPROC_NDIS_EN_ADDR, MT6350_PMIC_RG_VPROC_NDIS_EN_MASK, MT6350_PMIC_RG_VPROC_NDIS_EN_SHIFT},
  {PMIC_RG_VPROC_SLP, MT6350_PMIC_RG_VPROC_SLP_ADDR, MT6350_PMIC_RG_VPROC_SLP_MASK, MT6350_PMIC_RG_VPROC_SLP_SHIFT},
  {PMIC_QI_VPROC_VSLEEP, MT6350_PMIC_QI_VPROC_VSLEEP_ADDR, MT6350_PMIC_QI_VPROC_VSLEEP_MASK, MT6350_PMIC_QI_VPROC_VSLEEP_SHIFT},
  {PMIC_RG_VPROC_RSV, MT6350_PMIC_RG_VPROC_RSV_ADDR, MT6350_PMIC_RG_VPROC_RSV_MASK, MT6350_PMIC_RG_VPROC_RSV_SHIFT},
  {PMIC_VPROC_EN_CTRL, MT6350_PMIC_VPROC_EN_CTRL_ADDR, MT6350_PMIC_VPROC_EN_CTRL_MASK, MT6350_PMIC_VPROC_EN_CTRL_SHIFT},
  {PMIC_VPROC_VOSEL_CTRL, MT6350_PMIC_VPROC_VOSEL_CTRL_ADDR, MT6350_PMIC_VPROC_VOSEL_CTRL_MASK, MT6350_PMIC_VPROC_VOSEL_CTRL_SHIFT},
  {PMIC_VPROC_DLC_CTRL, MT6350_PMIC_VPROC_DLC_CTRL_ADDR, MT6350_PMIC_VPROC_DLC_CTRL_MASK, MT6350_PMIC_VPROC_DLC_CTRL_SHIFT},
  {PMIC_VPROC_BURST_CTRL, MT6350_PMIC_VPROC_BURST_CTRL_ADDR, MT6350_PMIC_VPROC_BURST_CTRL_MASK, MT6350_PMIC_VPROC_BURST_CTRL_SHIFT},
  {PMIC_VPROC_EN, MT6350_PMIC_VPROC_EN_ADDR, MT6350_PMIC_VPROC_EN_MASK, MT6350_PMIC_VPROC_EN_SHIFT},
  {PMIC_QI_VPROC_STB, MT6350_PMIC_QI_VPROC_STB_ADDR, MT6350_PMIC_QI_VPROC_STB_MASK, MT6350_PMIC_QI_VPROC_STB_SHIFT},
  {PMIC_QI_VPROC_EN, MT6350_PMIC_QI_VPROC_EN_ADDR, MT6350_PMIC_QI_VPROC_EN_MASK, MT6350_PMIC_QI_VPROC_EN_SHIFT},
  {PMIC_QI_VPROC_OC_STATUS, MT6350_PMIC_QI_VPROC_OC_STATUS_ADDR, MT6350_PMIC_QI_VPROC_OC_STATUS_MASK, MT6350_PMIC_QI_VPROC_OC_STATUS_SHIFT},
  {PMIC_VPROC_SFCHG_FRATE, MT6350_PMIC_VPROC_SFCHG_FRATE_ADDR, MT6350_PMIC_VPROC_SFCHG_FRATE_MASK, MT6350_PMIC_VPROC_SFCHG_FRATE_SHIFT},
  {PMIC_VPROC_SFCHG_FEN, MT6350_PMIC_VPROC_SFCHG_FEN_ADDR, MT6350_PMIC_VPROC_SFCHG_FEN_MASK, MT6350_PMIC_VPROC_SFCHG_FEN_SHIFT},
  {PMIC_VPROC_SFCHG_RRATE, MT6350_PMIC_VPROC_SFCHG_RRATE_ADDR, MT6350_PMIC_VPROC_SFCHG_RRATE_MASK, MT6350_PMIC_VPROC_SFCHG_RRATE_SHIFT},
  {PMIC_VPROC_SFCHG_REN, MT6350_PMIC_VPROC_SFCHG_REN_ADDR, MT6350_PMIC_VPROC_SFCHG_REN_MASK, MT6350_PMIC_VPROC_SFCHG_REN_SHIFT},
  {PMIC_VPROC_VOSEL, MT6350_PMIC_VPROC_VOSEL_ADDR, MT6350_PMIC_VPROC_VOSEL_MASK, MT6350_PMIC_VPROC_VOSEL_SHIFT},
  {PMIC_VPROC_VOSEL_ON, MT6350_PMIC_VPROC_VOSEL_ON_ADDR, MT6350_PMIC_VPROC_VOSEL_ON_MASK, MT6350_PMIC_VPROC_VOSEL_ON_SHIFT},
  {PMIC_VPROC_VOSEL_SLEEP, MT6350_PMIC_VPROC_VOSEL_SLEEP_ADDR, MT6350_PMIC_VPROC_VOSEL_SLEEP_MASK, MT6350_PMIC_VPROC_VOSEL_SLEEP_SHIFT},
  {PMIC_NI_VPROC_VOSEL, MT6350_PMIC_NI_VPROC_VOSEL_ADDR, MT6350_PMIC_NI_VPROC_VOSEL_MASK, MT6350_PMIC_NI_VPROC_VOSEL_SHIFT},
  {PMIC_VPROC_BURST, MT6350_PMIC_VPROC_BURST_ADDR, MT6350_PMIC_VPROC_BURST_MASK, MT6350_PMIC_VPROC_BURST_SHIFT},
  {PMIC_VPROC_BURST_ON, MT6350_PMIC_VPROC_BURST_ON_ADDR, MT6350_PMIC_VPROC_BURST_ON_MASK, MT6350_PMIC_VPROC_BURST_ON_SHIFT},
  {PMIC_VPROC_BURST_SLEEP, MT6350_PMIC_VPROC_BURST_SLEEP_ADDR, MT6350_PMIC_VPROC_BURST_SLEEP_MASK, MT6350_PMIC_VPROC_BURST_SLEEP_SHIFT},
  {PMIC_QI_VPROC_BURST, MT6350_PMIC_QI_VPROC_BURST_ADDR, MT6350_PMIC_QI_VPROC_BURST_MASK, MT6350_PMIC_QI_VPROC_BURST_SHIFT},
  {PMIC_VPROC_DLC, MT6350_PMIC_VPROC_DLC_ADDR, MT6350_PMIC_VPROC_DLC_MASK, MT6350_PMIC_VPROC_DLC_SHIFT},
  {PMIC_VPROC_DLC_ON, MT6350_PMIC_VPROC_DLC_ON_ADDR, MT6350_PMIC_VPROC_DLC_ON_MASK, MT6350_PMIC_VPROC_DLC_ON_SHIFT},
  {PMIC_VPROC_DLC_SLEEP, MT6350_PMIC_VPROC_DLC_SLEEP_ADDR, MT6350_PMIC_VPROC_DLC_SLEEP_MASK, MT6350_PMIC_VPROC_DLC_SLEEP_SHIFT},
  {PMIC_QI_VPROC_DLC, MT6350_PMIC_QI_VPROC_DLC_ADDR, MT6350_PMIC_QI_VPROC_DLC_MASK, MT6350_PMIC_QI_VPROC_DLC_SHIFT},
  {PMIC_VPROC_DLC_N, MT6350_PMIC_VPROC_DLC_N_ADDR, MT6350_PMIC_VPROC_DLC_N_MASK, MT6350_PMIC_VPROC_DLC_N_SHIFT},
  {PMIC_VPROC_DLC_N_ON, MT6350_PMIC_VPROC_DLC_N_ON_ADDR, MT6350_PMIC_VPROC_DLC_N_ON_MASK, MT6350_PMIC_VPROC_DLC_N_ON_SHIFT},
  {PMIC_VPROC_DLC_N_SLEEP, MT6350_PMIC_VPROC_DLC_N_SLEEP_ADDR, MT6350_PMIC_VPROC_DLC_N_SLEEP_MASK, MT6350_PMIC_VPROC_DLC_N_SLEEP_SHIFT},
  {PMIC_QI_VPROC_DLC_N, MT6350_PMIC_QI_VPROC_DLC_N_ADDR, MT6350_PMIC_QI_VPROC_DLC_N_MASK, MT6350_PMIC_QI_VPROC_DLC_N_SHIFT},
  {PMIC_VPROC_TRANSTD, MT6350_PMIC_VPROC_TRANSTD_ADDR, MT6350_PMIC_VPROC_TRANSTD_MASK, MT6350_PMIC_VPROC_TRANSTD_SHIFT},
  {PMIC_VPROC_VOSEL_TRANS_EN, MT6350_PMIC_VPROC_VOSEL_TRANS_EN_ADDR, MT6350_PMIC_VPROC_VOSEL_TRANS_EN_MASK, MT6350_PMIC_VPROC_VOSEL_TRANS_EN_SHIFT},
  {PMIC_VPROC_VOSEL_TRANS_ONCE, MT6350_PMIC_VPROC_VOSEL_TRANS_ONCE_ADDR, MT6350_PMIC_VPROC_VOSEL_TRANS_ONCE_MASK, MT6350_PMIC_VPROC_VOSEL_TRANS_ONCE_SHIFT},
  {PMIC_NI_VPROC_VOSEL_TRANS, MT6350_PMIC_NI_VPROC_VOSEL_TRANS_ADDR, MT6350_PMIC_NI_VPROC_VOSEL_TRANS_MASK, MT6350_PMIC_NI_VPROC_VOSEL_TRANS_SHIFT},
  {PMIC_VPROC_VSLEEP_EN, MT6350_PMIC_VPROC_VSLEEP_EN_ADDR, MT6350_PMIC_VPROC_VSLEEP_EN_MASK, MT6350_PMIC_VPROC_VSLEEP_EN_SHIFT},
  {PMIC_VPROC_R2R_PDN, MT6350_PMIC_VPROC_R2R_PDN_ADDR, MT6350_PMIC_VPROC_R2R_PDN_MASK, MT6350_PMIC_VPROC_R2R_PDN_SHIFT},
  {PMIC_VPROC_VSLEEP_SEL, MT6350_PMIC_VPROC_VSLEEP_SEL_ADDR, MT6350_PMIC_VPROC_VSLEEP_SEL_MASK, MT6350_PMIC_VPROC_VSLEEP_SEL_SHIFT},
  {PMIC_NI_VPROC_R2R_PDN, MT6350_PMIC_NI_VPROC_R2R_PDN_ADDR, MT6350_PMIC_NI_VPROC_R2R_PDN_MASK, MT6350_PMIC_NI_VPROC_R2R_PDN_SHIFT},
  {PMIC_NI_VPROC_VSLEEP_SEL, MT6350_PMIC_NI_VPROC_VSLEEP_SEL_ADDR, MT6350_PMIC_NI_VPROC_VSLEEP_SEL_MASK, MT6350_PMIC_NI_VPROC_VSLEEP_SEL_SHIFT},
  {PMIC_RG_VSYS_TRIML, MT6350_PMIC_RG_VSYS_TRIML_ADDR, MT6350_PMIC_RG_VSYS_TRIML_MASK, MT6350_PMIC_RG_VSYS_TRIML_SHIFT},
  {PMIC_RG_VSYS_TRIMH, MT6350_PMIC_RG_VSYS_TRIMH_ADDR, MT6350_PMIC_RG_VSYS_TRIMH_MASK, MT6350_PMIC_RG_VSYS_TRIMH_SHIFT},
  {PMIC_RG_VSYS_CSM, MT6350_PMIC_RG_VSYS_CSM_ADDR, MT6350_PMIC_RG_VSYS_CSM_MASK, MT6350_PMIC_RG_VSYS_CSM_SHIFT},
  {PMIC_RG_VSYS_ZXOS_TRIM, MT6350_PMIC_RG_VSYS_ZXOS_TRIM_ADDR, MT6350_PMIC_RG_VSYS_ZXOS_TRIM_MASK, MT6350_PMIC_RG_VSYS_ZXOS_TRIM_SHIFT},
  {PMIC_RG_VSYS_RZSEL, MT6350_PMIC_RG_VSYS_RZSEL_ADDR, MT6350_PMIC_RG_VSYS_RZSEL_MASK, MT6350_PMIC_RG_VSYS_RZSEL_SHIFT},
  {PMIC_RG_VSYS_CC, MT6350_PMIC_RG_VSYS_CC_ADDR, MT6350_PMIC_RG_VSYS_CC_MASK, MT6350_PMIC_RG_VSYS_CC_SHIFT},
  {PMIC_RG_VSYS_CSR, MT6350_PMIC_RG_VSYS_CSR_ADDR, MT6350_PMIC_RG_VSYS_CSR_MASK, MT6350_PMIC_RG_VSYS_CSR_SHIFT},
  {PMIC_RG_VSYS_CSL, MT6350_PMIC_RG_VSYS_CSL_ADDR, MT6350_PMIC_RG_VSYS_CSL_MASK, MT6350_PMIC_RG_VSYS_CSL_SHIFT},
  {PMIC_RG_VSYS_ZX_OS, MT6350_PMIC_RG_VSYS_ZX_OS_ADDR, MT6350_PMIC_RG_VSYS_ZX_OS_MASK, MT6350_PMIC_RG_VSYS_ZX_OS_SHIFT},
  {PMIC_RG_VSYS_AVP_OS, MT6350_PMIC_RG_VSYS_AVP_OS_ADDR, MT6350_PMIC_RG_VSYS_AVP_OS_MASK, MT6350_PMIC_RG_VSYS_AVP_OS_SHIFT},
  {PMIC_RG_VSYS_AVP_EN, MT6350_PMIC_RG_VSYS_AVP_EN_ADDR, MT6350_PMIC_RG_VSYS_AVP_EN_MASK, MT6350_PMIC_RG_VSYS_AVP_EN_SHIFT},
  {PMIC_RG_VSYS_MODESET, MT6350_PMIC_RG_VSYS_MODESET_ADDR, MT6350_PMIC_RG_VSYS_MODESET_MASK, MT6350_PMIC_RG_VSYS_MODESET_SHIFT},
  {PMIC_RG_VSYS_NDIS_EN, MT6350_PMIC_RG_VSYS_NDIS_EN_ADDR, MT6350_PMIC_RG_VSYS_NDIS_EN_MASK, MT6350_PMIC_RG_VSYS_NDIS_EN_SHIFT},
  {PMIC_RG_VSYS_SLP, MT6350_PMIC_RG_VSYS_SLP_ADDR, MT6350_PMIC_RG_VSYS_SLP_MASK, MT6350_PMIC_RG_VSYS_SLP_SHIFT},
  {PMIC_QI_VSYS_VSLEEP, MT6350_PMIC_QI_VSYS_VSLEEP_ADDR, MT6350_PMIC_QI_VSYS_VSLEEP_MASK, MT6350_PMIC_QI_VSYS_VSLEEP_SHIFT},
  {PMIC_RG_VSYS_RSV, MT6350_PMIC_RG_VSYS_RSV_ADDR, MT6350_PMIC_RG_VSYS_RSV_MASK, MT6350_PMIC_RG_VSYS_RSV_SHIFT},
  {PMIC_VSYS_EN_CTRL, MT6350_PMIC_VSYS_EN_CTRL_ADDR, MT6350_PMIC_VSYS_EN_CTRL_MASK, MT6350_PMIC_VSYS_EN_CTRL_SHIFT},
  {PMIC_VSYS_VOSEL_CTRL, MT6350_PMIC_VSYS_VOSEL_CTRL_ADDR, MT6350_PMIC_VSYS_VOSEL_CTRL_MASK, MT6350_PMIC_VSYS_VOSEL_CTRL_SHIFT},
  {PMIC_VSYS_DLC_CTRL, MT6350_PMIC_VSYS_DLC_CTRL_ADDR, MT6350_PMIC_VSYS_DLC_CTRL_MASK, MT6350_PMIC_VSYS_DLC_CTRL_SHIFT},
  {PMIC_VSYS_BURST_CTRL, MT6350_PMIC_VSYS_BURST_CTRL_ADDR, MT6350_PMIC_VSYS_BURST_CTRL_MASK, MT6350_PMIC_VSYS_BURST_CTRL_SHIFT},
  {PMIC_VSYS_EN, MT6350_PMIC_VSYS_EN_ADDR, MT6350_PMIC_VSYS_EN_MASK, MT6350_PMIC_VSYS_EN_SHIFT},
  {PMIC_QI_VSYS_STB, MT6350_PMIC_QI_VSYS_STB_ADDR, MT6350_PMIC_QI_VSYS_STB_MASK, MT6350_PMIC_QI_VSYS_STB_SHIFT},
  {PMIC_QI_VSYS_EN, MT6350_PMIC_QI_VSYS_EN_ADDR, MT6350_PMIC_QI_VSYS_EN_MASK, MT6350_PMIC_QI_VSYS_EN_SHIFT},
  {PMIC_QI_VSYS_OC_STATUS, MT6350_PMIC_QI_VSYS_OC_STATUS_ADDR, MT6350_PMIC_QI_VSYS_OC_STATUS_MASK, MT6350_PMIC_QI_VSYS_OC_STATUS_SHIFT},
  {PMIC_VSYS_SFCHG_FRATE, MT6350_PMIC_VSYS_SFCHG_FRATE_ADDR, MT6350_PMIC_VSYS_SFCHG_FRATE_MASK, MT6350_PMIC_VSYS_SFCHG_FRATE_SHIFT},
  {PMIC_VSYS_SFCHG_FEN, MT6350_PMIC_VSYS_SFCHG_FEN_ADDR, MT6350_PMIC_VSYS_SFCHG_FEN_MASK, MT6350_PMIC_VSYS_SFCHG_FEN_SHIFT},
  {PMIC_VSYS_SFCHG_RRATE, MT6350_PMIC_VSYS_SFCHG_RRATE_ADDR, MT6350_PMIC_VSYS_SFCHG_RRATE_MASK, MT6350_PMIC_VSYS_SFCHG_RRATE_SHIFT},
  {PMIC_VSYS_SFCHG_REN, MT6350_PMIC_VSYS_SFCHG_REN_ADDR, MT6350_PMIC_VSYS_SFCHG_REN_MASK, MT6350_PMIC_VSYS_SFCHG_REN_SHIFT},
  {PMIC_VSYS_VOSEL, MT6350_PMIC_VSYS_VOSEL_ADDR, MT6350_PMIC_VSYS_VOSEL_MASK, MT6350_PMIC_VSYS_VOSEL_SHIFT},
  {PMIC_VSYS_VOSEL_ON, MT6350_PMIC_VSYS_VOSEL_ON_ADDR, MT6350_PMIC_VSYS_VOSEL_ON_MASK, MT6350_PMIC_VSYS_VOSEL_ON_SHIFT},
  {PMIC_VSYS_VOSEL_SLEEP, MT6350_PMIC_VSYS_VOSEL_SLEEP_ADDR, MT6350_PMIC_VSYS_VOSEL_SLEEP_MASK, MT6350_PMIC_VSYS_VOSEL_SLEEP_SHIFT},
  {PMIC_NI_VSYS_VOSEL, MT6350_PMIC_NI_VSYS_VOSEL_ADDR, MT6350_PMIC_NI_VSYS_VOSEL_MASK, MT6350_PMIC_NI_VSYS_VOSEL_SHIFT},
  {PMIC_VSYS_BURST, MT6350_PMIC_VSYS_BURST_ADDR, MT6350_PMIC_VSYS_BURST_MASK, MT6350_PMIC_VSYS_BURST_SHIFT},
  {PMIC_VSYS_BURST_ON, MT6350_PMIC_VSYS_BURST_ON_ADDR, MT6350_PMIC_VSYS_BURST_ON_MASK, MT6350_PMIC_VSYS_BURST_ON_SHIFT},
  {PMIC_VSYS_BURST_SLEEP, MT6350_PMIC_VSYS_BURST_SLEEP_ADDR, MT6350_PMIC_VSYS_BURST_SLEEP_MASK, MT6350_PMIC_VSYS_BURST_SLEEP_SHIFT},
  {PMIC_QI_VSYS_BURST, MT6350_PMIC_QI_VSYS_BURST_ADDR, MT6350_PMIC_QI_VSYS_BURST_MASK, MT6350_PMIC_QI_VSYS_BURST_SHIFT},
  {PMIC_VSYS_DLC, MT6350_PMIC_VSYS_DLC_ADDR, MT6350_PMIC_VSYS_DLC_MASK, MT6350_PMIC_VSYS_DLC_SHIFT},
  {PMIC_VSYS_DLC_ON, MT6350_PMIC_VSYS_DLC_ON_ADDR, MT6350_PMIC_VSYS_DLC_ON_MASK, MT6350_PMIC_VSYS_DLC_ON_SHIFT},
  {PMIC_VSYS_DLC_SLEEP, MT6350_PMIC_VSYS_DLC_SLEEP_ADDR, MT6350_PMIC_VSYS_DLC_SLEEP_MASK, MT6350_PMIC_VSYS_DLC_SLEEP_SHIFT},
  {PMIC_QI_VSYS_DLC, MT6350_PMIC_QI_VSYS_DLC_ADDR, MT6350_PMIC_QI_VSYS_DLC_MASK, MT6350_PMIC_QI_VSYS_DLC_SHIFT},
  {PMIC_VSYS_DLC_N, MT6350_PMIC_VSYS_DLC_N_ADDR, MT6350_PMIC_VSYS_DLC_N_MASK, MT6350_PMIC_VSYS_DLC_N_SHIFT},
  {PMIC_VSYS_DLC_N_ON, MT6350_PMIC_VSYS_DLC_N_ON_ADDR, MT6350_PMIC_VSYS_DLC_N_ON_MASK, MT6350_PMIC_VSYS_DLC_N_ON_SHIFT},
  {PMIC_VSYS_DLC_N_SLEEP, MT6350_PMIC_VSYS_DLC_N_SLEEP_ADDR, MT6350_PMIC_VSYS_DLC_N_SLEEP_MASK, MT6350_PMIC_VSYS_DLC_N_SLEEP_SHIFT},
  {PMIC_QI_VSYS_DLC_N, MT6350_PMIC_QI_VSYS_DLC_N_ADDR, MT6350_PMIC_QI_VSYS_DLC_N_MASK, MT6350_PMIC_QI_VSYS_DLC_N_SHIFT},
  {PMIC_VSYS_TRANSTD, MT6350_PMIC_VSYS_TRANSTD_ADDR, MT6350_PMIC_VSYS_TRANSTD_MASK, MT6350_PMIC_VSYS_TRANSTD_SHIFT},
  {PMIC_VSYS_VOSEL_TRANS_EN, MT6350_PMIC_VSYS_VOSEL_TRANS_EN_ADDR, MT6350_PMIC_VSYS_VOSEL_TRANS_EN_MASK, MT6350_PMIC_VSYS_VOSEL_TRANS_EN_SHIFT},
  {PMIC_VSYS_VOSEL_TRANS_ONCE, MT6350_PMIC_VSYS_VOSEL_TRANS_ONCE_ADDR, MT6350_PMIC_VSYS_VOSEL_TRANS_ONCE_MASK, MT6350_PMIC_VSYS_VOSEL_TRANS_ONCE_SHIFT},
  {PMIC_NI_VSYS_VOSEL_TRANS, MT6350_PMIC_NI_VSYS_VOSEL_TRANS_ADDR, MT6350_PMIC_NI_VSYS_VOSEL_TRANS_MASK, MT6350_PMIC_NI_VSYS_VOSEL_TRANS_SHIFT},
  {PMIC_VSYS_VSLEEP_EN, MT6350_PMIC_VSYS_VSLEEP_EN_ADDR, MT6350_PMIC_VSYS_VSLEEP_EN_MASK, MT6350_PMIC_VSYS_VSLEEP_EN_SHIFT},
  {PMIC_VSYS_R2R_PDN, MT6350_PMIC_VSYS_R2R_PDN_ADDR, MT6350_PMIC_VSYS_R2R_PDN_MASK, MT6350_PMIC_VSYS_R2R_PDN_SHIFT},
  {PMIC_VSYS_VSLEEP_SEL, MT6350_PMIC_VSYS_VSLEEP_SEL_ADDR, MT6350_PMIC_VSYS_VSLEEP_SEL_MASK, MT6350_PMIC_VSYS_VSLEEP_SEL_SHIFT},
  {PMIC_NI_VSYS_R2R_PDN, MT6350_PMIC_NI_VSYS_R2R_PDN_ADDR, MT6350_PMIC_NI_VSYS_R2R_PDN_MASK, MT6350_PMIC_NI_VSYS_R2R_PDN_SHIFT},
  {PMIC_NI_VSYS_VSLEEP_SEL, MT6350_PMIC_NI_VSYS_VSLEEP_SEL_ADDR, MT6350_PMIC_NI_VSYS_VSLEEP_SEL_MASK, MT6350_PMIC_NI_VSYS_VSLEEP_SEL_SHIFT},
  {PMIC_RG_VPA_TRIML, MT6350_PMIC_RG_VPA_TRIML_ADDR, MT6350_PMIC_RG_VPA_TRIML_MASK, MT6350_PMIC_RG_VPA_TRIML_SHIFT},
  {PMIC_RG_VPA_TRIMH, MT6350_PMIC_RG_VPA_TRIMH_ADDR, MT6350_PMIC_RG_VPA_TRIMH_MASK, MT6350_PMIC_RG_VPA_TRIMH_SHIFT},
  {PMIC_RG_VPA_RZSEL, MT6350_PMIC_RG_VPA_RZSEL_ADDR, MT6350_PMIC_RG_VPA_RZSEL_MASK, MT6350_PMIC_RG_VPA_RZSEL_SHIFT},
  {PMIC_RG_VPA_CC, MT6350_PMIC_RG_VPA_CC_ADDR, MT6350_PMIC_RG_VPA_CC_MASK, MT6350_PMIC_RG_VPA_CC_SHIFT},
  {PMIC_RG_VPA_CSR, MT6350_PMIC_RG_VPA_CSR_ADDR, MT6350_PMIC_RG_VPA_CSR_MASK, MT6350_PMIC_RG_VPA_CSR_SHIFT},
  {PMIC_RG_VPA_CSL, MT6350_PMIC_RG_VPA_CSL_ADDR, MT6350_PMIC_RG_VPA_CSL_MASK, MT6350_PMIC_RG_VPA_CSL_SHIFT},
  {PMIC_RG_VPA_SLEW_NMOS, MT6350_PMIC_RG_VPA_SLEW_NMOS_ADDR, MT6350_PMIC_RG_VPA_SLEW_NMOS_MASK, MT6350_PMIC_RG_VPA_SLEW_NMOS_SHIFT},
  {PMIC_RG_VPA_SLEW, MT6350_PMIC_RG_VPA_SLEW_ADDR, MT6350_PMIC_RG_VPA_SLEW_MASK, MT6350_PMIC_RG_VPA_SLEW_SHIFT},
  {PMIC_RG_VPA_ZX_OS, MT6350_PMIC_RG_VPA_ZX_OS_ADDR, MT6350_PMIC_RG_VPA_ZX_OS_MASK, MT6350_PMIC_RG_VPA_ZX_OS_SHIFT},
  {PMIC_RG_VPA_MODESET, MT6350_PMIC_RG_VPA_MODESET_ADDR, MT6350_PMIC_RG_VPA_MODESET_MASK, MT6350_PMIC_RG_VPA_MODESET_SHIFT},
  {PMIC_RG_VPA_NDIS_EN, MT6350_PMIC_RG_VPA_NDIS_EN_ADDR, MT6350_PMIC_RG_VPA_NDIS_EN_MASK, MT6350_PMIC_RG_VPA_NDIS_EN_SHIFT},
  {PMIC_RG_VPA_CSMIR, MT6350_PMIC_RG_VPA_CSMIR_ADDR, MT6350_PMIC_RG_VPA_CSMIR_MASK, MT6350_PMIC_RG_VPA_CSMIR_SHIFT},
  {PMIC_RG_VPA_VBAT_DEL, MT6350_PMIC_RG_VPA_VBAT_DEL_ADDR, MT6350_PMIC_RG_VPA_VBAT_DEL_MASK, MT6350_PMIC_RG_VPA_VBAT_DEL_SHIFT},
  {PMIC_RG_VPA_SLP, MT6350_PMIC_RG_VPA_SLP_ADDR, MT6350_PMIC_RG_VPA_SLP_MASK, MT6350_PMIC_RG_VPA_SLP_SHIFT},
  {PMIC_RG_VPA_GPU_EN, MT6350_PMIC_RG_VPA_GPU_EN_ADDR, MT6350_PMIC_RG_VPA_GPU_EN_MASK, MT6350_PMIC_RG_VPA_GPU_EN_SHIFT},
  {PMIC_RG_VPA_RSV, MT6350_PMIC_RG_VPA_RSV_ADDR, MT6350_PMIC_RG_VPA_RSV_MASK, MT6350_PMIC_RG_VPA_RSV_SHIFT},
  {PMIC_VPA_EN_CTRL, MT6350_PMIC_VPA_EN_CTRL_ADDR, MT6350_PMIC_VPA_EN_CTRL_MASK, MT6350_PMIC_VPA_EN_CTRL_SHIFT},
  {PMIC_VPA_VOSEL_CTRL, MT6350_PMIC_VPA_VOSEL_CTRL_ADDR, MT6350_PMIC_VPA_VOSEL_CTRL_MASK, MT6350_PMIC_VPA_VOSEL_CTRL_SHIFT},
  {PMIC_VPA_DLC_CTRL, MT6350_PMIC_VPA_DLC_CTRL_ADDR, MT6350_PMIC_VPA_DLC_CTRL_MASK, MT6350_PMIC_VPA_DLC_CTRL_SHIFT},
  {PMIC_VPA_BURST_CTRL, MT6350_PMIC_VPA_BURST_CTRL_ADDR, MT6350_PMIC_VPA_BURST_CTRL_MASK, MT6350_PMIC_VPA_BURST_CTRL_SHIFT},
  {PMIC_VPA_EN, MT6350_PMIC_VPA_EN_ADDR, MT6350_PMIC_VPA_EN_MASK, MT6350_PMIC_VPA_EN_SHIFT},
  {PMIC_QI_VPA_STB, MT6350_PMIC_QI_VPA_STB_ADDR, MT6350_PMIC_QI_VPA_STB_MASK, MT6350_PMIC_QI_VPA_STB_SHIFT},
  {PMIC_QI_VPA_EN, MT6350_PMIC_QI_VPA_EN_ADDR, MT6350_PMIC_QI_VPA_EN_MASK, MT6350_PMIC_QI_VPA_EN_SHIFT},
  {PMIC_QI_VPA_OC_STATUS, MT6350_PMIC_QI_VPA_OC_STATUS_ADDR, MT6350_PMIC_QI_VPA_OC_STATUS_MASK, MT6350_PMIC_QI_VPA_OC_STATUS_SHIFT},
  {PMIC_VPA_SFCHG_FRATE, MT6350_PMIC_VPA_SFCHG_FRATE_ADDR, MT6350_PMIC_VPA_SFCHG_FRATE_MASK, MT6350_PMIC_VPA_SFCHG_FRATE_SHIFT},
  {PMIC_VPA_SFCHG_FEN, MT6350_PMIC_VPA_SFCHG_FEN_ADDR, MT6350_PMIC_VPA_SFCHG_FEN_MASK, MT6350_PMIC_VPA_SFCHG_FEN_SHIFT},
  {PMIC_VPA_SFCHG_RRATE, MT6350_PMIC_VPA_SFCHG_RRATE_ADDR, MT6350_PMIC_VPA_SFCHG_RRATE_MASK, MT6350_PMIC_VPA_SFCHG_RRATE_SHIFT},
  {PMIC_VPA_SFCHG_REN, MT6350_PMIC_VPA_SFCHG_REN_ADDR, MT6350_PMIC_VPA_SFCHG_REN_MASK, MT6350_PMIC_VPA_SFCHG_REN_SHIFT},
  {PMIC_VPA_VOSEL, MT6350_PMIC_VPA_VOSEL_ADDR, MT6350_PMIC_VPA_VOSEL_MASK, MT6350_PMIC_VPA_VOSEL_SHIFT},
  {PMIC_VPA_VOSEL_ON, MT6350_PMIC_VPA_VOSEL_ON_ADDR, MT6350_PMIC_VPA_VOSEL_ON_MASK, MT6350_PMIC_VPA_VOSEL_ON_SHIFT},
  {PMIC_VPA_VOSEL_SLEEP, MT6350_PMIC_VPA_VOSEL_SLEEP_ADDR, MT6350_PMIC_VPA_VOSEL_SLEEP_MASK, MT6350_PMIC_VPA_VOSEL_SLEEP_SHIFT},
  {PMIC_NI_VPA_VOSEL, MT6350_PMIC_NI_VPA_VOSEL_ADDR, MT6350_PMIC_NI_VPA_VOSEL_MASK, MT6350_PMIC_NI_VPA_VOSEL_SHIFT},
  {PMIC_VPA_DLC, MT6350_PMIC_VPA_DLC_ADDR, MT6350_PMIC_VPA_DLC_MASK, MT6350_PMIC_VPA_DLC_SHIFT},
  {PMIC_VPA_DLC_ON, MT6350_PMIC_VPA_DLC_ON_ADDR, MT6350_PMIC_VPA_DLC_ON_MASK, MT6350_PMIC_VPA_DLC_ON_SHIFT},
  {PMIC_VPA_DLC_SLEEP, MT6350_PMIC_VPA_DLC_SLEEP_ADDR, MT6350_PMIC_VPA_DLC_SLEEP_MASK, MT6350_PMIC_VPA_DLC_SLEEP_SHIFT},
  {PMIC_QI_VPA_DLC, MT6350_PMIC_QI_VPA_DLC_ADDR, MT6350_PMIC_QI_VPA_DLC_MASK, MT6350_PMIC_QI_VPA_DLC_SHIFT},
  {PMIC_VPA_BURSTH, MT6350_PMIC_VPA_BURSTH_ADDR, MT6350_PMIC_VPA_BURSTH_MASK, MT6350_PMIC_VPA_BURSTH_SHIFT},
  {PMIC_VPA_BURSTH_ON, MT6350_PMIC_VPA_BURSTH_ON_ADDR, MT6350_PMIC_VPA_BURSTH_ON_MASK, MT6350_PMIC_VPA_BURSTH_ON_SHIFT},
  {PMIC_VPA_BURSTH_SLEEP, MT6350_PMIC_VPA_BURSTH_SLEEP_ADDR, MT6350_PMIC_VPA_BURSTH_SLEEP_MASK, MT6350_PMIC_VPA_BURSTH_SLEEP_SHIFT},
  {PMIC_QI_VPA_BURSTH, MT6350_PMIC_QI_VPA_BURSTH_ADDR, MT6350_PMIC_QI_VPA_BURSTH_MASK, MT6350_PMIC_QI_VPA_BURSTH_SHIFT},
  {PMIC_VPA_BURSTL, MT6350_PMIC_VPA_BURSTL_ADDR, MT6350_PMIC_VPA_BURSTL_MASK, MT6350_PMIC_VPA_BURSTL_SHIFT},
  {PMIC_VPA_BURSTL_ON, MT6350_PMIC_VPA_BURSTL_ON_ADDR, MT6350_PMIC_VPA_BURSTL_ON_MASK, MT6350_PMIC_VPA_BURSTL_ON_SHIFT},
  {PMIC_VPA_BURSTL_SLEEP, MT6350_PMIC_VPA_BURSTL_SLEEP_ADDR, MT6350_PMIC_VPA_BURSTL_SLEEP_MASK, MT6350_PMIC_VPA_BURSTL_SLEEP_SHIFT},
  {PMIC_QI_VPA_BURSTL, MT6350_PMIC_QI_VPA_BURSTL_ADDR, MT6350_PMIC_QI_VPA_BURSTL_MASK, MT6350_PMIC_QI_VPA_BURSTL_SHIFT},
  {PMIC_VPA_TRANSTD, MT6350_PMIC_VPA_TRANSTD_ADDR, MT6350_PMIC_VPA_TRANSTD_MASK, MT6350_PMIC_VPA_TRANSTD_SHIFT},
  {PMIC_VPA_VOSEL_TRANS_EN, MT6350_PMIC_VPA_VOSEL_TRANS_EN_ADDR, MT6350_PMIC_VPA_VOSEL_TRANS_EN_MASK, MT6350_PMIC_VPA_VOSEL_TRANS_EN_SHIFT},
  {PMIC_VPA_VOSEL_TRANS_ONCE, MT6350_PMIC_VPA_VOSEL_TRANS_ONCE_ADDR, MT6350_PMIC_VPA_VOSEL_TRANS_ONCE_MASK, MT6350_PMIC_VPA_VOSEL_TRANS_ONCE_SHIFT},
  {PMIC_NI_VPA_DVS_BW, MT6350_PMIC_NI_VPA_DVS_BW_ADDR, MT6350_PMIC_NI_VPA_DVS_BW_MASK, MT6350_PMIC_NI_VPA_DVS_BW_SHIFT},
  {PMIC_VPA_DLC_MAP_EN, MT6350_PMIC_VPA_DLC_MAP_EN_ADDR, MT6350_PMIC_VPA_DLC_MAP_EN_MASK, MT6350_PMIC_VPA_DLC_MAP_EN_SHIFT},
  {PMIC_VPA_VOSEL_DLC001, MT6350_PMIC_VPA_VOSEL_DLC001_ADDR, MT6350_PMIC_VPA_VOSEL_DLC001_MASK, MT6350_PMIC_VPA_VOSEL_DLC001_SHIFT},
  {PMIC_VPA_VOSEL_DLC011, MT6350_PMIC_VPA_VOSEL_DLC011_ADDR, MT6350_PMIC_VPA_VOSEL_DLC011_MASK, MT6350_PMIC_VPA_VOSEL_DLC011_SHIFT},
  {PMIC_VPA_VOSEL_DLC111, MT6350_PMIC_VPA_VOSEL_DLC111_ADDR, MT6350_PMIC_VPA_VOSEL_DLC111_MASK, MT6350_PMIC_VPA_VOSEL_DLC111_SHIFT},
  {PMIC_K_RST_DONE, MT6350_PMIC_K_RST_DONE_ADDR, MT6350_PMIC_K_RST_DONE_MASK, MT6350_PMIC_K_RST_DONE_SHIFT},
  {PMIC_K_MAP_SEL, MT6350_PMIC_K_MAP_SEL_ADDR, MT6350_PMIC_K_MAP_SEL_MASK, MT6350_PMIC_K_MAP_SEL_SHIFT},
  {PMIC_K_ONCE_EN, MT6350_PMIC_K_ONCE_EN_ADDR, MT6350_PMIC_K_ONCE_EN_MASK, MT6350_PMIC_K_ONCE_EN_SHIFT},
  {PMIC_K_ONCE, MT6350_PMIC_K_ONCE_ADDR, MT6350_PMIC_K_ONCE_MASK, MT6350_PMIC_K_ONCE_SHIFT},
  {PMIC_K_START_MANUAL, MT6350_PMIC_K_START_MANUAL_ADDR, MT6350_PMIC_K_START_MANUAL_MASK, MT6350_PMIC_K_START_MANUAL_SHIFT},
  {PMIC_K_SRC_SEL, MT6350_PMIC_K_SRC_SEL_ADDR, MT6350_PMIC_K_SRC_SEL_MASK, MT6350_PMIC_K_SRC_SEL_SHIFT},
  {PMIC_K_AUTO_EN, MT6350_PMIC_K_AUTO_EN_ADDR, MT6350_PMIC_K_AUTO_EN_MASK, MT6350_PMIC_K_AUTO_EN_SHIFT},
  {PMIC_K_INV, MT6350_PMIC_K_INV_ADDR, MT6350_PMIC_K_INV_MASK, MT6350_PMIC_K_INV_SHIFT},
  {PMIC_K_CONTROL_SMPS, MT6350_PMIC_K_CONTROL_SMPS_ADDR, MT6350_PMIC_K_CONTROL_SMPS_MASK, MT6350_PMIC_K_CONTROL_SMPS_SHIFT},
  {PMIC_K_RESULT, MT6350_PMIC_K_RESULT_ADDR, MT6350_PMIC_K_RESULT_MASK, MT6350_PMIC_K_RESULT_SHIFT},
  {PMIC_K_DONE, MT6350_PMIC_K_DONE_ADDR, MT6350_PMIC_K_DONE_MASK, MT6350_PMIC_K_DONE_SHIFT},
  {PMIC_K_CONTROL, MT6350_PMIC_K_CONTROL_ADDR, MT6350_PMIC_K_CONTROL_MASK, MT6350_PMIC_K_CONTROL_SHIFT},
  {PMIC_QI_SMPS_OSC_CAL, MT6350_PMIC_QI_SMPS_OSC_CAL_ADDR, MT6350_PMIC_QI_SMPS_OSC_CAL_MASK, MT6350_PMIC_QI_SMPS_OSC_CAL_SHIFT},
  {PMIC_ISINK_CH0_MODE, MT6350_PMIC_ISINK_CH0_MODE_ADDR, MT6350_PMIC_ISINK_CH0_MODE_MASK, MT6350_PMIC_ISINK_CH0_MODE_SHIFT},
  {PMIC_ISINK0_RSV1, MT6350_PMIC_ISINK0_RSV1_ADDR, MT6350_PMIC_ISINK0_RSV1_MASK, MT6350_PMIC_ISINK0_RSV1_SHIFT},
  {PMIC_ISINK_DIM0_DUTY, MT6350_PMIC_ISINK_DIM0_DUTY_ADDR, MT6350_PMIC_ISINK_DIM0_DUTY_MASK, MT6350_PMIC_ISINK_DIM0_DUTY_SHIFT},
  {PMIC_ISINK0_RSV0, MT6350_PMIC_ISINK0_RSV0_ADDR, MT6350_PMIC_ISINK0_RSV0_MASK, MT6350_PMIC_ISINK0_RSV0_SHIFT},
  {PMIC_ISINK_DIM0_FSEL, MT6350_PMIC_ISINK_DIM0_FSEL_ADDR, MT6350_PMIC_ISINK_DIM0_FSEL_MASK, MT6350_PMIC_ISINK_DIM0_FSEL_SHIFT},
  {PMIC_ISINK_SFSTR0_EN, MT6350_PMIC_ISINK_SFSTR0_EN_ADDR, MT6350_PMIC_ISINK_SFSTR0_EN_MASK, MT6350_PMIC_ISINK_SFSTR0_EN_SHIFT},
  {PMIC_ISINK_SFSTR0_TC, MT6350_PMIC_ISINK_SFSTR0_TC_ADDR, MT6350_PMIC_ISINK_SFSTR0_TC_MASK, MT6350_PMIC_ISINK_SFSTR0_TC_SHIFT},
  {PMIC_ISINK_CH0_STEP, MT6350_PMIC_ISINK_CH0_STEP_ADDR, MT6350_PMIC_ISINK_CH0_STEP_MASK, MT6350_PMIC_ISINK_CH0_STEP_SHIFT},
  {PMIC_ISINK_BREATH0_TOFF_SEL, MT6350_PMIC_ISINK_BREATH0_TOFF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH0_TOFF_SEL_MASK, MT6350_PMIC_ISINK_BREATH0_TOFF_SEL_SHIFT},
  {PMIC_ISINK_BREATH0_TON_SEL, MT6350_PMIC_ISINK_BREATH0_TON_SEL_ADDR, MT6350_PMIC_ISINK_BREATH0_TON_SEL_MASK, MT6350_PMIC_ISINK_BREATH0_TON_SEL_SHIFT},
  {PMIC_ISINK_BREATH0_TRF_SEL, MT6350_PMIC_ISINK_BREATH0_TRF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH0_TRF_SEL_MASK, MT6350_PMIC_ISINK_BREATH0_TRF_SEL_SHIFT},
  {PMIC_ISINK_CH1_MODE, MT6350_PMIC_ISINK_CH1_MODE_ADDR, MT6350_PMIC_ISINK_CH1_MODE_MASK, MT6350_PMIC_ISINK_CH1_MODE_SHIFT},
  {PMIC_ISINK1_RSV1, MT6350_PMIC_ISINK1_RSV1_ADDR, MT6350_PMIC_ISINK1_RSV1_MASK, MT6350_PMIC_ISINK1_RSV1_SHIFT},
  {PMIC_ISINK_DIM1_DUTY, MT6350_PMIC_ISINK_DIM1_DUTY_ADDR, MT6350_PMIC_ISINK_DIM1_DUTY_MASK, MT6350_PMIC_ISINK_DIM1_DUTY_SHIFT},
  {PMIC_ISINK1_RSV0, MT6350_PMIC_ISINK1_RSV0_ADDR, MT6350_PMIC_ISINK1_RSV0_MASK, MT6350_PMIC_ISINK1_RSV0_SHIFT},
  {PMIC_ISINK_DIM1_FSEL, MT6350_PMIC_ISINK_DIM1_FSEL_ADDR, MT6350_PMIC_ISINK_DIM1_FSEL_MASK, MT6350_PMIC_ISINK_DIM1_FSEL_SHIFT},
  {PMIC_ISINK_SFSTR1_EN, MT6350_PMIC_ISINK_SFSTR1_EN_ADDR, MT6350_PMIC_ISINK_SFSTR1_EN_MASK, MT6350_PMIC_ISINK_SFSTR1_EN_SHIFT},
  {PMIC_ISINK_SFSTR1_TC, MT6350_PMIC_ISINK_SFSTR1_TC_ADDR, MT6350_PMIC_ISINK_SFSTR1_TC_MASK, MT6350_PMIC_ISINK_SFSTR1_TC_SHIFT},
  {PMIC_ISINK_CH1_STEP, MT6350_PMIC_ISINK_CH1_STEP_ADDR, MT6350_PMIC_ISINK_CH1_STEP_MASK, MT6350_PMIC_ISINK_CH1_STEP_SHIFT},
  {PMIC_ISINK_BREATH1_TOFF_SEL, MT6350_PMIC_ISINK_BREATH1_TOFF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH1_TOFF_SEL_MASK, MT6350_PMIC_ISINK_BREATH1_TOFF_SEL_SHIFT},
  {PMIC_ISINK_BREATH1_TON_SEL, MT6350_PMIC_ISINK_BREATH1_TON_SEL_ADDR, MT6350_PMIC_ISINK_BREATH1_TON_SEL_MASK, MT6350_PMIC_ISINK_BREATH1_TON_SEL_SHIFT},
  {PMIC_ISINK_BREATH1_TRF_SEL, MT6350_PMIC_ISINK_BREATH1_TRF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH1_TRF_SEL_MASK, MT6350_PMIC_ISINK_BREATH1_TRF_SEL_SHIFT},
  {PMIC_ISINK_CH2_MODE, MT6350_PMIC_ISINK_CH2_MODE_ADDR, MT6350_PMIC_ISINK_CH2_MODE_MASK, MT6350_PMIC_ISINK_CH2_MODE_SHIFT},
  {PMIC_ISINK2_RSV1, MT6350_PMIC_ISINK2_RSV1_ADDR, MT6350_PMIC_ISINK2_RSV1_MASK, MT6350_PMIC_ISINK2_RSV1_SHIFT},
  {PMIC_ISINK_DIM2_DUTY, MT6350_PMIC_ISINK_DIM2_DUTY_ADDR, MT6350_PMIC_ISINK_DIM2_DUTY_MASK, MT6350_PMIC_ISINK_DIM2_DUTY_SHIFT},
  {PMIC_ISINK2_RSV0, MT6350_PMIC_ISINK2_RSV0_ADDR, MT6350_PMIC_ISINK2_RSV0_MASK, MT6350_PMIC_ISINK2_RSV0_SHIFT},
  {PMIC_ISINK_DIM2_FSEL, MT6350_PMIC_ISINK_DIM2_FSEL_ADDR, MT6350_PMIC_ISINK_DIM2_FSEL_MASK, MT6350_PMIC_ISINK_DIM2_FSEL_SHIFT},
  {PMIC_ISINK_SFSTR2_EN, MT6350_PMIC_ISINK_SFSTR2_EN_ADDR, MT6350_PMIC_ISINK_SFSTR2_EN_MASK, MT6350_PMIC_ISINK_SFSTR2_EN_SHIFT},
  {PMIC_ISINK_SFSTR2_TC, MT6350_PMIC_ISINK_SFSTR2_TC_ADDR, MT6350_PMIC_ISINK_SFSTR2_TC_MASK, MT6350_PMIC_ISINK_SFSTR2_TC_SHIFT},
  {PMIC_ISINK_CH2_STEP, MT6350_PMIC_ISINK_CH2_STEP_ADDR, MT6350_PMIC_ISINK_CH2_STEP_MASK, MT6350_PMIC_ISINK_CH2_STEP_SHIFT},
  {PMIC_ISINK_BREATH2_TOFF_SEL, MT6350_PMIC_ISINK_BREATH2_TOFF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH2_TOFF_SEL_MASK, MT6350_PMIC_ISINK_BREATH2_TOFF_SEL_SHIFT},
  {PMIC_ISINK_BREATH2_TON_SEL, MT6350_PMIC_ISINK_BREATH2_TON_SEL_ADDR, MT6350_PMIC_ISINK_BREATH2_TON_SEL_MASK, MT6350_PMIC_ISINK_BREATH2_TON_SEL_SHIFT},
  {PMIC_ISINK_BREATH2_TRF_SEL, MT6350_PMIC_ISINK_BREATH2_TRF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH2_TRF_SEL_MASK, MT6350_PMIC_ISINK_BREATH2_TRF_SEL_SHIFT},
  {PMIC_ISINK_CH3_MODE, MT6350_PMIC_ISINK_CH3_MODE_ADDR, MT6350_PMIC_ISINK_CH3_MODE_MASK, MT6350_PMIC_ISINK_CH3_MODE_SHIFT},
  {PMIC_ISINK3_RSV1, MT6350_PMIC_ISINK3_RSV1_ADDR, MT6350_PMIC_ISINK3_RSV1_MASK, MT6350_PMIC_ISINK3_RSV1_SHIFT},
  {PMIC_ISINK_DIM3_DUTY, MT6350_PMIC_ISINK_DIM3_DUTY_ADDR, MT6350_PMIC_ISINK_DIM3_DUTY_MASK, MT6350_PMIC_ISINK_DIM3_DUTY_SHIFT},
  {PMIC_ISINK3_RSV0, MT6350_PMIC_ISINK3_RSV0_ADDR, MT6350_PMIC_ISINK3_RSV0_MASK, MT6350_PMIC_ISINK3_RSV0_SHIFT},
  {PMIC_ISINK_DIM3_FSEL, MT6350_PMIC_ISINK_DIM3_FSEL_ADDR, MT6350_PMIC_ISINK_DIM3_FSEL_MASK, MT6350_PMIC_ISINK_DIM3_FSEL_SHIFT},
  {PMIC_ISINK_SFSTR3_EN, MT6350_PMIC_ISINK_SFSTR3_EN_ADDR, MT6350_PMIC_ISINK_SFSTR3_EN_MASK, MT6350_PMIC_ISINK_SFSTR3_EN_SHIFT},
  {PMIC_ISINK_SFSTR3_TC, MT6350_PMIC_ISINK_SFSTR3_TC_ADDR, MT6350_PMIC_ISINK_SFSTR3_TC_MASK, MT6350_PMIC_ISINK_SFSTR3_TC_SHIFT},
  {PMIC_ISINK_CH3_STEP, MT6350_PMIC_ISINK_CH3_STEP_ADDR, MT6350_PMIC_ISINK_CH3_STEP_MASK, MT6350_PMIC_ISINK_CH3_STEP_SHIFT},
  {PMIC_ISINK_BREATH3_TOFF_SEL, MT6350_PMIC_ISINK_BREATH3_TOFF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH3_TOFF_SEL_MASK, MT6350_PMIC_ISINK_BREATH3_TOFF_SEL_SHIFT},
  {PMIC_ISINK_BREATH3_TON_SEL, MT6350_PMIC_ISINK_BREATH3_TON_SEL_ADDR, MT6350_PMIC_ISINK_BREATH3_TON_SEL_MASK, MT6350_PMIC_ISINK_BREATH3_TON_SEL_SHIFT},
  {PMIC_ISINK_BREATH3_TRF_SEL, MT6350_PMIC_ISINK_BREATH3_TRF_SEL_ADDR, MT6350_PMIC_ISINK_BREATH3_TRF_SEL_MASK, MT6350_PMIC_ISINK_BREATH3_TRF_SEL_SHIFT},
  {PMIC_RG_ISINKS_RSV, MT6350_PMIC_RG_ISINKS_RSV_ADDR, MT6350_PMIC_RG_ISINKS_RSV_MASK, MT6350_PMIC_RG_ISINKS_RSV_SHIFT},
  {PMIC_RG_ISINK3_DOUBLE_EN, MT6350_PMIC_RG_ISINK3_DOUBLE_EN_ADDR, MT6350_PMIC_RG_ISINK3_DOUBLE_EN_MASK, MT6350_PMIC_RG_ISINK3_DOUBLE_EN_SHIFT},
  {PMIC_RG_ISINK2_DOUBLE_EN, MT6350_PMIC_RG_ISINK2_DOUBLE_EN_ADDR, MT6350_PMIC_RG_ISINK2_DOUBLE_EN_MASK, MT6350_PMIC_RG_ISINK2_DOUBLE_EN_SHIFT},
  {PMIC_RG_ISINK1_DOUBLE_EN, MT6350_PMIC_RG_ISINK1_DOUBLE_EN_ADDR, MT6350_PMIC_RG_ISINK1_DOUBLE_EN_MASK, MT6350_PMIC_RG_ISINK1_DOUBLE_EN_SHIFT},
  {PMIC_RG_ISINK0_DOUBLE_EN, MT6350_PMIC_RG_ISINK0_DOUBLE_EN_ADDR, MT6350_PMIC_RG_ISINK0_DOUBLE_EN_MASK, MT6350_PMIC_RG_ISINK0_DOUBLE_EN_SHIFT},
  {PMIC_RG_TRIM_SEL, MT6350_PMIC_RG_TRIM_SEL_ADDR, MT6350_PMIC_RG_TRIM_SEL_MASK, MT6350_PMIC_RG_TRIM_SEL_SHIFT},
  {PMIC_RG_TRIM_EN, MT6350_PMIC_RG_TRIM_EN_ADDR, MT6350_PMIC_RG_TRIM_EN_MASK, MT6350_PMIC_RG_TRIM_EN_SHIFT},
  {PMIC_NI_ISINK3_STATUS, MT6350_PMIC_NI_ISINK3_STATUS_ADDR, MT6350_PMIC_NI_ISINK3_STATUS_MASK, MT6350_PMIC_NI_ISINK3_STATUS_SHIFT},
  {PMIC_NI_ISINK2_STATUS, MT6350_PMIC_NI_ISINK2_STATUS_ADDR, MT6350_PMIC_NI_ISINK2_STATUS_MASK, MT6350_PMIC_NI_ISINK2_STATUS_SHIFT},
  {PMIC_NI_ISINK1_STATUS, MT6350_PMIC_NI_ISINK1_STATUS_ADDR, MT6350_PMIC_NI_ISINK1_STATUS_MASK, MT6350_PMIC_NI_ISINK1_STATUS_SHIFT},
  {PMIC_NI_ISINK0_STATUS, MT6350_PMIC_NI_ISINK0_STATUS_ADDR, MT6350_PMIC_NI_ISINK0_STATUS_MASK, MT6350_PMIC_NI_ISINK0_STATUS_SHIFT},
  {PMIC_ISINK_PHASE0_DLY_EN, MT6350_PMIC_ISINK_PHASE0_DLY_EN_ADDR, MT6350_PMIC_ISINK_PHASE0_DLY_EN_MASK, MT6350_PMIC_ISINK_PHASE0_DLY_EN_SHIFT},
  {PMIC_ISINK_PHASE1_DLY_EN, MT6350_PMIC_ISINK_PHASE1_DLY_EN_ADDR, MT6350_PMIC_ISINK_PHASE1_DLY_EN_MASK, MT6350_PMIC_ISINK_PHASE1_DLY_EN_SHIFT},
  {PMIC_ISINK_PHASE2_DLY_EN, MT6350_PMIC_ISINK_PHASE2_DLY_EN_ADDR, MT6350_PMIC_ISINK_PHASE2_DLY_EN_MASK, MT6350_PMIC_ISINK_PHASE2_DLY_EN_SHIFT},
  {PMIC_ISINK_PHASE3_DLY_EN, MT6350_PMIC_ISINK_PHASE3_DLY_EN_ADDR, MT6350_PMIC_ISINK_PHASE3_DLY_EN_MASK, MT6350_PMIC_ISINK_PHASE3_DLY_EN_SHIFT},
  {PMIC_ISINK_PHASE_DLY_TC, MT6350_PMIC_ISINK_PHASE_DLY_TC_ADDR, MT6350_PMIC_ISINK_PHASE_DLY_TC_MASK, MT6350_PMIC_ISINK_PHASE_DLY_TC_SHIFT},
  {PMIC_ISINK_CH0_EN, MT6350_PMIC_ISINK_CH0_EN_ADDR, MT6350_PMIC_ISINK_CH0_EN_MASK, MT6350_PMIC_ISINK_CH0_EN_SHIFT},
  {PMIC_ISINK_CH1_EN, MT6350_PMIC_ISINK_CH1_EN_ADDR, MT6350_PMIC_ISINK_CH1_EN_MASK, MT6350_PMIC_ISINK_CH1_EN_SHIFT},
  {PMIC_ISINK_CH2_EN, MT6350_PMIC_ISINK_CH2_EN_ADDR, MT6350_PMIC_ISINK_CH2_EN_MASK, MT6350_PMIC_ISINK_CH2_EN_SHIFT},
  {PMIC_ISINK_CH3_EN, MT6350_PMIC_ISINK_CH3_EN_ADDR, MT6350_PMIC_ISINK_CH3_EN_MASK, MT6350_PMIC_ISINK_CH3_EN_SHIFT},
  {PMIC_ISINK_CHOP0_EN, MT6350_PMIC_ISINK_CHOP0_EN_ADDR, MT6350_PMIC_ISINK_CHOP0_EN_MASK, MT6350_PMIC_ISINK_CHOP0_EN_SHIFT},
  {PMIC_ISINK_CHOP1_EN, MT6350_PMIC_ISINK_CHOP1_EN_ADDR, MT6350_PMIC_ISINK_CHOP1_EN_MASK, MT6350_PMIC_ISINK_CHOP1_EN_SHIFT},
  {PMIC_ISINK_CHOP2_EN, MT6350_PMIC_ISINK_CHOP2_EN_ADDR, MT6350_PMIC_ISINK_CHOP2_EN_MASK, MT6350_PMIC_ISINK_CHOP2_EN_SHIFT},
  {PMIC_ISINK_CHOP3_EN, MT6350_PMIC_ISINK_CHOP3_EN_ADDR, MT6350_PMIC_ISINK_CHOP3_EN_MASK, MT6350_PMIC_ISINK_CHOP3_EN_SHIFT},
  {PMIC_RG_ANALDORSV1, MT6350_PMIC_RG_ANALDORSV1_ADDR, MT6350_PMIC_RG_ANALDORSV1_MASK, MT6350_PMIC_RG_ANALDORSV1_SHIFT},
  {PMIC_VTCXO_LP_SEL, MT6350_PMIC_VTCXO_LP_SEL_ADDR, MT6350_PMIC_VTCXO_LP_SEL_MASK, MT6350_PMIC_VTCXO_LP_SEL_SHIFT},
  {PMIC_VTCXO_LP_SET, MT6350_PMIC_VTCXO_LP_SET_ADDR, MT6350_PMIC_VTCXO_LP_SET_MASK, MT6350_PMIC_VTCXO_LP_SET_SHIFT},
  {PMIC_QI_VTCXO_MODE, MT6350_PMIC_QI_VTCXO_MODE_ADDR, MT6350_PMIC_QI_VTCXO_MODE_MASK, MT6350_PMIC_QI_VTCXO_MODE_SHIFT},
  {PMIC_RG_VTCXO_STBTD, MT6350_PMIC_RG_VTCXO_STBTD_ADDR, MT6350_PMIC_RG_VTCXO_STBTD_MASK, MT6350_PMIC_RG_VTCXO_STBTD_SHIFT},
  {PMIC_RG_VTCXO_EN, MT6350_PMIC_RG_VTCXO_EN_ADDR, MT6350_PMIC_RG_VTCXO_EN_MASK, MT6350_PMIC_RG_VTCXO_EN_SHIFT},
  {PMIC_VTCXO_ON_CTRL, MT6350_PMIC_VTCXO_ON_CTRL_ADDR, MT6350_PMIC_VTCXO_ON_CTRL_MASK, MT6350_PMIC_VTCXO_ON_CTRL_SHIFT},
  {PMIC_QI_VTCXO_EN, MT6350_PMIC_QI_VTCXO_EN_ADDR, MT6350_PMIC_QI_VTCXO_EN_MASK, MT6350_PMIC_QI_VTCXO_EN_SHIFT},
  {PMIC_VA_LP_SEL, MT6350_PMIC_VA_LP_SEL_ADDR, MT6350_PMIC_VA_LP_SEL_MASK, MT6350_PMIC_VA_LP_SEL_SHIFT},
  {PMIC_VA_LP_SET, MT6350_PMIC_VA_LP_SET_ADDR, MT6350_PMIC_VA_LP_SET_MASK, MT6350_PMIC_VA_LP_SET_SHIFT},
  {PMIC_QI_VA_MODE, MT6350_PMIC_QI_VA_MODE_ADDR, MT6350_PMIC_QI_VA_MODE_MASK, MT6350_PMIC_QI_VA_MODE_SHIFT},
  {PMIC_RG_VA_SENSE_SEL, MT6350_PMIC_RG_VA_SENSE_SEL_ADDR, MT6350_PMIC_RG_VA_SENSE_SEL_MASK, MT6350_PMIC_RG_VA_SENSE_SEL_SHIFT},
  {PMIC_RG_VA_STBTD, MT6350_PMIC_RG_VA_STBTD_ADDR, MT6350_PMIC_RG_VA_STBTD_MASK, MT6350_PMIC_RG_VA_STBTD_SHIFT},
  {PMIC_RG_VA_EN, MT6350_PMIC_RG_VA_EN_ADDR, MT6350_PMIC_RG_VA_EN_MASK, MT6350_PMIC_RG_VA_EN_SHIFT},
  {PMIC_QI_VA_EN, MT6350_PMIC_QI_VA_EN_ADDR, MT6350_PMIC_QI_VA_EN_MASK, MT6350_PMIC_QI_VA_EN_SHIFT},
  {PMIC_RG_ANALDORSV2, MT6350_PMIC_RG_ANALDORSV2_ADDR, MT6350_PMIC_RG_ANALDORSV2_MASK, MT6350_PMIC_RG_ANALDORSV2_SHIFT},
  {PMIC_RG_VCAMA_STBTD, MT6350_PMIC_RG_VCAMA_STBTD_ADDR, MT6350_PMIC_RG_VCAMA_STBTD_MASK, MT6350_PMIC_RG_VCAMA_STBTD_SHIFT},
  {PMIC_RG_VCAMA_EN, MT6350_PMIC_RG_VCAMA_EN_ADDR, MT6350_PMIC_RG_VCAMA_EN_MASK, MT6350_PMIC_RG_VCAMA_EN_SHIFT},
  {PMIC_RG_VCAMA_BIST_EN, MT6350_PMIC_RG_VCAMA_BIST_EN_ADDR, MT6350_PMIC_RG_VCAMA_BIST_EN_MASK, MT6350_PMIC_RG_VCAMA_BIST_EN_SHIFT},
  {PMIC_RG_VA_BIST_EN, MT6350_PMIC_RG_VA_BIST_EN_ADDR, MT6350_PMIC_RG_VA_BIST_EN_MASK, MT6350_PMIC_RG_VA_BIST_EN_SHIFT},
  {PMIC_RG_VTCXO_BIST_EN, MT6350_PMIC_RG_VTCXO_BIST_EN_ADDR, MT6350_PMIC_RG_VTCXO_BIST_EN_MASK, MT6350_PMIC_RG_VTCXO_BIST_EN_SHIFT},
  {PMIC_QI_VCAMA_OC_STATUS, MT6350_PMIC_QI_VCAMA_OC_STATUS_ADDR, MT6350_PMIC_QI_VCAMA_OC_STATUS_MASK, MT6350_PMIC_QI_VCAMA_OC_STATUS_SHIFT},
  {PMIC_QI_VA_OC_STATUS, MT6350_PMIC_QI_VA_OC_STATUS_ADDR, MT6350_PMIC_QI_VA_OC_STATUS_MASK, MT6350_PMIC_QI_VA_OC_STATUS_SHIFT},
  {PMIC_QI_VTCXO_OC_STATUS, MT6350_PMIC_QI_VTCXO_OC_STATUS_ADDR, MT6350_PMIC_QI_VTCXO_OC_STATUS_MASK, MT6350_PMIC_QI_VTCXO_OC_STATUS_SHIFT},
  {PMIC_RG_ANALDORSV3, MT6350_PMIC_RG_ANALDORSV3_ADDR, MT6350_PMIC_RG_ANALDORSV3_MASK, MT6350_PMIC_RG_ANALDORSV3_SHIFT},
  {PMIC_RG_VTCXO_NDIS_EN, MT6350_PMIC_RG_VTCXO_NDIS_EN_ADDR, MT6350_PMIC_RG_VTCXO_NDIS_EN_MASK, MT6350_PMIC_RG_VTCXO_NDIS_EN_SHIFT},
  {PMIC_RG_VTCXO_OCFB, MT6350_PMIC_RG_VTCXO_OCFB_ADDR, MT6350_PMIC_RG_VTCXO_OCFB_MASK, MT6350_PMIC_RG_VTCXO_OCFB_SHIFT},
  {PMIC_RG_VTCXO_CAL, MT6350_PMIC_RG_VTCXO_CAL_ADDR, MT6350_PMIC_RG_VTCXO_CAL_MASK, MT6350_PMIC_RG_VTCXO_CAL_SHIFT},
  {PMIC_RG_VA_NDIS_EN, MT6350_PMIC_RG_VA_NDIS_EN_ADDR, MT6350_PMIC_RG_VA_NDIS_EN_MASK, MT6350_PMIC_RG_VA_NDIS_EN_SHIFT},
  {PMIC_RG_VA_OCFB, MT6350_PMIC_RG_VA_OCFB_ADDR, MT6350_PMIC_RG_VA_OCFB_MASK, MT6350_PMIC_RG_VA_OCFB_SHIFT},
  {PMIC_RG_VA_VOSEL, MT6350_PMIC_RG_VA_VOSEL_ADDR, MT6350_PMIC_RG_VA_VOSEL_MASK, MT6350_PMIC_RG_VA_VOSEL_SHIFT},
  {PMIC_RG_VA_CAL, MT6350_PMIC_RG_VA_CAL_ADDR, MT6350_PMIC_RG_VA_CAL_MASK, MT6350_PMIC_RG_VA_CAL_SHIFT},
  {PMIC_RG_VCAMA_FBSEL, MT6350_PMIC_RG_VCAMA_FBSEL_ADDR, MT6350_PMIC_RG_VCAMA_FBSEL_MASK, MT6350_PMIC_RG_VCAMA_FBSEL_SHIFT},
  {PMIC_RG_VCAMA_NDIS_EN, MT6350_PMIC_RG_VCAMA_NDIS_EN_ADDR, MT6350_PMIC_RG_VCAMA_NDIS_EN_MASK, MT6350_PMIC_RG_VCAMA_NDIS_EN_SHIFT},
  {PMIC_RG_VCAMA_OCFB, MT6350_PMIC_RG_VCAMA_OCFB_ADDR, MT6350_PMIC_RG_VCAMA_OCFB_MASK, MT6350_PMIC_RG_VCAMA_OCFB_SHIFT},
  {PMIC_RG_VCAMA_STB_SEL, MT6350_PMIC_RG_VCAMA_STB_SEL_ADDR, MT6350_PMIC_RG_VCAMA_STB_SEL_MASK, MT6350_PMIC_RG_VCAMA_STB_SEL_SHIFT},
  {PMIC_RG_VCAMA_VOSEL, MT6350_PMIC_RG_VCAMA_VOSEL_ADDR, MT6350_PMIC_RG_VCAMA_VOSEL_MASK, MT6350_PMIC_RG_VCAMA_VOSEL_SHIFT},
  {PMIC_VCAMA_ON_CTRL, MT6350_PMIC_VCAMA_ON_CTRL_ADDR, MT6350_PMIC_VCAMA_ON_CTRL_MASK, MT6350_PMIC_VCAMA_ON_CTRL_SHIFT},
  {PMIC_RG_VCAMA_CAL, MT6350_PMIC_RG_VCAMA_CAL_ADDR, MT6350_PMIC_RG_VCAMA_CAL_MASK, MT6350_PMIC_RG_VCAMA_CAL_SHIFT},
  {PMIC_RG_RESERVE_STB_SEL, MT6350_PMIC_RG_RESERVE_STB_SEL_ADDR, MT6350_PMIC_RG_RESERVE_STB_SEL_MASK, MT6350_PMIC_RG_RESERVE_STB_SEL_SHIFT},
  {PMIC_RG_ALDO_RESERVE, MT6350_PMIC_RG_ALDO_RESERVE_ADDR, MT6350_PMIC_RG_ALDO_RESERVE_MASK, MT6350_PMIC_RG_ALDO_RESERVE_SHIFT},
  {PMIC_RG_VCN33_VOSEL, MT6350_PMIC_RG_VCN33_VOSEL_ADDR, MT6350_PMIC_RG_VCN33_VOSEL_MASK, MT6350_PMIC_RG_VCN33_VOSEL_SHIFT},
  {PMIC_RG_VCN33_NDIS_EN, MT6350_PMIC_RG_VCN33_NDIS_EN_ADDR, MT6350_PMIC_RG_VCN33_NDIS_EN_MASK, MT6350_PMIC_RG_VCN33_NDIS_EN_SHIFT},
  {PMIC_VCN33_ON_CTRL_BT, MT6350_PMIC_VCN33_ON_CTRL_BT_ADDR, MT6350_PMIC_VCN33_ON_CTRL_BT_MASK, MT6350_PMIC_VCN33_ON_CTRL_BT_SHIFT},
  {PMIC_RG_VCN33_OCFB, MT6350_PMIC_RG_VCN33_OCFB_ADDR, MT6350_PMIC_RG_VCN33_OCFB_MASK, MT6350_PMIC_RG_VCN33_OCFB_SHIFT},
  {PMIC_RG_VCN33_EN_BT, MT6350_PMIC_RG_VCN33_EN_BT_ADDR, MT6350_PMIC_RG_VCN33_EN_BT_MASK, MT6350_PMIC_RG_VCN33_EN_BT_SHIFT},
  {PMIC_RG_VCN33_CAL, MT6350_PMIC_RG_VCN33_CAL_ADDR, MT6350_PMIC_RG_VCN33_CAL_MASK, MT6350_PMIC_RG_VCN33_CAL_SHIFT},
  {PMIC_RG_VCN33_STBTD, MT6350_PMIC_RG_VCN33_STBTD_ADDR, MT6350_PMIC_RG_VCN33_STBTD_MASK, MT6350_PMIC_RG_VCN33_STBTD_SHIFT},
  {PMIC_RG_VCN33_EN_WIFI, MT6350_PMIC_RG_VCN33_EN_WIFI_ADDR, MT6350_PMIC_RG_VCN33_EN_WIFI_MASK, MT6350_PMIC_RG_VCN33_EN_WIFI_SHIFT},
  {PMIC_VCN33_ON_CTRL_WIFI, MT6350_PMIC_VCN33_ON_CTRL_WIFI_ADDR, MT6350_PMIC_VCN33_ON_CTRL_WIFI_MASK, MT6350_PMIC_VCN33_ON_CTRL_WIFI_SHIFT},
  {PMIC_QI_VCN33_EN, MT6350_PMIC_QI_VCN33_EN_ADDR, MT6350_PMIC_QI_VCN33_EN_MASK, MT6350_PMIC_QI_VCN33_EN_SHIFT},
  {PMIC_RG_VCN28_BIST_EN, MT6350_PMIC_RG_VCN28_BIST_EN_ADDR, MT6350_PMIC_RG_VCN28_BIST_EN_MASK, MT6350_PMIC_RG_VCN28_BIST_EN_SHIFT},
  {PMIC_RG_VCN28_NDIS_EN, MT6350_PMIC_RG_VCN28_NDIS_EN_ADDR, MT6350_PMIC_RG_VCN28_NDIS_EN_MASK, MT6350_PMIC_RG_VCN28_NDIS_EN_SHIFT},
  {PMIC_RG_VCN28_OCFB, MT6350_PMIC_RG_VCN28_OCFB_ADDR, MT6350_PMIC_RG_VCN28_OCFB_MASK, MT6350_PMIC_RG_VCN28_OCFB_SHIFT},
  {PMIC_RG_VCN28_VOSEL, MT6350_PMIC_RG_VCN28_VOSEL_ADDR, MT6350_PMIC_RG_VCN28_VOSEL_MASK, MT6350_PMIC_RG_VCN28_VOSEL_SHIFT},
  {PMIC_RG_VCN28_CAL, MT6350_PMIC_RG_VCN28_CAL_ADDR, MT6350_PMIC_RG_VCN28_CAL_MASK, MT6350_PMIC_RG_VCN28_CAL_SHIFT},
  {PMIC_RG_VCN28_STBTD, MT6350_PMIC_RG_VCN28_STBTD_ADDR, MT6350_PMIC_RG_VCN28_STBTD_MASK, MT6350_PMIC_RG_VCN28_STBTD_SHIFT},
  {PMIC_RG_VCN28_EN, MT6350_PMIC_RG_VCN28_EN_ADDR, MT6350_PMIC_RG_VCN28_EN_MASK, MT6350_PMIC_RG_VCN28_EN_SHIFT},
  {PMIC_VCN28_ON_CTRL, MT6350_PMIC_VCN28_ON_CTRL_ADDR, MT6350_PMIC_VCN28_ON_CTRL_MASK, MT6350_PMIC_VCN28_ON_CTRL_SHIFT},
  {PMIC_QI_VCN28_EN, MT6350_PMIC_QI_VCN28_EN_ADDR, MT6350_PMIC_QI_VCN28_EN_MASK, MT6350_PMIC_QI_VCN28_EN_SHIFT},
  {PMIC_VCN28_LP_SEL, MT6350_PMIC_VCN28_LP_SEL_ADDR, MT6350_PMIC_VCN28_LP_SEL_MASK, MT6350_PMIC_VCN28_LP_SEL_SHIFT},
  {PMIC_VCN28_LP_SET, MT6350_PMIC_VCN28_LP_SET_ADDR, MT6350_PMIC_VCN28_LP_SET_MASK, MT6350_PMIC_VCN28_LP_SET_SHIFT},
  {PMIC_QI_VCN28_MODE, MT6350_PMIC_QI_VCN28_MODE_ADDR, MT6350_PMIC_QI_VCN28_MODE_MASK, MT6350_PMIC_QI_VCN28_MODE_SHIFT},
  {PMIC_QI_VCN28_OC_STATUS, MT6350_PMIC_QI_VCN28_OC_STATUS_ADDR, MT6350_PMIC_QI_VCN28_OC_STATUS_MASK, MT6350_PMIC_QI_VCN28_OC_STATUS_SHIFT},
  {PMIC_VCN33_LP_SEL, MT6350_PMIC_VCN33_LP_SEL_ADDR, MT6350_PMIC_VCN33_LP_SEL_MASK, MT6350_PMIC_VCN33_LP_SEL_SHIFT},
  {PMIC_VCN33_LP_SET, MT6350_PMIC_VCN33_LP_SET_ADDR, MT6350_PMIC_VCN33_LP_SET_MASK, MT6350_PMIC_VCN33_LP_SET_SHIFT},
  {PMIC_QI_VCN33_MODE, MT6350_PMIC_QI_VCN33_MODE_ADDR, MT6350_PMIC_QI_VCN33_MODE_MASK, MT6350_PMIC_QI_VCN33_MODE_SHIFT},
  {PMIC_RG_VCN33_EN, MT6350_PMIC_RG_VCN33_EN_ADDR, MT6350_PMIC_RG_VCN33_EN_MASK, MT6350_PMIC_RG_VCN33_EN_SHIFT},
  {PMIC_RG_VCN33_BIST_EN, MT6350_PMIC_RG_VCN33_BIST_EN_ADDR, MT6350_PMIC_RG_VCN33_BIST_EN_MASK, MT6350_PMIC_RG_VCN33_BIST_EN_SHIFT},
  {PMIC_QI_VCN33_OC_STATUS, MT6350_PMIC_QI_VCN33_OC_STATUS_ADDR, MT6350_PMIC_QI_VCN33_OC_STATUS_MASK, MT6350_PMIC_QI_VCN33_OC_STATUS_SHIFT},
  {PMIC_VIO28_LP_SEL, MT6350_PMIC_VIO28_LP_SEL_ADDR, MT6350_PMIC_VIO28_LP_SEL_MASK, MT6350_PMIC_VIO28_LP_SEL_SHIFT},
  {PMIC_VIO28_LP_MODE_SET, MT6350_PMIC_VIO28_LP_MODE_SET_ADDR, MT6350_PMIC_VIO28_LP_MODE_SET_MASK, MT6350_PMIC_VIO28_LP_MODE_SET_SHIFT},
  {PMIC_QI_VIO28_MODE, MT6350_PMIC_QI_VIO28_MODE_ADDR, MT6350_PMIC_QI_VIO28_MODE_MASK, MT6350_PMIC_QI_VIO28_MODE_SHIFT},
  {PMIC_RG_VIO28_STBTD, MT6350_PMIC_RG_VIO28_STBTD_ADDR, MT6350_PMIC_RG_VIO28_STBTD_MASK, MT6350_PMIC_RG_VIO28_STBTD_SHIFT},
  {PMIC_VIO28_EN, MT6350_PMIC_VIO28_EN_ADDR, MT6350_PMIC_VIO28_EN_MASK, MT6350_PMIC_VIO28_EN_SHIFT},
  {PMIC_QI_VIO28_EN, MT6350_PMIC_QI_VIO28_EN_ADDR, MT6350_PMIC_QI_VIO28_EN_MASK, MT6350_PMIC_QI_VIO28_EN_SHIFT},
  {PMIC_VUSB_LP_SEL, MT6350_PMIC_VUSB_LP_SEL_ADDR, MT6350_PMIC_VUSB_LP_SEL_MASK, MT6350_PMIC_VUSB_LP_SEL_SHIFT},
  {PMIC_VUSB_LP_MODE_SET, MT6350_PMIC_VUSB_LP_MODE_SET_ADDR, MT6350_PMIC_VUSB_LP_MODE_SET_MASK, MT6350_PMIC_VUSB_LP_MODE_SET_SHIFT},
  {PMIC_QI_VUSB_MODE, MT6350_PMIC_QI_VUSB_MODE_ADDR, MT6350_PMIC_QI_VUSB_MODE_MASK, MT6350_PMIC_QI_VUSB_MODE_SHIFT},
  {PMIC_RG_VUSB_STBTD, MT6350_PMIC_RG_VUSB_STBTD_ADDR, MT6350_PMIC_RG_VUSB_STBTD_MASK, MT6350_PMIC_RG_VUSB_STBTD_SHIFT},
  {PMIC_RG_VUSB_EN, MT6350_PMIC_RG_VUSB_EN_ADDR, MT6350_PMIC_RG_VUSB_EN_MASK, MT6350_PMIC_RG_VUSB_EN_SHIFT},
  {PMIC_QI_VUSB_EN, MT6350_PMIC_QI_VUSB_EN_ADDR, MT6350_PMIC_QI_VUSB_EN_MASK, MT6350_PMIC_QI_VUSB_EN_SHIFT},
  {PMIC_VMC_LP_SEL, MT6350_PMIC_VMC_LP_SEL_ADDR, MT6350_PMIC_VMC_LP_SEL_MASK, MT6350_PMIC_VMC_LP_SEL_SHIFT},
  {PMIC_VMC_LP_MODE_SET, MT6350_PMIC_VMC_LP_MODE_SET_ADDR, MT6350_PMIC_VMC_LP_MODE_SET_MASK, MT6350_PMIC_VMC_LP_MODE_SET_SHIFT},
  {PMIC_RG_STB_SEL, MT6350_PMIC_RG_STB_SEL_ADDR, MT6350_PMIC_RG_STB_SEL_MASK, MT6350_PMIC_RG_STB_SEL_SHIFT},
  {PMIC_QI_VMC_MODE, MT6350_PMIC_QI_VMC_MODE_ADDR, MT6350_PMIC_QI_VMC_MODE_MASK, MT6350_PMIC_QI_VMC_MODE_SHIFT},
  {PMIC_RG_VMC_STBTD, MT6350_PMIC_RG_VMC_STBTD_ADDR, MT6350_PMIC_RG_VMC_STBTD_MASK, MT6350_PMIC_RG_VMC_STBTD_SHIFT},
  {PMIC_RG_VMC_EN, MT6350_PMIC_RG_VMC_EN_ADDR, MT6350_PMIC_RG_VMC_EN_MASK, MT6350_PMIC_RG_VMC_EN_SHIFT},
  {PMIC_RG_VMC_INT_DIS_SEL, MT6350_PMIC_RG_VMC_INT_DIS_SEL_ADDR, MT6350_PMIC_RG_VMC_INT_DIS_SEL_MASK, MT6350_PMIC_RG_VMC_INT_DIS_SEL_SHIFT},
  {PMIC_QI_VMC_EN, MT6350_PMIC_QI_VMC_EN_ADDR, MT6350_PMIC_QI_VMC_EN_MASK, MT6350_PMIC_QI_VMC_EN_SHIFT},
  {PMIC_VMCH_LP_SEL, MT6350_PMIC_VMCH_LP_SEL_ADDR, MT6350_PMIC_VMCH_LP_SEL_MASK, MT6350_PMIC_VMCH_LP_SEL_SHIFT},
  {PMIC_VMCH_LP_MODE_SET, MT6350_PMIC_VMCH_LP_MODE_SET_ADDR, MT6350_PMIC_VMCH_LP_MODE_SET_MASK, MT6350_PMIC_VMCH_LP_MODE_SET_SHIFT},
  {PMIC_QI_VMCH_MODE, MT6350_PMIC_QI_VMCH_MODE_ADDR, MT6350_PMIC_QI_VMCH_MODE_MASK, MT6350_PMIC_QI_VMCH_MODE_SHIFT},
  {PMIC_RG_VMCH_STBTD, MT6350_PMIC_RG_VMCH_STBTD_ADDR, MT6350_PMIC_RG_VMCH_STBTD_MASK, MT6350_PMIC_RG_VMCH_STBTD_SHIFT},
  {PMIC_RG_VMCH_EN, MT6350_PMIC_RG_VMCH_EN_ADDR, MT6350_PMIC_RG_VMCH_EN_MASK, MT6350_PMIC_RG_VMCH_EN_SHIFT},
  {PMIC_QI_VMCH_EN, MT6350_PMIC_QI_VMCH_EN_ADDR, MT6350_PMIC_QI_VMCH_EN_MASK, MT6350_PMIC_QI_VMCH_EN_SHIFT},
  {PMIC_VEMC_3V3_LP_SEL, MT6350_PMIC_VEMC_3V3_LP_SEL_ADDR, MT6350_PMIC_VEMC_3V3_LP_SEL_MASK, MT6350_PMIC_VEMC_3V3_LP_SEL_SHIFT},
  {PMIC_VEMC_3V3_LP_MODE_SET, MT6350_PMIC_VEMC_3V3_LP_MODE_SET_ADDR, MT6350_PMIC_VEMC_3V3_LP_MODE_SET_MASK, MT6350_PMIC_VEMC_3V3_LP_MODE_SET_SHIFT},
  {PMIC_QI_VEMC_3V3_MODE, MT6350_PMIC_QI_VEMC_3V3_MODE_ADDR, MT6350_PMIC_QI_VEMC_3V3_MODE_MASK, MT6350_PMIC_QI_VEMC_3V3_MODE_SHIFT},
  {PMIC_RG_VEMC_3V3_STBTD, MT6350_PMIC_RG_VEMC_3V3_STBTD_ADDR, MT6350_PMIC_RG_VEMC_3V3_STBTD_MASK, MT6350_PMIC_RG_VEMC_3V3_STBTD_SHIFT},
  {PMIC_RG_VEMC_3V3_EN, MT6350_PMIC_RG_VEMC_3V3_EN_ADDR, MT6350_PMIC_RG_VEMC_3V3_EN_MASK, MT6350_PMIC_RG_VEMC_3V3_EN_SHIFT},
  {PMIC_QI_VEMC_3V3_EN, MT6350_PMIC_QI_VEMC_3V3_EN_ADDR, MT6350_PMIC_QI_VEMC_3V3_EN_MASK, MT6350_PMIC_QI_VEMC_3V3_EN_SHIFT},
  {PMIC_VGP1_LP_SEL, MT6350_PMIC_VGP1_LP_SEL_ADDR, MT6350_PMIC_VGP1_LP_SEL_MASK, MT6350_PMIC_VGP1_LP_SEL_SHIFT},
  {PMIC_VGP1_LP_MODE_SET, MT6350_PMIC_VGP1_LP_MODE_SET_ADDR, MT6350_PMIC_VGP1_LP_MODE_SET_MASK, MT6350_PMIC_VGP1_LP_MODE_SET_SHIFT},
  {PMIC_QI_VGP1_MODE, MT6350_PMIC_QI_VGP1_MODE_ADDR, MT6350_PMIC_QI_VGP1_MODE_MASK, MT6350_PMIC_QI_VGP1_MODE_SHIFT},
  {PMIC_RG_VGP1_STBTD, MT6350_PMIC_RG_VGP1_STBTD_ADDR, MT6350_PMIC_RG_VGP1_STBTD_MASK, MT6350_PMIC_RG_VGP1_STBTD_SHIFT},
  {PMIC_RG_VGP1_EN, MT6350_PMIC_RG_VGP1_EN_ADDR, MT6350_PMIC_RG_VGP1_EN_MASK, MT6350_PMIC_RG_VGP1_EN_SHIFT},
  {PMIC_VGP2_LP_SEL, MT6350_PMIC_VGP2_LP_SEL_ADDR, MT6350_PMIC_VGP2_LP_SEL_MASK, MT6350_PMIC_VGP2_LP_SEL_SHIFT},
  {PMIC_VGP2_LP_MODE_SET, MT6350_PMIC_VGP2_LP_MODE_SET_ADDR, MT6350_PMIC_VGP2_LP_MODE_SET_MASK, MT6350_PMIC_VGP2_LP_MODE_SET_SHIFT},
  {PMIC_QI_VGP2_MODE, MT6350_PMIC_QI_VGP2_MODE_ADDR, MT6350_PMIC_QI_VGP2_MODE_MASK, MT6350_PMIC_QI_VGP2_MODE_SHIFT},
  {PMIC_RG_VGP2_STBTD, MT6350_PMIC_RG_VGP2_STBTD_ADDR, MT6350_PMIC_RG_VGP2_STBTD_MASK, MT6350_PMIC_RG_VGP2_STBTD_SHIFT},
  {PMIC_RG_VGP2_EN, MT6350_PMIC_RG_VGP2_EN_ADDR, MT6350_PMIC_RG_VGP2_EN_MASK, MT6350_PMIC_RG_VGP2_EN_SHIFT},
  {PMIC_VGP3_LP_SEL, MT6350_PMIC_VGP3_LP_SEL_ADDR, MT6350_PMIC_VGP3_LP_SEL_MASK, MT6350_PMIC_VGP3_LP_SEL_SHIFT},
  {PMIC_VGP3_LP_MODE_SET, MT6350_PMIC_VGP3_LP_MODE_SET_ADDR, MT6350_PMIC_VGP3_LP_MODE_SET_MASK, MT6350_PMIC_VGP3_LP_MODE_SET_SHIFT},
  {PMIC_QI_VGP3_MODE, MT6350_PMIC_QI_VGP3_MODE_ADDR, MT6350_PMIC_QI_VGP3_MODE_MASK, MT6350_PMIC_QI_VGP3_MODE_SHIFT},
  {PMIC_RG_VGP3_STBTD, MT6350_PMIC_RG_VGP3_STBTD_ADDR, MT6350_PMIC_RG_VGP3_STBTD_MASK, MT6350_PMIC_RG_VGP3_STBTD_SHIFT},
  {PMIC_RG_VGP3_EN, MT6350_PMIC_RG_VGP3_EN_ADDR, MT6350_PMIC_RG_VGP3_EN_MASK, MT6350_PMIC_RG_VGP3_EN_SHIFT},
  {PMIC_RG_VCN_1V8_NDIS_EN, MT6350_PMIC_RG_VCN_1V8_NDIS_EN_ADDR, MT6350_PMIC_RG_VCN_1V8_NDIS_EN_MASK, MT6350_PMIC_RG_VCN_1V8_NDIS_EN_SHIFT},
  {PMIC_VCN_1V8_ON_CTRL, MT6350_PMIC_VCN_1V8_ON_CTRL_ADDR, MT6350_PMIC_VCN_1V8_ON_CTRL_MASK, MT6350_PMIC_VCN_1V8_ON_CTRL_SHIFT},
  {PMIC_RG_VCN_1V8_OCFB, MT6350_PMIC_RG_VCN_1V8_OCFB_ADDR, MT6350_PMIC_RG_VCN_1V8_OCFB_MASK, MT6350_PMIC_RG_VCN_1V8_OCFB_SHIFT},
  {PMIC_RG_VCN_1V8_STB_SEL, MT6350_PMIC_RG_VCN_1V8_STB_SEL_ADDR, MT6350_PMIC_RG_VCN_1V8_STB_SEL_MASK, MT6350_PMIC_RG_VCN_1V8_STB_SEL_SHIFT},
  {PMIC_RG_VCN_1V8_CAL, MT6350_PMIC_RG_VCN_1V8_CAL_ADDR, MT6350_PMIC_RG_VCN_1V8_CAL_MASK, MT6350_PMIC_RG_VCN_1V8_CAL_SHIFT},
  {PMIC_VCN_1V8_LP_SEL, MT6350_PMIC_VCN_1V8_LP_SEL_ADDR, MT6350_PMIC_VCN_1V8_LP_SEL_MASK, MT6350_PMIC_VCN_1V8_LP_SEL_SHIFT},
  {PMIC_VCN_1V8_LP_MODE_SET, MT6350_PMIC_VCN_1V8_LP_MODE_SET_ADDR, MT6350_PMIC_VCN_1V8_LP_MODE_SET_MASK, MT6350_PMIC_VCN_1V8_LP_MODE_SET_SHIFT},
  {PMIC_QI_VCN_1V8_MODE, MT6350_PMIC_QI_VCN_1V8_MODE_ADDR, MT6350_PMIC_QI_VCN_1V8_MODE_MASK, MT6350_PMIC_QI_VCN_1V8_MODE_SHIFT},
  {PMIC_RG_VCN_1V8_STBTD, MT6350_PMIC_RG_VCN_1V8_STBTD_ADDR, MT6350_PMIC_RG_VCN_1V8_STBTD_MASK, MT6350_PMIC_RG_VCN_1V8_STBTD_SHIFT},
  {PMIC_RG_VCN_1V8_EN, MT6350_PMIC_RG_VCN_1V8_EN_ADDR, MT6350_PMIC_RG_VCN_1V8_EN_MASK, MT6350_PMIC_RG_VCN_1V8_EN_SHIFT},
  {PMIC_QI_VCN_1V8_EN, MT6350_PMIC_QI_VCN_1V8_EN_ADDR, MT6350_PMIC_QI_VCN_1V8_EN_MASK, MT6350_PMIC_QI_VCN_1V8_EN_SHIFT},
  {PMIC_RG_STB_SIM1_SIO, MT6350_PMIC_RG_STB_SIM1_SIO_ADDR, MT6350_PMIC_RG_STB_SIM1_SIO_MASK, MT6350_PMIC_RG_STB_SIM1_SIO_SHIFT},
  {PMIC_RG_SIMLS1_IES_OFF, MT6350_PMIC_RG_SIMLS1_IES_OFF_ADDR, MT6350_PMIC_RG_SIMLS1_IES_OFF_MASK, MT6350_PMIC_RG_SIMLS1_IES_OFF_SHIFT},
  {PMIC_RE_DIGLDORSV1, MT6350_PMIC_RE_DIGLDORSV1_ADDR, MT6350_PMIC_RE_DIGLDORSV1_MASK, MT6350_PMIC_RE_DIGLDORSV1_SHIFT},
  {PMIC_VSIM1_LP_SEL, MT6350_PMIC_VSIM1_LP_SEL_ADDR, MT6350_PMIC_VSIM1_LP_SEL_MASK, MT6350_PMIC_VSIM1_LP_SEL_SHIFT},
  {PMIC_VSIM1_LP_MODE_SET, MT6350_PMIC_VSIM1_LP_MODE_SET_ADDR, MT6350_PMIC_VSIM1_LP_MODE_SET_MASK, MT6350_PMIC_VSIM1_LP_MODE_SET_SHIFT},
  {PMIC_QI_VSIM1_MODE, MT6350_PMIC_QI_VSIM1_MODE_ADDR, MT6350_PMIC_QI_VSIM1_MODE_MASK, MT6350_PMIC_QI_VSIM1_MODE_SHIFT},
  {PMIC_RG_VSIM1_STBTD, MT6350_PMIC_RG_VSIM1_STBTD_ADDR, MT6350_PMIC_RG_VSIM1_STBTD_MASK, MT6350_PMIC_RG_VSIM1_STBTD_SHIFT},
  {PMIC_RG_VSIM1_EN, MT6350_PMIC_RG_VSIM1_EN_ADDR, MT6350_PMIC_RG_VSIM1_EN_MASK, MT6350_PMIC_RG_VSIM1_EN_SHIFT},
  {PMIC_VSIM2_LP_SEL, MT6350_PMIC_VSIM2_LP_SEL_ADDR, MT6350_PMIC_VSIM2_LP_SEL_MASK, MT6350_PMIC_VSIM2_LP_SEL_SHIFT},
  {PMIC_VSIM2_LP_MODE_SET, MT6350_PMIC_VSIM2_LP_MODE_SET_ADDR, MT6350_PMIC_VSIM2_LP_MODE_SET_MASK, MT6350_PMIC_VSIM2_LP_MODE_SET_SHIFT},
  {PMIC_VSIM2_THER_SHDN_EN, MT6350_PMIC_VSIM2_THER_SHDN_EN_ADDR, MT6350_PMIC_VSIM2_THER_SHDN_EN_MASK, MT6350_PMIC_VSIM2_THER_SHDN_EN_SHIFT},
  {PMIC_QI_VSIM2_MODE, MT6350_PMIC_QI_VSIM2_MODE_ADDR, MT6350_PMIC_QI_VSIM2_MODE_MASK, MT6350_PMIC_QI_VSIM2_MODE_SHIFT},
  {PMIC_RG_VSIM2_STBTD, MT6350_PMIC_RG_VSIM2_STBTD_ADDR, MT6350_PMIC_RG_VSIM2_STBTD_MASK, MT6350_PMIC_RG_VSIM2_STBTD_SHIFT},
  {PMIC_RG_VSIM2_EN, MT6350_PMIC_RG_VSIM2_EN_ADDR, MT6350_PMIC_RG_VSIM2_EN_MASK, MT6350_PMIC_RG_VSIM2_EN_SHIFT},
  {PMIC_RG_VRTC_FORCE_ON, MT6350_PMIC_RG_VRTC_FORCE_ON_ADDR, MT6350_PMIC_RG_VRTC_FORCE_ON_MASK, MT6350_PMIC_RG_VRTC_FORCE_ON_SHIFT},
  {PMIC_VRTC_EN, MT6350_PMIC_VRTC_EN_ADDR, MT6350_PMIC_VRTC_EN_MASK, MT6350_PMIC_VRTC_EN_SHIFT},
  {PMIC_QI_VRTC_EN, MT6350_PMIC_QI_VRTC_EN_ADDR, MT6350_PMIC_QI_VRTC_EN_MASK, MT6350_PMIC_QI_VRTC_EN_SHIFT},
  {PMIC_RG_VEMC_3V3_BIST_EN, MT6350_PMIC_RG_VEMC_3V3_BIST_EN_ADDR, MT6350_PMIC_RG_VEMC_3V3_BIST_EN_MASK, MT6350_PMIC_RG_VEMC_3V3_BIST_EN_SHIFT},
  {PMIC_RG_VMCH_BIST_EN, MT6350_PMIC_RG_VMCH_BIST_EN_ADDR, MT6350_PMIC_RG_VMCH_BIST_EN_MASK, MT6350_PMIC_RG_VMCH_BIST_EN_SHIFT},
  {PMIC_RG_VMC_BIST_EN, MT6350_PMIC_RG_VMC_BIST_EN_ADDR, MT6350_PMIC_RG_VMC_BIST_EN_MASK, MT6350_PMIC_RG_VMC_BIST_EN_SHIFT},
  {PMIC_RG_VUSB_BIST_EN, MT6350_PMIC_RG_VUSB_BIST_EN_ADDR, MT6350_PMIC_RG_VUSB_BIST_EN_MASK, MT6350_PMIC_RG_VUSB_BIST_EN_SHIFT},
  {PMIC_RG_VIO28_BIST_EN, MT6350_PMIC_RG_VIO28_BIST_EN_ADDR, MT6350_PMIC_RG_VIO28_BIST_EN_MASK, MT6350_PMIC_RG_VIO28_BIST_EN_SHIFT},
  {PMIC_RG_VRTC_BIST_EN, MT6350_PMIC_RG_VRTC_BIST_EN_ADDR, MT6350_PMIC_RG_VRTC_BIST_EN_MASK, MT6350_PMIC_RG_VRTC_BIST_EN_SHIFT},
  {PMIC_RG_VSIM2_BIST_EN, MT6350_PMIC_RG_VSIM2_BIST_EN_ADDR, MT6350_PMIC_RG_VSIM2_BIST_EN_MASK, MT6350_PMIC_RG_VSIM2_BIST_EN_SHIFT},
  {PMIC_RG_VSIM1_BIST_EN, MT6350_PMIC_RG_VSIM1_BIST_EN_ADDR, MT6350_PMIC_RG_VSIM1_BIST_EN_MASK, MT6350_PMIC_RG_VSIM1_BIST_EN_SHIFT},
  {PMIC_RG_VIBR_BIST_EN, MT6350_PMIC_RG_VIBR_BIST_EN_ADDR, MT6350_PMIC_RG_VIBR_BIST_EN_MASK, MT6350_PMIC_RG_VIBR_BIST_EN_SHIFT},
  {PMIC_RG_VGP3_BIST_EN, MT6350_PMIC_RG_VGP3_BIST_EN_ADDR, MT6350_PMIC_RG_VGP3_BIST_EN_MASK, MT6350_PMIC_RG_VGP3_BIST_EN_SHIFT},
  {PMIC_RG_VGP2_BIST_EN, MT6350_PMIC_RG_VGP2_BIST_EN_ADDR, MT6350_PMIC_RG_VGP2_BIST_EN_MASK, MT6350_PMIC_RG_VGP2_BIST_EN_SHIFT},
  {PMIC_RG_VGP1_BIST_EN, MT6350_PMIC_RG_VGP1_BIST_EN_ADDR, MT6350_PMIC_RG_VGP1_BIST_EN_MASK, MT6350_PMIC_RG_VGP1_BIST_EN_SHIFT},
  {PMIC_QI_VEMC_3V3_OC_STATUS, MT6350_PMIC_QI_VEMC_3V3_OC_STATUS_ADDR, MT6350_PMIC_QI_VEMC_3V3_OC_STATUS_MASK, MT6350_PMIC_QI_VEMC_3V3_OC_STATUS_SHIFT},
  {PMIC_QI_VMCH_OC_STATUS, MT6350_PMIC_QI_VMCH_OC_STATUS_ADDR, MT6350_PMIC_QI_VMCH_OC_STATUS_MASK, MT6350_PMIC_QI_VMCH_OC_STATUS_SHIFT},
  {PMIC_QI_VMC_OC_STATUS, MT6350_PMIC_QI_VMC_OC_STATUS_ADDR, MT6350_PMIC_QI_VMC_OC_STATUS_MASK, MT6350_PMIC_QI_VMC_OC_STATUS_SHIFT},
  {PMIC_QI_VUSB_OC_STATUS, MT6350_PMIC_QI_VUSB_OC_STATUS_ADDR, MT6350_PMIC_QI_VUSB_OC_STATUS_MASK, MT6350_PMIC_QI_VUSB_OC_STATUS_SHIFT},
  {PMIC_QI_VIO28_OC_STATUS, MT6350_PMIC_QI_VIO28_OC_STATUS_ADDR, MT6350_PMIC_QI_VIO28_OC_STATUS_MASK, MT6350_PMIC_QI_VIO28_OC_STATUS_SHIFT},
  {PMIC_QI_VSIM2_OC_STATUS, MT6350_PMIC_QI_VSIM2_OC_STATUS_ADDR, MT6350_PMIC_QI_VSIM2_OC_STATUS_MASK, MT6350_PMIC_QI_VSIM2_OC_STATUS_SHIFT},
  {PMIC_QI_VSIM1_OC_STATUS, MT6350_PMIC_QI_VSIM1_OC_STATUS_ADDR, MT6350_PMIC_QI_VSIM1_OC_STATUS_MASK, MT6350_PMIC_QI_VSIM1_OC_STATUS_SHIFT},
  {PMIC_QI_VIBR_OC_STATUS, MT6350_PMIC_QI_VIBR_OC_STATUS_ADDR, MT6350_PMIC_QI_VIBR_OC_STATUS_MASK, MT6350_PMIC_QI_VIBR_OC_STATUS_SHIFT},
  {PMIC_QI_VGP3_OC_STATUS, MT6350_PMIC_QI_VGP3_OC_STATUS_ADDR, MT6350_PMIC_QI_VGP3_OC_STATUS_MASK, MT6350_PMIC_QI_VGP3_OC_STATUS_SHIFT},
  {PMIC_QI_VGP2_OC_STATUS, MT6350_PMIC_QI_VGP2_OC_STATUS_ADDR, MT6350_PMIC_QI_VGP2_OC_STATUS_MASK, MT6350_PMIC_QI_VGP2_OC_STATUS_SHIFT},
  {PMIC_QI_VGP1_OC_STATUS, MT6350_PMIC_QI_VGP1_OC_STATUS_ADDR, MT6350_PMIC_QI_VGP1_OC_STATUS_MASK, MT6350_PMIC_QI_VGP1_OC_STATUS_SHIFT},
  {PMIC_RG_STB_SIM2_SIO, MT6350_PMIC_RG_STB_SIM2_SIO_ADDR, MT6350_PMIC_RG_STB_SIM2_SIO_MASK, MT6350_PMIC_RG_STB_SIM2_SIO_SHIFT},
  {PMIC_RG_SIMLS2_IES_OFF, MT6350_PMIC_RG_SIMLS2_IES_OFF_ADDR, MT6350_PMIC_RG_SIMLS2_IES_OFF_MASK, MT6350_PMIC_RG_SIMLS2_IES_OFF_SHIFT},
  {PMIC_RE_DIGLDORSV2, MT6350_PMIC_RE_DIGLDORSV2_ADDR, MT6350_PMIC_RE_DIGLDORSV2_MASK, MT6350_PMIC_RE_DIGLDORSV2_SHIFT},
  {PMIC_RG_VIO28_NDIS_EN, MT6350_PMIC_RG_VIO28_NDIS_EN_ADDR, MT6350_PMIC_RG_VIO28_NDIS_EN_MASK, MT6350_PMIC_RG_VIO28_NDIS_EN_SHIFT},
  {PMIC_RG_VIO28_OCFB, MT6350_PMIC_RG_VIO28_OCFB_ADDR, MT6350_PMIC_RG_VIO28_OCFB_MASK, MT6350_PMIC_RG_VIO28_OCFB_SHIFT},
  {PMIC_RG_VIO28_CAL, MT6350_PMIC_RG_VIO28_CAL_ADDR, MT6350_PMIC_RG_VIO28_CAL_MASK, MT6350_PMIC_RG_VIO28_CAL_SHIFT},
  {PMIC_RG_VUSB_NDIS_EN, MT6350_PMIC_RG_VUSB_NDIS_EN_ADDR, MT6350_PMIC_RG_VUSB_NDIS_EN_MASK, MT6350_PMIC_RG_VUSB_NDIS_EN_SHIFT},
  {PMIC_RG_VUSB_OCFB, MT6350_PMIC_RG_VUSB_OCFB_ADDR, MT6350_PMIC_RG_VUSB_OCFB_MASK, MT6350_PMIC_RG_VUSB_OCFB_SHIFT},
  {PMIC_RG_VUSB_CAL, MT6350_PMIC_RG_VUSB_CAL_ADDR, MT6350_PMIC_RG_VUSB_CAL_MASK, MT6350_PMIC_RG_VUSB_CAL_SHIFT},
  {PMIC_RG_VMC_NDIS_EN, MT6350_PMIC_RG_VMC_NDIS_EN_ADDR, MT6350_PMIC_RG_VMC_NDIS_EN_MASK, MT6350_PMIC_RG_VMC_NDIS_EN_SHIFT},
  {PMIC_VMC_ON_CTRL, MT6350_PMIC_VMC_ON_CTRL_ADDR, MT6350_PMIC_VMC_ON_CTRL_MASK, MT6350_PMIC_VMC_ON_CTRL_SHIFT},
  {PMIC_RG_VMC_OCFB, MT6350_PMIC_RG_VMC_OCFB_ADDR, MT6350_PMIC_RG_VMC_OCFB_MASK, MT6350_PMIC_RG_VMC_OCFB_SHIFT},
  {PMIC_RG_VMC_VOSEL, MT6350_PMIC_RG_VMC_VOSEL_ADDR, MT6350_PMIC_RG_VMC_VOSEL_MASK, MT6350_PMIC_RG_VMC_VOSEL_SHIFT},
  {PMIC_RG_VMC_STB_SEL, MT6350_PMIC_RG_VMC_STB_SEL_ADDR, MT6350_PMIC_RG_VMC_STB_SEL_MASK, MT6350_PMIC_RG_VMC_STB_SEL_SHIFT},
  {PMIC_RG_VMC_STB_SEL_CAL, MT6350_PMIC_RG_VMC_STB_SEL_CAL_ADDR, MT6350_PMIC_RG_VMC_STB_SEL_CAL_MASK, MT6350_PMIC_RG_VMC_STB_SEL_CAL_SHIFT},
  {PMIC_RG_VMC_CAL, MT6350_PMIC_RG_VMC_CAL_ADDR, MT6350_PMIC_RG_VMC_CAL_MASK, MT6350_PMIC_RG_VMC_CAL_SHIFT},
  {PMIC_RG_VMCH_NDIS_EN, MT6350_PMIC_RG_VMCH_NDIS_EN_ADDR, MT6350_PMIC_RG_VMCH_NDIS_EN_MASK, MT6350_PMIC_RG_VMCH_NDIS_EN_SHIFT},
  {PMIC_VMCH_ON_CTRL, MT6350_PMIC_VMCH_ON_CTRL_ADDR, MT6350_PMIC_VMCH_ON_CTRL_MASK, MT6350_PMIC_VMCH_ON_CTRL_SHIFT},
  {PMIC_RG_VMCH_OCFB, MT6350_PMIC_RG_VMCH_OCFB_ADDR, MT6350_PMIC_RG_VMCH_OCFB_MASK, MT6350_PMIC_RG_VMCH_OCFB_SHIFT},
  {PMIC_RG_VMCH_DB_EN, MT6350_PMIC_RG_VMCH_DB_EN_ADDR, MT6350_PMIC_RG_VMCH_DB_EN_MASK, MT6350_PMIC_RG_VMCH_DB_EN_SHIFT},
  {PMIC_RG_VMCH_STB_SEL, MT6350_PMIC_RG_VMCH_STB_SEL_ADDR, MT6350_PMIC_RG_VMCH_STB_SEL_MASK, MT6350_PMIC_RG_VMCH_STB_SEL_SHIFT},
  {PMIC_RG_VMCH_VOSEL, MT6350_PMIC_RG_VMCH_VOSEL_ADDR, MT6350_PMIC_RG_VMCH_VOSEL_MASK, MT6350_PMIC_RG_VMCH_VOSEL_SHIFT},
  {PMIC_RG_VMCH_STB_SEL_CAL, MT6350_PMIC_RG_VMCH_STB_SEL_CAL_ADDR, MT6350_PMIC_RG_VMCH_STB_SEL_CAL_MASK, MT6350_PMIC_RG_VMCH_STB_SEL_CAL_SHIFT},
  {PMIC_RG_VMCH_CAL, MT6350_PMIC_RG_VMCH_CAL_ADDR, MT6350_PMIC_RG_VMCH_CAL_MASK, MT6350_PMIC_RG_VMCH_CAL_SHIFT},
  {PMIC_RG_VEMC_3V3_NDIS_EN, MT6350_PMIC_RG_VEMC_3V3_NDIS_EN_ADDR, MT6350_PMIC_RG_VEMC_3V3_NDIS_EN_MASK, MT6350_PMIC_RG_VEMC_3V3_NDIS_EN_SHIFT},
  {PMIC_VEMC_3V3_ON_CTRL, MT6350_PMIC_VEMC_3V3_ON_CTRL_ADDR, MT6350_PMIC_VEMC_3V3_ON_CTRL_MASK, MT6350_PMIC_VEMC_3V3_ON_CTRL_SHIFT},
  {PMIC_RG_VEMC_3V3_OCFB, MT6350_PMIC_RG_VEMC_3V3_OCFB_ADDR, MT6350_PMIC_RG_VEMC_3V3_OCFB_MASK, MT6350_PMIC_RG_VEMC_3V3_OCFB_SHIFT},
  {PMIC_RG_VEMC_3V3_DL_EN, MT6350_PMIC_RG_VEMC_3V3_DL_EN_ADDR, MT6350_PMIC_RG_VEMC_3V3_DL_EN_MASK, MT6350_PMIC_RG_VEMC_3V3_DL_EN_SHIFT},
  {PMIC_RG_VEMC_3V3_DB_EN, MT6350_PMIC_RG_VEMC_3V3_DB_EN_ADDR, MT6350_PMIC_RG_VEMC_3V3_DB_EN_MASK, MT6350_PMIC_RG_VEMC_3V3_DB_EN_SHIFT},
  {PMIC_RG_VEMC_3V3_STB_SEL, MT6350_PMIC_RG_VEMC_3V3_STB_SEL_ADDR, MT6350_PMIC_RG_VEMC_3V3_STB_SEL_MASK, MT6350_PMIC_RG_VEMC_3V3_STB_SEL_SHIFT},
  {PMIC_RG_VEMC_3V3_VOSEL, MT6350_PMIC_RG_VEMC_3V3_VOSEL_ADDR, MT6350_PMIC_RG_VEMC_3V3_VOSEL_MASK, MT6350_PMIC_RG_VEMC_3V3_VOSEL_SHIFT},
  {PMIC_RG_VEMC_3V3_STB_SEL_CAL, MT6350_PMIC_RG_VEMC_3V3_STB_SEL_CAL_ADDR, MT6350_PMIC_RG_VEMC_3V3_STB_SEL_CAL_MASK, MT6350_PMIC_RG_VEMC_3V3_STB_SEL_CAL_SHIFT},
  {PMIC_RG_VEMC_3V3_CAL, MT6350_PMIC_RG_VEMC_3V3_CAL_ADDR, MT6350_PMIC_RG_VEMC_3V3_CAL_MASK, MT6350_PMIC_RG_VEMC_3V3_CAL_SHIFT},
  {PMIC_RG_VGP1_NDIS_EN, MT6350_PMIC_RG_VGP1_NDIS_EN_ADDR, MT6350_PMIC_RG_VGP1_NDIS_EN_MASK, MT6350_PMIC_RG_VGP1_NDIS_EN_SHIFT},
  {PMIC_RG_VGP1_OCFB, MT6350_PMIC_RG_VGP1_OCFB_ADDR, MT6350_PMIC_RG_VGP1_OCFB_MASK, MT6350_PMIC_RG_VGP1_OCFB_SHIFT},
  {PMIC_RG_VGP1_STB_SEL, MT6350_PMIC_RG_VGP1_STB_SEL_ADDR, MT6350_PMIC_RG_VGP1_STB_SEL_MASK, MT6350_PMIC_RG_VGP1_STB_SEL_SHIFT},
  {PMIC_RG_VGP1_VOSEL, MT6350_PMIC_RG_VGP1_VOSEL_ADDR, MT6350_PMIC_RG_VGP1_VOSEL_MASK, MT6350_PMIC_RG_VGP1_VOSEL_SHIFT},
  {PMIC_RG_VGP1_CAL, MT6350_PMIC_RG_VGP1_CAL_ADDR, MT6350_PMIC_RG_VGP1_CAL_MASK, MT6350_PMIC_RG_VGP1_CAL_SHIFT},
  {PMIC_RG_VGP2_NDIS_EN, MT6350_PMIC_RG_VGP2_NDIS_EN_ADDR, MT6350_PMIC_RG_VGP2_NDIS_EN_MASK, MT6350_PMIC_RG_VGP2_NDIS_EN_SHIFT},
  {PMIC_RG_VGP2_OCFB, MT6350_PMIC_RG_VGP2_OCFB_ADDR, MT6350_PMIC_RG_VGP2_OCFB_MASK, MT6350_PMIC_RG_VGP2_OCFB_SHIFT},
  {PMIC_RG_VGP2_STB_SEL, MT6350_PMIC_RG_VGP2_STB_SEL_ADDR, MT6350_PMIC_RG_VGP2_STB_SEL_MASK, MT6350_PMIC_RG_VGP2_STB_SEL_SHIFT},
  {PMIC_RG_VGP2_VOSEL, MT6350_PMIC_RG_VGP2_VOSEL_ADDR, MT6350_PMIC_RG_VGP2_VOSEL_MASK, MT6350_PMIC_RG_VGP2_VOSEL_SHIFT},
  {PMIC_RG_VGP2_CAL, MT6350_PMIC_RG_VGP2_CAL_ADDR, MT6350_PMIC_RG_VGP2_CAL_MASK, MT6350_PMIC_RG_VGP2_CAL_SHIFT},
  {PMIC_RG_VGP3_NDIS_EN, MT6350_PMIC_RG_VGP3_NDIS_EN_ADDR, MT6350_PMIC_RG_VGP3_NDIS_EN_MASK, MT6350_PMIC_RG_VGP3_NDIS_EN_SHIFT},
  {PMIC_RG_VGP3_OCFB, MT6350_PMIC_RG_VGP3_OCFB_ADDR, MT6350_PMIC_RG_VGP3_OCFB_MASK, MT6350_PMIC_RG_VGP3_OCFB_SHIFT},
  {PMIC_RG_VGP3_STB_SEL, MT6350_PMIC_RG_VGP3_STB_SEL_ADDR, MT6350_PMIC_RG_VGP3_STB_SEL_MASK, MT6350_PMIC_RG_VGP3_STB_SEL_SHIFT},
  {PMIC_RG_VGP3_VOSEL, MT6350_PMIC_RG_VGP3_VOSEL_ADDR, MT6350_PMIC_RG_VGP3_VOSEL_MASK, MT6350_PMIC_RG_VGP3_VOSEL_SHIFT},
  {PMIC_RG_VGP3_CAL, MT6350_PMIC_RG_VGP3_CAL_ADDR, MT6350_PMIC_RG_VGP3_CAL_MASK, MT6350_PMIC_RG_VGP3_CAL_SHIFT},
  {PMIC_VCAM_AF_LP_SEL, MT6350_PMIC_VCAM_AF_LP_SEL_ADDR, MT6350_PMIC_VCAM_AF_LP_SEL_MASK, MT6350_PMIC_VCAM_AF_LP_SEL_SHIFT},
  {PMIC_VCAM_AF_LP_MODE_SET, MT6350_PMIC_VCAM_AF_LP_MODE_SET_ADDR, MT6350_PMIC_VCAM_AF_LP_MODE_SET_MASK, MT6350_PMIC_VCAM_AF_LP_MODE_SET_SHIFT},
  {PMIC_QI_VCAM_AF_MODE, MT6350_PMIC_QI_VCAM_AF_MODE_ADDR, MT6350_PMIC_QI_VCAM_AF_MODE_MASK, MT6350_PMIC_QI_VCAM_AF_MODE_SHIFT},
  {PMIC_RG_VCAM_AF_STBTD, MT6350_PMIC_RG_VCAM_AF_STBTD_ADDR, MT6350_PMIC_RG_VCAM_AF_STBTD_MASK, MT6350_PMIC_RG_VCAM_AF_STBTD_SHIFT},
  {PMIC_RG_VCAM_AF_EN, MT6350_PMIC_RG_VCAM_AF_EN_ADDR, MT6350_PMIC_RG_VCAM_AF_EN_MASK, MT6350_PMIC_RG_VCAM_AF_EN_SHIFT},
  {PMIC_RG_VCAM_AF_NDIS_EN, MT6350_PMIC_RG_VCAM_AF_NDIS_EN_ADDR, MT6350_PMIC_RG_VCAM_AF_NDIS_EN_MASK, MT6350_PMIC_RG_VCAM_AF_NDIS_EN_SHIFT},
  {PMIC_RG_VCAM_AF_OCFB, MT6350_PMIC_RG_VCAM_AF_OCFB_ADDR, MT6350_PMIC_RG_VCAM_AF_OCFB_MASK, MT6350_PMIC_RG_VCAM_AF_OCFB_SHIFT},
  {PMIC_VCAM_AF_ON_CTRL, MT6350_PMIC_VCAM_AF_ON_CTRL_ADDR, MT6350_PMIC_VCAM_AF_ON_CTRL_MASK, MT6350_PMIC_VCAM_AF_ON_CTRL_SHIFT},
  {PMIC_RG_VCAM_AF_STB_SEL, MT6350_PMIC_RG_VCAM_AF_STB_SEL_ADDR, MT6350_PMIC_RG_VCAM_AF_STB_SEL_MASK, MT6350_PMIC_RG_VCAM_AF_STB_SEL_SHIFT},
  {PMIC_RG_VCAM_AF_VOSEL, MT6350_PMIC_RG_VCAM_AF_VOSEL_ADDR, MT6350_PMIC_RG_VCAM_AF_VOSEL_MASK, MT6350_PMIC_RG_VCAM_AF_VOSEL_SHIFT},
  {PMIC_RG_VCAM_AF_CAL, MT6350_PMIC_RG_VCAM_AF_CAL_ADDR, MT6350_PMIC_RG_VCAM_AF_CAL_MASK, MT6350_PMIC_RG_VCAM_AF_CAL_SHIFT},
  {PMIC_RE_DIGLDORSV3, MT6350_PMIC_RE_DIGLDORSV3_ADDR, MT6350_PMIC_RE_DIGLDORSV3_MASK, MT6350_PMIC_RE_DIGLDORSV3_SHIFT},
  {PMIC_RG_VSIM1_NDIS_EN, MT6350_PMIC_RG_VSIM1_NDIS_EN_ADDR, MT6350_PMIC_RG_VSIM1_NDIS_EN_MASK, MT6350_PMIC_RG_VSIM1_NDIS_EN_SHIFT},
  {PMIC_RG_VSIM1_OCFB, MT6350_PMIC_RG_VSIM1_OCFB_ADDR, MT6350_PMIC_RG_VSIM1_OCFB_MASK, MT6350_PMIC_RG_VSIM1_OCFB_SHIFT},
  {PMIC_RG_VSIM1_STB_SEL, MT6350_PMIC_RG_VSIM1_STB_SEL_ADDR, MT6350_PMIC_RG_VSIM1_STB_SEL_MASK, MT6350_PMIC_RG_VSIM1_STB_SEL_SHIFT},
  {PMIC_RG_VSIM1_VOSEL, MT6350_PMIC_RG_VSIM1_VOSEL_ADDR, MT6350_PMIC_RG_VSIM1_VOSEL_MASK, MT6350_PMIC_RG_VSIM1_VOSEL_SHIFT},
  {PMIC_RG_VSIM1_CAL, MT6350_PMIC_RG_VSIM1_CAL_ADDR, MT6350_PMIC_RG_VSIM1_CAL_MASK, MT6350_PMIC_RG_VSIM1_CAL_SHIFT},
  {PMIC_RG_VSIM2_NDIS_EN, MT6350_PMIC_RG_VSIM2_NDIS_EN_ADDR, MT6350_PMIC_RG_VSIM2_NDIS_EN_MASK, MT6350_PMIC_RG_VSIM2_NDIS_EN_SHIFT},
  {PMIC_RG_VSIM2_OCFB, MT6350_PMIC_RG_VSIM2_OCFB_ADDR, MT6350_PMIC_RG_VSIM2_OCFB_MASK, MT6350_PMIC_RG_VSIM2_OCFB_SHIFT},
  {PMIC_RG_VSIM2_STB_SEL, MT6350_PMIC_RG_VSIM2_STB_SEL_ADDR, MT6350_PMIC_RG_VSIM2_STB_SEL_MASK, MT6350_PMIC_RG_VSIM2_STB_SEL_SHIFT},
  {PMIC_RG_VSIM2_VOSEL, MT6350_PMIC_RG_VSIM2_VOSEL_ADDR, MT6350_PMIC_RG_VSIM2_VOSEL_MASK, MT6350_PMIC_RG_VSIM2_VOSEL_SHIFT},
  {PMIC_RG_VSIM2_CAL, MT6350_PMIC_RG_VSIM2_CAL_ADDR, MT6350_PMIC_RG_VSIM2_CAL_MASK, MT6350_PMIC_RG_VSIM2_CAL_SHIFT},
  {PMIC_RG_VSYSLDO_RESERVE, MT6350_PMIC_RG_VSYSLDO_RESERVE_ADDR, MT6350_PMIC_RG_VSYSLDO_RESERVE_MASK, MT6350_PMIC_RG_VSYSLDO_RESERVE_SHIFT},
  {PMIC_VIBR_LP_SEL, MT6350_PMIC_VIBR_LP_SEL_ADDR, MT6350_PMIC_VIBR_LP_SEL_MASK, MT6350_PMIC_VIBR_LP_SEL_SHIFT},
  {PMIC_VIBR_LP_MODE_SET, MT6350_PMIC_VIBR_LP_MODE_SET_ADDR, MT6350_PMIC_VIBR_LP_MODE_SET_MASK, MT6350_PMIC_VIBR_LP_MODE_SET_SHIFT},
  {PMIC_VIBR_THER_SHEN_EN, MT6350_PMIC_VIBR_THER_SHEN_EN_ADDR, MT6350_PMIC_VIBR_THER_SHEN_EN_MASK, MT6350_PMIC_VIBR_THER_SHEN_EN_SHIFT},
  {PMIC_QI_VIBR_MODE, MT6350_PMIC_QI_VIBR_MODE_ADDR, MT6350_PMIC_QI_VIBR_MODE_MASK, MT6350_PMIC_QI_VIBR_MODE_SHIFT},
  {PMIC_RG_VIBR_STBTD, MT6350_PMIC_RG_VIBR_STBTD_ADDR, MT6350_PMIC_RG_VIBR_STBTD_MASK, MT6350_PMIC_RG_VIBR_STBTD_SHIFT},
  {PMIC_RG_VIBR_EN, MT6350_PMIC_RG_VIBR_EN_ADDR, MT6350_PMIC_RG_VIBR_EN_MASK, MT6350_PMIC_RG_VIBR_EN_SHIFT},
  {PMIC_RG_VIBR_NDIS_EN, MT6350_PMIC_RG_VIBR_NDIS_EN_ADDR, MT6350_PMIC_RG_VIBR_NDIS_EN_MASK, MT6350_PMIC_RG_VIBR_NDIS_EN_SHIFT},
  {PMIC_RG_VIBR_OCFB, MT6350_PMIC_RG_VIBR_OCFB_ADDR, MT6350_PMIC_RG_VIBR_OCFB_MASK, MT6350_PMIC_RG_VIBR_OCFB_SHIFT},
  {PMIC_RG_VIBR_STB_SEL, MT6350_PMIC_RG_VIBR_STB_SEL_ADDR, MT6350_PMIC_RG_VIBR_STB_SEL_MASK, MT6350_PMIC_RG_VIBR_STB_SEL_SHIFT},
  {PMIC_RG_VIBR_VOSEL, MT6350_PMIC_RG_VIBR_VOSEL_ADDR, MT6350_PMIC_RG_VIBR_VOSEL_MASK, MT6350_PMIC_RG_VIBR_VOSEL_SHIFT},
  {PMIC_RG_VIBR_STB_SEL_CAL, MT6350_PMIC_RG_VIBR_STB_SEL_CAL_ADDR, MT6350_PMIC_RG_VIBR_STB_SEL_CAL_MASK, MT6350_PMIC_RG_VIBR_STB_SEL_CAL_SHIFT},
  {PMIC_RG_VIBR_CAL, MT6350_PMIC_RG_VIBR_CAL_ADDR, MT6350_PMIC_RG_VIBR_CAL_MASK, MT6350_PMIC_RG_VIBR_CAL_SHIFT},
  {PMIC_DIGLDO_RSV1, MT6350_PMIC_DIGLDO_RSV1_ADDR, MT6350_PMIC_DIGLDO_RSV1_MASK, MT6350_PMIC_DIGLDO_RSV1_SHIFT},
  {PMIC_DIGLDO_RSV0, MT6350_PMIC_DIGLDO_RSV0_ADDR, MT6350_PMIC_DIGLDO_RSV0_MASK, MT6350_PMIC_DIGLDO_RSV0_SHIFT},
  {PMIC_RG_LDO_FT, MT6350_PMIC_RG_LDO_FT_ADDR, MT6350_PMIC_RG_LDO_FT_MASK, MT6350_PMIC_RG_LDO_FT_SHIFT},
  {PMIC_QI_VCAM_IO_OC_STATUS, MT6350_PMIC_QI_VCAM_IO_OC_STATUS_ADDR, MT6350_PMIC_QI_VCAM_IO_OC_STATUS_MASK, MT6350_PMIC_QI_VCAM_IO_OC_STATUS_SHIFT},
  {PMIC_QI_VCAMD_OC_STATUS, MT6350_PMIC_QI_VCAMD_OC_STATUS_ADDR, MT6350_PMIC_QI_VCAMD_OC_STATUS_MASK, MT6350_PMIC_QI_VCAMD_OC_STATUS_SHIFT},
  {PMIC_QI_VCN_1V8_OC_STATUS, MT6350_PMIC_QI_VCN_1V8_OC_STATUS_ADDR, MT6350_PMIC_QI_VCN_1V8_OC_STATUS_MASK, MT6350_PMIC_QI_VCN_1V8_OC_STATUS_SHIFT},
  {PMIC_QI_VIO18_OC_STATUS, MT6350_PMIC_QI_VIO18_OC_STATUS_ADDR, MT6350_PMIC_QI_VIO18_OC_STATUS_MASK, MT6350_PMIC_QI_VIO18_OC_STATUS_SHIFT},
  {PMIC_QI_VRF18_OC_STATUS, MT6350_PMIC_QI_VRF18_OC_STATUS_ADDR, MT6350_PMIC_QI_VRF18_OC_STATUS_MASK, MT6350_PMIC_QI_VRF18_OC_STATUS_SHIFT},
  {PMIC_QI_VM_OC_STATUS, MT6350_PMIC_QI_VM_OC_STATUS_ADDR, MT6350_PMIC_QI_VM_OC_STATUS_MASK, MT6350_PMIC_QI_VM_OC_STATUS_SHIFT},
  {PMIC_QI_VCAM_AF_OC_STATUS, MT6350_PMIC_QI_VCAM_AF_OC_STATUS_ADDR, MT6350_PMIC_QI_VCAM_AF_OC_STATUS_MASK, MT6350_PMIC_QI_VCAM_AF_OC_STATUS_SHIFT},
  {PMIC_RG_VCAM_AF_BIST_EN, MT6350_PMIC_RG_VCAM_AF_BIST_EN_ADDR, MT6350_PMIC_RG_VCAM_AF_BIST_EN_MASK, MT6350_PMIC_RG_VCAM_AF_BIST_EN_SHIFT},
  {PMIC_RG_VCAMD_IO_BIST_EN, MT6350_PMIC_RG_VCAMD_IO_BIST_EN_ADDR, MT6350_PMIC_RG_VCAMD_IO_BIST_EN_MASK, MT6350_PMIC_RG_VCAMD_IO_BIST_EN_SHIFT},
  {PMIC_RG_VCN_1V8_BIST_EN, MT6350_PMIC_RG_VCN_1V8_BIST_EN_ADDR, MT6350_PMIC_RG_VCN_1V8_BIST_EN_MASK, MT6350_PMIC_RG_VCN_1V8_BIST_EN_SHIFT},
  {PMIC_RG_VCAMD_BIST_EN, MT6350_PMIC_RG_VCAMD_BIST_EN_ADDR, MT6350_PMIC_RG_VCAMD_BIST_EN_MASK, MT6350_PMIC_RG_VCAMD_BIST_EN_SHIFT},
  {PMIC_RG_VIO18_BIST_EN, MT6350_PMIC_RG_VIO18_BIST_EN_ADDR, MT6350_PMIC_RG_VIO18_BIST_EN_MASK, MT6350_PMIC_RG_VIO18_BIST_EN_SHIFT},
  {PMIC_RG_VM_BIST_EN, MT6350_PMIC_RG_VM_BIST_EN_ADDR, MT6350_PMIC_RG_VM_BIST_EN_MASK, MT6350_PMIC_RG_VM_BIST_EN_SHIFT},
  {PMIC_RG_VRF18_BIST_EN, MT6350_PMIC_RG_VRF18_BIST_EN_ADDR, MT6350_PMIC_RG_VRF18_BIST_EN_MASK, MT6350_PMIC_RG_VRF18_BIST_EN_SHIFT},
  {PMIC_VIBR_ON_CTRL, MT6350_PMIC_VIBR_ON_CTRL_ADDR, MT6350_PMIC_VIBR_ON_CTRL_MASK, MT6350_PMIC_VIBR_ON_CTRL_SHIFT},
  {PMIC_VSIM2_ON_CTRL, MT6350_PMIC_VSIM2_ON_CTRL_ADDR, MT6350_PMIC_VSIM2_ON_CTRL_MASK, MT6350_PMIC_VSIM2_ON_CTRL_SHIFT},
  {PMIC_VSIM1_ON_CTRL, MT6350_PMIC_VSIM1_ON_CTRL_ADDR, MT6350_PMIC_VSIM1_ON_CTRL_MASK, MT6350_PMIC_VSIM1_ON_CTRL_SHIFT},
  {PMIC_VGP3_ON_CTRL, MT6350_PMIC_VGP3_ON_CTRL_ADDR, MT6350_PMIC_VGP3_ON_CTRL_MASK, MT6350_PMIC_VGP3_ON_CTRL_SHIFT},
  {PMIC_VGP2_ON_CTRL, MT6350_PMIC_VGP2_ON_CTRL_ADDR, MT6350_PMIC_VGP2_ON_CTRL_MASK, MT6350_PMIC_VGP2_ON_CTRL_SHIFT},
  {PMIC_VGP1_ON_CTRL, MT6350_PMIC_VGP1_ON_CTRL_ADDR, MT6350_PMIC_VGP1_ON_CTRL_MASK, MT6350_PMIC_VGP1_ON_CTRL_SHIFT},
  {PMIC_VRF18_LP_SEL, MT6350_PMIC_VRF18_LP_SEL_ADDR, MT6350_PMIC_VRF18_LP_SEL_MASK, MT6350_PMIC_VRF18_LP_SEL_SHIFT},
  {PMIC_VRF18_LP_MODE_SET, MT6350_PMIC_VRF18_LP_MODE_SET_ADDR, MT6350_PMIC_VRF18_LP_MODE_SET_MASK, MT6350_PMIC_VRF18_LP_MODE_SET_SHIFT},
  {PMIC_QI_VRF18_MODE, MT6350_PMIC_QI_VRF18_MODE_ADDR, MT6350_PMIC_QI_VRF18_MODE_MASK, MT6350_PMIC_QI_VRF18_MODE_SHIFT},
  {PMIC_RG_VRF18_STBTD, MT6350_PMIC_RG_VRF18_STBTD_ADDR, MT6350_PMIC_RG_VRF18_STBTD_MASK, MT6350_PMIC_RG_VRF18_STBTD_SHIFT},
  {PMIC_RG_VRF18_EN, MT6350_PMIC_RG_VRF18_EN_ADDR, MT6350_PMIC_RG_VRF18_EN_MASK, MT6350_PMIC_RG_VRF18_EN_SHIFT},
  {PMIC_RG_VRF18_NDIS_EN, MT6350_PMIC_RG_VRF18_NDIS_EN_ADDR, MT6350_PMIC_RG_VRF18_NDIS_EN_MASK, MT6350_PMIC_RG_VRF18_NDIS_EN_SHIFT},
  {PMIC_VRF18_ON_CTRL, MT6350_PMIC_VRF18_ON_CTRL_ADDR, MT6350_PMIC_VRF18_ON_CTRL_MASK, MT6350_PMIC_VRF18_ON_CTRL_SHIFT},
  {PMIC_RG_VRF18_OCFB, MT6350_PMIC_RG_VRF18_OCFB_ADDR, MT6350_PMIC_RG_VRF18_OCFB_MASK, MT6350_PMIC_RG_VRF18_OCFB_SHIFT},
  {PMIC_RG_VRF18_STB_SEL, MT6350_PMIC_RG_VRF18_STB_SEL_ADDR, MT6350_PMIC_RG_VRF18_STB_SEL_MASK, MT6350_PMIC_RG_VRF18_STB_SEL_SHIFT},
  {PMIC_RG_VRF18_CAL, MT6350_PMIC_RG_VRF18_CAL_ADDR, MT6350_PMIC_RG_VRF18_CAL_MASK, MT6350_PMIC_RG_VRF18_CAL_SHIFT},
  {PMIC_VM_LP_SEL, MT6350_PMIC_VM_LP_SEL_ADDR, MT6350_PMIC_VM_LP_SEL_MASK, MT6350_PMIC_VM_LP_SEL_SHIFT},
  {PMIC_VM_LP_MODE_SET, MT6350_PMIC_VM_LP_MODE_SET_ADDR, MT6350_PMIC_VM_LP_MODE_SET_MASK, MT6350_PMIC_VM_LP_MODE_SET_SHIFT},
  {PMIC_QI_VM_MODE, MT6350_PMIC_QI_VM_MODE_ADDR, MT6350_PMIC_QI_VM_MODE_MASK, MT6350_PMIC_QI_VM_MODE_SHIFT},
  {PMIC_RG_VM_STBTD, MT6350_PMIC_RG_VM_STBTD_ADDR, MT6350_PMIC_RG_VM_STBTD_MASK, MT6350_PMIC_RG_VM_STBTD_SHIFT},
  {PMIC_RG_VM_EN, MT6350_PMIC_RG_VM_EN_ADDR, MT6350_PMIC_RG_VM_EN_MASK, MT6350_PMIC_RG_VM_EN_SHIFT},
  {PMIC_QI_VM_EN, MT6350_PMIC_QI_VM_EN_ADDR, MT6350_PMIC_QI_VM_EN_MASK, MT6350_PMIC_QI_VM_EN_SHIFT},
  {PMIC_RG_VM_NDIS_EN, MT6350_PMIC_RG_VM_NDIS_EN_ADDR, MT6350_PMIC_RG_VM_NDIS_EN_MASK, MT6350_PMIC_RG_VM_NDIS_EN_SHIFT},
  {PMIC_RG_VM_PLCUR_EN, MT6350_PMIC_RG_VM_PLCUR_EN_ADDR, MT6350_PMIC_RG_VM_PLCUR_EN_MASK, MT6350_PMIC_RG_VM_PLCUR_EN_SHIFT},
  {PMIC_RG_VM_PLCUR_CAL, MT6350_PMIC_RG_VM_PLCUR_CAL_ADDR, MT6350_PMIC_RG_VM_PLCUR_CAL_MASK, MT6350_PMIC_RG_VM_PLCUR_CAL_SHIFT},
  {PMIC_RG_VM_VOSEL, MT6350_PMIC_RG_VM_VOSEL_ADDR, MT6350_PMIC_RG_VM_VOSEL_MASK, MT6350_PMIC_RG_VM_VOSEL_SHIFT},
  {PMIC_RG_VM_OCFB, MT6350_PMIC_RG_VM_OCFB_ADDR, MT6350_PMIC_RG_VM_OCFB_MASK, MT6350_PMIC_RG_VM_OCFB_SHIFT},
  {PMIC_RG_VM_CAL, MT6350_PMIC_RG_VM_CAL_ADDR, MT6350_PMIC_RG_VM_CAL_MASK, MT6350_PMIC_RG_VM_CAL_SHIFT},
  {PMIC_VIO18_LP_SEL, MT6350_PMIC_VIO18_LP_SEL_ADDR, MT6350_PMIC_VIO18_LP_SEL_MASK, MT6350_PMIC_VIO18_LP_SEL_SHIFT},
  {PMIC_VIO18_LP_MODE_SET, MT6350_PMIC_VIO18_LP_MODE_SET_ADDR, MT6350_PMIC_VIO18_LP_MODE_SET_MASK, MT6350_PMIC_VIO18_LP_MODE_SET_SHIFT},
  {PMIC_QI_VIO18_MODE, MT6350_PMIC_QI_VIO18_MODE_ADDR, MT6350_PMIC_QI_VIO18_MODE_MASK, MT6350_PMIC_QI_VIO18_MODE_SHIFT},
  {PMIC_RG_VIO18_STBTD, MT6350_PMIC_RG_VIO18_STBTD_ADDR, MT6350_PMIC_RG_VIO18_STBTD_MASK, MT6350_PMIC_RG_VIO18_STBTD_SHIFT},
  {PMIC_RG_VIO18_EN, MT6350_PMIC_RG_VIO18_EN_ADDR, MT6350_PMIC_RG_VIO18_EN_MASK, MT6350_PMIC_RG_VIO18_EN_SHIFT},
  {PMIC_QI_VIO18_EN, MT6350_PMIC_QI_VIO18_EN_ADDR, MT6350_PMIC_QI_VIO18_EN_MASK, MT6350_PMIC_QI_VIO18_EN_SHIFT},
  {PMIC_RG_VIO18_NDIS_EN, MT6350_PMIC_RG_VIO18_NDIS_EN_ADDR, MT6350_PMIC_RG_VIO18_NDIS_EN_MASK, MT6350_PMIC_RG_VIO18_NDIS_EN_SHIFT},
  {PMIC_VIO18_ON_CTRL, MT6350_PMIC_VIO18_ON_CTRL_ADDR, MT6350_PMIC_VIO18_ON_CTRL_MASK, MT6350_PMIC_VIO18_ON_CTRL_SHIFT},
  {PMIC_RG_VIO18_OCFB, MT6350_PMIC_RG_VIO18_OCFB_ADDR, MT6350_PMIC_RG_VIO18_OCFB_MASK, MT6350_PMIC_RG_VIO18_OCFB_SHIFT},
  {PMIC_RG_VIO18_STB_SEL, MT6350_PMIC_RG_VIO18_STB_SEL_ADDR, MT6350_PMIC_RG_VIO18_STB_SEL_MASK, MT6350_PMIC_RG_VIO18_STB_SEL_SHIFT},
  {PMIC_RG_VIO18_CAL, MT6350_PMIC_RG_VIO18_CAL_ADDR, MT6350_PMIC_RG_VIO18_CAL_MASK, MT6350_PMIC_RG_VIO18_CAL_SHIFT},
  {PMIC_VCAMD_LP_SEL, MT6350_PMIC_VCAMD_LP_SEL_ADDR, MT6350_PMIC_VCAMD_LP_SEL_MASK, MT6350_PMIC_VCAMD_LP_SEL_SHIFT},
  {PMIC_VCAMD_LP_MODE_SET, MT6350_PMIC_VCAMD_LP_MODE_SET_ADDR, MT6350_PMIC_VCAMD_LP_MODE_SET_MASK, MT6350_PMIC_VCAMD_LP_MODE_SET_SHIFT},
  {PMIC_QI_VCAMD_MODE, MT6350_PMIC_QI_VCAMD_MODE_ADDR, MT6350_PMIC_QI_VCAMD_MODE_MASK, MT6350_PMIC_QI_VCAMD_MODE_SHIFT},
  {PMIC_RG_VCAMD_STBTD, MT6350_PMIC_RG_VCAMD_STBTD_ADDR, MT6350_PMIC_RG_VCAMD_STBTD_MASK, MT6350_PMIC_RG_VCAMD_STBTD_SHIFT},
  {PMIC_RG_VCAMD_EN, MT6350_PMIC_RG_VCAMD_EN_ADDR, MT6350_PMIC_RG_VCAMD_EN_MASK, MT6350_PMIC_RG_VCAMD_EN_SHIFT},
  {PMIC_QI_VCAMD_EN, MT6350_PMIC_QI_VCAMD_EN_ADDR, MT6350_PMIC_QI_VCAMD_EN_MASK, MT6350_PMIC_QI_VCAMD_EN_SHIFT},
  {PMIC_RG_VCAMD_NDIS_EN, MT6350_PMIC_RG_VCAMD_NDIS_EN_ADDR, MT6350_PMIC_RG_VCAMD_NDIS_EN_MASK, MT6350_PMIC_RG_VCAMD_NDIS_EN_SHIFT},
  {PMIC_VCAMD_ON_CTRL, MT6350_PMIC_VCAMD_ON_CTRL_ADDR, MT6350_PMIC_VCAMD_ON_CTRL_MASK, MT6350_PMIC_VCAMD_ON_CTRL_SHIFT},
  {PMIC_RG_VCAMD_OCFB, MT6350_PMIC_RG_VCAMD_OCFB_ADDR, MT6350_PMIC_RG_VCAMD_OCFB_MASK, MT6350_PMIC_RG_VCAMD_OCFB_SHIFT},
  {PMIC_RG_VCAMD_STB_SEL, MT6350_PMIC_RG_VCAMD_STB_SEL_ADDR, MT6350_PMIC_RG_VCAMD_STB_SEL_MASK, MT6350_PMIC_RG_VCAMD_STB_SEL_SHIFT},
  {PMIC_RG_VCAMD_VOSEL, MT6350_PMIC_RG_VCAMD_VOSEL_ADDR, MT6350_PMIC_RG_VCAMD_VOSEL_MASK, MT6350_PMIC_RG_VCAMD_VOSEL_SHIFT},
  {PMIC_RG_VCAMD_CAL, MT6350_PMIC_RG_VCAMD_CAL_ADDR, MT6350_PMIC_RG_VCAMD_CAL_MASK, MT6350_PMIC_RG_VCAMD_CAL_SHIFT},
  {PMIC_VCAM_IO_LP_SEL, MT6350_PMIC_VCAM_IO_LP_SEL_ADDR, MT6350_PMIC_VCAM_IO_LP_SEL_MASK, MT6350_PMIC_VCAM_IO_LP_SEL_SHIFT},
  {PMIC_VCAM_IO_LP_MODE_SET, MT6350_PMIC_VCAM_IO_LP_MODE_SET_ADDR, MT6350_PMIC_VCAM_IO_LP_MODE_SET_MASK, MT6350_PMIC_VCAM_IO_LP_MODE_SET_SHIFT},
  {PMIC_QI_VCAM_IO_MODE, MT6350_PMIC_QI_VCAM_IO_MODE_ADDR, MT6350_PMIC_QI_VCAM_IO_MODE_MASK, MT6350_PMIC_QI_VCAM_IO_MODE_SHIFT},
  {PMIC_RG_VCAM_IO_STBTD, MT6350_PMIC_RG_VCAM_IO_STBTD_ADDR, MT6350_PMIC_RG_VCAM_IO_STBTD_MASK, MT6350_PMIC_RG_VCAM_IO_STBTD_SHIFT},
  {PMIC_RG_VCAM_IO_EN, MT6350_PMIC_RG_VCAM_IO_EN_ADDR, MT6350_PMIC_RG_VCAM_IO_EN_MASK, MT6350_PMIC_RG_VCAM_IO_EN_SHIFT},
  {PMIC_QI_VCAM_IO_EN, MT6350_PMIC_QI_VCAM_IO_EN_ADDR, MT6350_PMIC_QI_VCAM_IO_EN_MASK, MT6350_PMIC_QI_VCAM_IO_EN_SHIFT},
  {PMIC_RG_VCAM_IO_NDIS_EN, MT6350_PMIC_RG_VCAM_IO_NDIS_EN_ADDR, MT6350_PMIC_RG_VCAM_IO_NDIS_EN_MASK, MT6350_PMIC_RG_VCAM_IO_NDIS_EN_SHIFT},
  {PMIC_VCAM_IO_ON_CTRL, MT6350_PMIC_VCAM_IO_ON_CTRL_ADDR, MT6350_PMIC_VCAM_IO_ON_CTRL_MASK, MT6350_PMIC_VCAM_IO_ON_CTRL_SHIFT},
  {PMIC_RG_VCAM_IO_OCFB, MT6350_PMIC_RG_VCAM_IO_OCFB_ADDR, MT6350_PMIC_RG_VCAM_IO_OCFB_MASK, MT6350_PMIC_RG_VCAM_IO_OCFB_SHIFT},
  {PMIC_RG_VCAM_IO_STB_SEL, MT6350_PMIC_RG_VCAM_IO_STB_SEL_ADDR, MT6350_PMIC_RG_VCAM_IO_STB_SEL_MASK, MT6350_PMIC_RG_VCAM_IO_STB_SEL_SHIFT},
  {PMIC_RG_VCAM_IO_CAL, MT6350_PMIC_RG_VCAM_IO_CAL_ADDR, MT6350_PMIC_RG_VCAM_IO_CAL_MASK, MT6350_PMIC_RG_VCAM_IO_CAL_SHIFT},
  {PMIC_RG_EFUSE_ADDR, MT6350_PMIC_RG_EFUSE_ADDR_ADDR, MT6350_PMIC_RG_EFUSE_ADDR_MASK, MT6350_PMIC_RG_EFUSE_ADDR_SHIFT},
  {PMIC_RG_EFUSE_PROG, MT6350_PMIC_RG_EFUSE_PROG_ADDR, MT6350_PMIC_RG_EFUSE_PROG_MASK, MT6350_PMIC_RG_EFUSE_PROG_SHIFT},
  {PMIC_RG_EFUSE_EN, MT6350_PMIC_RG_EFUSE_EN_ADDR, MT6350_PMIC_RG_EFUSE_EN_MASK, MT6350_PMIC_RG_EFUSE_EN_SHIFT},
  {PMIC_RG_EFUSE_PKEY, MT6350_PMIC_RG_EFUSE_PKEY_ADDR, MT6350_PMIC_RG_EFUSE_PKEY_MASK, MT6350_PMIC_RG_EFUSE_PKEY_SHIFT},
  {PMIC_RG_EFUSE_RD_TRIG, MT6350_PMIC_RG_EFUSE_RD_TRIG_ADDR, MT6350_PMIC_RG_EFUSE_RD_TRIG_MASK, MT6350_PMIC_RG_EFUSE_RD_TRIG_SHIFT},
  {PMIC_RG_EFUSE_PROG_SRC, MT6350_PMIC_RG_EFUSE_PROG_SRC_ADDR, MT6350_PMIC_RG_EFUSE_PROG_SRC_MASK, MT6350_PMIC_RG_EFUSE_PROG_SRC_SHIFT},
  {PMIC_RG_SKIP_EFUSE_OUT, MT6350_PMIC_RG_SKIP_EFUSE_OUT_ADDR, MT6350_PMIC_RG_SKIP_EFUSE_OUT_MASK, MT6350_PMIC_RG_SKIP_EFUSE_OUT_SHIFT},
  {PMIC_RG_RD_RDY_BYPASS, MT6350_PMIC_RG_RD_RDY_BYPASS_ADDR, MT6350_PMIC_RG_RD_RDY_BYPASS_MASK, MT6350_PMIC_RG_RD_RDY_BYPASS_SHIFT},
  {PMIC_RG_EFUSE_RD_ACK, MT6350_PMIC_RG_EFUSE_RD_ACK_ADDR, MT6350_PMIC_RG_EFUSE_RD_ACK_MASK, MT6350_PMIC_RG_EFUSE_RD_ACK_SHIFT},
  {PMIC_RG_EFUSE_BUSY, MT6350_PMIC_RG_EFUSE_BUSY_ADDR, MT6350_PMIC_RG_EFUSE_BUSY_MASK, MT6350_PMIC_RG_EFUSE_BUSY_SHIFT},
  {PMIC_RG_EFUSE_VAL_0_15, MT6350_PMIC_RG_EFUSE_VAL_0_15_ADDR, MT6350_PMIC_RG_EFUSE_VAL_0_15_MASK, MT6350_PMIC_RG_EFUSE_VAL_0_15_SHIFT},
  {PMIC_RG_EFUSE_VAL_16_31, MT6350_PMIC_RG_EFUSE_VAL_16_31_ADDR, MT6350_PMIC_RG_EFUSE_VAL_16_31_MASK, MT6350_PMIC_RG_EFUSE_VAL_16_31_SHIFT},
  {PMIC_RG_EFUSE_VAL_32_47, MT6350_PMIC_RG_EFUSE_VAL_32_47_ADDR, MT6350_PMIC_RG_EFUSE_VAL_32_47_MASK, MT6350_PMIC_RG_EFUSE_VAL_32_47_SHIFT},
  {PMIC_RG_EFUSE_VAL_48_63, MT6350_PMIC_RG_EFUSE_VAL_48_63_ADDR, MT6350_PMIC_RG_EFUSE_VAL_48_63_MASK, MT6350_PMIC_RG_EFUSE_VAL_48_63_SHIFT},
  {PMIC_RG_EFUSE_VAL_64_79, MT6350_PMIC_RG_EFUSE_VAL_64_79_ADDR, MT6350_PMIC_RG_EFUSE_VAL_64_79_MASK, MT6350_PMIC_RG_EFUSE_VAL_64_79_SHIFT},
  {PMIC_RG_EFUSE_VAL_80_95, MT6350_PMIC_RG_EFUSE_VAL_80_95_ADDR, MT6350_PMIC_RG_EFUSE_VAL_80_95_MASK, MT6350_PMIC_RG_EFUSE_VAL_80_95_SHIFT},
  {PMIC_RG_EFUSE_VAL_96_111, MT6350_PMIC_RG_EFUSE_VAL_96_111_ADDR, MT6350_PMIC_RG_EFUSE_VAL_96_111_MASK, MT6350_PMIC_RG_EFUSE_VAL_96_111_SHIFT},
  {PMIC_RG_EFUSE_VAL_112_127, MT6350_PMIC_RG_EFUSE_VAL_112_127_ADDR, MT6350_PMIC_RG_EFUSE_VAL_112_127_MASK, MT6350_PMIC_RG_EFUSE_VAL_112_127_SHIFT},
  {PMIC_RG_EFUSE_VAL_128_143, MT6350_PMIC_RG_EFUSE_VAL_128_143_ADDR, MT6350_PMIC_RG_EFUSE_VAL_128_143_MASK, MT6350_PMIC_RG_EFUSE_VAL_128_143_SHIFT},
  {PMIC_RG_EFUSE_VAL_144_159, MT6350_PMIC_RG_EFUSE_VAL_144_159_ADDR, MT6350_PMIC_RG_EFUSE_VAL_144_159_MASK, MT6350_PMIC_RG_EFUSE_VAL_144_159_SHIFT},
  {PMIC_RG_EFUSE_VAL_160_175, MT6350_PMIC_RG_EFUSE_VAL_160_175_ADDR, MT6350_PMIC_RG_EFUSE_VAL_160_175_MASK, MT6350_PMIC_RG_EFUSE_VAL_160_175_SHIFT},
  {PMIC_RG_EFUSE_VAL_176_191, MT6350_PMIC_RG_EFUSE_VAL_176_191_ADDR, MT6350_PMIC_RG_EFUSE_VAL_176_191_MASK, MT6350_PMIC_RG_EFUSE_VAL_176_191_SHIFT},
  {PMIC_RG_EFUSE_DOUT_0_15, MT6350_PMIC_RG_EFUSE_DOUT_0_15_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_0_15_MASK, MT6350_PMIC_RG_EFUSE_DOUT_0_15_SHIFT},
  {PMIC_RG_EFUSE_DOUT_16_31, MT6350_PMIC_RG_EFUSE_DOUT_16_31_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_16_31_MASK, MT6350_PMIC_RG_EFUSE_DOUT_16_31_SHIFT},
  {PMIC_RG_EFUSE_DOUT_32_47, MT6350_PMIC_RG_EFUSE_DOUT_32_47_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_32_47_MASK, MT6350_PMIC_RG_EFUSE_DOUT_32_47_SHIFT},
  {PMIC_RG_EFUSE_DOUT_48_63, MT6350_PMIC_RG_EFUSE_DOUT_48_63_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_48_63_MASK, MT6350_PMIC_RG_EFUSE_DOUT_48_63_SHIFT},
  {PMIC_RG_EFUSE_DOUT_64_79, MT6350_PMIC_RG_EFUSE_DOUT_64_79_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_64_79_MASK, MT6350_PMIC_RG_EFUSE_DOUT_64_79_SHIFT},
  {PMIC_RG_EFUSE_DOUT_80_95, MT6350_PMIC_RG_EFUSE_DOUT_80_95_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_80_95_MASK, MT6350_PMIC_RG_EFUSE_DOUT_80_95_SHIFT},
  {PMIC_RG_EFUSE_DOUT_96_111, MT6350_PMIC_RG_EFUSE_DOUT_96_111_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_96_111_MASK, MT6350_PMIC_RG_EFUSE_DOUT_96_111_SHIFT},
  {PMIC_RG_EFUSE_DOUT_112_127, MT6350_PMIC_RG_EFUSE_DOUT_112_127_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_112_127_MASK, MT6350_PMIC_RG_EFUSE_DOUT_112_127_SHIFT},
  {PMIC_RG_EFUSE_DOUT_128_143, MT6350_PMIC_RG_EFUSE_DOUT_128_143_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_128_143_MASK, MT6350_PMIC_RG_EFUSE_DOUT_128_143_SHIFT},
  {PMIC_RG_EFUSE_DOUT_144_159, MT6350_PMIC_RG_EFUSE_DOUT_144_159_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_144_159_MASK, MT6350_PMIC_RG_EFUSE_DOUT_144_159_SHIFT},
  {PMIC_RG_EFUSE_DOUT_160_175, MT6350_PMIC_RG_EFUSE_DOUT_160_175_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_160_175_MASK, MT6350_PMIC_RG_EFUSE_DOUT_160_175_SHIFT},
  {PMIC_RG_EFUSE_DOUT_176_191, MT6350_PMIC_RG_EFUSE_DOUT_176_191_ADDR, MT6350_PMIC_RG_EFUSE_DOUT_176_191_MASK, MT6350_PMIC_RG_EFUSE_DOUT_176_191_SHIFT},
  {PMIC_RG_OTP_PA, MT6350_PMIC_RG_OTP_PA_ADDR, MT6350_PMIC_RG_OTP_PA_MASK, MT6350_PMIC_RG_OTP_PA_SHIFT},
  {PMIC_RG_OTP_PDIN, MT6350_PMIC_RG_OTP_PDIN_ADDR, MT6350_PMIC_RG_OTP_PDIN_MASK, MT6350_PMIC_RG_OTP_PDIN_SHIFT},
  {PMIC_RG_OTP_PTM, MT6350_PMIC_RG_OTP_PTM_ADDR, MT6350_PMIC_RG_OTP_PTM_MASK, MT6350_PMIC_RG_OTP_PTM_SHIFT},
  {PMIC_MIX_EOSC32_OPT, MT6350_PMIC_MIX_EOSC32_OPT_ADDR, MT6350_PMIC_MIX_EOSC32_OPT_MASK, MT6350_PMIC_MIX_EOSC32_OPT_SHIFT},
  {PMIC_MIX_XOSC32_STP_CPDTB, MT6350_PMIC_MIX_XOSC32_STP_CPDTB_ADDR, MT6350_PMIC_MIX_XOSC32_STP_CPDTB_MASK, MT6350_PMIC_MIX_XOSC32_STP_CPDTB_SHIFT},
  {PMIC_MIX_XOSC32_STP_PWDB, MT6350_PMIC_MIX_XOSC32_STP_PWDB_ADDR, MT6350_PMIC_MIX_XOSC32_STP_PWDB_MASK, MT6350_PMIC_MIX_XOSC32_STP_PWDB_SHIFT},
  {PMIC_MIX_XOSC32_STP_LPDTB, MT6350_PMIC_MIX_XOSC32_STP_LPDTB_ADDR, MT6350_PMIC_MIX_XOSC32_STP_LPDTB_MASK, MT6350_PMIC_MIX_XOSC32_STP_LPDTB_SHIFT},
  {PMIC_MIX_XOSC32_STP_LPDEN, MT6350_PMIC_MIX_XOSC32_STP_LPDEN_ADDR, MT6350_PMIC_MIX_XOSC32_STP_LPDEN_MASK, MT6350_PMIC_MIX_XOSC32_STP_LPDEN_SHIFT},
  {PMIC_MIX_XOSC32_STP_LPDRST, MT6350_PMIC_MIX_XOSC32_STP_LPDRST_ADDR, MT6350_PMIC_MIX_XOSC32_STP_LPDRST_MASK, MT6350_PMIC_MIX_XOSC32_STP_LPDRST_SHIFT},
  {PMIC_MIX_XOSC32_STP_CALI, MT6350_PMIC_MIX_XOSC32_STP_CALI_ADDR, MT6350_PMIC_MIX_XOSC32_STP_CALI_MASK, MT6350_PMIC_MIX_XOSC32_STP_CALI_SHIFT},
  {PMIC_STMP_MODE, MT6350_PMIC_STMP_MODE_ADDR, MT6350_PMIC_STMP_MODE_MASK, MT6350_PMIC_STMP_MODE_SHIFT},
  {PMIC_MIX_EOSC32_STP_CHOP_EN, MT6350_PMIC_MIX_EOSC32_STP_CHOP_EN_ADDR, MT6350_PMIC_MIX_EOSC32_STP_CHOP_EN_MASK, MT6350_PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT},
  {PMIC_MIX_DCXO_STP_LVSH_EN, MT6350_PMIC_MIX_DCXO_STP_LVSH_EN_ADDR, MT6350_PMIC_MIX_DCXO_STP_LVSH_EN_MASK, MT6350_PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT},
  {PMIC_MIX_PMU_STP_DDLO_VRTC, MT6350_PMIC_MIX_PMU_STP_DDLO_VRTC_ADDR, MT6350_PMIC_MIX_PMU_STP_DDLO_VRTC_MASK, MT6350_PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT},
  {PMIC_MIX_PMU_STP_DDLO_VRTC_EN, MT6350_PMIC_MIX_PMU_STP_DDLO_VRTC_EN_ADDR, MT6350_PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK, MT6350_PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT},
  {PMIC_MIX_RTC_STP_XOSC32_ENB, MT6350_PMIC_MIX_RTC_STP_XOSC32_ENB_ADDR, MT6350_PMIC_MIX_RTC_STP_XOSC32_ENB_MASK, MT6350_PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT},
  {PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE, MT6350_PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_ADDR, MT6350_PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK, MT6350_PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT},
  {PMIC_MIX_EOSC32_STP_RSV, MT6350_PMIC_MIX_EOSC32_STP_RSV_ADDR, MT6350_PMIC_MIX_EOSC32_STP_RSV_MASK, MT6350_PMIC_MIX_EOSC32_STP_RSV_SHIFT},
  {PMIC_MIX_EOSC32_VCT_EN, MT6350_PMIC_MIX_EOSC32_VCT_EN_ADDR, MT6350_PMIC_MIX_EOSC32_VCT_EN_MASK, MT6350_PMIC_MIX_EOSC32_VCT_EN_SHIFT},
  {PMIC_MIX_STP_BBWAKEUP, MT6350_PMIC_MIX_STP_BBWAKEUP_ADDR, MT6350_PMIC_MIX_STP_BBWAKEUP_MASK, MT6350_PMIC_MIX_STP_BBWAKEUP_SHIFT},
  {PMIC_MIX_STP_RTC_DDLO, MT6350_PMIC_MIX_STP_RTC_DDLO_ADDR, MT6350_PMIC_MIX_STP_RTC_DDLO_MASK, MT6350_PMIC_MIX_STP_RTC_DDLO_SHIFT},
  {PMIC_MIX_RTC_XOSC32_ENB, MT6350_PMIC_MIX_RTC_XOSC32_ENB_ADDR, MT6350_PMIC_MIX_RTC_XOSC32_ENB_MASK, MT6350_PMIC_MIX_RTC_XOSC32_ENB_SHIFT},
  {PMIC_MIX_EFUSE_XOSC32_ENB_OPT, MT6350_PMIC_MIX_EFUSE_XOSC32_ENB_OPT_ADDR, MT6350_PMIC_MIX_EFUSE_XOSC32_ENB_OPT_MASK, MT6350_PMIC_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT},
  {PMIC_RG_AUDULL_VCFG, MT6350_PMIC_RG_AUDULL_VCFG_ADDR, MT6350_PMIC_RG_AUDULL_VCFG_MASK, MT6350_PMIC_RG_AUDULL_VCFG_SHIFT},
  {PMIC_RG_AUDULL_VUPG, MT6350_PMIC_RG_AUDULL_VUPG_ADDR, MT6350_PMIC_RG_AUDULL_VUPG_MASK, MT6350_PMIC_RG_AUDULL_VUPG_SHIFT},
  {PMIC_RG_AUDULL_VPWDB_PGA, MT6350_PMIC_RG_AUDULL_VPWDB_PGA_ADDR, MT6350_PMIC_RG_AUDULL_VPWDB_PGA_MASK, MT6350_PMIC_RG_AUDULL_VPWDB_PGA_SHIFT},
  {PMIC_RG_AUDULL_VPWDB_ADC, MT6350_PMIC_RG_AUDULL_VPWDB_ADC_ADDR, MT6350_PMIC_RG_AUDULL_VPWDB_ADC_MASK, MT6350_PMIC_RG_AUDULL_VPWDB_ADC_SHIFT},
  {PMIC_RG_AUDULL_VADC_DENB, MT6350_PMIC_RG_AUDULL_VADC_DENB_ADDR, MT6350_PMIC_RG_AUDULL_VADC_DENB_MASK, MT6350_PMIC_RG_AUDULL_VADC_DENB_SHIFT},
  {PMIC_RG_AUDULL_VADC_DVREF_CAL, MT6350_PMIC_RG_AUDULL_VADC_DVREF_CAL_ADDR, MT6350_PMIC_RG_AUDULL_VADC_DVREF_CAL_MASK, MT6350_PMIC_RG_AUDULL_VADC_DVREF_CAL_SHIFT},
  {PMIC_RG_AUDULL_VREF24_EN, MT6350_PMIC_RG_AUDULL_VREF24_EN_ADDR, MT6350_PMIC_RG_AUDULL_VREF24_EN_MASK, MT6350_PMIC_RG_AUDULL_VREF24_EN_SHIFT},
  {PMIC_RG_AUDULL_VCM14_EN, MT6350_PMIC_RG_AUDULL_VCM14_EN_ADDR, MT6350_PMIC_RG_AUDULL_VCM14_EN_MASK, MT6350_PMIC_RG_AUDULL_VCM14_EN_SHIFT},
  {PMIC_RG_AUDULL_VCMSEL, MT6350_PMIC_RG_AUDULL_VCMSEL_ADDR, MT6350_PMIC_RG_AUDULL_VCMSEL_MASK, MT6350_PMIC_RG_AUDULL_VCMSEL_SHIFT},
  {PMIC_RG_AUDULL_CHS_EN, MT6350_PMIC_RG_AUDULL_CHS_EN_ADDR, MT6350_PMIC_RG_AUDULL_CHS_EN_MASK, MT6350_PMIC_RG_AUDULL_CHS_EN_SHIFT},
  {PMIC_RG_AUDULL_VCALI, MT6350_PMIC_RG_AUDULL_VCALI_ADDR, MT6350_PMIC_RG_AUDULL_VCALI_MASK, MT6350_PMIC_RG_AUDULL_VCALI_SHIFT},
  {PMIC_RG_AUDULR_VCFG, MT6350_PMIC_RG_AUDULR_VCFG_ADDR, MT6350_PMIC_RG_AUDULR_VCFG_MASK, MT6350_PMIC_RG_AUDULR_VCFG_SHIFT},
  {PMIC_RG_AUDULR_VUPG, MT6350_PMIC_RG_AUDULR_VUPG_ADDR, MT6350_PMIC_RG_AUDULR_VUPG_MASK, MT6350_PMIC_RG_AUDULR_VUPG_SHIFT},
  {PMIC_RG_AUDULR_VPWDB_PGA, MT6350_PMIC_RG_AUDULR_VPWDB_PGA_ADDR, MT6350_PMIC_RG_AUDULR_VPWDB_PGA_MASK, MT6350_PMIC_RG_AUDULR_VPWDB_PGA_SHIFT},
  {PMIC_RG_AUDULR_VPWDB_ADC, MT6350_PMIC_RG_AUDULR_VPWDB_ADC_ADDR, MT6350_PMIC_RG_AUDULR_VPWDB_ADC_MASK, MT6350_PMIC_RG_AUDULR_VPWDB_ADC_SHIFT},
  {PMIC_RG_AUDULR_VADC_DENB, MT6350_PMIC_RG_AUDULR_VADC_DENB_ADDR, MT6350_PMIC_RG_AUDULR_VADC_DENB_MASK, MT6350_PMIC_RG_AUDULR_VADC_DENB_SHIFT},
  {PMIC_RG_AUDULR_VADC_DVREF_CAL, MT6350_PMIC_RG_AUDULR_VADC_DVREF_CAL_ADDR, MT6350_PMIC_RG_AUDULR_VADC_DVREF_CAL_MASK, MT6350_PMIC_RG_AUDULR_VADC_DVREF_CAL_SHIFT},
  {PMIC_RG_AUDULR_VREF24_EN, MT6350_PMIC_RG_AUDULR_VREF24_EN_ADDR, MT6350_PMIC_RG_AUDULR_VREF24_EN_MASK, MT6350_PMIC_RG_AUDULR_VREF24_EN_SHIFT},
  {PMIC_RG_AUDULR_VCM14_EN, MT6350_PMIC_RG_AUDULR_VCM14_EN_ADDR, MT6350_PMIC_RG_AUDULR_VCM14_EN_MASK, MT6350_PMIC_RG_AUDULR_VCM14_EN_SHIFT},
  {PMIC_RG_AUDULR_VCMSEL, MT6350_PMIC_RG_AUDULR_VCMSEL_ADDR, MT6350_PMIC_RG_AUDULR_VCMSEL_MASK, MT6350_PMIC_RG_AUDULR_VCMSEL_SHIFT},
  {PMIC_RG_AUDULR_CHS_EN, MT6350_PMIC_RG_AUDULR_CHS_EN_ADDR, MT6350_PMIC_RG_AUDULR_CHS_EN_MASK, MT6350_PMIC_RG_AUDULR_CHS_EN_SHIFT},
  {PMIC_RG_AUDULR_VCALI, MT6350_PMIC_RG_AUDULR_VCALI_ADDR, MT6350_PMIC_RG_AUDULR_VCALI_MASK, MT6350_PMIC_RG_AUDULR_VCALI_SHIFT},
  {PMIC_RG_AUD_IGBIAS_CALI, MT6350_PMIC_RG_AUD_IGBIAS_CALI_ADDR, MT6350_PMIC_RG_AUD_IGBIAS_CALI_MASK, MT6350_PMIC_RG_AUD_IGBIAS_CALI_SHIFT},
  {PMIC_RG_AUD_RSV, MT6350_PMIC_RG_AUD_RSV_ADDR, MT6350_PMIC_RG_AUD_RSV_MASK, MT6350_PMIC_RG_AUD_RSV_SHIFT},
  {PMIC_RG_AMUTER, MT6350_PMIC_RG_AMUTER_ADDR, MT6350_PMIC_RG_AMUTER_MASK, MT6350_PMIC_RG_AMUTER_SHIFT},
  {PMIC_RG_AMUTEL, MT6350_PMIC_RG_AMUTEL_ADDR, MT6350_PMIC_RG_AMUTEL_MASK, MT6350_PMIC_RG_AMUTEL_SHIFT},
  {PMIC_RG_ADACL_PWDB, MT6350_PMIC_RG_ADACL_PWDB_ADDR, MT6350_PMIC_RG_ADACL_PWDB_MASK, MT6350_PMIC_RG_ADACL_PWDB_SHIFT},
  {PMIC_RG_ADACR_PWDB, MT6350_PMIC_RG_ADACR_PWDB_ADDR, MT6350_PMIC_RG_ADACR_PWDB_MASK, MT6350_PMIC_RG_ADACR_PWDB_SHIFT},
  {PMIC_RG_ABIAS_PWDB, MT6350_PMIC_RG_ABIAS_PWDB_ADDR, MT6350_PMIC_RG_ABIAS_PWDB_MASK, MT6350_PMIC_RG_ABIAS_PWDB_SHIFT},
  {PMIC_RG_AOUTL_PWDB, MT6350_PMIC_RG_AOUTL_PWDB_ADDR, MT6350_PMIC_RG_AOUTL_PWDB_MASK, MT6350_PMIC_RG_AOUTL_PWDB_SHIFT},
  {PMIC_RG_AOUTR_PWDB, MT6350_PMIC_RG_AOUTR_PWDB_ADDR, MT6350_PMIC_RG_AOUTR_PWDB_MASK, MT6350_PMIC_RG_AOUTR_PWDB_SHIFT},
  {PMIC_RG_ACALI, MT6350_PMIC_RG_ACALI_ADDR, MT6350_PMIC_RG_ACALI_MASK, MT6350_PMIC_RG_ACALI_SHIFT},
  {PMIC_RG_APGR, MT6350_PMIC_RG_APGR_ADDR, MT6350_PMIC_RG_APGR_MASK, MT6350_PMIC_RG_APGR_SHIFT},
  {PMIC_RG_APGL, MT6350_PMIC_RG_APGL_ADDR, MT6350_PMIC_RG_APGL_MASK, MT6350_PMIC_RG_APGL_SHIFT},
  {PMIC_RG_ABUF_BIAS, MT6350_PMIC_RG_ABUF_BIAS_ADDR, MT6350_PMIC_RG_ABUF_BIAS_MASK, MT6350_PMIC_RG_ABUF_BIAS_SHIFT},
  {PMIC_RG_ABUF_INSHORT, MT6350_PMIC_RG_ABUF_INSHORT_ADDR, MT6350_PMIC_RG_ABUF_INSHORT_MASK, MT6350_PMIC_RG_ABUF_INSHORT_SHIFT},
  {PMIC_RG_AHFMODE, MT6350_PMIC_RG_AHFMODE_ADDR, MT6350_PMIC_RG_AHFMODE_MASK, MT6350_PMIC_RG_AHFMODE_SHIFT},
  {PMIC_RG_ADACCK_EN, MT6350_PMIC_RG_ADACCK_EN_ADDR, MT6350_PMIC_RG_ADACCK_EN_MASK, MT6350_PMIC_RG_ADACCK_EN_SHIFT},
  {PMIC_RG_DACREF, MT6350_PMIC_RG_DACREF_ADDR, MT6350_PMIC_RG_DACREF_MASK, MT6350_PMIC_RG_DACREF_SHIFT},
  {PMIC_RG_ADEPOPX_EN, MT6350_PMIC_RG_ADEPOPX_EN_ADDR, MT6350_PMIC_RG_ADEPOPX_EN_MASK, MT6350_PMIC_RG_ADEPOPX_EN_SHIFT},
  {PMIC_RG_ADEPOPX, MT6350_PMIC_RG_ADEPOPX_ADDR, MT6350_PMIC_RG_ADEPOPX_MASK, MT6350_PMIC_RG_ADEPOPX_SHIFT},
  {PMIC_RG_DEPOP_VCM_EN, MT6350_PMIC_RG_DEPOP_VCM_EN_ADDR, MT6350_PMIC_RG_DEPOP_VCM_EN_MASK, MT6350_PMIC_RG_DEPOP_VCM_EN_SHIFT},
  {PMIC_RG_DEPOP_VCMSEL, MT6350_PMIC_RG_DEPOP_VCMSEL_ADDR, MT6350_PMIC_RG_DEPOP_VCMSEL_MASK, MT6350_PMIC_RG_DEPOP_VCMSEL_SHIFT},
  {PMIC_RG_DEPOP_CURSEL, MT6350_PMIC_RG_DEPOP_CURSEL_ADDR, MT6350_PMIC_RG_DEPOP_CURSEL_MASK, MT6350_PMIC_RG_DEPOP_CURSEL_SHIFT},
  {PMIC_RG_CHARGEOPTION_DEPOP, MT6350_PMIC_RG_CHARGEOPTION_DEPOP_ADDR, MT6350_PMIC_RG_CHARGEOPTION_DEPOP_MASK, MT6350_PMIC_RG_CHARGEOPTION_DEPOP_SHIFT},
  {PMIC_RG_AVCMGEN_EN, MT6350_PMIC_RG_AVCMGEN_EN_ADDR, MT6350_PMIC_RG_AVCMGEN_EN_MASK, MT6350_PMIC_RG_AVCMGEN_EN_SHIFT},
  {PMIC_RG_AUDDL_VREF24_EN, MT6350_PMIC_RG_AUDDL_VREF24_EN_ADDR, MT6350_PMIC_RG_AUDDL_VREF24_EN_MASK, MT6350_PMIC_RG_AUDDL_VREF24_EN_SHIFT},
  {PMIC_RG_ABIRSV, MT6350_PMIC_RG_ABIRSV_ADDR, MT6350_PMIC_RG_ABIRSV_MASK, MT6350_PMIC_RG_ABIRSV_SHIFT},
  {PMIC_RG_VBUF_FLOAT, MT6350_PMIC_RG_VBUF_FLOAT_ADDR, MT6350_PMIC_RG_VBUF_FLOAT_MASK, MT6350_PMIC_RG_VBUF_FLOAT_SHIFT},
  {PMIC_RG_VDPG, MT6350_PMIC_RG_VDPG_ADDR, MT6350_PMIC_RG_VDPG_MASK, MT6350_PMIC_RG_VDPG_SHIFT},
  {PMIC_RG_VBUF_PWDB, MT6350_PMIC_RG_VBUF_PWDB_ADDR, MT6350_PMIC_RG_VBUF_PWDB_MASK, MT6350_PMIC_RG_VBUF_PWDB_SHIFT},
  {PMIC_RG_VBUF_BIAS, MT6350_PMIC_RG_VBUF_BIAS_ADDR, MT6350_PMIC_RG_VBUF_BIAS_MASK, MT6350_PMIC_RG_VBUF_BIAS_SHIFT},
  {PMIC_RG_VDEPOP, MT6350_PMIC_RG_VDEPOP_ADDR, MT6350_PMIC_RG_VDEPOP_MASK, MT6350_PMIC_RG_VDEPOP_SHIFT},
  {PMIC_RG_V2SPK, MT6350_PMIC_RG_V2SPK_ADDR, MT6350_PMIC_RG_V2SPK_MASK, MT6350_PMIC_RG_V2SPK_SHIFT},
  {PMIC_RG_HSOUTSTBENH, MT6350_PMIC_RG_HSOUTSTBENH_ADDR, MT6350_PMIC_RG_HSOUTSTBENH_MASK, MT6350_PMIC_RG_HSOUTSTBENH_SHIFT},
  {PMIC_AUDTOP_CON8_RSV_0, MT6350_PMIC_AUDTOP_CON8_RSV_0_ADDR, MT6350_PMIC_AUDTOP_CON8_RSV_0_MASK, MT6350_PMIC_AUDTOP_CON8_RSV_0_SHIFT},
  {PMIC_RG_CLKSQ_MONEN, MT6350_PMIC_RG_CLKSQ_MONEN_ADDR, MT6350_PMIC_RG_CLKSQ_MONEN_MASK, MT6350_PMIC_RG_CLKSQ_MONEN_SHIFT},
  {PMIC_RG_AUDDIGMICEN, MT6350_PMIC_RG_AUDDIGMICEN_ADDR, MT6350_PMIC_RG_AUDDIGMICEN_MASK, MT6350_PMIC_RG_AUDDIGMICEN_SHIFT},
  {PMIC_RG_AUDPWDBMICBIAS, MT6350_PMIC_RG_AUDPWDBMICBIAS_ADDR, MT6350_PMIC_RG_AUDPWDBMICBIAS_MASK, MT6350_PMIC_RG_AUDPWDBMICBIAS_SHIFT},
  {PMIC_RG_AUDDIGMICPDUTY, MT6350_PMIC_RG_AUDDIGMICPDUTY_ADDR, MT6350_PMIC_RG_AUDDIGMICPDUTY_MASK, MT6350_PMIC_RG_AUDDIGMICPDUTY_SHIFT},
  {PMIC_RG_AUDDIGMICNDUTY, MT6350_PMIC_RG_AUDDIGMICNDUTY_ADDR, MT6350_PMIC_RG_AUDDIGMICNDUTY_MASK, MT6350_PMIC_RG_AUDDIGMICNDUTY_SHIFT},
  {PMIC_RG_AUDDIGMICBIAS, MT6350_PMIC_RG_AUDDIGMICBIAS_ADDR, MT6350_PMIC_RG_AUDDIGMICBIAS_MASK, MT6350_PMIC_RG_AUDDIGMICBIAS_SHIFT},
  {PMIC_RG_AUDMICBIASVREF, MT6350_PMIC_RG_AUDMICBIASVREF_ADDR, MT6350_PMIC_RG_AUDMICBIASVREF_MASK, MT6350_PMIC_RG_AUDMICBIASVREF_SHIFT},
  {PMIC_RG_AUDSPAREVMIC, MT6350_PMIC_RG_AUDSPAREVMIC_ADDR, MT6350_PMIC_RG_AUDSPAREVMIC_MASK, MT6350_PMIC_RG_AUDSPAREVMIC_SHIFT},
  {PMIC_RG_VBIRX_ZCD_EN, MT6350_PMIC_RG_VBIRX_ZCD_EN_ADDR, MT6350_PMIC_RG_VBIRX_ZCD_EN_MASK, MT6350_PMIC_RG_VBIRX_ZCD_EN_SHIFT},
  {PMIC_RG_VBIRX_ZCD_CALI, MT6350_PMIC_RG_VBIRX_ZCD_CALI_ADDR, MT6350_PMIC_RG_VBIRX_ZCD_CALI_MASK, MT6350_PMIC_RG_VBIRX_ZCD_CALI_SHIFT},
  {PMIC_RG_VBIRX_ZCD_HYS_ENB, MT6350_PMIC_RG_VBIRX_ZCD_HYS_ENB_ADDR, MT6350_PMIC_RG_VBIRX_ZCD_HYS_ENB_MASK, MT6350_PMIC_RG_VBIRX_ZCD_HYS_ENB_SHIFT},
  {PMIC_RG_VBIRX_ZCD_STATUS, MT6350_PMIC_RG_VBIRX_ZCD_STATUS_ADDR, MT6350_PMIC_RG_VBIRX_ZCD_STATUS_MASK, MT6350_PMIC_RG_VBIRX_ZCD_STATUS_SHIFT},
  {PMIC_RG_ADC_OUT_BATSNS, MT6350_PMIC_RG_ADC_OUT_BATSNS_ADDR, MT6350_PMIC_RG_ADC_OUT_BATSNS_MASK, MT6350_PMIC_RG_ADC_OUT_BATSNS_SHIFT},
  {PMIC_RG_ADC_RDY_BATSNS, MT6350_PMIC_RG_ADC_RDY_BATSNS_ADDR, MT6350_PMIC_RG_ADC_RDY_BATSNS_MASK, MT6350_PMIC_RG_ADC_RDY_BATSNS_SHIFT},
  {PMIC_RG_ADC_OUT_ISENSE, MT6350_PMIC_RG_ADC_OUT_ISENSE_ADDR, MT6350_PMIC_RG_ADC_OUT_ISENSE_MASK, MT6350_PMIC_RG_ADC_OUT_ISENSE_SHIFT},
  {PMIC_RG_ADC_RDY_ISENSE, MT6350_PMIC_RG_ADC_RDY_ISENSE_ADDR, MT6350_PMIC_RG_ADC_RDY_ISENSE_MASK, MT6350_PMIC_RG_ADC_RDY_ISENSE_SHIFT},
  {PMIC_RG_ADC_OUT_VCDT, MT6350_PMIC_RG_ADC_OUT_VCDT_ADDR, MT6350_PMIC_RG_ADC_OUT_VCDT_MASK, MT6350_PMIC_RG_ADC_OUT_VCDT_SHIFT},
  {PMIC_RG_ADC_RDY_VCDT, MT6350_PMIC_RG_ADC_RDY_VCDT_ADDR, MT6350_PMIC_RG_ADC_RDY_VCDT_MASK, MT6350_PMIC_RG_ADC_RDY_VCDT_SHIFT},
  {PMIC_RG_ADC_OUT_BATON1, MT6350_PMIC_RG_ADC_OUT_BATON1_ADDR, MT6350_PMIC_RG_ADC_OUT_BATON1_MASK, MT6350_PMIC_RG_ADC_OUT_BATON1_SHIFT},
  {PMIC_RG_ADC_RDY_BATON1, MT6350_PMIC_RG_ADC_RDY_BATON1_ADDR, MT6350_PMIC_RG_ADC_RDY_BATON1_MASK, MT6350_PMIC_RG_ADC_RDY_BATON1_SHIFT},
  {PMIC_RG_ADC_OUT_THR_SENSE1, MT6350_PMIC_RG_ADC_OUT_THR_SENSE1_ADDR, MT6350_PMIC_RG_ADC_OUT_THR_SENSE1_MASK, MT6350_PMIC_RG_ADC_OUT_THR_SENSE1_SHIFT},
  {PMIC_RG_ADC_RDY_THR_SENSE1, MT6350_PMIC_RG_ADC_RDY_THR_SENSE1_ADDR, MT6350_PMIC_RG_ADC_RDY_THR_SENSE1_MASK, MT6350_PMIC_RG_ADC_RDY_THR_SENSE1_SHIFT},
  {PMIC_RG_ADC_OUT_THR_SENSE2, MT6350_PMIC_RG_ADC_OUT_THR_SENSE2_ADDR, MT6350_PMIC_RG_ADC_OUT_THR_SENSE2_MASK, MT6350_PMIC_RG_ADC_OUT_THR_SENSE2_SHIFT},
  {PMIC_RG_ADC_RDY_THR_SENSE2, MT6350_PMIC_RG_ADC_RDY_THR_SENSE2_ADDR, MT6350_PMIC_RG_ADC_RDY_THR_SENSE2_MASK, MT6350_PMIC_RG_ADC_RDY_THR_SENSE2_SHIFT},
  {PMIC_RG_ADC_OUT_BATON2, MT6350_PMIC_RG_ADC_OUT_BATON2_ADDR, MT6350_PMIC_RG_ADC_OUT_BATON2_MASK, MT6350_PMIC_RG_ADC_OUT_BATON2_SHIFT},
  {PMIC_RG_ADC_RDY_BATON2, MT6350_PMIC_RG_ADC_RDY_BATON2_ADDR, MT6350_PMIC_RG_ADC_RDY_BATON2_MASK, MT6350_PMIC_RG_ADC_RDY_BATON2_SHIFT},
  {PMIC_RG_ADC_OUT_CH5, MT6350_PMIC_RG_ADC_OUT_CH5_ADDR, MT6350_PMIC_RG_ADC_OUT_CH5_MASK, MT6350_PMIC_RG_ADC_OUT_CH5_SHIFT},
  {PMIC_RG_ADC_RDY_CH5, MT6350_PMIC_RG_ADC_RDY_CH5_ADDR, MT6350_PMIC_RG_ADC_RDY_CH5_MASK, MT6350_PMIC_RG_ADC_RDY_CH5_SHIFT},
  {PMIC_RG_ADC_OUT_WAKEUP_PCHR, MT6350_PMIC_RG_ADC_OUT_WAKEUP_PCHR_ADDR, MT6350_PMIC_RG_ADC_OUT_WAKEUP_PCHR_MASK, MT6350_PMIC_RG_ADC_OUT_WAKEUP_PCHR_SHIFT},
  {PMIC_RG_ADC_RDY_WAKEUP_PCHR, MT6350_PMIC_RG_ADC_RDY_WAKEUP_PCHR_ADDR, MT6350_PMIC_RG_ADC_RDY_WAKEUP_PCHR_MASK, MT6350_PMIC_RG_ADC_RDY_WAKEUP_PCHR_SHIFT},
  {PMIC_RG_ADC_OUT_WAKEUP_SWCHR, MT6350_PMIC_RG_ADC_OUT_WAKEUP_SWCHR_ADDR, MT6350_PMIC_RG_ADC_OUT_WAKEUP_SWCHR_MASK, MT6350_PMIC_RG_ADC_OUT_WAKEUP_SWCHR_SHIFT},
  {PMIC_RG_ADC_RDY_WAKEUP_SWCHR, MT6350_PMIC_RG_ADC_RDY_WAKEUP_SWCHR_ADDR, MT6350_PMIC_RG_ADC_RDY_WAKEUP_SWCHR_MASK, MT6350_PMIC_RG_ADC_RDY_WAKEUP_SWCHR_SHIFT},
  {PMIC_RG_ADC_OUT_LBAT, MT6350_PMIC_RG_ADC_OUT_LBAT_ADDR, MT6350_PMIC_RG_ADC_OUT_LBAT_MASK, MT6350_PMIC_RG_ADC_OUT_LBAT_SHIFT},
  {PMIC_RG_ADC_RDY_LBAT, MT6350_PMIC_RG_ADC_RDY_LBAT_ADDR, MT6350_PMIC_RG_ADC_RDY_LBAT_MASK, MT6350_PMIC_RG_ADC_RDY_LBAT_SHIFT},
  {PMIC_RG_ADC_OUT_CH6, MT6350_PMIC_RG_ADC_OUT_CH6_ADDR, MT6350_PMIC_RG_ADC_OUT_CH6_MASK, MT6350_PMIC_RG_ADC_OUT_CH6_SHIFT},
  {PMIC_RG_ADC_RDY_CH6, MT6350_PMIC_RG_ADC_RDY_CH6_ADDR, MT6350_PMIC_RG_ADC_RDY_CH6_MASK, MT6350_PMIC_RG_ADC_RDY_CH6_SHIFT},
  {PMIC_RG_ADC_RDY_GPS, MT6350_PMIC_RG_ADC_RDY_GPS_ADDR, MT6350_PMIC_RG_ADC_RDY_GPS_MASK, MT6350_PMIC_RG_ADC_RDY_GPS_SHIFT},
  {PMIC_RG_ADC_OUT_GPS, MT6350_PMIC_RG_ADC_OUT_GPS_ADDR, MT6350_PMIC_RG_ADC_OUT_GPS_MASK, MT6350_PMIC_RG_ADC_OUT_GPS_SHIFT},
  {PMIC_RG_ADC_OUT_GPS_LSB, MT6350_PMIC_RG_ADC_OUT_GPS_LSB_ADDR, MT6350_PMIC_RG_ADC_OUT_GPS_LSB_MASK, MT6350_PMIC_RG_ADC_OUT_GPS_LSB_SHIFT},
  {PMIC_RG_ADC_OUT_MD, MT6350_PMIC_RG_ADC_OUT_MD_ADDR, MT6350_PMIC_RG_ADC_OUT_MD_MASK, MT6350_PMIC_RG_ADC_OUT_MD_SHIFT},
  {PMIC_RG_ADC_OUT_MD_LSB, MT6350_PMIC_RG_ADC_OUT_MD_LSB_ADDR, MT6350_PMIC_RG_ADC_OUT_MD_LSB_MASK, MT6350_PMIC_RG_ADC_OUT_MD_LSB_SHIFT},
  {PMIC_RG_ADC_RDY_MD, MT6350_PMIC_RG_ADC_RDY_MD_ADDR, MT6350_PMIC_RG_ADC_RDY_MD_MASK, MT6350_PMIC_RG_ADC_RDY_MD_SHIFT},
  {PMIC_RG_ADC_OUT_INT, MT6350_PMIC_RG_ADC_OUT_INT_ADDR, MT6350_PMIC_RG_ADC_OUT_INT_MASK, MT6350_PMIC_RG_ADC_OUT_INT_SHIFT},
  {PMIC_RG_ADC_RDY_INT, MT6350_PMIC_RG_ADC_RDY_INT_ADDR, MT6350_PMIC_RG_ADC_RDY_INT_MASK, MT6350_PMIC_RG_ADC_RDY_INT_SHIFT},
  {PMIC_RG_ADC_OUT_CIC_RAW_16_1, MT6350_PMIC_RG_ADC_OUT_CIC_RAW_16_1_ADDR, MT6350_PMIC_RG_ADC_OUT_CIC_RAW_16_1_MASK, MT6350_PMIC_RG_ADC_OUT_CIC_RAW_16_1_SHIFT},
  {PMIC_RG_ADC_OUT_CIC_RAW_0, MT6350_PMIC_RG_ADC_OUT_CIC_RAW_0_ADDR, MT6350_PMIC_RG_ADC_OUT_CIC_RAW_0_MASK, MT6350_PMIC_RG_ADC_OUT_CIC_RAW_0_SHIFT},
  {PMIC_RG_ADC_BUSY, MT6350_PMIC_RG_ADC_BUSY_ADDR, MT6350_PMIC_RG_ADC_BUSY_MASK, MT6350_PMIC_RG_ADC_BUSY_SHIFT},
  {PMIC_RG_ADC_OUT_RSV3, MT6350_PMIC_RG_ADC_OUT_RSV3_ADDR, MT6350_PMIC_RG_ADC_OUT_RSV3_MASK, MT6350_PMIC_RG_ADC_OUT_RSV3_SHIFT},
  {PMIC_RG_SW_GAIN_TRIM, MT6350_PMIC_RG_SW_GAIN_TRIM_ADDR, MT6350_PMIC_RG_SW_GAIN_TRIM_MASK, MT6350_PMIC_RG_SW_GAIN_TRIM_SHIFT},
  {PMIC_RG_SW_OFFSET_TRIM, MT6350_PMIC_RG_SW_OFFSET_TRIM_ADDR, MT6350_PMIC_RG_SW_OFFSET_TRIM_MASK, MT6350_PMIC_RG_SW_OFFSET_TRIM_SHIFT},
  {PMIC_RG_ADC_PWDB, MT6350_PMIC_RG_ADC_PWDB_ADDR, MT6350_PMIC_RG_ADC_PWDB_MASK, MT6350_PMIC_RG_ADC_PWDB_SHIFT},
  {PMIC_RG_ADC_PWDB_SWCTRL, MT6350_PMIC_RG_ADC_PWDB_SWCTRL_ADDR, MT6350_PMIC_RG_ADC_PWDB_SWCTRL_MASK, MT6350_PMIC_RG_ADC_PWDB_SWCTRL_SHIFT},
  {PMIC_RG_ADC_CALI_RATE, MT6350_PMIC_RG_ADC_CALI_RATE_ADDR, MT6350_PMIC_RG_ADC_CALI_RATE_MASK, MT6350_PMIC_RG_ADC_CALI_RATE_SHIFT},
  {PMIC_RG_ADC_CALI_EN, MT6350_PMIC_RG_ADC_CALI_EN_ADDR, MT6350_PMIC_RG_ADC_CALI_EN_MASK, MT6350_PMIC_RG_ADC_CALI_EN_SHIFT},
  {PMIC_RG_ADC_CALI_FORCE, MT6350_PMIC_RG_ADC_CALI_FORCE_ADDR, MT6350_PMIC_RG_ADC_CALI_FORCE_MASK, MT6350_PMIC_RG_ADC_CALI_FORCE_SHIFT},
  {PMIC_RG_ADC_AUTORST_RANGE, MT6350_PMIC_RG_ADC_AUTORST_RANGE_ADDR, MT6350_PMIC_RG_ADC_AUTORST_RANGE_MASK, MT6350_PMIC_RG_ADC_AUTORST_RANGE_SHIFT},
  {PMIC_RG_ADC_AUTORST_EN, MT6350_PMIC_RG_ADC_AUTORST_EN_ADDR, MT6350_PMIC_RG_ADC_AUTORST_EN_MASK, MT6350_PMIC_RG_ADC_AUTORST_EN_SHIFT},
  {PMIC_RG_ADC_LATCH_EDGE, MT6350_PMIC_RG_ADC_LATCH_EDGE_ADDR, MT6350_PMIC_RG_ADC_LATCH_EDGE_MASK, MT6350_PMIC_RG_ADC_LATCH_EDGE_SHIFT},
  {PMIC_RG_ADC_FILTER_ORDER, MT6350_PMIC_RG_ADC_FILTER_ORDER_ADDR, MT6350_PMIC_RG_ADC_FILTER_ORDER_MASK, MT6350_PMIC_RG_ADC_FILTER_ORDER_SHIFT},
  {PMIC_RG_ADC_SWCTRL_EN, MT6350_PMIC_RG_ADC_SWCTRL_EN_ADDR, MT6350_PMIC_RG_ADC_SWCTRL_EN_MASK, MT6350_PMIC_RG_ADC_SWCTRL_EN_SHIFT},
  {PMIC_RG_ADCIN_VSEN_EN, MT6350_PMIC_RG_ADCIN_VSEN_EN_ADDR, MT6350_PMIC_RG_ADCIN_VSEN_EN_MASK, MT6350_PMIC_RG_ADCIN_VSEN_EN_SHIFT},
  {PMIC_RG_ADCIN_VSEN_MUX_EN, MT6350_PMIC_RG_ADCIN_VSEN_MUX_EN_ADDR, MT6350_PMIC_RG_ADCIN_VSEN_MUX_EN_MASK, MT6350_PMIC_RG_ADCIN_VSEN_MUX_EN_SHIFT},
  {PMIC_RG_ADCIN_VBAT_EN, MT6350_PMIC_RG_ADCIN_VBAT_EN_ADDR, MT6350_PMIC_RG_ADCIN_VBAT_EN_MASK, MT6350_PMIC_RG_ADCIN_VBAT_EN_SHIFT},
  {PMIC_RG_ADCIN_CHR_EN, MT6350_PMIC_RG_ADCIN_CHR_EN_ADDR, MT6350_PMIC_RG_ADCIN_CHR_EN_MASK, MT6350_PMIC_RG_ADCIN_CHR_EN_SHIFT},
  {PMIC_RG_AUXADC_CHSEL, MT6350_PMIC_RG_AUXADC_CHSEL_ADDR, MT6350_PMIC_RG_AUXADC_CHSEL_MASK, MT6350_PMIC_RG_AUXADC_CHSEL_SHIFT},
  {PMIC_RG_LBAT_DEBT_MAX, MT6350_PMIC_RG_LBAT_DEBT_MAX_ADDR, MT6350_PMIC_RG_LBAT_DEBT_MAX_MASK, MT6350_PMIC_RG_LBAT_DEBT_MAX_SHIFT},
  {PMIC_RG_LBAT_DEBT_MIN, MT6350_PMIC_RG_LBAT_DEBT_MIN_ADDR, MT6350_PMIC_RG_LBAT_DEBT_MIN_MASK, MT6350_PMIC_RG_LBAT_DEBT_MIN_SHIFT},
  {PMIC_RG_LBAT_DET_PRD_15_0, MT6350_PMIC_RG_LBAT_DET_PRD_15_0_ADDR, MT6350_PMIC_RG_LBAT_DET_PRD_15_0_MASK, MT6350_PMIC_RG_LBAT_DET_PRD_15_0_SHIFT},
  {PMIC_RG_LBAT_DET_PRD_19_16, MT6350_PMIC_RG_LBAT_DET_PRD_19_16_ADDR, MT6350_PMIC_RG_LBAT_DET_PRD_19_16_MASK, MT6350_PMIC_RG_LBAT_DET_PRD_19_16_SHIFT},
  {PMIC_RG_LBAT_VOLT_MAX, MT6350_PMIC_RG_LBAT_VOLT_MAX_ADDR, MT6350_PMIC_RG_LBAT_VOLT_MAX_MASK, MT6350_PMIC_RG_LBAT_VOLT_MAX_SHIFT},
  {PMIC_RG_LBAT_IRQ_EN_MAX, MT6350_PMIC_RG_LBAT_IRQ_EN_MAX_ADDR, MT6350_PMIC_RG_LBAT_IRQ_EN_MAX_MASK, MT6350_PMIC_RG_LBAT_IRQ_EN_MAX_SHIFT},
  {PMIC_RG_LBAT_EN_MAX, MT6350_PMIC_RG_LBAT_EN_MAX_ADDR, MT6350_PMIC_RG_LBAT_EN_MAX_MASK, MT6350_PMIC_RG_LBAT_EN_MAX_SHIFT},
  {PMIC_RG_LBAT_MAX_IRQ_B, MT6350_PMIC_RG_LBAT_MAX_IRQ_B_ADDR, MT6350_PMIC_RG_LBAT_MAX_IRQ_B_MASK, MT6350_PMIC_RG_LBAT_MAX_IRQ_B_SHIFT},
  {PMIC_RG_LBAT_VOLT_MIN, MT6350_PMIC_RG_LBAT_VOLT_MIN_ADDR, MT6350_PMIC_RG_LBAT_VOLT_MIN_MASK, MT6350_PMIC_RG_LBAT_VOLT_MIN_SHIFT},
  {PMIC_RG_LBAT_IRQ_EN_MIN, MT6350_PMIC_RG_LBAT_IRQ_EN_MIN_ADDR, MT6350_PMIC_RG_LBAT_IRQ_EN_MIN_MASK, MT6350_PMIC_RG_LBAT_IRQ_EN_MIN_SHIFT},
  {PMIC_RG_LBAT_EN_MIN, MT6350_PMIC_RG_LBAT_EN_MIN_ADDR, MT6350_PMIC_RG_LBAT_EN_MIN_MASK, MT6350_PMIC_RG_LBAT_EN_MIN_SHIFT},
  {PMIC_RG_LBAT_MIN_IRQ_B, MT6350_PMIC_RG_LBAT_MIN_IRQ_B_ADDR, MT6350_PMIC_RG_LBAT_MIN_IRQ_B_MASK, MT6350_PMIC_RG_LBAT_MIN_IRQ_B_SHIFT},
  {PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX, MT6350_PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_ADDR, MT6350_PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_MASK, MT6350_PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_SHIFT},
  {PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN, MT6350_PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_ADDR, MT6350_PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_MASK, MT6350_PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_SHIFT},
  {PMIC_RG_DATA_REUSE_SEL, MT6350_PMIC_RG_DATA_REUSE_SEL_ADDR, MT6350_PMIC_RG_DATA_REUSE_SEL_MASK, MT6350_PMIC_RG_DATA_REUSE_SEL_SHIFT},
  {PMIC_RG_AUXADC_BIST_ENB, MT6350_PMIC_RG_AUXADC_BIST_ENB_ADDR, MT6350_PMIC_RG_AUXADC_BIST_ENB_MASK, MT6350_PMIC_RG_AUXADC_BIST_ENB_SHIFT},
  {PMIC_RG_OSR, MT6350_PMIC_RG_OSR_ADDR, MT6350_PMIC_RG_OSR_MASK, MT6350_PMIC_RG_OSR_SHIFT},
  {PMIC_RG_OSR_GPS, MT6350_PMIC_RG_OSR_GPS_ADDR, MT6350_PMIC_RG_OSR_GPS_MASK, MT6350_PMIC_RG_OSR_GPS_SHIFT},
  {PMIC_RG_ADC_TRIM_CH7_SEL, MT6350_PMIC_RG_ADC_TRIM_CH7_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH7_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH7_SEL_SHIFT},
  {PMIC_RG_ADC_TRIM_CH6_SEL, MT6350_PMIC_RG_ADC_TRIM_CH6_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH6_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH6_SEL_SHIFT},
  {PMIC_RG_ADC_TRIM_CH5_SEL, MT6350_PMIC_RG_ADC_TRIM_CH5_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH5_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH5_SEL_SHIFT},
  {PMIC_RG_ADC_TRIM_CH4_SEL, MT6350_PMIC_RG_ADC_TRIM_CH4_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH4_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH4_SEL_SHIFT},
  {PMIC_RG_ADC_TRIM_CH3_SEL, MT6350_PMIC_RG_ADC_TRIM_CH3_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH3_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH3_SEL_SHIFT},
  {PMIC_RG_ADC_TRIM_CH2_SEL, MT6350_PMIC_RG_ADC_TRIM_CH2_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH2_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH2_SEL_SHIFT},
  {PMIC_RG_ADC_TRIM_CH0_SEL, MT6350_PMIC_RG_ADC_TRIM_CH0_SEL_ADDR, MT6350_PMIC_RG_ADC_TRIM_CH0_SEL_MASK, MT6350_PMIC_RG_ADC_TRIM_CH0_SEL_SHIFT},
  {PMIC_RG_VBUF_CALEN, MT6350_PMIC_RG_VBUF_CALEN_ADDR, MT6350_PMIC_RG_VBUF_CALEN_MASK, MT6350_PMIC_RG_VBUF_CALEN_SHIFT},
  {PMIC_RG_VBUF_EXTEN, MT6350_PMIC_RG_VBUF_EXTEN_ADDR, MT6350_PMIC_RG_VBUF_EXTEN_MASK, MT6350_PMIC_RG_VBUF_EXTEN_SHIFT},
  {PMIC_RG_VBUF_BYP, MT6350_PMIC_RG_VBUF_BYP_ADDR, MT6350_PMIC_RG_VBUF_BYP_MASK, MT6350_PMIC_RG_VBUF_BYP_SHIFT},
  {PMIC_RG_VBUF_EN, MT6350_PMIC_RG_VBUF_EN_ADDR, MT6350_PMIC_RG_VBUF_EN_MASK, MT6350_PMIC_RG_VBUF_EN_SHIFT},
  {PMIC_RG_SOURCE_LBAT_SEL, MT6350_PMIC_RG_SOURCE_LBAT_SEL_ADDR, MT6350_PMIC_RG_SOURCE_LBAT_SEL_MASK, MT6350_PMIC_RG_SOURCE_LBAT_SEL_SHIFT},
  {PMIC_EFUSE_GAIN_CH0_TRIM, MT6350_PMIC_EFUSE_GAIN_CH0_TRIM_ADDR, MT6350_PMIC_EFUSE_GAIN_CH0_TRIM_MASK, MT6350_PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT},
  {PMIC_EFUSE_OFFSET_CH0_TRIM, MT6350_PMIC_EFUSE_OFFSET_CH0_TRIM_ADDR, MT6350_PMIC_EFUSE_OFFSET_CH0_TRIM_MASK, MT6350_PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT},
  {PMIC_EFUSE_GAIN_CH4_TRIM, MT6350_PMIC_EFUSE_GAIN_CH4_TRIM_ADDR, MT6350_PMIC_EFUSE_GAIN_CH4_TRIM_MASK, MT6350_PMIC_EFUSE_GAIN_CH4_TRIM_SHIFT},
  {PMIC_EFUSE_OFFSET_CH4_TRIM, MT6350_PMIC_EFUSE_OFFSET_CH4_TRIM_ADDR, MT6350_PMIC_EFUSE_OFFSET_CH4_TRIM_MASK, MT6350_PMIC_EFUSE_OFFSET_CH4_TRIM_SHIFT},
  {PMIC_EFUSE_GAIN_CH7_TRIM, MT6350_PMIC_EFUSE_GAIN_CH7_TRIM_ADDR, MT6350_PMIC_EFUSE_GAIN_CH7_TRIM_MASK, MT6350_PMIC_EFUSE_GAIN_CH7_TRIM_SHIFT},
  {PMIC_EFUSE_OFFSET_CH7_TRIM, MT6350_PMIC_EFUSE_OFFSET_CH7_TRIM_ADDR, MT6350_PMIC_EFUSE_OFFSET_CH7_TRIM_MASK, MT6350_PMIC_EFUSE_OFFSET_CH7_TRIM_SHIFT},
  {PMIC_RG_ADC_IBIAS, MT6350_PMIC_RG_ADC_IBIAS_ADDR, MT6350_PMIC_RG_ADC_IBIAS_MASK, MT6350_PMIC_RG_ADC_IBIAS_SHIFT},
  {PMIC_RG_ADC_RST, MT6350_PMIC_RG_ADC_RST_ADDR, MT6350_PMIC_RG_ADC_RST_MASK, MT6350_PMIC_RG_ADC_RST_SHIFT},
  {PMIC_RG_ADC_LP_EN, MT6350_PMIC_RG_ADC_LP_EN_ADDR, MT6350_PMIC_RG_ADC_LP_EN_MASK, MT6350_PMIC_RG_ADC_LP_EN_SHIFT},
  {PMIC_RG_ADC_INPUT_SHORT, MT6350_PMIC_RG_ADC_INPUT_SHORT_ADDR, MT6350_PMIC_RG_ADC_INPUT_SHORT_MASK, MT6350_PMIC_RG_ADC_INPUT_SHORT_SHIFT},
  {PMIC_RG_ADC_CHOPPER_EN, MT6350_PMIC_RG_ADC_CHOPPER_EN_ADDR, MT6350_PMIC_RG_ADC_CHOPPER_EN_MASK, MT6350_PMIC_RG_ADC_CHOPPER_EN_SHIFT},
  {PMIC_RG_VPWDB_ADC, MT6350_PMIC_RG_VPWDB_ADC_ADDR, MT6350_PMIC_RG_VPWDB_ADC_MASK, MT6350_PMIC_RG_VPWDB_ADC_SHIFT},
  {PMIC_RG_VREF18_EN, MT6350_PMIC_RG_VREF18_EN_ADDR, MT6350_PMIC_RG_VREF18_EN_MASK, MT6350_PMIC_RG_VREF18_EN_SHIFT},
  {PMIC_RG_ADC_CHS_SEL, MT6350_PMIC_RG_ADC_CHS_SEL_ADDR, MT6350_PMIC_RG_ADC_CHS_SEL_MASK, MT6350_PMIC_RG_ADC_CHS_SEL_SHIFT},
  {PMIC_RG_ADC_DVREF_CAL, MT6350_PMIC_RG_ADC_DVREF_CAL_ADDR, MT6350_PMIC_RG_ADC_DVREF_CAL_MASK, MT6350_PMIC_RG_ADC_DVREF_CAL_SHIFT},
  {PMIC_RG_ADC_DENB, MT6350_PMIC_RG_ADC_DENB_ADDR, MT6350_PMIC_RG_ADC_DENB_MASK, MT6350_PMIC_RG_ADC_DENB_SHIFT},
  {PMIC_RG_ADC_SLEEP_MODE_EN, MT6350_PMIC_RG_ADC_SLEEP_MODE_EN_ADDR, MT6350_PMIC_RG_ADC_SLEEP_MODE_EN_MASK, MT6350_PMIC_RG_ADC_SLEEP_MODE_EN_SHIFT},
  {PMIC_RG_ADC_GPS_STATUS, MT6350_PMIC_RG_ADC_GPS_STATUS_ADDR, MT6350_PMIC_RG_ADC_GPS_STATUS_MASK, MT6350_PMIC_RG_ADC_GPS_STATUS_SHIFT},
  {PMIC_RG_ADC_RSV_BIT, MT6350_PMIC_RG_ADC_RSV_BIT_ADDR, MT6350_PMIC_RG_ADC_RSV_BIT_MASK, MT6350_PMIC_RG_ADC_RSV_BIT_SHIFT},
  {PMIC_RG_ADC_TEST_MODE_EN, MT6350_PMIC_RG_ADC_TEST_MODE_EN_ADDR, MT6350_PMIC_RG_ADC_TEST_MODE_EN_MASK, MT6350_PMIC_RG_ADC_TEST_MODE_EN_SHIFT},
  {PMIC_RG_ADC_TEST_OUT_SEL, MT6350_PMIC_RG_ADC_TEST_OUT_SEL_ADDR, MT6350_PMIC_RG_ADC_TEST_OUT_SEL_MASK, MT6350_PMIC_RG_ADC_TEST_OUT_SEL_SHIFT},
  {PMIC_RG_DECI_BYPASS_EN, MT6350_PMIC_RG_DECI_BYPASS_EN_ADDR, MT6350_PMIC_RG_DECI_BYPASS_EN_MASK, MT6350_PMIC_RG_DECI_BYPASS_EN_SHIFT},
  {PMIC_RG_ADC_CLK_AON, MT6350_PMIC_RG_ADC_CLK_AON_ADDR, MT6350_PMIC_RG_ADC_CLK_AON_MASK, MT6350_PMIC_RG_ADC_CLK_AON_SHIFT},
  {PMIC_RG_ADC_DECI_FORCE, MT6350_PMIC_RG_ADC_DECI_FORCE_ADDR, MT6350_PMIC_RG_ADC_DECI_FORCE_MASK, MT6350_PMIC_RG_ADC_DECI_FORCE_SHIFT},
  {PMIC_RG_ADC_DECI_GDLY, MT6350_PMIC_RG_ADC_DECI_GDLY_ADDR, MT6350_PMIC_RG_ADC_DECI_GDLY_MASK, MT6350_PMIC_RG_ADC_DECI_GDLY_SHIFT},
  {PMIC_RG_MD_RQST, MT6350_PMIC_RG_MD_RQST_ADDR, MT6350_PMIC_RG_MD_RQST_MASK, MT6350_PMIC_RG_MD_RQST_SHIFT},
  {PMIC_RG_GPS_RQST, MT6350_PMIC_RG_GPS_RQST_ADDR, MT6350_PMIC_RG_GPS_RQST_MASK, MT6350_PMIC_RG_GPS_RQST_SHIFT},
  {PMIC_RG_AP_RQST_LIST, MT6350_PMIC_RG_AP_RQST_LIST_ADDR, MT6350_PMIC_RG_AP_RQST_LIST_MASK, MT6350_PMIC_RG_AP_RQST_LIST_SHIFT},
  {PMIC_RG_AP_RQST, MT6350_PMIC_RG_AP_RQST_ADDR, MT6350_PMIC_RG_AP_RQST_MASK, MT6350_PMIC_RG_AP_RQST_SHIFT},
  {PMIC_RG_AP_RQST_LIST_RSV, MT6350_PMIC_RG_AP_RQST_LIST_RSV_ADDR, MT6350_PMIC_RG_AP_RQST_LIST_RSV_MASK, MT6350_PMIC_RG_AP_RQST_LIST_RSV_SHIFT},
  {PMIC_RG_ADC_OUT_TRIM_ENB, MT6350_PMIC_RG_ADC_OUT_TRIM_ENB_ADDR, MT6350_PMIC_RG_ADC_OUT_TRIM_ENB_MASK, MT6350_PMIC_RG_ADC_OUT_TRIM_ENB_SHIFT},
  {PMIC_RG_ADC_TRIM_COMP, MT6350_PMIC_RG_ADC_TRIM_COMP_ADDR, MT6350_PMIC_RG_ADC_TRIM_COMP_MASK, MT6350_PMIC_RG_ADC_TRIM_COMP_SHIFT},
  {PMIC_RG_ADC_2S_COMP_ENB, MT6350_PMIC_RG_ADC_2S_COMP_ENB_ADDR, MT6350_PMIC_RG_ADC_2S_COMP_ENB_MASK, MT6350_PMIC_RG_ADC_2S_COMP_ENB_SHIFT},
  {PMIC_RG_CIC_OUT_RAW, MT6350_PMIC_RG_CIC_OUT_RAW_ADDR, MT6350_PMIC_RG_CIC_OUT_RAW_MASK, MT6350_PMIC_RG_CIC_OUT_RAW_SHIFT},
  {PMIC_RG_DATA_SKIP_ENB, MT6350_PMIC_RG_DATA_SKIP_ENB_ADDR, MT6350_PMIC_RG_DATA_SKIP_ENB_MASK, MT6350_PMIC_RG_DATA_SKIP_ENB_SHIFT},
  {PMIC_RG_DATA_SKIP_NUM, MT6350_PMIC_RG_DATA_SKIP_NUM_ADDR, MT6350_PMIC_RG_DATA_SKIP_NUM_MASK, MT6350_PMIC_RG_DATA_SKIP_NUM_SHIFT},
  {PMIC_RG_ADC_REV, MT6350_PMIC_RG_ADC_REV_ADDR, MT6350_PMIC_RG_ADC_REV_MASK, MT6350_PMIC_RG_ADC_REV_SHIFT},
  {PMIC_RG_DECI_GDLY_SEL_MODE, MT6350_PMIC_RG_DECI_GDLY_SEL_MODE_ADDR, MT6350_PMIC_RG_DECI_GDLY_SEL_MODE_MASK, MT6350_PMIC_RG_DECI_GDLY_SEL_MODE_SHIFT},
  {PMIC_RG_DECI_GDLY_VREF18_SELB, MT6350_PMIC_RG_DECI_GDLY_VREF18_SELB_ADDR, MT6350_PMIC_RG_DECI_GDLY_VREF18_SELB_MASK, MT6350_PMIC_RG_DECI_GDLY_VREF18_SELB_SHIFT},
  {PMIC_RG_ADC_RSV1, MT6350_PMIC_RG_ADC_RSV1_ADDR, MT6350_PMIC_RG_ADC_RSV1_MASK, MT6350_PMIC_RG_ADC_RSV1_SHIFT},
  {PMIC_RG_VREF18_ENB, MT6350_PMIC_RG_VREF18_ENB_ADDR, MT6350_PMIC_RG_VREF18_ENB_MASK, MT6350_PMIC_RG_VREF18_ENB_SHIFT},
  {PMIC_RG_ADC_MD_STATUS, MT6350_PMIC_RG_ADC_MD_STATUS_ADDR, MT6350_PMIC_RG_ADC_MD_STATUS_MASK, MT6350_PMIC_RG_ADC_MD_STATUS_SHIFT},
  {PMIC_RG_ADC_RSV2, MT6350_PMIC_RG_ADC_RSV2_ADDR, MT6350_PMIC_RG_ADC_RSV2_MASK, MT6350_PMIC_RG_ADC_RSV2_SHIFT},
  {PMIC_RG_VREF18_ENB_MD, MT6350_PMIC_RG_VREF18_ENB_MD_ADDR, MT6350_PMIC_RG_VREF18_ENB_MD_MASK, MT6350_PMIC_RG_VREF18_ENB_MD_SHIFT},
  {PMIC_RG_AUDACCDETVTHCAL, MT6350_PMIC_RG_AUDACCDETVTHCAL_ADDR, MT6350_PMIC_RG_AUDACCDETVTHCAL_MASK, MT6350_PMIC_RG_AUDACCDETVTHCAL_SHIFT},
  {PMIC_RG_AUDACCDETSWCTRL, MT6350_PMIC_RG_AUDACCDETSWCTRL_ADDR, MT6350_PMIC_RG_AUDACCDETSWCTRL_MASK, MT6350_PMIC_RG_AUDACCDETSWCTRL_SHIFT},
  {PMIC_RG_AUDACCDETTVDET, MT6350_PMIC_RG_AUDACCDETTVDET_ADDR, MT6350_PMIC_RG_AUDACCDETTVDET_MASK, MT6350_PMIC_RG_AUDACCDETTVDET_SHIFT},
  {PMIC_RG_AUDACCDETVIN1PULLLOW, MT6350_PMIC_RG_AUDACCDETVIN1PULLLOW_ADDR, MT6350_PMIC_RG_AUDACCDETVIN1PULLLOW_MASK, MT6350_PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT},
  {PMIC_AUDACCDETAUXADCSWCTRL, MT6350_PMIC_AUDACCDETAUXADCSWCTRL_ADDR, MT6350_PMIC_AUDACCDETAUXADCSWCTRL_MASK, MT6350_PMIC_AUDACCDETAUXADCSWCTRL_SHIFT},
  {PMIC_AUDACCDETAUXADCSWCTRL_SEL, MT6350_PMIC_AUDACCDETAUXADCSWCTRL_SEL_ADDR, MT6350_PMIC_AUDACCDETAUXADCSWCTRL_SEL_MASK, MT6350_PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT},
  {PMIC_RG_AUDACCDETRSV, MT6350_PMIC_RG_AUDACCDETRSV_ADDR, MT6350_PMIC_RG_AUDACCDETRSV_MASK, MT6350_PMIC_RG_AUDACCDETRSV_SHIFT},
  {PMIC_ACCDET_EN, MT6350_PMIC_ACCDET_EN_ADDR, MT6350_PMIC_ACCDET_EN_MASK, MT6350_PMIC_ACCDET_EN_SHIFT},
  {PMIC_ACCDET_SEQ_INIT, MT6350_PMIC_ACCDET_SEQ_INIT_ADDR, MT6350_PMIC_ACCDET_SEQ_INIT_MASK, MT6350_PMIC_ACCDET_SEQ_INIT_SHIFT},
  {PMIC_ACCDET_CMP_PWM_EN, MT6350_PMIC_ACCDET_CMP_PWM_EN_ADDR, MT6350_PMIC_ACCDET_CMP_PWM_EN_MASK, MT6350_PMIC_ACCDET_CMP_PWM_EN_SHIFT},
  {PMIC_ACCDET_VTH_PWM_EN, MT6350_PMIC_ACCDET_VTH_PWM_EN_ADDR, MT6350_PMIC_ACCDET_VTH_PWM_EN_MASK, MT6350_PMIC_ACCDET_VTH_PWM_EN_SHIFT},
  {PMIC_ACCDET_MBIAS_PWM_EN, MT6350_PMIC_ACCDET_MBIAS_PWM_EN_ADDR, MT6350_PMIC_ACCDET_MBIAS_PWM_EN_MASK, MT6350_PMIC_ACCDET_MBIAS_PWM_EN_SHIFT},
  {PMIC_ACCDET_CMP_PWM_IDLE, MT6350_PMIC_ACCDET_CMP_PWM_IDLE_ADDR, MT6350_PMIC_ACCDET_CMP_PWM_IDLE_MASK, MT6350_PMIC_ACCDET_CMP_PWM_IDLE_SHIFT},
  {PMIC_ACCDET_VTH_PWM_IDLE, MT6350_PMIC_ACCDET_VTH_PWM_IDLE_ADDR, MT6350_PMIC_ACCDET_VTH_PWM_IDLE_MASK, MT6350_PMIC_ACCDET_VTH_PWM_IDLE_SHIFT},
  {PMIC_ACCDET_MBIAS_PWM_IDLE, MT6350_PMIC_ACCDET_MBIAS_PWM_IDLE_ADDR, MT6350_PMIC_ACCDET_MBIAS_PWM_IDLE_MASK, MT6350_PMIC_ACCDET_MBIAS_PWM_IDLE_SHIFT},
  {PMIC_ACCDET_PWM_WIDTH, MT6350_PMIC_ACCDET_PWM_WIDTH_ADDR, MT6350_PMIC_ACCDET_PWM_WIDTH_MASK, MT6350_PMIC_ACCDET_PWM_WIDTH_SHIFT},
  {PMIC_ACCDET_PWM_THRESH, MT6350_PMIC_ACCDET_PWM_THRESH_ADDR, MT6350_PMIC_ACCDET_PWM_THRESH_MASK, MT6350_PMIC_ACCDET_PWM_THRESH_SHIFT},
  {PMIC_ACCDET_RISE_DELAY, MT6350_PMIC_ACCDET_RISE_DELAY_ADDR, MT6350_PMIC_ACCDET_RISE_DELAY_MASK, MT6350_PMIC_ACCDET_RISE_DELAY_SHIFT},
  {PMIC_ACCDET_FALL_DELAY, MT6350_PMIC_ACCDET_FALL_DELAY_ADDR, MT6350_PMIC_ACCDET_FALL_DELAY_MASK, MT6350_PMIC_ACCDET_FALL_DELAY_SHIFT},
  {PMIC_ACCDET_DEBOUNCE0, MT6350_PMIC_ACCDET_DEBOUNCE0_ADDR, MT6350_PMIC_ACCDET_DEBOUNCE0_MASK, MT6350_PMIC_ACCDET_DEBOUNCE0_SHIFT},
  {PMIC_ACCDET_DEBOUNCE1, MT6350_PMIC_ACCDET_DEBOUNCE1_ADDR, MT6350_PMIC_ACCDET_DEBOUNCE1_MASK, MT6350_PMIC_ACCDET_DEBOUNCE1_SHIFT},
  {PMIC_ACCDET_DEBOUNCE2, MT6350_PMIC_ACCDET_DEBOUNCE2_ADDR, MT6350_PMIC_ACCDET_DEBOUNCE2_MASK, MT6350_PMIC_ACCDET_DEBOUNCE2_SHIFT},
  {PMIC_ACCDET_DEBOUNCE3, MT6350_PMIC_ACCDET_DEBOUNCE3_ADDR, MT6350_PMIC_ACCDET_DEBOUNCE3_MASK, MT6350_PMIC_ACCDET_DEBOUNCE3_SHIFT},
  {PMIC_ACCDET_IVAL_CUR_IN, MT6350_PMIC_ACCDET_IVAL_CUR_IN_ADDR, MT6350_PMIC_ACCDET_IVAL_CUR_IN_MASK, MT6350_PMIC_ACCDET_IVAL_CUR_IN_SHIFT},
  {PMIC_ACCDET_IVAL_SAM_IN, MT6350_PMIC_ACCDET_IVAL_SAM_IN_ADDR, MT6350_PMIC_ACCDET_IVAL_SAM_IN_MASK, MT6350_PMIC_ACCDET_IVAL_SAM_IN_SHIFT},
  {PMIC_ACCDET_IVAL_MEM_IN, MT6350_PMIC_ACCDET_IVAL_MEM_IN_ADDR, MT6350_PMIC_ACCDET_IVAL_MEM_IN_MASK, MT6350_PMIC_ACCDET_IVAL_MEM_IN_SHIFT},
  {PMIC_ACCDET_IVAL_SEL, MT6350_PMIC_ACCDET_IVAL_SEL_ADDR, MT6350_PMIC_ACCDET_IVAL_SEL_MASK, MT6350_PMIC_ACCDET_IVAL_SEL_SHIFT},
  {PMIC_ACCDET_IRQ, MT6350_PMIC_ACCDET_IRQ_ADDR, MT6350_PMIC_ACCDET_IRQ_MASK, MT6350_PMIC_ACCDET_IRQ_SHIFT},
  {PMIC_ACCDET_IRQ_CLR, MT6350_PMIC_ACCDET_IRQ_CLR_ADDR, MT6350_PMIC_ACCDET_IRQ_CLR_MASK, MT6350_PMIC_ACCDET_IRQ_CLR_SHIFT},
  {PMIC_ACCDET_TEST_MODE0, MT6350_PMIC_ACCDET_TEST_MODE0_ADDR, MT6350_PMIC_ACCDET_TEST_MODE0_MASK, MT6350_PMIC_ACCDET_TEST_MODE0_SHIFT},
  {PMIC_ACCDET_TEST_MODE1, MT6350_PMIC_ACCDET_TEST_MODE1_ADDR, MT6350_PMIC_ACCDET_TEST_MODE1_MASK, MT6350_PMIC_ACCDET_TEST_MODE1_SHIFT},
  {PMIC_ACCDET_TEST_MODE2, MT6350_PMIC_ACCDET_TEST_MODE2_ADDR, MT6350_PMIC_ACCDET_TEST_MODE2_MASK, MT6350_PMIC_ACCDET_TEST_MODE2_SHIFT},
  {PMIC_ACCDET_TEST_MODE3, MT6350_PMIC_ACCDET_TEST_MODE3_ADDR, MT6350_PMIC_ACCDET_TEST_MODE3_MASK, MT6350_PMIC_ACCDET_TEST_MODE3_SHIFT},
  {PMIC_ACCDET_TEST_MODE4, MT6350_PMIC_ACCDET_TEST_MODE4_ADDR, MT6350_PMIC_ACCDET_TEST_MODE4_MASK, MT6350_PMIC_ACCDET_TEST_MODE4_SHIFT},
  {PMIC_ACCDET_TEST_MODE5, MT6350_PMIC_ACCDET_TEST_MODE5_ADDR, MT6350_PMIC_ACCDET_TEST_MODE5_MASK, MT6350_PMIC_ACCDET_TEST_MODE5_SHIFT},
  {PMIC_ACCDET_PWM_SEL, MT6350_PMIC_ACCDET_PWM_SEL_ADDR, MT6350_PMIC_ACCDET_PWM_SEL_MASK, MT6350_PMIC_ACCDET_PWM_SEL_SHIFT},
  {PMIC_ACCDET_IN_SW, MT6350_PMIC_ACCDET_IN_SW_ADDR, MT6350_PMIC_ACCDET_IN_SW_MASK, MT6350_PMIC_ACCDET_IN_SW_SHIFT},
  {PMIC_ACCDET_CMP_EN_SW, MT6350_PMIC_ACCDET_CMP_EN_SW_ADDR, MT6350_PMIC_ACCDET_CMP_EN_SW_MASK, MT6350_PMIC_ACCDET_CMP_EN_SW_SHIFT},
  {PMIC_ACCDET_VTH_EN_SW, MT6350_PMIC_ACCDET_VTH_EN_SW_ADDR, MT6350_PMIC_ACCDET_VTH_EN_SW_MASK, MT6350_PMIC_ACCDET_VTH_EN_SW_SHIFT},
  {PMIC_ACCDET_MBIAS_EN_SW, MT6350_PMIC_ACCDET_MBIAS_EN_SW_ADDR, MT6350_PMIC_ACCDET_MBIAS_EN_SW_MASK, MT6350_PMIC_ACCDET_MBIAS_EN_SW_SHIFT},
  {PMIC_ACCDET_PWM_EN_SW, MT6350_PMIC_ACCDET_PWM_EN_SW_ADDR, MT6350_PMIC_ACCDET_PWM_EN_SW_MASK, MT6350_PMIC_ACCDET_PWM_EN_SW_SHIFT},
  {PMIC_ACCDET_IN, MT6350_PMIC_ACCDET_IN_ADDR, MT6350_PMIC_ACCDET_IN_MASK, MT6350_PMIC_ACCDET_IN_SHIFT},
  {PMIC_ACCDET_CUR_IN, MT6350_PMIC_ACCDET_CUR_IN_ADDR, MT6350_PMIC_ACCDET_CUR_IN_MASK, MT6350_PMIC_ACCDET_CUR_IN_SHIFT},
  {PMIC_ACCDET_SAM_IN, MT6350_PMIC_ACCDET_SAM_IN_ADDR, MT6350_PMIC_ACCDET_SAM_IN_MASK, MT6350_PMIC_ACCDET_SAM_IN_SHIFT},
  {PMIC_ACCDET_MEM_IN, MT6350_PMIC_ACCDET_MEM_IN_ADDR, MT6350_PMIC_ACCDET_MEM_IN_MASK, MT6350_PMIC_ACCDET_MEM_IN_SHIFT},
  {PMIC_ACCDET_STATE, MT6350_PMIC_ACCDET_STATE_ADDR, MT6350_PMIC_ACCDET_STATE_MASK, MT6350_PMIC_ACCDET_STATE_SHIFT},
  {PMIC_ACCDET_MBIAS_CLK, MT6350_PMIC_ACCDET_MBIAS_CLK_ADDR, MT6350_PMIC_ACCDET_MBIAS_CLK_MASK, MT6350_PMIC_ACCDET_MBIAS_CLK_SHIFT},
  {PMIC_ACCDET_VTH_CLK, MT6350_PMIC_ACCDET_VTH_CLK_ADDR, MT6350_PMIC_ACCDET_VTH_CLK_MASK, MT6350_PMIC_ACCDET_VTH_CLK_SHIFT},
  {PMIC_ACCDET_CMP_CLK, MT6350_PMIC_ACCDET_CMP_CLK_ADDR, MT6350_PMIC_ACCDET_CMP_CLK_MASK, MT6350_PMIC_ACCDET_CMP_CLK_SHIFT},
  {PMIC_DA_AUDACCDETAUXADCSWCTRL, MT6350_PMIC_DA_AUDACCDETAUXADCSWCTRL_ADDR, MT6350_PMIC_DA_AUDACCDETAUXADCSWCTRL_MASK, MT6350_PMIC_DA_AUDACCDETAUXADCSWCTRL_SHIFT},
  {PMIC_ACCDET_CUR_DEB, MT6350_PMIC_ACCDET_CUR_DEB_ADDR, MT6350_PMIC_ACCDET_CUR_DEB_MASK, MT6350_PMIC_ACCDET_CUR_DEB_SHIFT},
  {PMIC_ACCDET_RSV_CON0, MT6350_PMIC_ACCDET_RSV_CON0_ADDR, MT6350_PMIC_ACCDET_RSV_CON0_MASK, MT6350_PMIC_ACCDET_RSV_CON0_SHIFT},
  {PMIC_ACCDET_RSV_CON1, MT6350_PMIC_ACCDET_RSV_CON1_ADDR, MT6350_PMIC_ACCDET_RSV_CON1_MASK, MT6350_PMIC_ACCDET_RSV_CON1_SHIFT},
};

kal_uint16 mt6350_set_register_value(PMU_FLAGS_LIST_ENUM flagname,kal_uint32 val)
{
	const PMU_FLAG_TABLE_ENTRY *pFlag=&pmu_flags_table[flagname];
  	kal_uint32 ret=0;


	if (pFlag->flagname!=flagname)
	{
		dprintf(CRITICAL,"[pmu_set_register_value]pmic flag idx error\n");	
		return 1;
	}

  	

	ret=pmic_config_interface( (pFlag->offset),
	                         (kal_uint32)(val),
	                         (kal_uint32)(pFlag->mask),
	                         (kal_uint32)(pFlag->shift)
	                         );	
  	
    if(ret !=0)
    {
    }
	return 0;     
}

kal_uint16 mt6350_get_register_value(PMU_FLAGS_LIST_ENUM flagname)
{
	const PMU_FLAG_TABLE_ENTRY *pFlag=&pmu_flags_table[flagname];
	U32 val = 0;
	kal_uint32 ret;

	ret=pmic_read_interface((U32)pFlag->offset, &val, (U32)(pFlag->mask),  (U32)(pFlag->shift));
    
    if(ret !=0)
    {
    }
	return val;
}

kal_uint16 pmic_set_register_value(PMU_FLAGS_LIST_ENUM flagname,kal_uint32 val)
{
	return mt6350_set_register_value(flagname, val);
}

kal_uint16 pmic_get_register_value(PMU_FLAGS_LIST_ENUM flagname)
{
	return mt6350_get_register_value(flagname);
}

kal_uint16 bc11_set_register_value(PMU_FLAGS_LIST_ENUM flagname,kal_uint32 val)
{
	return mt6350_set_register_value(flagname, val);
}


kal_uint16 bc11_get_register_value(PMU_FLAGS_LIST_ENUM flagname)
{
	return mt6350_get_register_value(flagname);
}