rt9458.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792
  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <platform/mt_typedefs.h>
  32. #include <platform/mt_reg_base.h>
  33. #include <platform/errno.h>
  34. #include <platform/mt_i2c.h>
  35. #include <platform/mt_pmic.h>
  36. #include <platform/rt9458.h>
  37. #include <platform/mtk_charger_intf.h>
  38. #include <printf.h>
  39. #if !defined(CONFIG_POWER_EXT)
  40. #include <platform/upmu_common.h>
  41. #endif
  42. #define RT9458_LK_DRV_VERSION "1.0.1_MTK"
  43. /* ================= */
  44. /* Internal variable */
  45. /* ================= */
  46. struct rt9458_info {
  47. struct mtk_charger_info mchr_info;
  48. struct mt_i2c_t i2c;
  49. int i2c_log_level;
  50. };
  51. static const unsigned char rt9458_reg_addr[] = {
  52. RT9458_REG_CTRL1,
  53. RT9458_REG_CTRL2,
  54. RT9458_REG_CTRL3,
  55. RT9458_REG_DEVID,
  56. RT9458_REG_CTRL4,
  57. RT9458_REG_CTRL5,
  58. RT9458_REG_CTRL6,
  59. RT9458_REG_CTRL7,
  60. RT9458_REG_IRQ1,
  61. RT9458_REG_IRQ2,
  62. RT9458_REG_IRQ3,
  63. RT9458_REG_MASK1,
  64. RT9458_REG_MASK2,
  65. RT9458_REG_MASK3,
  66. RT9458_REG_CTRL8,
  67. };
  68. enum rt9458_charging_status {
  69. RT9458_CHG_STATUS_READY = 0,
  70. RT9458_CHG_STATUS_PROGRESS,
  71. RT9458_CHG_STATUS_DONE,
  72. RT9458_CHG_STATUS_FAULT,
  73. RT9458_CHG_STATUS_MAX,
  74. };
  75. /* Charging status name */
  76. static const char *rt9458_chg_status_name[RT9458_CHG_STATUS_MAX] = {
  77. "ready", "progress", "done", "fault",
  78. };
  79. /* uV, step is 20000uA except 4300000->4330000 */
  80. static const u32 rt9458_battery_voreg[] = {
  81. 3500000, 3520000, 3540000, 3560000, 3580000, 3600000, 3620000, 3640000,
  82. 3660000, 3680000, 3700000, 3720000, 3740000, 3760000, 3780000, 3800000,
  83. 3820000, 3840000, 3860000, 3880000, 3900000, 3920000, 3940000, 3960000,
  84. 3980000, 4000000, 4020000, 4040000, 4060000, 4080000, 4100000, 4120000,
  85. 4140000, 4160000, 4180000, 4200000, 4220000, 4240000, 4260000, 4280000,
  86. 4300000, 4330000, 4350000, 4370000, 4390000, 4410000, 4430000, 4450000,
  87. 4450000, 4450000, 4450000, 4450000, 4450000, 4450000, 4450000, 4450000,
  88. 4450000, 4450000, 4450000, 4450000, 4450000, 4450000, 4450000, 4450000,
  89. };
  90. /* uV, step is 20000uA except 4300000->4330000 */
  91. static const u32 rt9458_battery_vmreg[] = {
  92. 4200000, 4220000, 4240000, 4260000, 4280000, 4300000, 4320000, 4340000,
  93. 4360000, 4380000, 4400000, 4430000, 4450000, 4450000, 4450000, 4450000,
  94. };
  95. /* ========================= */
  96. /* I2C operations */
  97. /* ========================= */
  98. static int rt9458_i2c_write_byte(struct rt9458_info *info, u8 cmd, u8 data)
  99. {
  100. unsigned int ret = I2C_OK;
  101. unsigned char write_buf[2] = {cmd, data};
  102. struct mt_i2c_t *i2c = &info->i2c;
  103. ret = i2c_write(i2c, write_buf, 2);
  104. if (ret != I2C_OK)
  105. dprintf(CRITICAL,
  106. "%s: I2CW[0x%02X] = 0x%02X failed, code = %d\n",
  107. __func__, cmd, data, ret);
  108. else
  109. dprintf(info->i2c_log_level, "%s: I2CW[0x%02X] = 0x%02X\n",
  110. __func__, cmd, data);
  111. return ret;
  112. }
  113. static int rt9458_i2c_read_byte(struct rt9458_info *info, u8 cmd, u8 *data)
  114. {
  115. int ret = I2C_OK;
  116. u8 ret_data = cmd;
  117. struct mt_i2c_t *i2c = &info->i2c;
  118. ret = i2c_write_read(i2c, &ret_data, 1, 1);
  119. if (ret != I2C_OK)
  120. dprintf(CRITICAL, "%s: I2CR[0x%02X] failed, code = %d\n",
  121. __func__, cmd, ret);
  122. else {
  123. dprintf(info->i2c_log_level, "%s: I2CR[0x%02X] = 0x%02X\n",
  124. __func__, cmd, ret_data);
  125. *data = ret_data;
  126. }
  127. return ret;
  128. }
  129. static int rt9458_i2c_test_bit(struct rt9458_info *info, u8 cmd, u8 shift,
  130. bool *is_one)
  131. {
  132. int ret = 0;
  133. u8 data = 0;
  134. ret = rt9458_i2c_read_byte(info, cmd, &data);
  135. if (ret != I2C_OK)
  136. return ret;
  137. data &= (1 << shift);
  138. *is_one = (data == 0 ? false : true);
  139. return ret;
  140. }
  141. static int rt9458_i2c_update_bits(struct rt9458_info *info, u8 cmd, u8 data,
  142. u8 mask)
  143. {
  144. int ret = 0;
  145. u8 reg_data = 0;
  146. ret = rt9458_i2c_read_byte(info, cmd, &reg_data);
  147. if (ret != I2C_OK)
  148. return ret;
  149. reg_data = reg_data & 0xFF;
  150. reg_data &= ~mask;
  151. reg_data |= (data & mask);
  152. return rt9458_i2c_write_byte(info, cmd, reg_data);
  153. }
  154. static inline int rt9458_set_bit(struct rt9458_info *info, u8 reg, u8 mask)
  155. {
  156. return rt9458_i2c_update_bits(info, reg, mask, mask);
  157. }
  158. static inline int rt9458_clr_bit(struct rt9458_info *info, u8 reg, u8 mask)
  159. {
  160. return rt9458_i2c_update_bits(info, reg, 0x00, mask);
  161. }
  162. /* ================== */
  163. /* internal functions */
  164. /* ================== */
  165. static int rt_charger_set_ichg(struct mtk_charger_info *mchr_info, u32 ichg);
  166. static int rt_charger_set_aicr(struct mtk_charger_info *mchr_info, u32 aicr);
  167. static int rt_charger_set_mivr(struct mtk_charger_info *mchr_info, u32 mivr);
  168. static int rt_charger_get_ichg(struct mtk_charger_info *mchr_info, u32 *ichg);
  169. static int rt_charger_get_aicr(struct mtk_charger_info *mchr_info, u32 *aicr);
  170. static u8 rt9458_find_closest_reg_value(u32 min, u32 max,
  171. u32 step, u32 num, u32 target)
  172. {
  173. u32 i = 0, cur_val = 0, next_val = 0;
  174. /* Smaller than minimum supported value, use minimum one */
  175. if (target < min)
  176. return 0;
  177. for (i = 0; i < num - 1; i++) {
  178. cur_val = min + i * step;
  179. next_val = cur_val + step;
  180. if (cur_val > max)
  181. cur_val = max;
  182. if (next_val > max)
  183. next_val = max;
  184. if (target >= cur_val && target < next_val)
  185. return i;
  186. }
  187. /* Greater than maximum supported value, use maximum one */
  188. return num - 1;
  189. }
  190. static u8 rt9458_find_closest_reg_value_via_table(const u32 *value_table,
  191. u32 table_size, u32 target_value)
  192. {
  193. u32 i = 0;
  194. /* Smaller than minimum supported value, use minimum one */
  195. if (target_value < value_table[0])
  196. return 0;
  197. for (i = 0; i < table_size - 1; i++) {
  198. if (target_value >= value_table[i] && target_value < value_table[i + 1])
  199. return i;
  200. }
  201. /* Greater than maximum supported value, use maximum one */
  202. return table_size - 1;
  203. }
  204. static u32 rt9458_find_closest_real_value(u32 min, u32 max, u32 step,
  205. u8 reg_val)
  206. {
  207. u32 ret_val = 0;
  208. ret_val = min + reg_val * step;
  209. if (ret_val > max)
  210. ret_val = max;
  211. return ret_val;
  212. }
  213. /*
  214. * internal: use AICR setting in CTRL2
  215. * otherwise, AICR is decided by OTG_PinP
  216. */
  217. static int rt9458_set_aicr_int(struct rt9458_info *info, bool internal)
  218. {
  219. int ret = 0;
  220. dprintf(CRITICAL, "%s: internal = %d\n", __func__, internal);
  221. ret = (internal ? rt9458_set_bit : rt9458_clr_bit)
  222. (info, RT9458_REG_CTRL2, RT9458_MASK_AICR_INT);
  223. return ret;
  224. }
  225. static int rt9458_set_aicr_sel(struct rt9458_info *info, bool sel)
  226. {
  227. int ret = 0;
  228. dprintf(CRITICAL, "%s: sel = %d\n", __func__, sel);
  229. ret = (sel ? rt9458_set_bit : rt9458_clr_bit)
  230. (info, RT9458_REG_CTRL6, RT9458_MASK_AICR_SEL);
  231. return ret;
  232. }
  233. static bool rt9458_is_hw_exist(struct rt9458_info *info)
  234. {
  235. int ret = 0;
  236. u8 vendor_id = 0, chip_rev = 0, data = 0;
  237. ret = rt9458_i2c_read_byte(info, RT9458_REG_DEVID, &data);
  238. if (ret < 0)
  239. return 0;
  240. vendor_id = data & 0xF0;
  241. chip_rev = data & 0x0F;
  242. if (vendor_id != RT9458_VENDOR_ID) {
  243. dprintf(CRITICAL, "%s: vendor id is incorrect (0x%02X)\n",
  244. __func__, vendor_id);
  245. return false;
  246. }
  247. dprintf(CRITICAL, "%s: chip rev (E%d, 0x%02X)\n", __func__, chip_rev,
  248. chip_rev);
  249. info->mchr_info.device_id = chip_rev;
  250. return true;
  251. }
  252. static int rt9458_enable_hz(struct rt9458_info *info, bool en)
  253. {
  254. int ret = 0;
  255. dprintf(CRITICAL, "%s: en = %d\n", __func__, en);
  256. ret = (en ? rt9458_set_bit : rt9458_clr_bit)
  257. (info, RT9458_REG_CTRL2, RT9458_MASK_HZ_EN);
  258. return ret;
  259. }
  260. static int rt9458_reset_chip(struct rt9458_info *info)
  261. {
  262. int ret = 0;
  263. dprintf(CRITICAL, "%s\n", __func__);
  264. ret = rt9458_enable_hz(info, false);
  265. if (ret < 0)
  266. dprintf(CRITICAL, "%s: disable hz fail\n", __func__);
  267. ret = rt9458_set_bit(info, RT9458_REG_CTRL4, RT9458_MASK_RST);
  268. return ret;
  269. }
  270. static int rt9458_set_battery_voreg(struct rt9458_info *info, u32 voreg)
  271. {
  272. int ret = 0;
  273. u8 reg_voreg = 0;
  274. reg_voreg = rt9458_find_closest_reg_value_via_table(
  275. rt9458_battery_voreg,
  276. ARRAY_SIZE(rt9458_battery_voreg),
  277. voreg
  278. );
  279. dprintf(CRITICAL, "%s: voreg = %d(0x%02X)\n", __func__, voreg, reg_voreg);
  280. ret = rt9458_i2c_update_bits(
  281. info,
  282. RT9458_REG_CTRL3,
  283. reg_voreg << RT9458_SHIFT_VOREG,
  284. RT9458_MASK_VOREG
  285. );
  286. return ret;
  287. }
  288. static int rt9458_enable_wdt(struct rt9458_info *info, bool enable)
  289. {
  290. int ret = 0;
  291. dprintf(CRITICAL, "%s: enable = %d\n", __func__, enable);
  292. ret = (enable ? rt9458_set_bit : rt9458_clr_bit)
  293. (info, RT9458_REG_CTRL5, RT9458_MASK_TMR_EN);
  294. return ret;
  295. }
  296. static int rt9458_get_charging_status(struct rt9458_info *info,
  297. enum rt9458_charging_status *chg_stat)
  298. {
  299. int ret = 0;
  300. u8 data = 0;
  301. ret = rt9458_i2c_read_byte(info, RT9458_REG_CTRL1, &data);
  302. if (ret < 0)
  303. return ret;
  304. *chg_stat = (data & RT9458_MASK_CHG_STAT) >> RT9458_SHIFT_CHG_STAT;
  305. return ret;
  306. }
  307. static int rt9458_enable_te(struct rt9458_info *info, bool enable)
  308. {
  309. int ret = 0;
  310. dprintf(CRITICAL, "%s: enable = %d\n", __func__, enable);
  311. ret = (enable ? rt9458_set_bit : rt9458_clr_bit)
  312. (info, RT9458_REG_CTRL2, RT9458_MASK_TE_EN);
  313. return ret;
  314. }
  315. static int rt9458_enable_te_shutdown(struct rt9458_info *info, bool enable)
  316. {
  317. int ret = 0;
  318. dprintf(CRITICAL, "%s: enable = %d\n", __func__, enable);
  319. ret = (enable ? rt9458_set_bit : rt9458_clr_bit)
  320. (info, RT9458_REG_CTRL2, RT9458_MASK_TE_SHTDM_EN);
  321. return ret;
  322. }
  323. static int rt9458_set_battery_vmreg(struct rt9458_info *info, u32 vmreg)
  324. {
  325. int ret = 0;
  326. u8 reg_vmreg = 0;
  327. reg_vmreg = rt9458_find_closest_reg_value_via_table(
  328. rt9458_battery_vmreg,
  329. ARRAY_SIZE(rt9458_battery_vmreg),
  330. vmreg
  331. );
  332. dprintf(CRITICAL, "%s: vmreg = %d(0x%02X)\n", __func__, vmreg, reg_vmreg);
  333. ret = rt9458_i2c_update_bits(
  334. info,
  335. RT9458_REG_CTRL7,
  336. reg_vmreg << RT9458_SHIFT_VMREG,
  337. RT9458_MASK_VMREG
  338. );
  339. return ret;
  340. }
  341. static int rt9458_set_ieoc(struct rt9458_info *info, u32 ieoc)
  342. {
  343. int ret = 0;
  344. /* Find corresponding reg value */
  345. u8 reg_ieoc = rt9458_find_closest_reg_value(RT9458_IEOC_MIN,
  346. RT9458_IEOC_MAX, RT9458_IEOC_STEP, RT9458_IEOC_NUM, ieoc);
  347. dprintf(CRITICAL, "%s: ieoc = %d(0x%02X)\n", __func__, ieoc, reg_ieoc);
  348. ret = rt9458_i2c_update_bits(
  349. info,
  350. RT9458_REG_CTRL5,
  351. reg_ieoc << RT9458_SHIFT_IEOC,
  352. RT9458_MASK_IEOC
  353. );
  354. return ret;
  355. }
  356. static int rt9458_get_mivr(struct rt9458_info *info, u32 *mivr)
  357. {
  358. int ret = 0;
  359. u8 reg_mivr = 0, data = 0;
  360. ret = rt9458_i2c_read_byte(info, RT9458_REG_CTRL8, &data);
  361. if (ret < 0)
  362. return ret;
  363. reg_mivr = ((data & RT9458_MASK_MIVR) >> RT9458_SHIFT_MIVR) & 0xFF;
  364. *mivr = rt9458_find_closest_real_value(RT9458_MIVR_MIN, RT9458_MIVR_MAX,
  365. RT9458_MIVR_STEP, reg_mivr);
  366. return ret;
  367. }
  368. static int rt9458_get_ieoc(struct rt9458_info *info, u32 *ieoc)
  369. {
  370. int ret = 0;
  371. u8 reg_ieoc = 0, data = 0;
  372. ret = rt9458_i2c_read_byte(info, RT9458_REG_CTRL5, &data);
  373. if (ret < 0)
  374. return ret;
  375. reg_ieoc = (data & RT9458_MASK_IEOC) >> RT9458_SHIFT_IEOC;
  376. *ieoc = rt9458_find_closest_real_value(RT9458_IEOC_MIN, RT9458_IEOC_MAX,
  377. RT9458_IEOC_STEP, reg_ieoc);
  378. return ret;
  379. }
  380. static int rt9458_is_charging_enable(struct rt9458_info *info, bool *enable)
  381. {
  382. int ret = 0;
  383. ret = rt9458_i2c_test_bit(info, RT9458_REG_CTRL7, RT9458_SHIFT_CHG_EN,
  384. enable);
  385. return ret;
  386. }
  387. static int rt9458_init_setting(struct rt9458_info *info)
  388. {
  389. int ret = 0;
  390. dprintf(CRITICAL, "%s\n", __func__);
  391. /* Set AICR to internal */
  392. ret = rt9458_set_aicr_int(info, true);
  393. if (ret < 0)
  394. dprintf(CRITICAL, "%s: set AICR int failed\n", __func__);
  395. /* Set VMREG to maximum, uV */
  396. ret = rt9458_set_battery_vmreg(info, 4450000);
  397. if (ret < 0)
  398. dprintf(CRITICAL, "%s: set vmreg failed\n", __func__);
  399. ret = rt9458_set_battery_voreg(info, 4350000);
  400. if (ret < 0)
  401. dprintf(CRITICAL, "%s: set voreg failed\n", __func__);
  402. ret = rt_charger_set_ichg(&info->mchr_info, 1550000);
  403. if (ret < 0)
  404. dprintf(CRITICAL, "%s: set ichg failed\n", __func__);
  405. ret = rt_charger_set_aicr(&info->mchr_info, 500000);
  406. if (ret < 0)
  407. dprintf(CRITICAL, "%s: set aicr failed\n", __func__);
  408. ret = rt_charger_set_mivr(&info->mchr_info, 4500000);
  409. if (ret < 0)
  410. dprintf(CRITICAL, "%s: set mivr failed\n", __func__);
  411. ret = rt9458_set_ieoc(info, 200000);
  412. if (ret < 0)
  413. dprintf(CRITICAL, "%s: set ieoc failed\n", __func__);
  414. ret = rt9458_enable_te(info, true);
  415. if (ret < 0)
  416. dprintf(CRITICAL, "%s: set te failed\n", __func__);
  417. ret = rt9458_enable_te_shutdown(info, true);
  418. if (ret < 0)
  419. dprintf(CRITICAL, "%s: set te shutdown failed\n", __func__);
  420. ret = rt9458_enable_wdt(info, true);
  421. if (ret < 0)
  422. dprintf(CRITICAL, "%s: set wdt failed\n", __func__);
  423. return ret;
  424. }
  425. /* =========================================================== */
  426. /* The following is implementation for interface of rt_charger */
  427. /* =========================================================== */
  428. static int rt_charger_dump_register(struct mtk_charger_info *mchr_info)
  429. {
  430. u32 i = 0;
  431. int ret = 0;
  432. u32 ichg = 0, aicr = 0, mivr = 0, ieoc = 0;
  433. u8 data = 0;
  434. bool chg_enable = 0;
  435. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  436. enum rt9458_charging_status chg_status = RT9458_CHG_STATUS_READY;
  437. ret = rt9458_get_charging_status(info, &chg_status);
  438. if (chg_status == RT9458_CHG_STATUS_FAULT) {
  439. for (i = 0; i < ARRAY_SIZE(rt9458_reg_addr); i++)
  440. ret = rt9458_i2c_read_byte(info, rt9458_reg_addr[i],
  441. &data);
  442. }
  443. ret = rt_charger_get_ichg(&info->mchr_info, &ichg);
  444. ret = rt9458_get_mivr(info, &mivr);
  445. ret = rt_charger_get_aicr(&info->mchr_info, &aicr);
  446. ret = rt9458_get_ieoc(info, &ieoc);
  447. ret = rt9458_is_charging_enable(info, &chg_enable);
  448. dprintf(CRITICAL, "%s: ICHG = %dmA, AICR = %dmA, MIVR = %dmV, IEOC = %dmA\n",
  449. __func__, ichg / 1000, aicr / 1000, mivr / 1000, ieoc / 1000);
  450. dprintf(CRITICAL, "%s: CHG_EN = %d, CHG_STATUS = %s\n",
  451. __func__, chg_enable, rt9458_chg_status_name[chg_status]);
  452. return ret;
  453. }
  454. static int rt_charger_enable_charging(struct mtk_charger_info *mchr_info,
  455. bool enable)
  456. {
  457. int ret = 0;
  458. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  459. dprintf(CRITICAL, "%s: enable = %d\n", __func__, enable);
  460. ret = (enable ? rt9458_set_bit : rt9458_clr_bit)
  461. (info, RT9458_REG_CTRL7, RT9458_MASK_CHG_EN);
  462. return ret;
  463. }
  464. static int rt_charger_set_ichg(struct mtk_charger_info *mchr_info, u32 ichg)
  465. {
  466. int ret = 0;
  467. u8 reg_ichg = 0;
  468. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  469. /* Find corresponding reg value */
  470. reg_ichg = rt9458_find_closest_reg_value(RT9458_ICHG_MIN,
  471. RT9458_ICHG_MAX, RT9458_ICHG_STEP, RT9458_ICHG_NUM, ichg);
  472. dprintf(CRITICAL, "%s: ichg = %d(0x%02X)\n", __func__, ichg, reg_ichg);
  473. ret = rt9458_i2c_update_bits(
  474. info,
  475. RT9458_REG_CTRL6,
  476. reg_ichg << RT9458_SHIFT_ICHG,
  477. RT9458_MASK_ICHG
  478. );
  479. return ret;
  480. }
  481. static int rt_charger_set_aicr(struct mtk_charger_info *mchr_info, u32 aicr)
  482. {
  483. int ret = 0;
  484. u8 reg_aicr = 0;
  485. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  486. if (aicr < 500000) /* AICR = 100 mA */
  487. reg_aicr = 0x00;
  488. else if (aicr < 700000) { /* AICR = 500 mA */
  489. ret = rt9458_set_aicr_sel(info, false);
  490. if (ret < 0)
  491. return ret;
  492. reg_aicr = 0x01;
  493. } else if (aicr < 1000000) { /* AICR = 700 mA */
  494. ret = rt9458_set_aicr_sel(info, true);
  495. if (ret < 0)
  496. return ret;
  497. reg_aicr = 0x01;
  498. } else if (aicr == 1000000) { /* AICR = 1000mA */
  499. ret = rt9458_set_aicr_sel(info, false);
  500. if (ret < 0)
  501. return ret;
  502. reg_aicr = 0x02;
  503. } else /* AICR = no limit */
  504. reg_aicr = 0x03;
  505. dprintf(CRITICAL, "%s: aicr = %d(0x%02X)\n", __func__, aicr, reg_aicr);
  506. ret = rt9458_i2c_update_bits(
  507. info,
  508. RT9458_REG_CTRL2,
  509. reg_aicr << RT9458_SHIFT_AICR,
  510. RT9458_MASK_AICR
  511. );
  512. return ret;
  513. }
  514. static int rt_charger_set_mivr(struct mtk_charger_info *mchr_info, u32 mivr)
  515. {
  516. int ret = 0;
  517. u8 reg_mivr = 0;
  518. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  519. reg_mivr = rt9458_find_closest_reg_value(RT9458_MIVR_MIN,
  520. RT9458_MIVR_MAX, RT9458_MIVR_STEP, RT9458_MIVR_NUM, mivr);
  521. dprintf(CRITICAL, "%s: mivr = %d(0x%02X)\n", __func__, mivr, reg_mivr);
  522. ret = rt9458_i2c_update_bits(
  523. info,
  524. RT9458_REG_CTRL8,
  525. reg_mivr << RT9458_SHIFT_MIVR,
  526. RT9458_MASK_MIVR
  527. );
  528. return ret;
  529. }
  530. static int rt_charger_get_ichg(struct mtk_charger_info *mchr_info, u32 *ichg)
  531. {
  532. int ret = 0;
  533. u8 reg_ichg = 0, data = 0;
  534. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  535. ret = rt9458_i2c_read_byte(info, RT9458_REG_CTRL6, &data);
  536. if (ret < 0)
  537. return ret;
  538. reg_ichg = (data & RT9458_MASK_ICHG) >> RT9458_SHIFT_ICHG;
  539. *ichg = rt9458_find_closest_real_value(RT9458_ICHG_MIN, RT9458_ICHG_MAX,
  540. RT9458_ICHG_STEP, reg_ichg);
  541. return ret;
  542. }
  543. static int rt_charger_get_aicr(struct mtk_charger_info *mchr_info, u32 *aicr)
  544. {
  545. int ret = 0;
  546. bool aicr_sel = false;
  547. u8 reg_aicr = 0, data = 0;
  548. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  549. /* Read AICR sel */
  550. ret = rt9458_i2c_test_bit(info, RT9458_REG_CTRL6, RT9458_SHIFT_AICR_SEL,
  551. &aicr_sel);
  552. if (ret < 0)
  553. return ret;
  554. /* Read AICR */
  555. ret = rt9458_i2c_read_byte(info, RT9458_REG_CTRL2, &data);
  556. if (ret < 0)
  557. return ret;
  558. reg_aicr = ((data & RT9458_MASK_AICR) >> RT9458_SHIFT_AICR) & 0xFF;
  559. switch (reg_aicr) {
  560. case 0:
  561. *aicr = 100000;
  562. break;
  563. case 1:
  564. *aicr = aicr_sel ? 700000 : 500000;
  565. break;
  566. case 2:
  567. *aicr = aicr_sel ? 700000 : 1000000;
  568. break;
  569. case 3:
  570. *aicr = 0;
  571. break;
  572. }
  573. return ret;
  574. }
  575. static int rt_charger_enable_wdt(struct mtk_charger_info *mchr_info, bool en)
  576. {
  577. struct rt9458_info *info = (struct rt9458_info *)mchr_info;
  578. return rt9458_enable_wdt(info, en);
  579. }
  580. static struct mtk_charger_ops rt9458_mchr_ops = {
  581. .dump_register = rt_charger_dump_register,
  582. .enable_charging = rt_charger_enable_charging,
  583. .get_ichg = rt_charger_get_ichg,
  584. .set_ichg = rt_charger_set_ichg,
  585. .set_aicr = rt_charger_set_aicr,
  586. .set_mivr = rt_charger_set_mivr,
  587. .get_aicr = rt_charger_get_aicr,
  588. .enable_wdt = rt_charger_enable_wdt,
  589. };
  590. /* Info of primary charger */
  591. static struct rt9458_info g_rt9458_info = {
  592. .mchr_info = {
  593. .name = "primary_charger",
  594. .alias_name = "rt9458",
  595. .device_id = -1,
  596. .mchr_ops = &rt9458_mchr_ops,
  597. },
  598. .i2c = {
  599. .id = I2C1,
  600. .addr = RT9458_SLAVE_ADDR,
  601. .mode = ST_MODE,
  602. .speed = 100,
  603. },
  604. .i2c_log_level = INFO,
  605. };
  606. int rt9458_probe(void)
  607. {
  608. int ret = 0;
  609. /* Check primary charger */
  610. if (rt9458_is_hw_exist(&g_rt9458_info)) {
  611. ret = rt9458_reset_chip(&g_rt9458_info);
  612. if (ret < 0)
  613. dprintf(CRITICAL, "%s: reset chip fail\n", __func__);
  614. ret = rt9458_init_setting(&g_rt9458_info);
  615. mtk_charger_set_info(&(g_rt9458_info.mchr_info));
  616. dprintf(CRITICAL, "%s: %s\n", __func__, RT9458_LK_DRV_VERSION);
  617. }
  618. return ret;
  619. }
  620. /*
  621. * Revision Note
  622. * 1.0.1
  623. * (1) Add chip reset function
  624. *
  625. * 1.0.0
  626. * (1) Initial release
  627. */