primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. //#include<linux/timer.h>
  44. #define DDP_LK_BOOT
  45. #ifndef HZ
  46. #define HZ 100
  47. #endif
  48. #ifdef DDP_LK_BOOT
  49. typedef void * cmdqRecHandle;
  50. #endif
  51. #define ALIGN_TO(x, n) \
  52. (((x) + ((n) - 1)) & ~((n) - 1))
  53. int primary_display_use_cmdq = CMDQ_DISABLE;
  54. int primary_display_use_m4u = 1;
  55. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  56. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  57. static UINT32 disp_fb_pages = 3; ///double buffer
  58. static UINT32 display_init;
  59. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  60. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  61. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  62. extern void video_printf(const char *fmt, ...);
  63. extern void disp_path_clock_on(char *str);
  64. typedef struct _disp_dfo_item {
  65. char name[32];
  66. int value;
  67. } disp_dfo_item_t;
  68. static disp_dfo_item_t disp_dfo_setting[] = {
  69. {"LCM_FAKE_WIDTH", 0},
  70. {"LCM_FAKE_HEIGHT", 0},
  71. {"DISP_DEBUG_SWITCH", 0}
  72. };
  73. typedef struct {
  74. int state;
  75. int need_trigger_overlay;
  76. DISP_PRIMARY_PATH_MODE mode;
  77. unsigned int last_vsync_tick;
  78. #ifndef DDP_LK_BOOT
  79. struct mutex lock;
  80. #endif
  81. disp_lcm_handle * plcm;
  82. cmdqRecHandle cmdq_handle_config;
  83. cmdqRecHandle cmdq_handle_trigger;
  84. disp_path_handle dpmgr_handle;
  85. disp_path_handle ovl2mem_path_handle;
  86. } display_primary_path_context;
  87. #define pgc _get_context()
  88. static display_primary_path_context* _get_context(void)
  89. {
  90. static int is_context_inited = 0;
  91. static display_primary_path_context g_context;
  92. if (!is_context_inited) {
  93. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  94. is_context_inited = 1;
  95. }
  96. return &g_context;
  97. }
  98. static void _primary_path_lock(void)
  99. {
  100. #ifndef DDP_LK_BOOT
  101. disp_sw_mutex_lock(&(pgc->lock));
  102. #endif
  103. }
  104. static void _primary_path_unlock(void)
  105. {
  106. #ifndef DDP_LK_BOOT
  107. disp_sw_mutex_unlock(&(pgc->lock));
  108. #endif
  109. }
  110. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  111. {
  112. if (plcm == NULL) {
  113. DISPERR("plcm is null\n");
  114. return DISP_MODULE_UNKNOWN;
  115. }
  116. if (plcm->params->type == LCM_TYPE_DSI) {
  117. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  118. return DISP_MODULE_DSI0;
  119. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  120. return DISP_MODULE_DSI1;
  121. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  122. return DISP_MODULE_DSIDUAL;
  123. } else {
  124. return DISP_MODULE_DSI0;
  125. }
  126. } else if (plcm->params->type == LCM_TYPE_DPI) {
  127. return DISP_MODULE_UNKNOWN;
  128. } else {
  129. DISPERR("can't find primary path dst module\n");
  130. return DISP_MODULE_UNKNOWN;
  131. }
  132. }
  133. static int _build_path_direct_link(void)
  134. {
  135. int ret = 0;
  136. DISP_MODULE_ENUM dst_module = 0;
  137. DISPFUNC();
  138. pgc->mode = DIRECT_LINK_MODE;
  139. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  140. if (pgc->dpmgr_handle) {
  141. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  142. } else {
  143. DISPCHECK("dpmgr create path FAIL\n");
  144. return -1;
  145. }
  146. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  147. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  148. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  149. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  150. return ret;
  151. }
  152. static int _build_path_decouple(void)
  153. {
  154. return 0;
  155. }
  156. static int _build_path_single_layer(void)
  157. {
  158. return 0;
  159. }
  160. static int _build_path_debug_rdma1_dsi0(void)
  161. {
  162. return 0;
  163. }
  164. static void _build_cmdq_trigger_loop(void)
  165. {
  166. #ifndef DDP_LK_BOOT
  167. int ret = 0;
  168. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  169. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  170. cmdqRecReset(pgc->cmdq_handle_trigger);
  171. if (primary_display_is_video_mode()) {
  172. // wait and clear stream_done
  173. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  174. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  175. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  176. } else {
  177. // only in DSI Command mode we need to wait these
  178. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  179. // no internal te on fpga now.
  180. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  181. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  182. // block config threads, we'll about to update frame
  183. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  184. // only in DSI command mode we need to enable mutex explicitly
  185. // WRITE mutex enable
  186. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  187. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  188. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  189. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  190. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  191. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  192. // polling DSI idle
  193. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  194. // polling wdma frame done
  195. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  196. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  197. /*********************/
  198. /***build cmdq finished***/
  199. /*********************/
  200. // TODO:
  201. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  202. // RUN forever!!!!
  203. BUG_ON(ret < 0);
  204. }
  205. #endif
  206. }
  207. static void _start_cmdq_trigger_loop(void)
  208. {
  209. #ifndef DDP_LK_BOOT
  210. int ret = 0;
  211. // this should be called only once because trigger loop will nevet stop
  212. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  213. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  214. #endif
  215. }
  216. static void _set_cmdq_config_handle_dirty(void)
  217. {
  218. #ifndef DDP_LK_BOOT
  219. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  220. cmdqRecFlush(pgc->cmdq_handle_config);
  221. #endif
  222. }
  223. static void _reset_cmdq_config_handle(void)
  224. {
  225. #ifndef DDP_LK_BOOT
  226. cmdqRecReset(pgc->cmdq_handle_config);
  227. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  228. #endif
  229. }
  230. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  231. {
  232. if (src && dst) {
  233. dst->inputFormat = src->fmt;
  234. dst->address = src->addr;
  235. dst->width = src->src_w;
  236. dst->height = src->src_h;
  237. dst->pitch = src->src_pitch;
  238. return 0;
  239. } else {
  240. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  241. return -1;
  242. }
  243. }
  244. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  245. {
  246. if (src && dst) {
  247. dst->layer = src->layer;
  248. dst->layer_en = src->layer_en;
  249. dst->fmt = src->fmt;
  250. dst->addr = src->addr;
  251. dst->vaddr = src->vaddr;
  252. dst->src_x = src->src_x;
  253. dst->src_y = src->src_y;
  254. dst->src_w = src->src_w;
  255. dst->src_h = src->src_h;
  256. dst->src_pitch = src->src_pitch;
  257. dst->dst_x = src->dst_x;
  258. dst->dst_y = src->dst_y;
  259. dst->dst_w = src->dst_w;
  260. dst->dst_h = src->dst_h;
  261. dst->keyEn = src->keyEn;
  262. dst->key = src->key;
  263. dst->aen = src->aen;
  264. dst->alpha = src->alpha;
  265. dst->isDirty = src->isDirty;
  266. dst->buff_idx = src->buff_idx;
  267. dst->identity = src->identity;
  268. dst->connected_type = src->connected_type;
  269. dst->security = src->security;
  270. return 0;
  271. } else {
  272. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  273. return -1;
  274. }
  275. }
  276. void _dump_lcm_info_by_video_printf(void)
  277. {
  278. LCM_DRIVER *l = NULL;
  279. LCM_PARAMS *p = NULL;
  280. disp_lcm_handle *plcm = pgc->plcm;
  281. if (plcm == NULL) {
  282. DISPERR("plcm is null\n");
  283. return;
  284. }
  285. l = plcm->drv;
  286. p = plcm->params;
  287. if (l && p) {
  288. video_printf("[LCM], name: %s\n", l->name);
  289. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  290. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  291. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  292. switch (p->lcm_if) {
  293. case LCM_INTERFACE_DSI0:
  294. video_printf("[LCM] interface: DSI0\n");
  295. break;
  296. case LCM_INTERFACE_DSI1:
  297. video_printf("[LCM] interface: DSI1\n");
  298. break;
  299. case LCM_INTERFACE_DPI0:
  300. video_printf("[LCM] interface: DPI0\n");
  301. break;
  302. case LCM_INTERFACE_DPI1:
  303. video_printf("[LCM] interface: DPI1\n");
  304. break;
  305. case LCM_INTERFACE_DBI0:
  306. video_printf("[LCM] interface: DBI0\n");
  307. break;
  308. default:
  309. video_printf("[LCM] interface: unknown\n");
  310. break;
  311. }
  312. switch (p->type) {
  313. case LCM_TYPE_DBI:
  314. video_printf("[LCM] Type: DBI\n");
  315. break;
  316. case LCM_TYPE_DSI:
  317. video_printf("[LCM] Type: DSI\n");
  318. break;
  319. case LCM_TYPE_DPI:
  320. video_printf("[LCM] Type: DPI\n");
  321. break;
  322. default:
  323. video_printf("[LCM] TYPE: unknown\n");
  324. break;
  325. }
  326. if (p->type == LCM_TYPE_DSI) {
  327. switch (p->dsi.mode) {
  328. case CMD_MODE:
  329. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  330. break;
  331. case SYNC_PULSE_VDO_MODE:
  332. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  333. break;
  334. case SYNC_EVENT_VDO_MODE:
  335. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  336. break;
  337. case BURST_VDO_MODE:
  338. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  339. break;
  340. default:
  341. video_printf("[LCM] DSI Mode: Unknown\n");
  342. break;
  343. }
  344. }
  345. if (p->type == LCM_TYPE_DSI) {
  346. video_printf("[LCM] LANE_NUM: %d,data_format: %d,"
  347. " vertical_sync_active: %d\n",
  348. p->dsi.LANE_NUM,
  349. p->dsi.data_format.format,
  350. p->dsi.vertical_sync_active);
  351. #ifdef MY_TODO
  352. #error
  353. #endif
  354. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d,"
  355. "hact: %d, hbp: %d, hfp: %d, hblank: %d\n",
  356. p->dsi.vertical_sync_active,
  357. p->dsi.vertical_backporch,
  358. p->dsi.vertical_frontporch,
  359. p->dsi.vertical_active_line,
  360. p->dsi.horizontal_sync_active,
  361. p->dsi.horizontal_backporch,
  362. p->dsi.horizontal_frontporch,
  363. p->dsi.horizontal_blanking_pixel);
  364. video_printf("[LCM] pll_select: %d, pll_div1: %d,"
  365. " pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",
  366. p->dsi.pll_select,
  367. p->dsi.pll_div1,
  368. p->dsi.pll_div2,
  369. p->dsi.fbk_div,
  370. p->dsi.fbk_sel,
  371. p->dsi.rg_bir);
  372. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d,"
  373. " dsi_clock: %d, ssc_range: %d, ssc_disable: %d,"
  374. " compatibility_for_nvk: %d, cont_clock: %d\n",
  375. p->dsi.rg_bic,
  376. p->dsi.rg_bp,
  377. p->dsi.PLL_CLOCK,
  378. p->dsi.dsi_clock,
  379. p->dsi.ssc_range,
  380. p->dsi.ssc_disable,
  381. p->dsi.compatibility_for_nvk,
  382. p->dsi.cont_clock);
  383. video_printf("[LCM] lcm_ext_te_enable: %d,"
  384. " noncont_clock: %d, noncont_clock_period: %d\n",
  385. p->dsi.lcm_ext_te_enable,
  386. p->dsi.noncont_clock,
  387. p->dsi.noncont_clock_period);
  388. }
  389. }
  390. return;
  391. }
  392. unsigned int mt_disp_parse_dfo_setting(void)
  393. {
  394. unsigned int i, j=0 ;
  395. char tmp[11];
  396. char *buffer = NULL;
  397. char *ptr = NULL;
  398. buffer = (char *)get_env("DFO");
  399. DISPMSG("env buffer = %s\n", buffer);
  400. if (buffer != NULL) {
  401. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  402. j = 0;
  403. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  404. ptr = strstr(buffer, disp_dfo_setting[i].name);
  405. if (ptr == NULL) continue;
  406. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  407. do {} while ((*ptr++) != ',');
  408. do {tmp[j++] = *ptr++;}
  409. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  410. disp_dfo_setting[i].value = atoi((const char*)tmp);
  411. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  412. }
  413. } else {
  414. DISPMSG("env buffer = NULL\n");
  415. }
  416. return 0;
  417. }
  418. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  419. {
  420. char *disp_name;
  421. int disp_value;
  422. unsigned int i = 0;
  423. if (string == NULL)
  424. return -1;
  425. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  426. disp_name = disp_dfo_setting[i].name;
  427. disp_value = disp_dfo_setting[i].value;
  428. if (!strcmp(disp_name, string)) {
  429. *value = disp_value;
  430. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  431. return 0;
  432. }
  433. }
  434. return 0;
  435. }
  436. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  437. int primary_display_is_lcm_connected(void)
  438. {
  439. return pgc->plcm->is_connected;
  440. }
  441. const char* primary_display_get_lcm_name(void)
  442. {
  443. return disp_lcm_get_name(pgc->plcm);
  444. }
  445. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  446. {
  447. if (pgc->plcm) {
  448. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  449. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  450. // otherwise we will have a panic in lk(root cause unknown).
  451. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  452. DISPERR("Invalid resolution: %dx%d\n", width, height);
  453. return -1;
  454. }
  455. if (primary_display_is_video_mode()) {
  456. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  457. return -1;
  458. }
  459. pgc->plcm->params->width = width;
  460. pgc->plcm->params->height = height;
  461. return 0;
  462. } else {
  463. return -1;
  464. }
  465. }
  466. int primary_display_init(char *lcm_name)
  467. {
  468. DISPFUNC();
  469. DISP_STATUS ret = DISP_STATUS_OK;
  470. LCM_PARAMS *lcm_param = NULL;
  471. dpmgr_init();
  472. #ifndef DDP_LK_BOOT
  473. mutex_init(&(pgc->lock));
  474. #endif
  475. _primary_path_lock();
  476. if (pgc->plcm == NULL)
  477. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  478. if (pgc->plcm == NULL) {
  479. DISPCHECK("disp_lcm_probe returns null\n");
  480. ret = DISP_STATUS_ERROR;
  481. goto done;
  482. } else {
  483. DISPCHECK("disp_lcm_probe SUCCESS\n");
  484. }
  485. lcm_param = disp_lcm_get_params(pgc->plcm);
  486. if (lcm_param == NULL) {
  487. DISPERR("get lcm params FAILED\n");
  488. ret = DISP_STATUS_ERROR;
  489. goto done;
  490. }
  491. if (primary_display_mode == DIRECT_LINK_MODE) {
  492. _build_path_direct_link();
  493. DISPCHECK("primary display is DIRECT LINK MODE\n");
  494. } else if (primary_display_mode == DECOUPLE_MODE) {
  495. _build_path_decouple();
  496. DISPCHECK("primary display is DECOUPLE MODE\n");
  497. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  498. _build_path_single_layer();
  499. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  500. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  501. _build_path_debug_rdma1_dsi0();
  502. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  503. } else {
  504. DISPCHECK("primary display mode is WRONG\n");
  505. }
  506. _build_cmdq_trigger_loop();
  507. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  508. _start_cmdq_trigger_loop();
  509. DISPCHECK("primary display START cmdq trigger loop finished\n");
  510. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  511. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  512. disp_ddp_path_config data_config;
  513. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  514. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  515. data_config.dst_w = disp_lcm_width(pgc->plcm);
  516. data_config.dst_h = disp_lcm_height(pgc->plcm);
  517. if (lcm_param->type == LCM_TYPE_DSI) {
  518. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  519. data_config.lcm_bpp = 24;
  520. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  521. data_config.lcm_bpp = 16;
  522. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  523. data_config.lcm_bpp = 18;
  524. } else if (lcm_param->type == LCM_TYPE_DPI) {
  525. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  526. data_config.lcm_bpp = 24;
  527. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  528. data_config.lcm_bpp = 16;
  529. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  530. data_config.lcm_bpp = 18;
  531. }
  532. data_config.dst_dirty = 1;
  533. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  534. ret = disp_lcm_init(pgc->plcm);
  535. if (primary_display_is_video_mode()) {
  536. if (lcm_param->dsi.lfr_enable == 1) {
  537. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  538. } else {
  539. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  540. }
  541. } else {
  542. }
  543. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  544. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  545. pgc->state = 1;
  546. display_init = 1;
  547. done:
  548. _primary_path_unlock();
  549. return ret;
  550. }
  551. // register rdma done event
  552. int primary_display_wait_for_idle(void)
  553. {
  554. DISP_STATUS ret = DISP_STATUS_OK;
  555. DISPFUNC();
  556. _primary_path_lock();
  557. _primary_path_unlock();
  558. return ret;
  559. }
  560. int primary_display_wait_for_dump(void)
  561. {
  562. return 0;
  563. }
  564. static long int get_current_time_us(void)
  565. {
  566. return get_timer(0);
  567. }
  568. int priamry_display_wait_for_vsync(void)
  569. {
  570. int ret = 0;
  571. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  572. if (ret == -2) {
  573. DISPCHECK("vsync for primary display path not enabled yet\n");
  574. return -1;
  575. }
  576. // pgc->last_vsync_tick = get_current_time_us();
  577. pgc->last_vsync_tick = 0;
  578. return 0;
  579. }
  580. int primary_display_suspend(void)
  581. {
  582. DISP_STATUS ret = DISP_STATUS_OK;
  583. if (display_init == 0) {
  584. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  585. return -1;
  586. }
  587. DISPFUNC();
  588. _primary_path_lock();
  589. disp_lcm_suspend(pgc->plcm);
  590. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  591. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  592. #ifndef DDP_LK_BOOT
  593. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  594. #endif
  595. pgc->state = 0;
  596. _primary_path_unlock();
  597. return ret;
  598. }
  599. int primary_display_resume(void)
  600. {
  601. DISP_STATUS ret = DISP_STATUS_OK;
  602. DISPFUNC();
  603. _primary_path_lock();
  604. disp_path_clock_on("Primary Display Path");
  605. pgc->state = 1;
  606. _primary_path_unlock();
  607. return ret;
  608. }
  609. int primary_display_is_alive(void)
  610. {
  611. unsigned int temp = 0;
  612. DISPFUNC();
  613. _primary_path_lock();
  614. temp = pgc->state;
  615. _primary_path_unlock();
  616. return temp;
  617. }
  618. int primary_display_is_sleepd(void)
  619. {
  620. unsigned int temp = 0;
  621. DISPFUNC();
  622. _primary_path_lock();
  623. temp = !pgc->state;
  624. _primary_path_unlock();
  625. return temp;
  626. }
  627. #ifdef MTK_ROUND_CORNER_SUPPORT
  628. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  629. {
  630. if (pgc->plcm == NULL) {
  631. return NULL;
  632. }
  633. if (pgc->plcm->params) {
  634. return &(pgc->plcm->params->round_corner_params);
  635. } else {
  636. DISPERR("lcm_params is null!\n");
  637. return NULL;
  638. }
  639. }
  640. int disp_get_round_corner_size(void)
  641. {
  642. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  643. int pitch = DISP_GetScreenWidth();
  644. int size = 0;
  645. if (corner_params) {
  646. if (corner_params->round_corner_en) {
  647. if (corner_params->full_content)
  648. size = (corner_params->h + corner_params->h_bot) * pitch * 2;
  649. else
  650. size = corner_params->h * pitch * 2 * 2;
  651. } else
  652. DISPERR("corner_params is null!\n");
  653. }
  654. return size;
  655. }
  656. #endif
  657. int primary_display_get_width(void)
  658. {
  659. if (pgc->plcm == NULL) {
  660. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  661. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  662. if (pgc->plcm == NULL)
  663. return 0;
  664. }
  665. if (pgc->plcm->params) {
  666. return pgc->plcm->params->width;
  667. } else {
  668. DISPERR("lcm_params is null!\n");
  669. return 0;
  670. }
  671. }
  672. int primary_display_get_height(void)
  673. {
  674. if (pgc->plcm == NULL) {
  675. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  676. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  677. if (pgc->plcm == NULL)
  678. return 0;
  679. }
  680. if (pgc->plcm->params) {
  681. return pgc->plcm->params->height;
  682. } else {
  683. DISPERR("lcm_params is null!\n");
  684. return 0;
  685. }
  686. }
  687. int primary_display_get_bpp(void)
  688. {
  689. return 32;
  690. }
  691. int primary_display_get_info(void *dispif_info)
  692. {
  693. #if 0
  694. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  695. switch (pgc->lcm_param->type) {
  696. case LCM_TYPE_DBI: {
  697. dispif_info->displayType = DISPIF_TYPE_DBI;
  698. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  699. dispif_info->isHwVsyncAvailable = 1;
  700. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  701. break;
  702. }
  703. case LCM_TYPE_DPI: {
  704. dispif_info->displayType = DISPIF_TYPE_DPI0;
  705. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  706. dispif_info->isHwVsyncAvailable = 1;
  707. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  708. break;
  709. }
  710. case LCM_TYPE_DSI: {
  711. dispif_info->displayType = DISPIF_TYPE_DSI0;
  712. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  713. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  714. dispif_info->isHwVsyncAvailable = 1;
  715. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  716. } else {
  717. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  718. dispif_info->isHwVsyncAvailable = 1;
  719. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  720. }
  721. break;
  722. }
  723. default:
  724. break;
  725. }
  726. #ifdef MY_TODO
  727. #error
  728. if (disp_if_drv->get_panel_color_format()) {
  729. switch (disp_if_drv->get_panel_color_format()) {
  730. case PANEL_COLOR_FORMAT_RGB565:
  731. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  732. case PANEL_COLOR_FORMAT_RGB666:
  733. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  734. case PANEL_COLOR_FORMAT_RGB888:
  735. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  736. default:
  737. break;
  738. }
  739. }
  740. #endif
  741. dispif_info->displayWidth = primary_display_get_width();
  742. dispif_info->displayHeight = primary_display_get_height();
  743. #ifdef MY_TODO
  744. #error
  745. dispif_info->vsyncFPS = lcd_fps;
  746. #endif
  747. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  748. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  749. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  750. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  751. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  752. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  753. } else {
  754. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  755. }
  756. dispif_info->isConnected = 1;
  757. #ifdef MY_TODO
  758. #error
  759. {
  760. LCM_PARAMS lcm_params_temp;
  761. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  762. if (lcm_drv) {
  763. lcm_drv->get_params(&lcm_params_temp);
  764. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  765. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  766. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  767. } else {
  768. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  769. }
  770. }
  771. #endif
  772. #endif
  773. return 0;
  774. }
  775. int primary_display_get_pages(void)
  776. {
  777. return 3;
  778. }
  779. int primary_display_config_output()
  780. {
  781. return 0;
  782. }
  783. int primary_display_diagnose(void)
  784. {
  785. int ret = 0;
  786. dpmgr_check_status(pgc->dpmgr_handle);
  787. return ret;
  788. }
  789. int primary_display_trigger(int blocking)
  790. {
  791. int ret = 0;
  792. DISPFUNC();
  793. int x=0, y=0;
  794. int width = 0, height =0;
  795. x = disp_lcm_x(pgc->plcm);
  796. y = disp_lcm_y(pgc->plcm);
  797. width = disp_lcm_width(pgc->plcm);
  798. height = disp_lcm_height(pgc->plcm);
  799. _primary_path_lock();
  800. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  801. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  802. if (primary_display_is_video_mode()) {
  803. _primary_path_unlock();
  804. return 0;
  805. }
  806. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  807. }
  808. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  809. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  810. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  811. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  812. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  813. }
  814. //_set_cmdq_config_handle_dirty();
  815. //_reset_cmdq_config_handle();
  816. //if(blocking)
  817. {
  818. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  819. }
  820. } else if (pgc->mode == DECOUPLE_MODE) {
  821. DISPCHECK("trigger mode: DECOUPLE\n");
  822. if (pgc->need_trigger_overlay) {
  823. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  824. if (blocking) {
  825. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  826. }
  827. } else {
  828. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  829. // this request of trigger should be called by AAL or ovl2mem done event
  830. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  831. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  832. }
  833. _set_cmdq_config_handle_dirty();
  834. _reset_cmdq_config_handle();
  835. if (blocking) {
  836. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  837. }
  838. }
  839. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  840. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  841. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  842. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  843. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  844. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  845. }
  846. if (blocking) {
  847. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  848. }
  849. } else {
  850. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  851. }
  852. _primary_path_unlock();
  853. //primary_display_diagnose();
  854. return ret;
  855. }
  856. int primary_display_config_input(disp_input_config* input)
  857. {
  858. int ret = 0;
  859. DISPFUNC();
  860. disp_ddp_path_config data_config;
  861. // all dirty should be cleared in dpmgr_path_get_last_config()
  862. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  863. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  864. data_config.dst_dirty = 0;
  865. data_config.ovl_dirty = 0;
  866. data_config.rdma_dirty = 0;
  867. data_config.wdma_dirty = 0;
  868. _primary_path_lock();
  869. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  870. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  871. if (primary_display_is_video_mode()) {
  872. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  873. }
  874. }
  875. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  876. data_config.ovl_dirty = 1;
  877. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  878. // this is used for decouple mode, to indicate whether we need to trigger ovl
  879. pgc->need_trigger_overlay = 1;
  880. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  881. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  882. data_config.rdma_dirty= 1;
  883. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  884. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  885. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  886. data_config.rdma_dirty= 1;
  887. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  888. // TODO: should use wait_event_timeout_or_idle
  889. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  890. }
  891. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  892. } else {
  893. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  894. }
  895. _primary_path_unlock();
  896. return ret;
  897. }
  898. int primary_display_is_video_mode(void)
  899. {
  900. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  901. return disp_lcm_is_video_mode(pgc->plcm);
  902. }
  903. int primary_display_get_vsync_interval(void)
  904. {
  905. int ret = 0;
  906. unsigned int time0 = 0;
  907. unsigned int time1 = 0;
  908. unsigned int lcd_time = 0;
  909. if (pgc->plcm->is_connected == false)
  910. goto fail;
  911. if (pgc->plcm->is_connected == false)
  912. goto fail;
  913. pgc->plcm->is_connected = false;
  914. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  915. if (ret <= 0)
  916. goto fail;
  917. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  918. if (ret <= 0)
  919. goto fail;
  920. // because we are polling irq status, so the first event should be ignored
  921. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  922. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  923. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  924. if (ret <= 0)
  925. goto fail;
  926. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  927. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  928. if (ret > 0) {
  929. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  930. } else
  931. goto fail;
  932. lcd_time = (time1 - time0)/2;
  933. pgc->plcm->is_connected = true;
  934. if (0 != lcd_time)
  935. return (100000000/lcd_time);
  936. else
  937. return (6000);
  938. fail:
  939. DISPERR("wait event fail\n");
  940. return 0;
  941. }
  942. int primary_display_setbacklight(unsigned int level)
  943. {
  944. DISPMSG("lk %s level=%d\n",__func__,level);
  945. int ret=0;
  946. if (pgc->dpmgr_handle == NULL) {
  947. DISPCHECK("lk set backlight early!\n");
  948. return 0;
  949. }
  950. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  951. DISPCHECK("primary display path is busy\n");
  952. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  953. DISPCHECK("wait frame done ret:%d\n", ret);
  954. }
  955. disp_lcm_set_backlight(pgc->plcm,level);
  956. return 0;
  957. }
  958. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  959. /***********************/
  960. /*****Legacy DISP API*****/
  961. /***********************/
  962. UINT32 DISP_GetScreenWidth(void)
  963. {
  964. return primary_display_get_width();
  965. }
  966. UINT32 DISP_GetScreenHeight(void)
  967. {
  968. return primary_display_get_height();
  969. }
  970. UINT32 DISP_GetActiveHeight(void)
  971. {
  972. if (pgc->plcm == NULL) {
  973. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  974. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  975. if (pgc->plcm == NULL)return 0;
  976. }
  977. if (pgc->plcm->params) {
  978. return pgc->plcm->params->physical_height;
  979. } else {
  980. DISPERR("lcm_params is null!\n");
  981. return 0;
  982. }
  983. }
  984. UINT32 DISP_GetActiveWidth(void)
  985. {
  986. if (pgc->plcm == NULL) {
  987. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  988. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  989. if (pgc->plcm == NULL)return 0;
  990. }
  991. if (pgc->plcm->params) {
  992. return pgc->plcm->params->physical_width;
  993. } else {
  994. DISPERR("lcm_params is null!\n");
  995. return 0;
  996. }
  997. }
  998. int primary_display_capture_framebuffer(unsigned int *pbuf)
  999. {
  1000. return 0;
  1001. }
  1002. UINT32 DISP_GetPanelBPP(void)
  1003. {
  1004. #if 0
  1005. PANEL_COLOR_FORMAT fmt;
  1006. disp_drv_init_context();
  1007. if (disp_if_drv->get_panel_color_format == NULL) {
  1008. return DISP_STATUS_NOT_IMPLEMENTED;
  1009. }
  1010. fmt = disp_if_drv->get_panel_color_format();
  1011. switch (fmt) {
  1012. case PANEL_COLOR_FORMAT_RGB332:
  1013. return 8;
  1014. case PANEL_COLOR_FORMAT_RGB444:
  1015. return 12;
  1016. case PANEL_COLOR_FORMAT_RGB565:
  1017. return 16;
  1018. case PANEL_COLOR_FORMAT_RGB666:
  1019. return 18;
  1020. case PANEL_COLOR_FORMAT_RGB888:
  1021. return 24;
  1022. default:
  1023. return 0;
  1024. }
  1025. #endif
  1026. return 0;
  1027. }
  1028. UINT32 DISP_GetScreenBpp(void)
  1029. {
  1030. return disp_fb_bpp;
  1031. }
  1032. UINT32 DISP_GetPages(void)
  1033. {
  1034. return disp_fb_pages; // Double Buffers
  1035. }
  1036. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1037. #define DAL_BPP (2)
  1038. #define DAL_WIDTH (DISP_GetScreenWidth())
  1039. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1040. UINT32 DAL_GetLayerSize(void)
  1041. {
  1042. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1043. }
  1044. UINT32 DISP_GetFBRamSize(void)
  1045. {
  1046. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1047. }
  1048. unsigned int DISP_GetVRamSize(void)
  1049. {
  1050. static UINT32 vramSize = 0;
  1051. unsigned int fb_ram_size =0;
  1052. //FB RAM(n blocks)+(Assert layer size)
  1053. if (0 == vramSize) {
  1054. vramSize = DISP_GetFBRamSize();
  1055. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1056. fb_ram_size = vramSize;
  1057. vramSize += DAL_GetLayerSize();
  1058. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1059. #ifdef MTK_ROUND_CORNER_SUPPORT
  1060. fb_ram_size = vramSize;
  1061. vramSize += disp_get_round_corner_size();
  1062. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1063. #endif
  1064. #if 0
  1065. if (g_is_64bit_kernel) {
  1066. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1067. } else {
  1068. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1069. }
  1070. #else
  1071. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1072. #endif
  1073. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1074. }
  1075. return vramSize;
  1076. }