primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <target/board.h>
  33. #include <env.h>
  34. #include "lcm_drv.h"
  35. #include <string.h>
  36. #include <stdlib.h>
  37. #include <platform/mt_gpt.h>
  38. #include <platform/disp_drv_platform.h>
  39. #include <platform/disp_drv_log.h>
  40. #include <platform/boot_mode.h>
  41. #include <platform/primary_display.h>
  42. #include <platform/disp_lcm.h>
  43. #include <platform/ddp_disp_bdg.h>
  44. #include <platform/ddp_reg_disp_bdg.h>
  45. #define DDP_LK_BOOT
  46. #ifndef HZ
  47. #define HZ 100
  48. #endif
  49. #ifdef DDP_LK_BOOT
  50. typedef void * cmdqRecHandle;
  51. #endif
  52. #define ALIGN_TO(x, n) \
  53. (((x) + ((n) - 1)) & ~((n) - 1))
  54. int primary_display_use_cmdq = CMDQ_DISABLE;
  55. int primary_display_use_m4u = 1;
  56. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  57. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  58. static UINT32 disp_fb_pages = 3; ///double buffer
  59. static UINT32 display_init;
  60. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  61. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  62. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  63. extern void video_printf(const char *fmt, ...);
  64. extern void disp_path_clock_on(char *str);
  65. typedef struct _disp_dfo_item {
  66. char name[32];
  67. int value;
  68. } disp_dfo_item_t;
  69. static disp_dfo_item_t disp_dfo_setting[] = {
  70. {"LCM_FAKE_WIDTH", 0},
  71. {"LCM_FAKE_HEIGHT", 0},
  72. {"DISP_DEBUG_SWITCH", 0}
  73. };
  74. typedef struct {
  75. int state;
  76. int need_trigger_overlay;
  77. DISP_PRIMARY_PATH_MODE mode;
  78. unsigned int last_vsync_tick;
  79. #ifndef DDP_LK_BOOT
  80. struct mutex lock;
  81. #endif
  82. disp_lcm_handle * plcm;
  83. cmdqRecHandle cmdq_handle_config;
  84. cmdqRecHandle cmdq_handle_trigger;
  85. disp_path_handle dpmgr_handle;
  86. disp_path_handle ovl2mem_path_handle;
  87. } display_primary_path_context;
  88. #define pgc _get_context()
  89. static display_primary_path_context* _get_context(void)
  90. {
  91. static int is_context_inited = 0;
  92. static display_primary_path_context g_context;
  93. if (!is_context_inited) {
  94. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  95. is_context_inited = 1;
  96. }
  97. return &g_context;
  98. }
  99. static void _primary_path_lock(void)
  100. {
  101. #ifndef DDP_LK_BOOT
  102. disp_sw_mutex_lock(&(pgc->lock));
  103. #endif
  104. }
  105. static void _primary_path_unlock(void)
  106. {
  107. #ifndef DDP_LK_BOOT
  108. disp_sw_mutex_unlock(&(pgc->lock));
  109. #endif
  110. }
  111. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  112. {
  113. if (plcm == NULL) {
  114. DISPERR("plcm is null\n");
  115. return DISP_MODULE_UNKNOWN;
  116. }
  117. if (plcm->params->type == LCM_TYPE_DSI) {
  118. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  119. return DISP_MODULE_DSI0;
  120. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  121. return DISP_MODULE_DSI1;
  122. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  123. return DISP_MODULE_DSIDUAL;
  124. } else {
  125. return DISP_MODULE_DSI0;
  126. }
  127. } else if (plcm->params->type == LCM_TYPE_DPI) {
  128. return DISP_MODULE_UNKNOWN;
  129. } else {
  130. DISPERR("can't find primary path dst module\n");
  131. return DISP_MODULE_UNKNOWN;
  132. }
  133. }
  134. static int _build_path_direct_link(void)
  135. {
  136. int ret = 0;
  137. DISP_MODULE_ENUM dst_module = 0;
  138. DISPFUNC();
  139. pgc->mode = DIRECT_LINK_MODE;
  140. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  141. if (pgc->dpmgr_handle) {
  142. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  143. } else {
  144. DISPCHECK("dpmgr create path FAIL\n");
  145. return -1;
  146. }
  147. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  148. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  149. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  150. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  151. return ret;
  152. }
  153. static int _build_path_decouple(void)
  154. {
  155. return 0;
  156. }
  157. static int _build_path_single_layer(void)
  158. {
  159. return 0;
  160. }
  161. static int _build_path_debug_rdma1_dsi0(void)
  162. {
  163. return 0;
  164. }
  165. static void _build_cmdq_trigger_loop(void)
  166. {
  167. #ifndef DDP_LK_BOOT
  168. int ret = 0;
  169. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  170. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  171. cmdqRecReset(pgc->cmdq_handle_trigger);
  172. if (primary_display_is_video_mode()) {
  173. // wait and clear stream_done
  174. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  175. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  176. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  177. } else {
  178. // only in DSI Command mode we need to wait these
  179. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  180. // no internal te on fpga now.
  181. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  182. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  183. // block config threads, we'll about to update frame
  184. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  185. // only in DSI command mode we need to enable mutex explicitly
  186. // WRITE mutex enable
  187. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  188. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  189. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  190. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  191. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  192. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  193. // polling DSI idle
  194. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  195. // polling wdma frame done
  196. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  197. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  198. /*********************/
  199. /***build cmdq finished***/
  200. /*********************/
  201. // TODO:
  202. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  203. // RUN forever!!!!
  204. BUG_ON(ret < 0);
  205. }
  206. #endif
  207. }
  208. static void _start_cmdq_trigger_loop(void)
  209. {
  210. #ifndef DDP_LK_BOOT
  211. int ret = 0;
  212. // this should be called only once because trigger loop will nevet stop
  213. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  214. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  215. #endif
  216. }
  217. static void _set_cmdq_config_handle_dirty(void)
  218. {
  219. #ifndef DDP_LK_BOOT
  220. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  221. cmdqRecFlush(pgc->cmdq_handle_config);
  222. #endif
  223. }
  224. static void _reset_cmdq_config_handle(void)
  225. {
  226. #ifndef DDP_LK_BOOT
  227. cmdqRecReset(pgc->cmdq_handle_config);
  228. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  229. #endif
  230. }
  231. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  232. {
  233. if (src && dst) {
  234. dst->inputFormat = src->fmt;
  235. dst->address = src->addr;
  236. dst->width = src->src_w;
  237. dst->height = src->src_h;
  238. dst->pitch = src->src_pitch;
  239. return 0;
  240. } else {
  241. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  242. return -1;
  243. }
  244. }
  245. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  246. {
  247. if (src && dst) {
  248. dst->layer = src->layer;
  249. dst->layer_en = src->layer_en;
  250. dst->fmt = src->fmt;
  251. dst->addr = src->addr;
  252. dst->vaddr = src->vaddr;
  253. dst->src_x = src->src_x;
  254. dst->src_y = src->src_y;
  255. dst->src_w = src->src_w;
  256. dst->src_h = src->src_h;
  257. dst->src_pitch = src->src_pitch;
  258. dst->dst_x = src->dst_x;
  259. dst->dst_y = src->dst_y;
  260. dst->dst_w = src->dst_w;
  261. dst->dst_h = src->dst_h;
  262. dst->keyEn = src->keyEn;
  263. dst->key = src->key;
  264. dst->aen = src->aen;
  265. dst->alpha = src->alpha;
  266. dst->isDirty = src->isDirty;
  267. dst->buff_idx = src->buff_idx;
  268. dst->identity = src->identity;
  269. dst->connected_type = src->connected_type;
  270. dst->security = src->security;
  271. return 0;
  272. } else {
  273. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  274. return -1;
  275. }
  276. }
  277. void _dump_lcm_info_by_video_printf(void)
  278. {
  279. LCM_DRIVER *l = NULL;
  280. LCM_PARAMS *p = NULL;
  281. disp_lcm_handle *plcm = pgc->plcm;
  282. if (plcm == NULL) {
  283. DISPERR("plcm is null\n");
  284. return;
  285. }
  286. l = plcm->drv;
  287. p = plcm->params;
  288. if (l && p) {
  289. video_printf("[LCM], name: %s\n", l->name);
  290. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  291. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  292. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  293. switch (p->lcm_if) {
  294. case LCM_INTERFACE_DSI0:
  295. video_printf("[LCM] interface: DSI0\n");
  296. break;
  297. case LCM_INTERFACE_DSI1:
  298. video_printf("[LCM] interface: DSI1\n");
  299. break;
  300. case LCM_INTERFACE_DPI0:
  301. video_printf("[LCM] interface: DPI0\n");
  302. break;
  303. case LCM_INTERFACE_DPI1:
  304. video_printf("[LCM] interface: DPI1\n");
  305. break;
  306. case LCM_INTERFACE_DBI0:
  307. video_printf("[LCM] interface: DBI0\n");
  308. break;
  309. default:
  310. video_printf("[LCM] interface: unknown\n");
  311. break;
  312. }
  313. switch (p->type) {
  314. case LCM_TYPE_DBI:
  315. video_printf("[LCM] Type: DBI\n");
  316. break;
  317. case LCM_TYPE_DSI:
  318. video_printf("[LCM] Type: DSI\n");
  319. break;
  320. case LCM_TYPE_DPI:
  321. video_printf("[LCM] Type: DPI\n");
  322. break;
  323. default:
  324. video_printf("[LCM] TYPE: unknown\n");
  325. break;
  326. }
  327. if (p->type == LCM_TYPE_DSI) {
  328. switch (p->dsi.mode) {
  329. case CMD_MODE:
  330. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  331. break;
  332. case SYNC_PULSE_VDO_MODE:
  333. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  334. break;
  335. case SYNC_EVENT_VDO_MODE:
  336. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  337. break;
  338. case BURST_VDO_MODE:
  339. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  340. break;
  341. default:
  342. video_printf("[LCM] DSI Mode: Unknown\n");
  343. break;
  344. }
  345. }
  346. if (p->type == LCM_TYPE_DSI) {
  347. video_printf("[LCM] LANE_NUM: %d,data_format: %d,"
  348. " vertical_sync_active: %d\n",
  349. p->dsi.LANE_NUM,
  350. p->dsi.data_format.format,
  351. p->dsi.vertical_sync_active);
  352. #ifdef MY_TODO
  353. #error
  354. #endif
  355. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  356. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  357. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  358. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  359. }
  360. }
  361. return;
  362. }
  363. unsigned int mt_disp_parse_dfo_setting(void)
  364. {
  365. unsigned int i, j=0 ;
  366. char tmp[11];
  367. char *buffer = NULL;
  368. char *ptr = NULL;
  369. buffer = (char *)get_env("DFO");
  370. DISPMSG("env buffer = %s\n", buffer);
  371. if (buffer != NULL) {
  372. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  373. j = 0;
  374. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  375. ptr = strstr(buffer, disp_dfo_setting[i].name);
  376. if (ptr == NULL) continue;
  377. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  378. do {} while ((*ptr++) != ',');
  379. do {tmp[j++] = *ptr++;}
  380. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  381. disp_dfo_setting[i].value = atoi((const char*)tmp);
  382. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  383. }
  384. } else {
  385. DISPMSG("env buffer = NULL\n");
  386. }
  387. return 0;
  388. }
  389. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  390. {
  391. char *disp_name;
  392. int disp_value;
  393. unsigned int i = 0;
  394. if (string == NULL)
  395. return -1;
  396. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  397. disp_name = disp_dfo_setting[i].name;
  398. disp_value = disp_dfo_setting[i].value;
  399. if (!strcmp(disp_name, string)) {
  400. *value = disp_value;
  401. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  402. return 0;
  403. }
  404. }
  405. return 0;
  406. }
  407. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  408. int primary_display_is_lcm_connected(void)
  409. {
  410. return pgc->plcm->is_connected;
  411. }
  412. const char* primary_display_get_lcm_name(void)
  413. {
  414. return disp_lcm_get_name(pgc->plcm);
  415. }
  416. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  417. {
  418. if (pgc->plcm) {
  419. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  420. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  421. // otherwise we will have a panic in lk(root cause unknown).
  422. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  423. DISPERR("Invalid resolution: %dx%d\n", width, height);
  424. return -1;
  425. }
  426. if (primary_display_is_video_mode()) {
  427. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  428. return -1;
  429. }
  430. pgc->plcm->params->width = width;
  431. pgc->plcm->params->height = height;
  432. return 0;
  433. } else {
  434. return -1;
  435. }
  436. }
  437. int primary_display_init(char *lcm_name)
  438. {
  439. DISPFUNC();
  440. DISP_STATUS ret = DISP_STATUS_OK;
  441. int i = 0;
  442. LCM_PARAMS *lcm_param = NULL;
  443. disp_ddp_path_config data_config;
  444. dpmgr_init();
  445. #ifndef DDP_LK_BOOT
  446. mutex_init(&(pgc->lock));
  447. #endif
  448. _primary_path_lock();
  449. bdg_is_bdg_connected();
  450. if (pgc->plcm == NULL)
  451. pgc->plcm = disp_lcm_probe( lcm_name, LCM_INTERFACE_NOTDEFINED);
  452. if (pgc->plcm == NULL) {
  453. DISPCHECK("disp_lcm_probe returns null\n");
  454. ret = DISP_STATUS_ERROR;
  455. goto done;
  456. } else {
  457. DISPCHECK("disp_lcm_probe SUCCESS\n");
  458. }
  459. lcm_param = disp_lcm_get_params(pgc->plcm);
  460. if (lcm_param == NULL) {
  461. DISPERR("get lcm params FAILED\n");
  462. ret = DISP_STATUS_ERROR;
  463. goto done;
  464. }
  465. if (primary_display_mode == DIRECT_LINK_MODE) {
  466. _build_path_direct_link();
  467. DISPCHECK("primary display is DIRECT LINK MODE\n");
  468. } else if (primary_display_mode == DECOUPLE_MODE) {
  469. _build_path_decouple();
  470. DISPCHECK("primary display is DECOUPLE MODE\n");
  471. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  472. _build_path_single_layer();
  473. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  474. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  475. _build_path_debug_rdma1_dsi0();
  476. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  477. } else {
  478. DISPCHECK("primary display mode is WRONG\n");
  479. }
  480. _build_cmdq_trigger_loop();
  481. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  482. _start_cmdq_trigger_loop();
  483. DISPCHECK("primary display START cmdq trigger loop finished\n");
  484. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  485. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  486. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  487. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  488. if (bdg_is_bdg_connected() == 1) {
  489. bdg_common_init(DISP_BDG_DSI0, &data_config, NULL);
  490. mipi_dsi_rx_mac_init(DISP_BDG_DSI0, &data_config, NULL);
  491. }
  492. data_config.dst_w = disp_lcm_width(pgc->plcm);
  493. data_config.dst_h = disp_lcm_height(pgc->plcm);
  494. if (lcm_param->type == LCM_TYPE_DSI) {
  495. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  496. data_config.lcm_bpp = 24;
  497. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  498. data_config.lcm_bpp = 16;
  499. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  500. data_config.lcm_bpp = 18;
  501. } else if (lcm_param->type == LCM_TYPE_DPI) {
  502. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  503. data_config.lcm_bpp = 24;
  504. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  505. data_config.lcm_bpp = 16;
  506. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  507. data_config.lcm_bpp = 18;
  508. }
  509. data_config.dst_dirty = 1;
  510. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  511. if (bdg_is_bdg_connected() == 1)
  512. check_stopstate(NULL);
  513. ret = disp_lcm_init(pgc->plcm);
  514. if (primary_display_is_video_mode()) {
  515. if (lcm_param->dsi.lfr_enable == 1) {
  516. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  517. } else {
  518. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  519. }
  520. } else {
  521. }
  522. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  523. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  524. pgc->state = 1;
  525. display_init = 1;
  526. done:
  527. _primary_path_unlock();
  528. return ret;
  529. }
  530. // register rdma done event
  531. int primary_display_wait_for_idle(void)
  532. {
  533. DISP_STATUS ret = DISP_STATUS_OK;
  534. DISPFUNC();
  535. _primary_path_lock();
  536. _primary_path_unlock();
  537. return ret;
  538. }
  539. int primary_display_wait_for_dump(void)
  540. {
  541. return 0;
  542. }
  543. static long int get_current_time_us(void)
  544. {
  545. return get_timer(0);
  546. }
  547. int priamry_display_wait_for_vsync(void)
  548. {
  549. int ret = 0;
  550. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  551. if (ret == -2) {
  552. DISPCHECK("vsync for primary display path not enabled yet\n");
  553. return -1;
  554. }
  555. // pgc->last_vsync_tick = get_current_time_us();
  556. pgc->last_vsync_tick = 0;
  557. return 0;
  558. }
  559. int primary_display_suspend(void)
  560. {
  561. DISP_STATUS ret = DISP_STATUS_OK;
  562. if (display_init == 0) {
  563. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  564. return -1;
  565. }
  566. DISPFUNC();
  567. _primary_path_lock();
  568. disp_lcm_suspend(pgc->plcm);
  569. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  570. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  571. #ifndef DDP_LK_BOOT
  572. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  573. #endif
  574. pgc->state = 0;
  575. _primary_path_unlock();
  576. return ret;
  577. }
  578. int primary_display_resume(void)
  579. {
  580. DISP_STATUS ret = DISP_STATUS_OK;
  581. DISPFUNC();
  582. _primary_path_lock();
  583. disp_path_clock_on("Primary Display Path");
  584. pgc->state = 1;
  585. _primary_path_unlock();
  586. return ret;
  587. }
  588. int primary_display_is_alive(void)
  589. {
  590. unsigned int temp = 0;
  591. DISPFUNC();
  592. _primary_path_lock();
  593. temp = pgc->state;
  594. _primary_path_unlock();
  595. return temp;
  596. }
  597. int primary_display_is_sleepd(void)
  598. {
  599. unsigned int temp = 0;
  600. DISPFUNC();
  601. _primary_path_lock();
  602. temp = !pgc->state;
  603. _primary_path_unlock();
  604. return temp;
  605. }
  606. #ifdef MTK_ROUND_CORNER_SUPPORT
  607. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  608. {
  609. if (pgc->plcm == NULL) {
  610. return NULL;
  611. }
  612. if (pgc->plcm->params) {
  613. return &(pgc->plcm->params->round_corner_params);
  614. } else {
  615. DISPERR("lcm_params is null!\n");
  616. return NULL;
  617. }
  618. }
  619. int disp_get_round_corner_size(void)
  620. {
  621. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  622. int pitch = DISP_GetScreenWidth();
  623. int size = 0;
  624. if (corner_params) {
  625. if (corner_params->round_corner_en) {
  626. if (corner_params->full_content)
  627. size = (corner_params->h + corner_params->h_bot) * pitch * 2;
  628. else
  629. size = corner_params->h * pitch * 2 * 2;
  630. } else
  631. DISPERR("corner_params is null!\n");
  632. }
  633. return size;
  634. }
  635. #endif
  636. int primary_display_get_width(void)
  637. {
  638. if (pgc->plcm == NULL) {
  639. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  640. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  641. if (pgc->plcm == NULL)
  642. return 0;
  643. }
  644. if (pgc->plcm->params) {
  645. return pgc->plcm->params->width;
  646. } else {
  647. DISPERR("lcm_params is null!\n");
  648. return 0;
  649. }
  650. }
  651. int primary_display_get_height(void)
  652. {
  653. if (pgc->plcm == NULL) {
  654. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  655. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  656. if (pgc->plcm == NULL)
  657. return 0;
  658. }
  659. if (pgc->plcm->params) {
  660. return pgc->plcm->params->height;
  661. } else {
  662. DISPERR("lcm_params is null!\n");
  663. return 0;
  664. }
  665. }
  666. int primary_display_get_bpp(void)
  667. {
  668. return 32;
  669. }
  670. int primary_display_get_info(void *dispif_info)
  671. {
  672. #if 0
  673. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  674. switch (pgc->lcm_param->type) {
  675. case LCM_TYPE_DBI: {
  676. dispif_info->displayType = DISPIF_TYPE_DBI;
  677. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  678. dispif_info->isHwVsyncAvailable = 1;
  679. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  680. break;
  681. }
  682. case LCM_TYPE_DPI: {
  683. dispif_info->displayType = DISPIF_TYPE_DPI0;
  684. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  685. dispif_info->isHwVsyncAvailable = 1;
  686. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  687. break;
  688. }
  689. case LCM_TYPE_DSI: {
  690. dispif_info->displayType = DISPIF_TYPE_DSI0;
  691. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  692. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  693. dispif_info->isHwVsyncAvailable = 1;
  694. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  695. } else {
  696. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  697. dispif_info->isHwVsyncAvailable = 1;
  698. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  699. }
  700. break;
  701. }
  702. default:
  703. break;
  704. }
  705. #ifdef MY_TODO
  706. #error
  707. if (disp_if_drv->get_panel_color_format()) {
  708. switch (disp_if_drv->get_panel_color_format()) {
  709. case PANEL_COLOR_FORMAT_RGB565:
  710. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  711. case PANEL_COLOR_FORMAT_RGB666:
  712. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  713. case PANEL_COLOR_FORMAT_RGB888:
  714. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  715. default:
  716. break;
  717. }
  718. }
  719. #endif
  720. dispif_info->displayWidth = primary_display_get_width();
  721. dispif_info->displayHeight = primary_display_get_height();
  722. #ifdef MY_TODO
  723. #error
  724. dispif_info->vsyncFPS = lcd_fps;
  725. #endif
  726. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  727. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  728. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  729. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  730. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  731. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  732. } else {
  733. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  734. }
  735. dispif_info->isConnected = 1;
  736. #ifdef MY_TODO
  737. #error
  738. {
  739. LCM_PARAMS lcm_params_temp;
  740. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  741. if (lcm_drv) {
  742. lcm_drv->get_params(&lcm_params_temp);
  743. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  744. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  745. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  746. } else {
  747. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  748. }
  749. }
  750. #endif
  751. #endif
  752. return 0;
  753. }
  754. int primary_display_get_pages(void)
  755. {
  756. return 3;
  757. }
  758. int primary_display_config_output()
  759. {
  760. return 0;
  761. }
  762. int primary_display_diagnose(void)
  763. {
  764. int ret = 0;
  765. dpmgr_check_status(pgc->dpmgr_handle);
  766. return ret;
  767. }
  768. int primary_display_trigger(int blocking)
  769. {
  770. int ret = 0;
  771. DISPFUNC();
  772. int x=0, y=0;
  773. int width = 0, height =0;
  774. x = disp_lcm_x(pgc->plcm);
  775. y = disp_lcm_y(pgc->plcm);
  776. width = disp_lcm_width(pgc->plcm);
  777. height = disp_lcm_height(pgc->plcm);
  778. _primary_path_lock();
  779. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  780. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  781. if (primary_display_is_video_mode()) {
  782. _primary_path_unlock();
  783. return 0;
  784. }
  785. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  786. }
  787. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  788. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  789. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  790. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  791. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  792. }
  793. //_set_cmdq_config_handle_dirty();
  794. //_reset_cmdq_config_handle();
  795. //if(blocking)
  796. {
  797. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  798. }
  799. } else if (pgc->mode == DECOUPLE_MODE) {
  800. DISPCHECK("trigger mode: DECOUPLE\n");
  801. if (pgc->need_trigger_overlay) {
  802. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  803. if (blocking) {
  804. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  805. }
  806. } else {
  807. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  808. // this request of trigger should be called by AAL or ovl2mem done event
  809. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  810. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  811. }
  812. _set_cmdq_config_handle_dirty();
  813. _reset_cmdq_config_handle();
  814. if (blocking) {
  815. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  816. }
  817. }
  818. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  819. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  820. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  821. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  822. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  823. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  824. }
  825. if (blocking) {
  826. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  827. }
  828. } else {
  829. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  830. }
  831. _primary_path_unlock();
  832. //primary_display_diagnose();
  833. return ret;
  834. }
  835. int primary_display_config_input(disp_input_config* input)
  836. {
  837. int ret = 0;
  838. DISPFUNC();
  839. disp_ddp_path_config data_config;
  840. // all dirty should be cleared in dpmgr_path_get_last_config()
  841. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  842. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  843. data_config.dst_dirty = 0;
  844. data_config.ovl_dirty = 0;
  845. data_config.rdma_dirty = 0;
  846. data_config.wdma_dirty = 0;
  847. _primary_path_lock();
  848. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  849. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  850. if (primary_display_is_video_mode()) {
  851. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  852. }
  853. }
  854. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  855. data_config.ovl_dirty = 1;
  856. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  857. // this is used for decouple mode, to indicate whether we need to trigger ovl
  858. pgc->need_trigger_overlay = 1;
  859. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  860. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  861. data_config.rdma_dirty= 1;
  862. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  863. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  864. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  865. data_config.rdma_dirty= 1;
  866. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  867. // TODO: should use wait_event_timeout_or_idle
  868. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  869. }
  870. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  871. } else {
  872. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  873. }
  874. _primary_path_unlock();
  875. return ret;
  876. }
  877. int primary_display_is_video_mode(void)
  878. {
  879. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  880. return disp_lcm_is_video_mode(pgc->plcm);
  881. }
  882. int primary_display_get_vsync_interval(void)
  883. {
  884. int ret = 0;
  885. unsigned int time0 = 0;
  886. unsigned int time1 = 0;
  887. unsigned int lcd_time = 0;
  888. if (pgc->plcm->is_connected == false)
  889. goto fail;
  890. if (pgc->plcm->is_connected == false)
  891. goto fail;
  892. pgc->plcm->is_connected = false;
  893. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  894. if (ret <= 0)
  895. goto fail;
  896. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  897. if (ret <= 0)
  898. goto fail;
  899. // because we are polling irq status, so the first event should be ignored
  900. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  901. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  902. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  903. if (ret <= 0)
  904. goto fail;
  905. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  906. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  907. if (ret > 0) {
  908. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  909. } else
  910. goto fail;
  911. lcd_time = (time1 - time0)/2;
  912. pgc->plcm->is_connected = true;
  913. if (0 != lcd_time)
  914. return (100000000/lcd_time);
  915. else
  916. return (6000);
  917. fail:
  918. DISPERR("wait event fail\n");
  919. return 0;
  920. }
  921. int primary_display_setbacklight(unsigned int level)
  922. {
  923. DISPMSG("lk %s level=%d\n",__func__,level);
  924. int ret=0;
  925. if (pgc->dpmgr_handle == NULL) {
  926. DISPCHECK("lk set backlight early!\n");
  927. return 0;
  928. }
  929. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  930. DISPCHECK("primary display path is busy\n");
  931. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  932. DISPCHECK("wait frame done ret:%d\n", ret);
  933. }
  934. disp_lcm_set_backlight(pgc->plcm,level);
  935. return 0;
  936. }
  937. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  938. /***********************/
  939. /*****Legacy DISP API*****/
  940. /***********************/
  941. UINT32 DISP_GetScreenWidth(void)
  942. {
  943. return primary_display_get_width();
  944. }
  945. UINT32 DISP_GetScreenHeight(void)
  946. {
  947. return primary_display_get_height();
  948. }
  949. UINT32 DISP_GetActiveHeight(void)
  950. {
  951. if (pgc->plcm == NULL) {
  952. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  953. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  954. if (pgc->plcm == NULL)return 0;
  955. }
  956. if (pgc->plcm->params) {
  957. return pgc->plcm->params->physical_height;
  958. } else {
  959. DISPERR("lcm_params is null!\n");
  960. return 0;
  961. }
  962. }
  963. UINT32 DISP_GetActiveWidth(void)
  964. {
  965. if (pgc->plcm == NULL) {
  966. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  967. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  968. if (pgc->plcm == NULL)return 0;
  969. }
  970. if (pgc->plcm->params) {
  971. return pgc->plcm->params->physical_width;
  972. } else {
  973. DISPERR("lcm_params is null!\n");
  974. return 0;
  975. }
  976. }
  977. int primary_display_capture_framebuffer(unsigned int *pbuf)
  978. {
  979. return 0;
  980. }
  981. UINT32 DISP_GetPanelBPP(void)
  982. {
  983. #if 0
  984. PANEL_COLOR_FORMAT fmt;
  985. disp_drv_init_context();
  986. if (disp_if_drv->get_panel_color_format == NULL) {
  987. return DISP_STATUS_NOT_IMPLEMENTED;
  988. }
  989. fmt = disp_if_drv->get_panel_color_format();
  990. switch (fmt) {
  991. case PANEL_COLOR_FORMAT_RGB332:
  992. return 8;
  993. case PANEL_COLOR_FORMAT_RGB444:
  994. return 12;
  995. case PANEL_COLOR_FORMAT_RGB565:
  996. return 16;
  997. case PANEL_COLOR_FORMAT_RGB666:
  998. return 18;
  999. case PANEL_COLOR_FORMAT_RGB888:
  1000. return 24;
  1001. default:
  1002. return 0;
  1003. }
  1004. #endif
  1005. return 0;
  1006. }
  1007. UINT32 DISP_GetScreenBpp(void)
  1008. {
  1009. return disp_fb_bpp;
  1010. }
  1011. UINT32 DISP_GetPages(void)
  1012. {
  1013. return disp_fb_pages; // Double Buffers
  1014. }
  1015. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1016. #define DAL_BPP (2)
  1017. #define DAL_WIDTH (DISP_GetScreenWidth())
  1018. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1019. UINT32 DAL_GetLayerSize(void)
  1020. {
  1021. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1022. }
  1023. UINT32 DISP_GetFBRamSize(void)
  1024. {
  1025. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1026. }
  1027. unsigned int DISP_GetVRamSize(void)
  1028. {
  1029. static UINT32 vramSize = 0;
  1030. unsigned int fb_ram_size =0;
  1031. //FB RAM(n blocks)+(Assert layer size)
  1032. if (0 == vramSize) {
  1033. vramSize = DISP_GetFBRamSize();
  1034. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1035. fb_ram_size = vramSize;
  1036. vramSize += DAL_GetLayerSize();
  1037. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1038. #ifdef MTK_ROUND_CORNER_SUPPORT
  1039. fb_ram_size = vramSize;
  1040. vramSize += disp_get_round_corner_size();
  1041. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1042. #endif
  1043. #if 0
  1044. if (g_is_64bit_kernel) {
  1045. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1046. } else {
  1047. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1048. }
  1049. #else
  1050. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1051. #endif
  1052. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1053. }
  1054. return vramSize;
  1055. }