primary_display.c 34 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <video.h>
  33. #include <target/board.h>
  34. #include <env.h>
  35. #include "lcm_drv.h"
  36. #include <string.h>
  37. #include <stdlib.h>
  38. #include <platform/mt_gpt.h>
  39. #include <platform/disp_drv_platform.h>
  40. #include <platform/disp_drv_log.h>
  41. #include <platform/boot_mode.h>
  42. #include <platform/primary_display.h>
  43. #include <platform/disp_lcm.h>
  44. //#include<linux/timer.h>
  45. #define DDP_LK_BOOT
  46. #ifndef HZ
  47. #define HZ 100
  48. #endif
  49. #ifdef DDP_LK_BOOT
  50. typedef void * cmdqRecHandle;
  51. #endif
  52. #define ALIGN_TO(x, n) \
  53. (((x) + ((n) - 1)) & ~((n) - 1))
  54. int primary_display_use_cmdq = CMDQ_DISABLE;
  55. int primary_display_use_m4u = 0;
  56. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  57. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  58. static UINT32 disp_fb_pages = 3; ///double buffer
  59. static UINT32 display_init;
  60. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  61. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  62. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  63. extern void disp_path_clock_on(char *str);
  64. typedef struct _disp_dfo_item {
  65. char name[32];
  66. int value;
  67. } disp_dfo_item_t;
  68. static disp_dfo_item_t disp_dfo_setting[] = {
  69. {"LCM_FAKE_WIDTH", 0},
  70. {"LCM_FAKE_HEIGHT", 0},
  71. {"DISP_DEBUG_SWITCH", 0}
  72. };
  73. typedef struct {
  74. int state;
  75. int need_trigger_overlay;
  76. DISP_PRIMARY_PATH_MODE mode;
  77. unsigned int last_vsync_tick;
  78. #ifndef DDP_LK_BOOT
  79. struct mutex lock;
  80. #endif
  81. disp_lcm_handle * plcm;
  82. cmdqRecHandle cmdq_handle_config;
  83. cmdqRecHandle cmdq_handle_trigger;
  84. disp_path_handle dpmgr_handle;
  85. disp_path_handle ovl2mem_path_handle;
  86. } display_primary_path_context;
  87. #define pgc _get_context()
  88. static display_primary_path_context* _get_context(void)
  89. {
  90. static int is_context_inited = 0;
  91. static display_primary_path_context g_context;
  92. if (!is_context_inited) {
  93. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  94. is_context_inited = 1;
  95. }
  96. return &g_context;
  97. }
  98. static void _primary_path_lock(void)
  99. {
  100. #ifndef DDP_LK_BOOT
  101. disp_sw_mutex_lock(&(pgc->lock));
  102. #endif
  103. }
  104. static void _primary_path_unlock(void)
  105. {
  106. #ifndef DDP_LK_BOOT
  107. disp_sw_mutex_unlock(&(pgc->lock));
  108. #endif
  109. }
  110. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  111. {
  112. if (plcm == NULL) {
  113. DISPERR("plcm is null\n");
  114. return DISP_MODULE_UNKNOWN;
  115. }
  116. if (plcm->params->type == LCM_TYPE_DSI) {
  117. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  118. return DISP_MODULE_DSI0;
  119. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  120. return DISP_MODULE_DSI1;
  121. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  122. return DISP_MODULE_DSIDUAL;
  123. } else {
  124. return DISP_MODULE_DSI0;
  125. }
  126. } else if (plcm->params->type == LCM_TYPE_DPI) {
  127. return DISP_MODULE_DPI;
  128. } else {
  129. DISPERR("can't find primary path dst module\n");
  130. return DISP_MODULE_UNKNOWN;
  131. }
  132. }
  133. static int _build_path_direct_link(void)
  134. {
  135. int ret = 0;
  136. DISP_MODULE_ENUM dst_module = 0;
  137. DISPFUNC();
  138. pgc->mode = DIRECT_LINK_MODE;
  139. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  140. if (pgc->dpmgr_handle) {
  141. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  142. } else {
  143. DISPCHECK("dpmgr create path FAIL\n");
  144. return -1;
  145. }
  146. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  147. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  148. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  149. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  150. return ret;
  151. }
  152. static int _build_path_decouple(void)
  153. {
  154. return 0;
  155. }
  156. static int _build_path_single_layer(void)
  157. {
  158. return 0;
  159. }
  160. static int _build_path_debug_rdma1_dsi0(void)
  161. {
  162. int ret = 0;
  163. DISP_MODULE_ENUM dst_module = 0;
  164. DISPFUNC();
  165. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  166. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  167. if (pgc->dpmgr_handle) {
  168. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  169. } else {
  170. DISPCHECK("dpmgr create path FAIL\n");
  171. return -1;
  172. }
  173. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  174. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  175. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  176. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  177. return ret;
  178. }
  179. static void _build_cmdq_trigger_loop(void)
  180. {
  181. #ifndef DDP_LK_BOOT
  182. int ret = 0;
  183. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  184. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  185. cmdqRecReset(pgc->cmdq_handle_trigger);
  186. if (primary_display_is_video_mode()) {
  187. // wait and clear stream_done
  188. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  189. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  190. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  191. } else {
  192. // only in DSI Command mode we need to wait these
  193. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  194. // no internal te on fpga now.
  195. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  196. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  197. // block config threads, we'll about to update frame
  198. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  199. // only in DSI command mode we need to enable mutex explicitly
  200. // WRITE mutex enable
  201. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  202. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  203. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  204. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  205. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  206. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  207. // polling DSI idle
  208. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  209. // polling wdma frame done
  210. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  211. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  212. /*********************/
  213. /***build cmdq finished***/
  214. /*********************/
  215. // TODO:
  216. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  217. // RUN forever!!!!
  218. BUG_ON(ret < 0);
  219. }
  220. #endif
  221. }
  222. static void _start_cmdq_trigger_loop(void)
  223. {
  224. #ifndef DDP_LK_BOOT
  225. int ret = 0;
  226. // this should be called only once because trigger loop will nevet stop
  227. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  228. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  229. #endif
  230. }
  231. static void _set_cmdq_config_handle_dirty(void)
  232. {
  233. #ifndef DDP_LK_BOOT
  234. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  235. cmdqRecFlush(pgc->cmdq_handle_config);
  236. #endif
  237. }
  238. static void _reset_cmdq_config_handle(void)
  239. {
  240. #ifndef DDP_LK_BOOT
  241. cmdqRecReset(pgc->cmdq_handle_config);
  242. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  243. #endif
  244. }
  245. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  246. {
  247. if (src && dst) {
  248. dst->inputFormat = src->fmt;
  249. dst->address = src->addr;
  250. dst->width = src->src_w;
  251. dst->height = src->src_h;
  252. dst->pitch = src->src_pitch;
  253. return 0;
  254. } else {
  255. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  256. return -1;
  257. }
  258. }
  259. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  260. {
  261. if (src && dst) {
  262. dst->layer = src->layer;
  263. dst->layer_en = src->layer_en;
  264. dst->fmt = src->fmt;
  265. dst->addr = src->addr;
  266. dst->vaddr = src->vaddr;
  267. dst->src_x = src->src_x;
  268. dst->src_y = src->src_y;
  269. dst->src_w = src->src_w;
  270. dst->src_h = src->src_h;
  271. dst->src_pitch = src->src_pitch;
  272. dst->dst_x = src->dst_x;
  273. dst->dst_y = src->dst_y;
  274. dst->dst_w = src->dst_w;
  275. dst->dst_h = src->dst_h;
  276. dst->keyEn = src->keyEn;
  277. dst->key = src->key;
  278. dst->aen = src->aen;
  279. dst->alpha = src->alpha;
  280. dst->isDirty = src->isDirty;
  281. dst->buff_idx = src->buff_idx;
  282. dst->identity = src->identity;
  283. dst->connected_type = src->connected_type;
  284. dst->security = src->security;
  285. return 0;
  286. } else {
  287. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  288. return -1;
  289. }
  290. }
  291. void _dump_lcm_info_by_video_printf(void)
  292. {
  293. LCM_DRIVER *l = NULL;
  294. LCM_PARAMS *p = NULL;
  295. disp_lcm_handle *plcm = pgc->plcm;
  296. if (plcm == NULL) {
  297. DISPERR("plcm is null\n");
  298. return;
  299. }
  300. l = plcm->drv;
  301. p = plcm->params;
  302. if (l && p) {
  303. video_printf("[LCM], name: %s\n", l->name);
  304. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  305. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  306. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  307. switch (p->lcm_if) {
  308. case LCM_INTERFACE_DSI0:
  309. video_printf("[LCM] interface: DSI0\n");
  310. break;
  311. case LCM_INTERFACE_DSI1:
  312. video_printf("[LCM] interface: DSI1\n");
  313. break;
  314. case LCM_INTERFACE_DPI0:
  315. video_printf("[LCM] interface: DPI0\n");
  316. break;
  317. case LCM_INTERFACE_DPI1:
  318. video_printf("[LCM] interface: DPI1\n");
  319. break;
  320. case LCM_INTERFACE_DBI0:
  321. video_printf("[LCM] interface: DBI0\n");
  322. break;
  323. default:
  324. video_printf("[LCM] interface: unknown\n");
  325. break;
  326. }
  327. switch (p->type) {
  328. case LCM_TYPE_DBI:
  329. video_printf("[LCM] Type: DBI\n");
  330. break;
  331. case LCM_TYPE_DSI:
  332. video_printf("[LCM] Type: DSI\n");
  333. break;
  334. case LCM_TYPE_DPI:
  335. video_printf("[LCM] Type: DPI\n");
  336. break;
  337. default:
  338. video_printf("[LCM] TYPE: unknown\n");
  339. break;
  340. }
  341. if (p->type == LCM_TYPE_DSI) {
  342. switch (p->dsi.mode) {
  343. case CMD_MODE:
  344. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  345. break;
  346. case SYNC_PULSE_VDO_MODE:
  347. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  348. break;
  349. case SYNC_EVENT_VDO_MODE:
  350. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  351. break;
  352. case BURST_VDO_MODE:
  353. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  354. break;
  355. default:
  356. video_printf("[LCM] DSI Mode: Unknown\n");
  357. break;
  358. }
  359. }
  360. if (p->type == LCM_TYPE_DSI) {
  361. video_printf("[LCM] LANE_NUM: %d,data_format: %d\n",p->dsi.LANE_NUM,p->dsi.data_format.format);
  362. #ifdef MY_TODO
  363. #error
  364. #endif
  365. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  366. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  367. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  368. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  369. }
  370. }
  371. return;
  372. }
  373. unsigned int mt_disp_parse_dfo_setting(void)
  374. {
  375. unsigned int i, j=0 ;
  376. char tmp[11];
  377. char *buffer = NULL;
  378. char *ptr = NULL;
  379. buffer = (char *)get_env("DFO");
  380. DISPMSG("env buffer = %s\n", buffer);
  381. if (buffer != NULL) {
  382. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  383. j = 0;
  384. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  385. ptr = strstr(buffer, disp_dfo_setting[i].name);
  386. if (ptr == NULL) continue;
  387. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  388. do {} while ((*ptr++) != ',');
  389. do {tmp[j++] = *ptr++;}
  390. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  391. disp_dfo_setting[i].value = atoi((const char*)tmp);
  392. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  393. }
  394. } else {
  395. DISPMSG("env buffer = NULL\n");
  396. }
  397. return 0;
  398. }
  399. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  400. {
  401. char *disp_name;
  402. int disp_value;
  403. unsigned int i = 0;
  404. if (string == NULL)
  405. return -1;
  406. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  407. disp_name = disp_dfo_setting[i].name;
  408. disp_value = disp_dfo_setting[i].value;
  409. if (!strcmp(disp_name, string)) {
  410. *value = disp_value;
  411. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  412. return 0;
  413. }
  414. }
  415. return 0;
  416. }
  417. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  418. int primary_display_is_lcm_connected(void)
  419. {
  420. return pgc->plcm->is_connected;
  421. }
  422. const char* primary_display_get_lcm_name(void)
  423. {
  424. return disp_lcm_get_name(pgc->plcm);
  425. }
  426. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  427. {
  428. if (pgc->plcm) {
  429. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  430. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  431. // otherwise we will have a panic in lk(root cause unknown).
  432. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  433. DISPERR("Invalid resolution: %dx%d\n", width, height);
  434. return -1;
  435. }
  436. if (primary_display_is_video_mode()) {
  437. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  438. return -1;
  439. }
  440. pgc->plcm->params->width = width;
  441. pgc->plcm->params->height = height;
  442. return 0;
  443. } else {
  444. return -1;
  445. }
  446. }
  447. int primary_display_init(char *lcm_name)
  448. {
  449. DISPFUNC();
  450. DISP_STATUS ret = DISP_STATUS_OK;
  451. LCM_PARAMS *lcm_param = NULL;
  452. dpmgr_init();
  453. #ifndef DDP_LK_BOOT
  454. mutex_init(&(pgc->lock));
  455. #endif
  456. _primary_path_lock();
  457. if (pgc->plcm == NULL)
  458. pgc->plcm = disp_lcm_probe(lcm_name, LCM_INTERFACE_NOTDEFINED);
  459. if (pgc->plcm == NULL) {
  460. DISPCHECK("disp_lcm_probe returns null\n");
  461. ret = DISP_STATUS_ERROR;
  462. goto done;
  463. } else {
  464. DISPCHECK("disp_lcm_probe SUCCESS\n");
  465. }
  466. lcm_param = disp_lcm_get_params(pgc->plcm);
  467. if (lcm_param == NULL) {
  468. DISPERR("get lcm params FAILED\n");
  469. ret = DISP_STATUS_ERROR;
  470. goto done;
  471. }
  472. if (primary_display_mode == DIRECT_LINK_MODE) {
  473. _build_path_direct_link();
  474. DISPCHECK("primary display is DIRECT LINK MODE\n");
  475. } else if (primary_display_mode == DECOUPLE_MODE) {
  476. _build_path_decouple();
  477. DISPCHECK("primary display is DECOUPLE MODE\n");
  478. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  479. _build_path_single_layer();
  480. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  481. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  482. _build_path_debug_rdma1_dsi0();
  483. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  484. } else {
  485. DISPCHECK("primary display mode is WRONG\n");
  486. }
  487. _build_cmdq_trigger_loop();
  488. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  489. _start_cmdq_trigger_loop();
  490. DISPCHECK("primary display START cmdq trigger loop finished\n");
  491. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  492. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  493. disp_ddp_path_config data_config;
  494. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  495. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  496. #if defined(MTK_ROUND_CORNER_SUPPORT) && defined(DISP_HW_RC)
  497. memcpy(&(data_config.round_corner_params), &(lcm_param->round_corner_params), sizeof(LCM_ROUND_CORNER));
  498. #endif
  499. data_config.dst_w = disp_lcm_width(pgc->plcm);
  500. data_config.dst_h = disp_lcm_height(pgc->plcm);
  501. if (lcm_param->type == LCM_TYPE_DSI) {
  502. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  503. data_config.lcm_bpp = 24;
  504. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  505. data_config.lcm_bpp = 16;
  506. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  507. data_config.lcm_bpp = 18;
  508. } else if (lcm_param->type == LCM_TYPE_DPI) {
  509. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  510. data_config.lcm_bpp = 24;
  511. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  512. data_config.lcm_bpp = 16;
  513. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  514. data_config.lcm_bpp = 18;
  515. }
  516. data_config.dst_dirty = 1;
  517. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  518. ret = disp_lcm_init(pgc->plcm);
  519. if (primary_display_is_video_mode()) {
  520. if (lcm_param->dsi.lfr_enable == 1) {
  521. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  522. } else {
  523. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  524. }
  525. } else {
  526. }
  527. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  528. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  529. pgc->state = 1;
  530. display_init = 1;
  531. done:
  532. _primary_path_unlock();
  533. return ret;
  534. }
  535. // register rdma done event
  536. int primary_display_wait_for_idle(void)
  537. {
  538. DISP_STATUS ret = DISP_STATUS_OK;
  539. DISPFUNC();
  540. _primary_path_lock();
  541. _primary_path_unlock();
  542. return ret;
  543. }
  544. int primary_display_wait_for_dump(void)
  545. {
  546. return 0;
  547. }
  548. static long int get_current_time_us(void)
  549. {
  550. return get_timer(0);
  551. }
  552. int priamry_display_wait_for_vsync(void)
  553. {
  554. int ret = 0;
  555. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  556. if (ret == -2) {
  557. DISPCHECK("vsync for primary display path not enabled yet\n");
  558. return -1;
  559. }
  560. // pgc->last_vsync_tick = get_current_time_us();
  561. pgc->last_vsync_tick = 0;
  562. return 0;
  563. }
  564. int primary_display_suspend(void)
  565. {
  566. DISP_STATUS ret = DISP_STATUS_OK;
  567. if (display_init == 0) {
  568. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  569. return -1;
  570. }
  571. DISPFUNC();
  572. _primary_path_lock();
  573. disp_lcm_suspend(pgc->plcm);
  574. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  575. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  576. #ifndef DDP_LK_BOOT
  577. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  578. #endif
  579. pgc->state = 0;
  580. _primary_path_unlock();
  581. return ret;
  582. }
  583. int primary_display_resume(void)
  584. {
  585. DISP_STATUS ret = DISP_STATUS_OK;
  586. DISPFUNC();
  587. _primary_path_lock();
  588. disp_path_clock_on("Primary Display Path");
  589. pgc->state = 1;
  590. _primary_path_unlock();
  591. return ret;
  592. }
  593. int primary_display_is_alive(void)
  594. {
  595. unsigned int temp = 0;
  596. DISPFUNC();
  597. _primary_path_lock();
  598. temp = pgc->state;
  599. _primary_path_unlock();
  600. return temp;
  601. }
  602. int primary_display_is_sleepd(void)
  603. {
  604. unsigned int temp = 0;
  605. DISPFUNC();
  606. _primary_path_lock();
  607. temp = !pgc->state;
  608. _primary_path_unlock();
  609. return temp;
  610. }
  611. #if defined(MTK_ROUND_CORNER_SUPPORT) && !defined(DISP_HW_RC)
  612. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  613. {
  614. if (pgc->plcm == NULL) {
  615. return NULL;
  616. }
  617. if (pgc->plcm->params) {
  618. return &(pgc->plcm->params->round_corner_params);
  619. } else {
  620. DISPERR("lcm_params is null!\n");
  621. return NULL;
  622. }
  623. }
  624. int disp_get_round_corner_size(void)
  625. {
  626. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  627. int pitch = DISP_GetScreenWidth();
  628. int size = 0;
  629. if (corner_params->round_corner_en) {
  630. if (corner_params)
  631. size = corner_params->h * pitch * 2 * 2;
  632. else
  633. DISPERR("corner_params is null!\n");
  634. }
  635. return size;
  636. }
  637. #endif
  638. int primary_display_get_width(void)
  639. {
  640. if (pgc->plcm == NULL) {
  641. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  642. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  643. if (pgc->plcm == NULL)
  644. return 0;
  645. }
  646. if (pgc->plcm->params) {
  647. return pgc->plcm->params->width;
  648. } else {
  649. DISPERR("lcm_params is null!\n");
  650. return 0;
  651. }
  652. }
  653. int primary_display_get_height(void)
  654. {
  655. if (pgc->plcm == NULL) {
  656. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  657. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  658. if (pgc->plcm == NULL)
  659. return 0;
  660. }
  661. if (pgc->plcm->params) {
  662. return pgc->plcm->params->height;
  663. } else {
  664. DISPERR("lcm_params is null!\n");
  665. return 0;
  666. }
  667. }
  668. int primary_display_get_bpp(void)
  669. {
  670. return 32;
  671. }
  672. int primary_display_get_info(void *dispif_info)
  673. {
  674. #if 0
  675. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  676. switch (pgc->lcm_param->type) {
  677. case LCM_TYPE_DBI: {
  678. dispif_info->displayType = DISPIF_TYPE_DBI;
  679. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  680. dispif_info->isHwVsyncAvailable = 1;
  681. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  682. break;
  683. }
  684. case LCM_TYPE_DPI: {
  685. dispif_info->displayType = DISPIF_TYPE_DPI0;
  686. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  687. dispif_info->isHwVsyncAvailable = 1;
  688. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  689. break;
  690. }
  691. case LCM_TYPE_DSI: {
  692. dispif_info->displayType = DISPIF_TYPE_DSI0;
  693. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  694. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  695. dispif_info->isHwVsyncAvailable = 1;
  696. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  697. } else {
  698. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  699. dispif_info->isHwVsyncAvailable = 1;
  700. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  701. }
  702. break;
  703. }
  704. default:
  705. break;
  706. }
  707. #ifdef MY_TODO
  708. #error
  709. if (disp_if_drv->get_panel_color_format()) {
  710. switch (disp_if_drv->get_panel_color_format()) {
  711. case PANEL_COLOR_FORMAT_RGB565:
  712. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  713. case PANEL_COLOR_FORMAT_RGB666:
  714. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  715. case PANEL_COLOR_FORMAT_RGB888:
  716. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  717. default:
  718. break;
  719. }
  720. }
  721. #endif
  722. dispif_info->displayWidth = primary_display_get_width();
  723. dispif_info->displayHeight = primary_display_get_height();
  724. #ifdef MY_TODO
  725. #error
  726. dispif_info->vsyncFPS = lcd_fps;
  727. #endif
  728. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  729. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  730. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  731. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  732. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  733. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  734. } else {
  735. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  736. }
  737. dispif_info->isConnected = 1;
  738. #ifdef MY_TODO
  739. #error
  740. {
  741. LCM_PARAMS lcm_params_temp;
  742. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  743. if (lcm_drv) {
  744. lcm_drv->get_params(&lcm_params_temp);
  745. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  746. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  747. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  748. } else {
  749. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  750. }
  751. }
  752. #endif
  753. #endif
  754. return 0;
  755. }
  756. int primary_display_get_pages(void)
  757. {
  758. return 3;
  759. }
  760. int primary_display_config_output()
  761. {
  762. return 0;
  763. }
  764. int primary_display_diagnose(void)
  765. {
  766. int ret = 0;
  767. dpmgr_check_status(pgc->dpmgr_handle);
  768. return ret;
  769. }
  770. int primary_display_trigger(int blocking)
  771. {
  772. int ret = 0;
  773. DISPFUNC();
  774. int x=0, y=0;
  775. int width = 0, height =0;
  776. x = disp_lcm_x(pgc->plcm);
  777. y = disp_lcm_y(pgc->plcm);
  778. width = disp_lcm_width(pgc->plcm);
  779. height = disp_lcm_height(pgc->plcm);
  780. _primary_path_lock();
  781. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  782. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  783. if (primary_display_is_video_mode()) {
  784. _primary_path_unlock();
  785. return 0;
  786. }
  787. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  788. }
  789. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  790. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  791. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  792. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  793. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  794. }
  795. //_set_cmdq_config_handle_dirty();
  796. //_reset_cmdq_config_handle();
  797. //if(blocking)
  798. {
  799. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  800. }
  801. } else if (pgc->mode == DECOUPLE_MODE) {
  802. DISPCHECK("trigger mode: DECOUPLE\n");
  803. if (pgc->need_trigger_overlay) {
  804. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  805. if (blocking) {
  806. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  807. }
  808. } else {
  809. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  810. // this request of trigger should be called by AAL or ovl2mem done event
  811. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  812. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  813. }
  814. _set_cmdq_config_handle_dirty();
  815. _reset_cmdq_config_handle();
  816. if (blocking) {
  817. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  818. }
  819. }
  820. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  821. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  822. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  823. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  824. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  825. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  826. }
  827. if (blocking) {
  828. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  829. }
  830. } else {
  831. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  832. }
  833. _primary_path_unlock();
  834. /* comment for performance issue */
  835. #if 0
  836. primary_display_diagnose();
  837. #endif
  838. return ret;
  839. }
  840. int primary_display_config_input(disp_input_config* input)
  841. {
  842. int ret = 0;
  843. DISPFUNC();
  844. disp_ddp_path_config data_config;
  845. // all dirty should be cleared in dpmgr_path_get_last_config()
  846. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  847. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  848. data_config.dst_dirty = 0;
  849. data_config.ovl_dirty = 0;
  850. data_config.rdma_dirty = 0;
  851. data_config.wdma_dirty = 0;
  852. _primary_path_lock();
  853. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  854. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  855. if (primary_display_is_video_mode()) {
  856. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  857. }
  858. }
  859. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  860. data_config.ovl_dirty = 1;
  861. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  862. // this is used for decouple mode, to indicate whether we need to trigger ovl
  863. pgc->need_trigger_overlay = 1;
  864. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  865. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  866. data_config.rdma_dirty= 1;
  867. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  868. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  869. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  870. data_config.rdma_dirty= 1;
  871. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  872. // TODO: should use wait_event_timeout_or_idle
  873. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  874. }
  875. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  876. } else {
  877. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  878. }
  879. _primary_path_unlock();
  880. return ret;
  881. }
  882. int primary_display_is_video_mode(void)
  883. {
  884. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  885. return disp_lcm_is_video_mode(pgc->plcm);
  886. }
  887. int primary_display_get_vsync_interval(void)
  888. {
  889. int ret = 0;
  890. unsigned int time0 = 0;
  891. unsigned int time1 = 0;
  892. unsigned int lcd_time = 0;
  893. pgc->plcm->is_connected = false;
  894. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  895. if (ret <= 0)
  896. goto fail;
  897. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  898. if (ret <= 0)
  899. goto fail;
  900. // because we are polling irq status, so the first event should be ignored
  901. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  902. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  903. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  904. if (ret <= 0)
  905. goto fail;
  906. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  907. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  908. if (ret > 0) {
  909. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  910. } else
  911. goto fail;
  912. lcd_time = (time1 - time0)/2;
  913. pgc->plcm->is_connected = true;
  914. if (0 != lcd_time)
  915. return (100000000/lcd_time);
  916. else
  917. return (6000);
  918. fail:
  919. DISPERR("wait event fail\n");
  920. return 0;
  921. }
  922. int primary_display_setbacklight(unsigned int level)
  923. {
  924. DISPMSG("lk %s level=%d\n",__func__,level);
  925. int ret=0;
  926. if (pgc->dpmgr_handle == NULL) {
  927. DISPCHECK("lk set backlight early!\n");
  928. return 0;
  929. }
  930. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  931. DISPCHECK("primary display path is busy\n");
  932. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  933. DISPCHECK("wait frame done ret:%d\n", ret);
  934. }
  935. disp_lcm_set_backlight(pgc->plcm,level);
  936. return 0;
  937. }
  938. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  939. /***********************/
  940. /*****Legacy DISP API*****/
  941. /***********************/
  942. UINT32 DISP_GetScreenWidth(void)
  943. {
  944. return primary_display_get_width();
  945. }
  946. UINT32 DISP_GetScreenHeight(void)
  947. {
  948. return primary_display_get_height();
  949. }
  950. UINT32 DISP_GetActiveHeight(void)
  951. {
  952. if (pgc->plcm == NULL) {
  953. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  954. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  955. if (pgc->plcm == NULL)return 0;
  956. }
  957. if (pgc->plcm->params) {
  958. return pgc->plcm->params->physical_height;
  959. } else {
  960. DISPERR("lcm_params is null!\n");
  961. return 0;
  962. }
  963. }
  964. UINT32 DISP_GetActiveWidth(void)
  965. {
  966. if (pgc->plcm == NULL) {
  967. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  968. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  969. if (pgc->plcm == NULL)return 0;
  970. }
  971. if (pgc->plcm->params) {
  972. return pgc->plcm->params->physical_width;
  973. } else {
  974. DISPERR("lcm_params is null!\n");
  975. return 0;
  976. }
  977. }
  978. int primary_display_capture_framebuffer(unsigned int *pbuf)
  979. {
  980. return 0;
  981. }
  982. UINT32 DISP_GetPanelBPP(void)
  983. {
  984. #if 0
  985. PANEL_COLOR_FORMAT fmt;
  986. disp_drv_init_context();
  987. if (disp_if_drv->get_panel_color_format == NULL) {
  988. return DISP_STATUS_NOT_IMPLEMENTED;
  989. }
  990. fmt = disp_if_drv->get_panel_color_format();
  991. switch (fmt) {
  992. case PANEL_COLOR_FORMAT_RGB332:
  993. return 8;
  994. case PANEL_COLOR_FORMAT_RGB444:
  995. return 12;
  996. case PANEL_COLOR_FORMAT_RGB565:
  997. return 16;
  998. case PANEL_COLOR_FORMAT_RGB666:
  999. return 18;
  1000. case PANEL_COLOR_FORMAT_RGB888:
  1001. return 24;
  1002. default:
  1003. return 0;
  1004. }
  1005. #endif
  1006. return 0;
  1007. }
  1008. UINT32 DISP_GetScreenBpp(void)
  1009. {
  1010. return disp_fb_bpp;
  1011. }
  1012. UINT32 DISP_GetPages(void)
  1013. {
  1014. return disp_fb_pages; // Double Buffers
  1015. }
  1016. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1017. #define DAL_BPP (2)
  1018. #define DAL_WIDTH (DISP_GetScreenWidth())
  1019. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1020. UINT32 DAL_GetLayerSize(void)
  1021. {
  1022. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1023. }
  1024. UINT32 DISP_GetFBRamSize(void)
  1025. {
  1026. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1027. }
  1028. unsigned int DISP_GetVRamSize(void)
  1029. {
  1030. static UINT32 vramSize = 0;
  1031. unsigned int fb_ram_size =0;
  1032. //FB RAM(n blocks)+(Assert layer size)
  1033. if (0 == vramSize) {
  1034. vramSize = DISP_GetFBRamSize();
  1035. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1036. fb_ram_size = vramSize;
  1037. vramSize += DAL_GetLayerSize();
  1038. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1039. #if defined(MTK_ROUND_CORNER_SUPPORT) && !defined(DISP_HW_RC)
  1040. fb_ram_size = vramSize;
  1041. vramSize += disp_get_round_corner_size();
  1042. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1043. #endif
  1044. #if 0
  1045. if (g_is_64bit_kernel) {
  1046. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1047. } else {
  1048. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1049. }
  1050. #else
  1051. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1052. #endif
  1053. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1054. }
  1055. return vramSize;
  1056. }