primary_display.c 35 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #include <video_fb.h>
  32. #include <video.h>
  33. #include <target/board.h>
  34. #include <env.h>
  35. #ifdef CONFIG_MTK_MT6382_BDG
  36. #include <platform/ddp_disp_bdg.h>
  37. #include <platform/ddp_reg_disp_bdg.h>
  38. #endif
  39. #include "lcm_drv.h"
  40. #include <string.h>
  41. #include <stdlib.h>
  42. #include <platform/mt_gpt.h>
  43. #include <platform/disp_drv_platform.h>
  44. #include <platform/disp_drv_log.h>
  45. #include <platform/boot_mode.h>
  46. #include <platform/primary_display.h>
  47. #include <platform/disp_lcm.h>
  48. //#include<linux/timer.h>
  49. #define DDP_LK_BOOT
  50. #ifndef HZ
  51. #define HZ 100
  52. #endif
  53. #ifdef DDP_LK_BOOT
  54. typedef void * cmdqRecHandle;
  55. #endif
  56. #define ALIGN_TO(x, n) \
  57. (((x) + ((n) - 1)) & ~((n) - 1))
  58. int primary_display_use_cmdq = CMDQ_DISABLE;
  59. int primary_display_use_m4u = 0;
  60. DISP_PRIMARY_PATH_MODE primary_display_mode = DIRECT_LINK_MODE;
  61. static UINT32 disp_fb_bpp = 32; ///ARGB8888
  62. static UINT32 disp_fb_pages = 3; ///double buffer
  63. static UINT32 display_init;
  64. //DDP_SCENARIO_ENUM ddp_scenario = DDP_SCENARIO_RDMA1_DISP;
  65. extern int ddp_dsi_set_lcm_utils(DISP_MODULE_ENUM module, LCM_DRIVER *lcm_drv);
  66. extern int ddp_dsi_dump(DISP_MODULE_ENUM module, int level);
  67. extern void disp_path_clock_on(char *str);
  68. typedef struct _disp_dfo_item {
  69. char name[32];
  70. int value;
  71. } disp_dfo_item_t;
  72. static disp_dfo_item_t disp_dfo_setting[] = {
  73. {"LCM_FAKE_WIDTH", 0},
  74. {"LCM_FAKE_HEIGHT", 0},
  75. {"DISP_DEBUG_SWITCH", 0}
  76. };
  77. typedef struct {
  78. int state;
  79. int need_trigger_overlay;
  80. DISP_PRIMARY_PATH_MODE mode;
  81. unsigned int last_vsync_tick;
  82. #ifndef DDP_LK_BOOT
  83. struct mutex lock;
  84. #endif
  85. disp_lcm_handle * plcm;
  86. cmdqRecHandle cmdq_handle_config;
  87. cmdqRecHandle cmdq_handle_trigger;
  88. disp_path_handle dpmgr_handle;
  89. disp_path_handle ovl2mem_path_handle;
  90. } display_primary_path_context;
  91. #define pgc _get_context()
  92. static display_primary_path_context* _get_context(void)
  93. {
  94. static int is_context_inited = 0;
  95. static display_primary_path_context g_context;
  96. if (!is_context_inited) {
  97. memset((void*)&g_context, 0, sizeof(display_primary_path_context));
  98. is_context_inited = 1;
  99. }
  100. return &g_context;
  101. }
  102. static void _primary_path_lock(void)
  103. {
  104. #ifndef DDP_LK_BOOT
  105. disp_sw_mutex_lock(&(pgc->lock));
  106. #endif
  107. }
  108. static void _primary_path_unlock(void)
  109. {
  110. #ifndef DDP_LK_BOOT
  111. disp_sw_mutex_unlock(&(pgc->lock));
  112. #endif
  113. }
  114. static DISP_MODULE_ENUM _get_dst_module_by_lcm(disp_lcm_handle *plcm)
  115. {
  116. if (plcm == NULL) {
  117. DISPERR("plcm is null\n");
  118. return DISP_MODULE_UNKNOWN;
  119. }
  120. if (plcm->params->type == LCM_TYPE_DSI) {
  121. if (plcm->lcm_if_id == LCM_INTERFACE_DSI0) {
  122. return DISP_MODULE_DSI0;
  123. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI1) {
  124. return DISP_MODULE_DSI1;
  125. } else if (plcm->lcm_if_id == LCM_INTERFACE_DSI_DUAL) {
  126. return DISP_MODULE_DSIDUAL;
  127. } else {
  128. return DISP_MODULE_DSI0;
  129. }
  130. } else if (plcm->params->type == LCM_TYPE_DPI) {
  131. return DISP_MODULE_DPI;
  132. } else {
  133. DISPERR("can't find primary path dst module\n");
  134. return DISP_MODULE_UNKNOWN;
  135. }
  136. }
  137. static int _build_path_direct_link(void)
  138. {
  139. int ret = 0;
  140. DISP_MODULE_ENUM dst_module = 0;
  141. DISPFUNC();
  142. pgc->mode = DIRECT_LINK_MODE;
  143. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_PRIMARY_DISP, pgc->cmdq_handle_config);
  144. if (pgc->dpmgr_handle) {
  145. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  146. } else {
  147. DISPCHECK("dpmgr create path FAIL\n");
  148. return -1;
  149. }
  150. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  151. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  152. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  153. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  154. return ret;
  155. }
  156. static int _build_path_decouple(void)
  157. {
  158. return 0;
  159. }
  160. static int _build_path_single_layer(void)
  161. {
  162. return 0;
  163. }
  164. static int _build_path_debug_rdma1_dsi0(void)
  165. {
  166. int ret = 0;
  167. DISP_MODULE_ENUM dst_module = 0;
  168. DISPFUNC();
  169. pgc->mode = DEBUG_RDMA1_DSI0_MODE;
  170. pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
  171. if (pgc->dpmgr_handle) {
  172. DISPCHECK("dpmgr create path SUCCESS(0x%08x)\n", (unsigned int)pgc->dpmgr_handle);
  173. } else {
  174. DISPCHECK("dpmgr create path FAIL\n");
  175. return -1;
  176. }
  177. dst_module = _get_dst_module_by_lcm(pgc->plcm);
  178. dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
  179. DISPCHECK("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
  180. dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
  181. return ret;
  182. }
  183. static void _build_cmdq_trigger_loop(void)
  184. {
  185. #ifndef DDP_LK_BOOT
  186. int ret = 0;
  187. cmdqRecCreate(CMDQ_SCENARIO_TRIGGER_LOOP, &(pgc->cmdq_handle_trigger));
  188. DISPMSG("primary path trigger thread cmd handle=0x%08x\n", pgc->cmdq_handle_trigger);
  189. cmdqRecReset(pgc->cmdq_handle_trigger);
  190. if (primary_display_is_video_mode()) {
  191. // wait and clear stream_done
  192. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MUTEX0_STREAM_EOF);
  193. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  194. //ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  195. } else {
  196. // only in DSI Command mode we need to wait these
  197. ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_DIRTY);
  198. // no internal te on fpga now.
  199. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_MDP_DSI0_TE_SOF);
  200. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_BEFORE_STREAM_SOF);
  201. // block config threads, we'll about to update frame
  202. ret = cmdqRecClearEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  203. // only in DSI command mode we need to enable mutex explicitly
  204. // WRITE mutex enable
  205. dpmgr_path_trigger(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,primary_display_use_cmdq);
  206. //ret = cmdqRecWrite(pgc->cmdq_handle_trigger, (unsigned int)(DISP_REG_CONFIG_MUTEX_EN(0))&0x1fffffff, 1, ~0);
  207. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_WAIT_STREAM_EOF_EVENT);
  208. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_CHECK_IDLE_AFTER_STREAM_EOF);
  209. dpmgr_path_build_cmdq(pgc->dpmgr_handle, pgc->cmdq_handle_trigger,CMDQ_AFTER_STREAM_EOF);
  210. //ret = cmdqRecWait(pgc->cmdq_handle_trigger, CMDQ_EVENT_DISP_RDMA0_EOF);
  211. // polling DSI idle
  212. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x1401b00c, 0, 0x80000000);
  213. // polling wdma frame done
  214. //ret = cmdqRecPoll(pgc->cmdq_handle_trigger, 0x140060A0, 1, 0x1);
  215. ret = cmdqRecSetEventToken(pgc->cmdq_handle_trigger, CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  216. /*********************/
  217. /***build cmdq finished***/
  218. /*********************/
  219. // TODO:
  220. // cmdqRecDumphandle(pgc->cmdq_handle_trigger);
  221. // RUN forever!!!!
  222. BUG_ON(ret < 0);
  223. }
  224. #endif
  225. }
  226. static void _start_cmdq_trigger_loop(void)
  227. {
  228. #ifndef DDP_LK_BOOT
  229. int ret = 0;
  230. // this should be called only once because trigger loop will nevet stop
  231. cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_CONFIG_ALLOW);
  232. ret = cmdqRecStartLoop(pgc->cmdq_handle_trigger);
  233. #endif
  234. }
  235. static void _set_cmdq_config_handle_dirty(void)
  236. {
  237. #ifndef DDP_LK_BOOT
  238. ddp_insert_config_dirty_rec(pgc->cmdq_handle_config);
  239. cmdqRecFlush(pgc->cmdq_handle_config);
  240. #endif
  241. }
  242. static void _reset_cmdq_config_handle(void)
  243. {
  244. #ifndef DDP_LK_BOOT
  245. cmdqRecReset(pgc->cmdq_handle_config);
  246. ddp_insert_config_allow_rec(pgc->cmdq_handle_config);
  247. #endif
  248. }
  249. static int _convert_disp_input_to_rdma(RDMA_CONFIG_STRUCT *dst, disp_input_config* src)
  250. {
  251. if (src && dst) {
  252. dst->inputFormat = src->fmt;
  253. dst->address = src->addr;
  254. dst->width = src->src_w;
  255. dst->height = src->src_h;
  256. dst->pitch = src->src_pitch;
  257. return 0;
  258. } else {
  259. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  260. return -1;
  261. }
  262. }
  263. static int _convert_disp_input_to_ovl(OVL_CONFIG_STRUCT *dst, disp_input_config* src)
  264. {
  265. if (src && dst) {
  266. dst->layer = src->layer;
  267. dst->layer_en = src->layer_en;
  268. dst->fmt = src->fmt;
  269. dst->addr = src->addr;
  270. dst->vaddr = src->vaddr;
  271. dst->src_x = src->src_x;
  272. dst->src_y = src->src_y;
  273. dst->src_w = src->src_w;
  274. dst->src_h = src->src_h;
  275. dst->src_pitch = src->src_pitch;
  276. dst->dst_x = src->dst_x;
  277. dst->dst_y = src->dst_y;
  278. dst->dst_w = src->dst_w;
  279. dst->dst_h = src->dst_h;
  280. dst->keyEn = src->keyEn;
  281. dst->key = src->key;
  282. dst->aen = src->aen;
  283. dst->alpha = src->alpha;
  284. dst->isDirty = src->isDirty;
  285. dst->buff_idx = src->buff_idx;
  286. dst->identity = src->identity;
  287. dst->connected_type = src->connected_type;
  288. dst->security = src->security;
  289. return 0;
  290. } else {
  291. DISPERR("src(0x%08x) or dst(0x%08x) is null\n", (unsigned int)src, (unsigned int)dst);
  292. return -1;
  293. }
  294. }
  295. void _dump_lcm_info_by_video_printf(void)
  296. {
  297. LCM_DRIVER *l = NULL;
  298. LCM_PARAMS *p = NULL;
  299. disp_lcm_handle *plcm = pgc->plcm;
  300. if (plcm == NULL) {
  301. DISPERR("plcm is null\n");
  302. return;
  303. }
  304. l = plcm->drv;
  305. p = plcm->params;
  306. if (l && p) {
  307. video_printf("[LCM], name: %s\n", l->name);
  308. video_printf("[LCM] resolution: %d x %d\n", p->width, p->height);
  309. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  310. video_printf("[LCM] physical size: %d x %d\n", p->physical_width, p->physical_height);
  311. switch (p->lcm_if) {
  312. case LCM_INTERFACE_DSI0:
  313. video_printf("[LCM] interface: DSI0\n");
  314. break;
  315. case LCM_INTERFACE_DSI1:
  316. video_printf("[LCM] interface: DSI1\n");
  317. break;
  318. case LCM_INTERFACE_DPI0:
  319. video_printf("[LCM] interface: DPI0\n");
  320. break;
  321. case LCM_INTERFACE_DPI1:
  322. video_printf("[LCM] interface: DPI1\n");
  323. break;
  324. case LCM_INTERFACE_DBI0:
  325. video_printf("[LCM] interface: DBI0\n");
  326. break;
  327. default:
  328. video_printf("[LCM] interface: unknown\n");
  329. break;
  330. }
  331. switch (p->type) {
  332. case LCM_TYPE_DBI:
  333. video_printf("[LCM] Type: DBI\n");
  334. break;
  335. case LCM_TYPE_DSI:
  336. video_printf("[LCM] Type: DSI\n");
  337. break;
  338. case LCM_TYPE_DPI:
  339. video_printf("[LCM] Type: DPI\n");
  340. break;
  341. default:
  342. video_printf("[LCM] TYPE: unknown\n");
  343. break;
  344. }
  345. if (p->type == LCM_TYPE_DSI) {
  346. switch (p->dsi.mode) {
  347. case CMD_MODE:
  348. video_printf("[LCM] DSI Mode: CMD_MODE\n");
  349. break;
  350. case SYNC_PULSE_VDO_MODE:
  351. video_printf("[LCM] DSI Mode: SYNC_PULSE_VDO_MODE\n");
  352. break;
  353. case SYNC_EVENT_VDO_MODE:
  354. video_printf("[LCM] DSI Mode: SYNC_EVENT_VDO_MODE\n");
  355. break;
  356. case BURST_VDO_MODE:
  357. video_printf("[LCM] DSI Mode: BURST_VDO_MODE\n");
  358. break;
  359. default:
  360. video_printf("[LCM] DSI Mode: Unknown\n");
  361. break;
  362. }
  363. }
  364. if (p->type == LCM_TYPE_DSI) {
  365. video_printf("[LCM] LANE_NUM: %d,data_format: %d\n",
  366. p->dsi.LANE_NUM,p->dsi.data_format.format);
  367. #ifdef MY_TODO
  368. #error
  369. #endif
  370. video_printf("[LCM] vact: %d, vbp: %d, vfp: %d, vact_line: %d, hact: %d, hbp: %d, hfp: %d, hblank: %d\n",p->dsi.vertical_sync_active, p->dsi.vertical_backporch,p->dsi.vertical_frontporch,p->dsi.vertical_active_line,p->dsi.horizontal_sync_active,p->dsi.horizontal_backporch,p->dsi.horizontal_frontporch,p->dsi.horizontal_blanking_pixel);
  371. video_printf("[LCM] pll_select: %d, pll_div1: %d, pll_div2: %d, fbk_div: %d,fbk_sel: %d, rg_bir: %d\n",p->dsi.pll_select,p->dsi.pll_div1,p->dsi.pll_div2,p->dsi.fbk_div,p->dsi.fbk_sel,p->dsi.rg_bir);
  372. video_printf("[LCM] rg_bic: %d, rg_bp: %d, PLL_CLOCK: %d, dsi_clock: %d, ssc_range: %d, ssc_disable: %d, compatibility_for_nvk: %d, cont_clock: %d\n", p->dsi.rg_bic, p->dsi.rg_bp,p->dsi.PLL_CLOCK,p->dsi.dsi_clock,p->dsi.ssc_range,p->dsi.ssc_disable,p->dsi.compatibility_for_nvk,p->dsi.cont_clock);
  373. video_printf("[LCM] lcm_ext_te_enable: %d, noncont_clock: %d, noncont_clock_period: %d\n", p->dsi.lcm_ext_te_enable,p->dsi.noncont_clock,p->dsi.noncont_clock_period);
  374. }
  375. }
  376. return;
  377. }
  378. unsigned int mt_disp_parse_dfo_setting(void)
  379. {
  380. unsigned int i, j=0 ;
  381. char tmp[11];
  382. char *buffer = NULL;
  383. char *ptr = NULL;
  384. buffer = (char *)get_env("DFO");
  385. DISPMSG("env buffer = %s\n", buffer);
  386. if (buffer != NULL) {
  387. for (i = 0; i< (sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  388. j = 0;
  389. memset((void*)tmp, 0, sizeof(tmp)/sizeof(tmp[0]));
  390. ptr = strstr(buffer, disp_dfo_setting[i].name);
  391. if (ptr == NULL) continue;
  392. DISPMSG("disp_dfo_setting[%d].name = [%s]\n", i, ptr);
  393. do {} while ((*ptr++) != ',');
  394. do {tmp[j++] = *ptr++;}
  395. while (*ptr != ',' && j < sizeof(tmp)/sizeof(tmp[0]));
  396. disp_dfo_setting[i].value = atoi((const char*)tmp);
  397. DISPMSG("disp_dfo_setting[%d].name = [%s|%d]\n", i, tmp, disp_dfo_setting[i].value);
  398. }
  399. } else {
  400. DISPMSG("env buffer = NULL\n");
  401. }
  402. return 0;
  403. }
  404. int mt_disp_get_dfo_setting(const char *string, unsigned int *value)
  405. {
  406. char *disp_name;
  407. int disp_value;
  408. unsigned int i = 0;
  409. if (string == NULL)
  410. return -1;
  411. for (i=0; i<(sizeof(disp_dfo_setting)/sizeof(disp_dfo_item_t)); i++) {
  412. disp_name = disp_dfo_setting[i].name;
  413. disp_value = disp_dfo_setting[i].value;
  414. if (!strcmp(disp_name, string)) {
  415. *value = disp_value;
  416. DISPMSG("%s = [DEC]%d [HEX]0x%08x\n", disp_name, disp_value, disp_value);
  417. return 0;
  418. }
  419. }
  420. return 0;
  421. }
  422. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  423. int primary_display_is_lcm_connected(void)
  424. {
  425. return pgc->plcm->is_connected;
  426. }
  427. const char* primary_display_get_lcm_name(void)
  428. {
  429. return disp_lcm_get_name(pgc->plcm);
  430. }
  431. int primary_display_change_lcm_resolution(unsigned int width, unsigned int height)
  432. {
  433. if (pgc->plcm) {
  434. DISPMSG("LCM Resolution will be changed, original: %dx%d, now: %dx%d\n", pgc->plcm->params->width, pgc->plcm->params->height, width, height);
  435. // align with 4 is the minimal check, to ensure we can boot up into kernel, and could modify dfo setting again using meta tool
  436. // otherwise we will have a panic in lk(root cause unknown).
  437. if (width >pgc->plcm->params->width || height > pgc->plcm->params->height || width == 0 || height == 0 || width %4 || height %2) {
  438. DISPERR("Invalid resolution: %dx%d\n", width, height);
  439. return -1;
  440. }
  441. if (primary_display_is_video_mode()) {
  442. DISPERR("Warning!!!Video Mode can't support multiple resolution!\n");
  443. return -1;
  444. }
  445. pgc->plcm->params->width = width;
  446. pgc->plcm->params->height = height;
  447. return 0;
  448. } else {
  449. return -1;
  450. }
  451. }
  452. int primary_display_init(char *lcm_name)
  453. {
  454. DISPFUNC();
  455. DISP_STATUS ret = DISP_STATUS_OK;
  456. LCM_PARAMS *lcm_param = NULL;
  457. disp_ddp_path_config data_config;
  458. dpmgr_init();
  459. #ifndef DDP_LK_BOOT
  460. mutex_init(&(pgc->lock));
  461. #endif
  462. _primary_path_lock();
  463. if (pgc->plcm == NULL)
  464. pgc->plcm = disp_lcm_probe(lcm_name, LCM_INTERFACE_NOTDEFINED);
  465. if (pgc->plcm == NULL) {
  466. DISPCHECK("disp_lcm_probe returns null\n");
  467. ret = DISP_STATUS_ERROR;
  468. goto done;
  469. } else {
  470. DISPCHECK("disp_lcm_probe SUCCESS\n");
  471. }
  472. lcm_param = disp_lcm_get_params(pgc->plcm);
  473. if (lcm_param == NULL) {
  474. DISPERR("get lcm params FAILED\n");
  475. ret = DISP_STATUS_ERROR;
  476. goto done;
  477. }
  478. if (primary_display_mode == DIRECT_LINK_MODE) {
  479. _build_path_direct_link();
  480. DISPCHECK("primary display is DIRECT LINK MODE\n");
  481. } else if (primary_display_mode == DECOUPLE_MODE) {
  482. _build_path_decouple();
  483. DISPCHECK("primary display is DECOUPLE MODE\n");
  484. } else if (primary_display_mode == SINGLE_LAYER_MODE) {
  485. _build_path_single_layer();
  486. DISPCHECK("primary display is SINGLE LAYER MODE\n");
  487. } else if (primary_display_mode == DEBUG_RDMA1_DSI0_MODE) {
  488. _build_path_debug_rdma1_dsi0();
  489. DISPCHECK("primary display is DEBUG RDMA1 DSI0 MODE\n");
  490. } else {
  491. DISPCHECK("primary display mode is WRONG\n");
  492. }
  493. _build_cmdq_trigger_loop();
  494. DISPCHECK("primary display BUILD cmdq trigger loop finished\n");
  495. _start_cmdq_trigger_loop();
  496. DISPCHECK("primary display START cmdq trigger loop finished\n");
  497. dpmgr_path_set_video_mode(pgc->dpmgr_handle, primary_display_is_video_mode());
  498. dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
  499. memset((void*)&data_config, 0, sizeof(disp_ddp_path_config));
  500. memcpy(&(data_config.dsi_config), &(lcm_param->dsi), sizeof(LCM_DSI_PARAMS));
  501. #if defined(MTK_ROUND_CORNER_SUPPORT) && defined(DISP_HW_RC)
  502. memcpy(&(data_config.round_corner_params), &(lcm_param->round_corner_params), sizeof(LCM_ROUND_CORNER));
  503. #endif
  504. #ifdef CONFIG_MTK_MT6382_BDG
  505. bdg_common_init(DISP_BDG_DSI0, &data_config, NULL);
  506. mipi_dsi_rx_mac_init(DISP_BDG_DSI0, &data_config, NULL);
  507. #endif
  508. data_config.dst_w = disp_lcm_width(pgc->plcm);
  509. data_config.dst_h = disp_lcm_height(pgc->plcm);
  510. if (lcm_param->type == LCM_TYPE_DSI) {
  511. if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB888)
  512. data_config.lcm_bpp = 24;
  513. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB565)
  514. data_config.lcm_bpp = 16;
  515. else if (lcm_param->dsi.data_format.format == LCM_DSI_FORMAT_RGB666)
  516. data_config.lcm_bpp = 18;
  517. } else if (lcm_param->type == LCM_TYPE_DPI) {
  518. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB888)
  519. data_config.lcm_bpp = 24;
  520. else if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB565)
  521. data_config.lcm_bpp = 16;
  522. if ( lcm_param->dpi.format == LCM_DPI_FORMAT_RGB666)
  523. data_config.lcm_bpp = 18;
  524. }
  525. data_config.dst_dirty = 1;
  526. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  527. #ifdef CONFIG_MTK_MT6382_BDG
  528. check_stopstate(NULL);
  529. #endif
  530. ret = disp_lcm_init(pgc->plcm);
  531. if (primary_display_is_video_mode()) {
  532. if (lcm_param->dsi.lfr_enable == 1) {
  533. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_DSI0_FRAME_DONE);
  534. } else {
  535. dpmgr_map_event_to_irq(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC, DDP_IRQ_RDMA0_DONE);
  536. }
  537. } else {
  538. }
  539. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  540. dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
  541. pgc->state = 1;
  542. display_init = 1;
  543. done:
  544. _primary_path_unlock();
  545. return ret;
  546. }
  547. // register rdma done event
  548. int primary_display_wait_for_idle(void)
  549. {
  550. DISP_STATUS ret = DISP_STATUS_OK;
  551. DISPFUNC();
  552. _primary_path_lock();
  553. _primary_path_unlock();
  554. return ret;
  555. }
  556. int primary_display_wait_for_dump(void)
  557. {
  558. return 0;
  559. }
  560. static long int get_current_time_us(void)
  561. {
  562. return get_timer(0);
  563. }
  564. int priamry_display_wait_for_vsync(void)
  565. {
  566. int ret = 0;
  567. ret = dpmgr_wait_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
  568. if (ret == -2) {
  569. DISPCHECK("vsync for primary display path not enabled yet\n");
  570. return -1;
  571. }
  572. // pgc->last_vsync_tick = get_current_time_us();
  573. pgc->last_vsync_tick = 0;
  574. return 0;
  575. }
  576. int primary_display_suspend(void)
  577. {
  578. DISP_STATUS ret = DISP_STATUS_OK;
  579. if (display_init == 0) {
  580. dprintf(CRITICAL, "skip primary_display_suspend() before init\n");
  581. return -1;
  582. }
  583. DISPFUNC();
  584. _primary_path_lock();
  585. disp_lcm_suspend(pgc->plcm);
  586. dpmgr_path_stop(pgc->dpmgr_handle, CMDQ_DISABLE);
  587. dpmgr_path_power_off(pgc->dpmgr_handle, CMDQ_DISABLE);
  588. #ifndef DDP_LK_BOOT
  589. cmdqRecStopLoop(pgc->cmdq_handle_trigger);
  590. #endif
  591. pgc->state = 0;
  592. _primary_path_unlock();
  593. return ret;
  594. }
  595. int primary_display_resume(void)
  596. {
  597. DISP_STATUS ret = DISP_STATUS_OK;
  598. DISPFUNC();
  599. _primary_path_lock();
  600. disp_path_clock_on("Primary Display Path");
  601. pgc->state = 1;
  602. _primary_path_unlock();
  603. return ret;
  604. }
  605. int primary_display_is_alive(void)
  606. {
  607. unsigned int temp = 0;
  608. DISPFUNC();
  609. _primary_path_lock();
  610. temp = pgc->state;
  611. _primary_path_unlock();
  612. return temp;
  613. }
  614. int primary_display_is_sleepd(void)
  615. {
  616. unsigned int temp = 0;
  617. DISPFUNC();
  618. _primary_path_lock();
  619. temp = !pgc->state;
  620. _primary_path_unlock();
  621. return temp;
  622. }
  623. #if defined(MTK_ROUND_CORNER_SUPPORT) && !defined(DISP_HW_RC)
  624. LCM_ROUND_CORNER *primary_display_get_corner_params(void)
  625. {
  626. if (pgc->plcm == NULL) {
  627. return NULL;
  628. }
  629. if (pgc->plcm->params) {
  630. return &(pgc->plcm->params->round_corner_params);
  631. } else {
  632. DISPERR("lcm_params is null!\n");
  633. return NULL;
  634. }
  635. }
  636. int disp_get_round_corner_size(void)
  637. {
  638. LCM_ROUND_CORNER *corner_params = primary_display_get_corner_params();
  639. int pitch = DISP_GetScreenWidth();
  640. int size = 0;
  641. if (corner_params->round_corner_en) {
  642. if (corner_params)
  643. size = corner_params->h * pitch * 2 * 2;
  644. else
  645. DISPERR("corner_params is null!\n");
  646. }
  647. return size;
  648. }
  649. #endif
  650. int primary_display_get_width(void)
  651. {
  652. if (pgc->plcm == NULL) {
  653. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  654. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  655. if (pgc->plcm == NULL)
  656. return 0;
  657. }
  658. if (pgc->plcm->params) {
  659. return pgc->plcm->params->width;
  660. } else {
  661. DISPERR("lcm_params is null!\n");
  662. return 0;
  663. }
  664. }
  665. int primary_display_get_height(void)
  666. {
  667. if (pgc->plcm == NULL) {
  668. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  669. DISPDBG("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  670. if (pgc->plcm == NULL)
  671. return 0;
  672. }
  673. if (pgc->plcm->params) {
  674. return pgc->plcm->params->height;
  675. } else {
  676. DISPERR("lcm_params is null!\n");
  677. return 0;
  678. }
  679. }
  680. int primary_display_get_bpp(void)
  681. {
  682. return 32;
  683. }
  684. int primary_display_get_info(void *dispif_info)
  685. {
  686. #if 0
  687. memset((void*)dispif_info, 0, sizeof(mtk_dispif_info_t));
  688. switch (pgc->lcm_param->type) {
  689. case LCM_TYPE_DBI: {
  690. dispif_info->displayType = DISPIF_TYPE_DBI;
  691. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  692. dispif_info->isHwVsyncAvailable = 1;
  693. DISPMSG("DISP Info: DBI, CMD Mode, HW Vsync enable\n");
  694. break;
  695. }
  696. case LCM_TYPE_DPI: {
  697. dispif_info->displayType = DISPIF_TYPE_DPI0;
  698. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  699. dispif_info->isHwVsyncAvailable = 1;
  700. DISPMSG("DISP Info: DPI, VDO Mode, HW Vsync enable\n");
  701. break;
  702. }
  703. case LCM_TYPE_DSI: {
  704. dispif_info->displayType = DISPIF_TYPE_DSI0;
  705. if (pgc->lcm_param->dsi.mode == CMD_MODE) {
  706. dispif_info->displayMode = DISPIF_MODE_COMMAND;
  707. dispif_info->isHwVsyncAvailable = 1;
  708. DISPMSG("DISP Info: DSI, CMD Mode, HW Vsync enable\n");
  709. } else {
  710. dispif_info->displayMode = DISPIF_MODE_VIDEO;
  711. dispif_info->isHwVsyncAvailable = 1;
  712. DISPMSG("DISP Info: DSI, VDO Mode, HW Vsync enable\n");
  713. }
  714. break;
  715. }
  716. default:
  717. break;
  718. }
  719. #ifdef MY_TODO
  720. #error
  721. if (disp_if_drv->get_panel_color_format()) {
  722. switch (disp_if_drv->get_panel_color_format()) {
  723. case PANEL_COLOR_FORMAT_RGB565:
  724. dispif_info->displayFormat = DISPIF_FORMAT_RGB565;
  725. case PANEL_COLOR_FORMAT_RGB666:
  726. dispif_info->displayFormat = DISPIF_FORMAT_RGB666;
  727. case PANEL_COLOR_FORMAT_RGB888:
  728. dispif_info->displayFormat = DISPIF_FORMAT_RGB888;
  729. default:
  730. break;
  731. }
  732. }
  733. #endif
  734. dispif_info->displayWidth = primary_display_get_width();
  735. dispif_info->displayHeight = primary_display_get_height();
  736. #ifdef MY_TODO
  737. #error
  738. dispif_info->vsyncFPS = lcd_fps;
  739. #endif
  740. if (dispif_info->displayWidth * dispif_info->displayHeight <= 240*432) {
  741. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  742. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 320*480) {
  743. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  744. } else if (dispif_info->displayWidth * dispif_info->displayHeight <= 480*854) {
  745. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  746. } else {
  747. dispif_info->physicalHeight= dispif_info->physicalWidth= 0;
  748. }
  749. dispif_info->isConnected = 1;
  750. #ifdef MY_TODO
  751. #error
  752. {
  753. LCM_PARAMS lcm_params_temp;
  754. memset((void*)&lcm_params_temp, 0, sizeof(lcm_params_temp));
  755. if (lcm_drv) {
  756. lcm_drv->get_params(&lcm_params_temp);
  757. dispif_info->lcmOriginalWidth = lcm_params_temp.width;
  758. dispif_info->lcmOriginalHeight = lcm_params_temp.height;
  759. DISPMSG("DISP Info: LCM Panel Original Resolution(For DFO Only): %d x %d\n", dispif_info->lcmOriginalWidth, dispif_info->lcmOriginalHeight);
  760. } else {
  761. DISPMSG("DISP Info: Fatal Error!!, lcm_drv is null\n");
  762. }
  763. }
  764. #endif
  765. #endif
  766. return 0;
  767. }
  768. int primary_display_get_pages(void)
  769. {
  770. return 3;
  771. }
  772. int primary_display_config_output()
  773. {
  774. return 0;
  775. }
  776. int primary_display_diagnose(void)
  777. {
  778. int ret = 0;
  779. dpmgr_check_status(pgc->dpmgr_handle);
  780. return ret;
  781. }
  782. int primary_display_trigger(int blocking)
  783. {
  784. int ret = 0;
  785. DISPFUNC();
  786. int x=0, y=0;
  787. int width = 0, height =0;
  788. x = disp_lcm_x(pgc->plcm);
  789. y = disp_lcm_y(pgc->plcm);
  790. width = disp_lcm_width(pgc->plcm);
  791. height = disp_lcm_height(pgc->plcm);
  792. _primary_path_lock();
  793. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == SINGLE_LAYER_MODE) {
  794. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  795. if (primary_display_is_video_mode()) {
  796. _primary_path_unlock();
  797. return 0;
  798. }
  799. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  800. }
  801. DISPCHECK("trigger mode: %s\n", (pgc->mode == DIRECT_LINK_MODE)?"DIRECT_LINK":"SINGLE_LAYER");
  802. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  803. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  804. if (primary_display_use_cmdq == CMDQ_DISABLE) {
  805. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  806. }
  807. //_set_cmdq_config_handle_dirty();
  808. //_reset_cmdq_config_handle();
  809. //if(blocking)
  810. {
  811. //dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  812. }
  813. } else if (pgc->mode == DECOUPLE_MODE) {
  814. DISPCHECK("trigger mode: DECOUPLE\n");
  815. if (pgc->need_trigger_overlay) {
  816. dpmgr_path_trigger(pgc->ovl2mem_path_handle, NULL,primary_display_use_cmdq);
  817. if (blocking) {
  818. dpmgr_wait_event_timeout(pgc->ovl2mem_path_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  819. }
  820. } else {
  821. if (dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  822. // this request of trigger should be called by AAL or ovl2mem done event
  823. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  824. dpmgr_path_start(pgc->dpmgr_handle, primary_display_use_cmdq);
  825. }
  826. _set_cmdq_config_handle_dirty();
  827. _reset_cmdq_config_handle();
  828. if (blocking) {
  829. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*2);
  830. }
  831. }
  832. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  833. if (!primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 0) {
  834. DISPCHECK("trigger mode: DEBUG_RDMA1_DSI0\n");
  835. disp_lcm_update(pgc->plcm, x, y, width, height, 0);
  836. dpmgr_path_start(pgc->dpmgr_handle, CMDQ_DISABLE);
  837. dpmgr_path_trigger(pgc->dpmgr_handle, NULL,primary_display_use_cmdq);
  838. }
  839. if (blocking) {
  840. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  841. }
  842. } else {
  843. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  844. }
  845. _primary_path_unlock();
  846. /* comment for performance issue */
  847. #if 0
  848. primary_display_diagnose();
  849. #endif
  850. return ret;
  851. }
  852. int primary_display_config_input(disp_input_config* input)
  853. {
  854. int ret = 0;
  855. DISPFUNC();
  856. disp_ddp_path_config data_config;
  857. // all dirty should be cleared in dpmgr_path_get_last_config()
  858. memcpy((void*)&data_config, (void*)dpmgr_path_get_last_config(pgc->dpmgr_handle), sizeof(disp_ddp_path_config));
  859. // no need do this dirty = 0; dpmgr_path_get_last_config do this.
  860. data_config.dst_dirty = 0;
  861. data_config.ovl_dirty = 0;
  862. data_config.rdma_dirty = 0;
  863. data_config.wdma_dirty = 0;
  864. _primary_path_lock();
  865. if (pgc->mode == DIRECT_LINK_MODE || pgc->mode == DECOUPLE_MODE) {
  866. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  867. if (primary_display_is_video_mode()) {
  868. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  869. }
  870. }
  871. ret = _convert_disp_input_to_ovl(&(data_config.ovl_config[input->layer]), input);
  872. data_config.ovl_dirty = 1;
  873. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  874. // this is used for decouple mode, to indicate whether we need to trigger ovl
  875. pgc->need_trigger_overlay = 1;
  876. } else if (pgc->mode == SINGLE_LAYER_MODE) {
  877. ret = _convert_disp_input_to_rdma(&data_config.rdma_config, input);
  878. data_config.rdma_dirty= 1;
  879. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, primary_display_use_cmdq);
  880. } else if (pgc->mode == DEBUG_RDMA1_DSI0_MODE) {
  881. ret = _convert_disp_input_to_rdma(&(data_config.rdma_config), input);
  882. data_config.rdma_dirty= 1;
  883. if (primary_display_is_video_mode() && dpmgr_path_is_busy(pgc->dpmgr_handle) == 1) {
  884. // TODO: should use wait_event_timeout_or_idle
  885. dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*5);
  886. }
  887. ret = dpmgr_path_config(pgc->dpmgr_handle, &data_config, CMDQ_DISABLE);
  888. } else {
  889. DISPCHECK("primary display mode is WRONG(%d)\n", (unsigned int)pgc->mode);
  890. }
  891. _primary_path_unlock();
  892. return ret;
  893. }
  894. int primary_display_is_video_mode(void)
  895. {
  896. //we should store the video/cmd mode in runtime, because will support cmd/vdo dynamic switch
  897. return disp_lcm_is_video_mode(pgc->plcm);
  898. }
  899. int primary_display_get_vsync_interval(void)
  900. {
  901. int ret = 0;
  902. unsigned int time0 = 0;
  903. unsigned int time1 = 0;
  904. unsigned int lcd_time = 0;
  905. pgc->plcm->is_connected = false;
  906. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  907. if (ret <= 0)
  908. goto fail;
  909. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  910. if (ret <= 0)
  911. goto fail;
  912. // because we are polling irq status, so the first event should be ignored
  913. time0 = gpt4_tick2time_us(gpt4_get_current_tick());
  914. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  915. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  916. if (ret <= 0)
  917. goto fail;
  918. //DISPMSG("vsync signaled:%d\n", gpt4_tick2time_us(gpt4_get_current_tick()));
  919. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC,1000);
  920. if (ret > 0) {
  921. time1 = gpt4_tick2time_us(gpt4_get_current_tick());
  922. } else
  923. goto fail;
  924. lcd_time = (time1 - time0)/2;
  925. pgc->plcm->is_connected = true;
  926. if (0 != lcd_time)
  927. return (100000000/lcd_time);
  928. else
  929. return (6000);
  930. fail:
  931. DISPERR("wait event fail\n");
  932. return 0;
  933. }
  934. int primary_display_setbacklight(unsigned int level)
  935. {
  936. DISPMSG("lk %s level=%d\n",__func__,level);
  937. int ret=0;
  938. if (pgc->dpmgr_handle == NULL) {
  939. DISPCHECK("lk set backlight early!\n");
  940. return 0;
  941. }
  942. if (dpmgr_path_is_busy(pgc->dpmgr_handle)) {
  943. DISPCHECK("primary display path is busy\n");
  944. ret = dpmgr_wait_event_timeout(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE, HZ*1);
  945. DISPCHECK("wait frame done ret:%d\n", ret);
  946. }
  947. disp_lcm_set_backlight(pgc->plcm,level);
  948. return 0;
  949. }
  950. /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  951. /***********************/
  952. /*****Legacy DISP API*****/
  953. /***********************/
  954. UINT32 DISP_GetScreenWidth(void)
  955. {
  956. return primary_display_get_width();
  957. }
  958. UINT32 DISP_GetScreenHeight(void)
  959. {
  960. return primary_display_get_height();
  961. }
  962. UINT32 DISP_GetActiveHeight(void)
  963. {
  964. if (pgc->plcm == NULL) {
  965. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  966. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  967. if (pgc->plcm == NULL)return 0;
  968. }
  969. if (pgc->plcm->params) {
  970. return pgc->plcm->params->physical_height;
  971. } else {
  972. DISPERR("lcm_params is null!\n");
  973. return 0;
  974. }
  975. }
  976. UINT32 DISP_GetActiveWidth(void)
  977. {
  978. if (pgc->plcm == NULL) {
  979. pgc->plcm = disp_lcm_probe(NULL, LCM_INTERFACE_NOTDEFINED);
  980. DISPERR("lcm handle is null, after probe:0x%08x\n", (unsigned int)pgc->plcm);
  981. if (pgc->plcm == NULL)return 0;
  982. }
  983. if (pgc->plcm->params) {
  984. return pgc->plcm->params->physical_width;
  985. } else {
  986. DISPERR("lcm_params is null!\n");
  987. return 0;
  988. }
  989. }
  990. int primary_display_capture_framebuffer(unsigned int *pbuf)
  991. {
  992. return 0;
  993. }
  994. UINT32 DISP_GetPanelBPP(void)
  995. {
  996. #if 0
  997. PANEL_COLOR_FORMAT fmt;
  998. disp_drv_init_context();
  999. if (disp_if_drv->get_panel_color_format == NULL) {
  1000. return DISP_STATUS_NOT_IMPLEMENTED;
  1001. }
  1002. fmt = disp_if_drv->get_panel_color_format();
  1003. switch (fmt) {
  1004. case PANEL_COLOR_FORMAT_RGB332:
  1005. return 8;
  1006. case PANEL_COLOR_FORMAT_RGB444:
  1007. return 12;
  1008. case PANEL_COLOR_FORMAT_RGB565:
  1009. return 16;
  1010. case PANEL_COLOR_FORMAT_RGB666:
  1011. return 18;
  1012. case PANEL_COLOR_FORMAT_RGB888:
  1013. return 24;
  1014. default:
  1015. return 0;
  1016. }
  1017. #endif
  1018. return 0;
  1019. }
  1020. UINT32 DISP_GetScreenBpp(void)
  1021. {
  1022. return disp_fb_bpp;
  1023. }
  1024. UINT32 DISP_GetPages(void)
  1025. {
  1026. return disp_fb_pages; // Double Buffers
  1027. }
  1028. // could we use the same header file between lk/kernel to avoid definition non-match issue?
  1029. #define DAL_BPP (2)
  1030. #define DAL_WIDTH (DISP_GetScreenWidth())
  1031. #define DAL_HEIGHT (DISP_GetScreenHeight())
  1032. UINT32 DAL_GetLayerSize(void)
  1033. {
  1034. return DAL_WIDTH * DAL_HEIGHT * DAL_BPP + 4096;
  1035. }
  1036. UINT32 DISP_GetFBRamSize(void)
  1037. {
  1038. #ifdef ENLARGE_FB_FOR_COMPRESS
  1039. static bool fb_size_cal = 0;
  1040. static UINT32 frame_buf_size = 0;
  1041. if (!fb_size_cal) {
  1042. UINT32 body_buf_size = ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) *
  1043. ((DISP_GetScreenBpp() + 7) >> 3);
  1044. UINT32 header_buf_size = (ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT)) /
  1045. (OVL_TILE_W * OVL_TILE_H) * OVL_HEADER_SIZE_PER_TILE_BYTES;
  1046. header_buf_size = ALIGN_TO(header_buf_size, OVL_HEADER_ALIGN_BYTES);
  1047. frame_buf_size = (body_buf_size + body_buf_size) * DISP_GetPages();
  1048. fb_size_cal = 1;
  1049. }
  1050. return frame_buf_size;
  1051. #else
  1052. return ALIGN_TO(DISP_GetScreenWidth(), MTK_FB_ALIGNMENT) * ALIGN_TO(DISP_GetScreenHeight(), MTK_FB_ALIGNMENT) * ((DISP_GetScreenBpp() + 7) >> 3) * DISP_GetPages();
  1053. #endif
  1054. }
  1055. unsigned int DISP_GetVRamSize(void)
  1056. {
  1057. static UINT32 vramSize = 0;
  1058. unsigned int fb_ram_size =0;
  1059. //FB RAM(n blocks)+(Assert layer size)
  1060. if (0 == vramSize) {
  1061. vramSize = DISP_GetFBRamSize();
  1062. DISPDBG("^^ DISP_GetFBRamSize: %u bytes\n", vramSize);
  1063. fb_ram_size = vramSize;
  1064. vramSize += DAL_GetLayerSize();
  1065. DISPDBG("^^ DAL_GetLayerSize: %u bytes\n", vramSize-fb_ram_size);
  1066. #if defined(MTK_ROUND_CORNER_SUPPORT) && !defined(DISP_HW_RC)
  1067. fb_ram_size = vramSize;
  1068. vramSize += disp_get_round_corner_size();
  1069. DISPDBG("^^ round corner Size: %u bytes\n", vramSize-fb_ram_size);
  1070. #endif
  1071. #if 0
  1072. if (g_is_64bit_kernel) {
  1073. vramSize = ALIGN_TO(vramSize, 0x400000); // both start addr and size needs 2MB align, so size must 4MB align
  1074. } else {
  1075. vramSize = ALIGN_TO(vramSize, 0x100000); // both start addr and size needs 2MB align, so size must 4MB align
  1076. }
  1077. #else
  1078. vramSize = ALIGN_TO(vramSize, 0x10000); // just align to 64KB is OK
  1079. #endif
  1080. DISPDBG("^^ DISP_GetVRamSize: %u bytes\n", vramSize);
  1081. }
  1082. return vramSize;
  1083. }