ddp_misc.c 8.5 KB

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  1. /* Copyright Statement:
  2. *
  3. * This software/firmware and related documentation ("MediaTek Software") are
  4. * protected under relevant copyright laws. The information contained herein
  5. * is confidential and proprietary to MediaTek Inc. and/or its licensors.
  6. * Without the prior written permission of MediaTek inc. and/or its licensors,
  7. * any reproduction, modification, use or disclosure of MediaTek Software,
  8. * and information contained herein, in whole or in part, shall be strictly prohibited.
  9. */
  10. /* MediaTek Inc. (C) 2015. All rights reserved.
  11. *
  12. * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
  13. * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
  14. * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
  15. * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
  16. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
  17. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
  18. * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
  19. * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
  20. * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
  21. * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
  22. * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
  23. * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
  24. * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
  25. * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
  26. * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
  27. * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
  28. * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
  29. * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  30. */
  31. #define LOG_TAG "MISC"
  32. #include <platform/ddp_reg.h>
  33. #include <platform/ddp_misc.h>
  34. #include <platform/disp_drv_platform.h>
  35. #include <debug.h>
  36. void ddp_bypass_color(int idx, unsigned int width, unsigned int height, void * handle)
  37. {
  38. dprintf(CRITICAL, "bypass color\n");
  39. DISP_REG_SET(NULL,DISP_COLOR_CFG_MAIN, 1<<7); //bypass color engine
  40. DISP_REG_SET(NULL,DISP_COLOR_INTERNAL_IP_WIDTH, width); //bypass color engine
  41. DISP_REG_SET(NULL,DISP_COLOR_INTERNAL_IP_HEIGHT, height); //bypass color engine
  42. DISP_REG_SET(NULL,DISP_COLOR_START, 0x1); // start
  43. }
  44. void ddp_bypass_ccorr(int idx, unsigned int width, unsigned int height, void * handle)
  45. {
  46. dprintf(CRITICAL, "bypass ccorr\n");
  47. DISP_REG_MASK(NULL, (DISP_REG_CCORR_CFG - idx * 0x1000), 1, 1);
  48. DISP_REG_SET(NULL, (DISP_REG_CCORR_SIZE - idx * 0x1000), (width<<16)|height); //bypass color engine
  49. DISP_REG_SET(NULL, (DISP_REG_CCORR_EN - idx * 0x1000), 1);
  50. }
  51. static int ddp_ccorr_start(DISP_MODULE_ENUM module, void *handle)
  52. {
  53. #ifdef LK_BYPASS_SHADOW_REG
  54. DISP_REG_SET_FIELD(handle, FLD_CCORR_BYPASS_SHADOW,
  55. DISP_REG_CCORR_SHADOW_CTRL, 0x1);
  56. DISP_REG_SET_FIELD(handle, FLD_CCORR_READ_WRK_REG,
  57. DISP_REG_CCORR_SHADOW_CTRL, 0x1);
  58. #endif
  59. return 0;
  60. }
  61. static int ddp_aal_start(DISP_MODULE_ENUM module, void *handle)
  62. {
  63. #ifdef LK_BYPASS_SHADOW_REG
  64. DISP_REG_SET_FIELD(handle, FLD_AAL_BYPASS_SHADOW,
  65. DISP_REG_AAL_SHADOW_CTRL, 0x1);
  66. DISP_REG_SET_FIELD(handle, FLD_AAL_READ_WRK_REG,
  67. DISP_REG_AAL_SHADOW_CTRL, 0x1);
  68. #endif
  69. return 0;
  70. }
  71. void ddp_bypass_mdp_aal(unsigned int width, unsigned int height, void * handle)
  72. {
  73. dprintf(CRITICAL, "bypass mdp_aal\n");
  74. }
  75. void ddp_bypass_aal(unsigned int width, unsigned int height, void * handle)
  76. {
  77. dprintf(CRITICAL, "bypass aal\n");
  78. DISP_REG_SET_FIELD(handle, CFG_FLD_RELAY_MODE, DISP_AAL_CFG, 0x1); //relay_mode
  79. DISP_REG_SET(handle, DISP_AAL_SIZE, (width<<16)|height); //bypass color engine
  80. DISP_REG_SET(handle, DISP_AAL_OUTPUT_SIZE, (width << 16) | height);
  81. DISP_REG_SET(handle,DISP_AAL_EN, 0x1); //bypass mode
  82. }
  83. void ddp_bypass_gamma(unsigned int width, unsigned int height, void * handle)
  84. {
  85. dprintf(CRITICAL, "bypass gamma\n");
  86. DISP_REG_MASK(NULL,DISP_REG_GAMMA_CFG, 1, 1);
  87. DISP_REG_SET(NULL,DISP_REG_GAMMA_SIZE, (width<<16)|height); //bypass color engine
  88. DISP_REG_SET(handle,DISP_REG_GAMMA_EN, 0x1); //bypass mode
  89. }
  90. static int ddp_gamma_start(DISP_MODULE_ENUM module, void *handle)
  91. {
  92. #ifdef LK_BYPASS_SHADOW_REG
  93. DISP_REG_SET_FIELD(handle, FLD_GAMMA_BYPASS_SHADOW,
  94. DISP_REG_GAMMA_SHADOW_CTRL, 0x1);
  95. DISP_REG_SET_FIELD(handle, FLD_GAMMA_READ_WRK_REG,
  96. DISP_REG_GAMMA_SHADOW_CTRL, 0x1);
  97. #endif
  98. return 0;
  99. }
  100. static int ddp_color_start(DISP_MODULE_ENUM module, void *handle)
  101. {
  102. #ifdef LK_BYPASS_SHADOW_REG
  103. DISP_REG_SET_FIELD(handle, FLD_COLOR_BYPASS_SHADOW,
  104. DISP_REG_COLOR_SHADOW_CTRL, 0x1);
  105. DISP_REG_SET_FIELD(handle, FLD_COLOR_READ_WRK_REG,
  106. DISP_REG_COLOR_SHADOW_CTRL, 0x1);
  107. #endif
  108. return 0;
  109. }
  110. static int config_color(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  111. {
  112. int color_idx;
  113. if (module == DISP_MODULE_COLOR0)
  114. color_idx = 0;
  115. else
  116. color_idx = 1;
  117. dprintf(CRITICAL, "config color dirty = %d\n", pConfig->dst_dirty);
  118. if (!pConfig->dst_dirty) {
  119. return 0;
  120. }
  121. ddp_bypass_color(color_idx,pConfig->dst_w, pConfig->dst_h,cmdq);
  122. return 0;
  123. }
  124. static int config_ccorr(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  125. {
  126. int ccorr_idx;
  127. if (module == DISP_MODULE_CCORR0)
  128. ccorr_idx = 0;
  129. else
  130. ccorr_idx = 1;
  131. dprintf(CRITICAL, "config ccorr%d dirty = %d\n", ccorr_idx, pConfig->dst_dirty);
  132. if (!pConfig->dst_dirty) {
  133. return 0;
  134. }
  135. ddp_bypass_ccorr(ccorr_idx, pConfig->dst_w, pConfig->dst_h,cmdq);
  136. return 0;
  137. }
  138. static int config_mdp_aal(DISP_MODULE_ENUM module, disp_ddp_path_config *pConfig, void *cmdq)
  139. {
  140. dprintf(CRITICAL, "config mdp_aal dirty = %d\n", pConfig->dst_dirty);
  141. if (!pConfig->dst_dirty) {
  142. return 0;
  143. }
  144. ddp_bypass_mdp_aal(pConfig->dst_w, pConfig->dst_h,cmdq);
  145. return 0;
  146. }
  147. static int config_aal(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  148. {
  149. dprintf(CRITICAL, "config aal dirty = %d\n", pConfig->dst_dirty);
  150. if (!pConfig->dst_dirty) {
  151. return 0;
  152. }
  153. ddp_bypass_aal(pConfig->dst_w, pConfig->dst_h,cmdq);
  154. return 0;
  155. }
  156. static int config_gamma(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
  157. {
  158. dprintf(CRITICAL, "config gamma dirty = %d\n", pConfig->dst_dirty);
  159. if (!pConfig->dst_dirty) {
  160. return 0;
  161. }
  162. ddp_bypass_gamma(pConfig->dst_w, pConfig->dst_h,cmdq);
  163. return 0;
  164. }
  165. static int clock_on(DISP_MODULE_ENUM module,void * handle)
  166. {
  167. ddp_enable_module_clock(module);
  168. return 0;
  169. }
  170. static int clock_off(DISP_MODULE_ENUM module,void * handle)
  171. {
  172. ddp_disable_module_clock(module);
  173. return 0;
  174. }
  175. ///////////////////////////////////////////////////////////
  176. // color
  177. DDP_MODULE_DRIVER ddp_driver_color = {
  178. .init = clock_on,
  179. .deinit = clock_off,
  180. .config = config_color,
  181. .start = ddp_color_start,
  182. .trigger = NULL,
  183. .stop = NULL,
  184. .reset = NULL,
  185. .power_on = clock_on,
  186. .power_off = clock_off,
  187. .is_idle = NULL,
  188. .is_busy = NULL,
  189. .dump_info = NULL,
  190. .bypass = NULL,
  191. .build_cmdq = NULL,
  192. .set_lcm_utils = NULL,
  193. };
  194. // ccorr
  195. DDP_MODULE_DRIVER ddp_driver_ccorr = {
  196. .init = clock_on,
  197. .deinit = clock_off,
  198. .config = config_ccorr,
  199. .start = ddp_ccorr_start,
  200. .trigger = NULL,
  201. .stop = NULL,
  202. .reset = NULL,
  203. .power_on = clock_on,
  204. .power_off = clock_off,
  205. .is_idle = NULL,
  206. .is_busy = NULL,
  207. .dump_info = NULL,
  208. .bypass = NULL,
  209. .build_cmdq = NULL,
  210. .set_lcm_utils = NULL,
  211. };
  212. // aal
  213. DDP_MODULE_DRIVER ddp_driver_aal = {
  214. .init = clock_on,
  215. .deinit = clock_off,
  216. .config = config_aal,
  217. .start = ddp_aal_start,
  218. .trigger = NULL,
  219. .stop = NULL,
  220. .reset = NULL,
  221. .power_on = clock_on,
  222. .power_off = clock_off,
  223. .is_idle = NULL,
  224. .is_busy = NULL,
  225. .dump_info = NULL,
  226. .bypass = NULL,
  227. .build_cmdq = NULL,
  228. .set_lcm_utils = NULL,
  229. };
  230. // gamma
  231. DDP_MODULE_DRIVER ddp_driver_gamma = {
  232. .init = clock_on,
  233. .deinit = clock_off,
  234. .config = config_gamma,
  235. .start = ddp_gamma_start,
  236. .trigger = NULL,
  237. .stop = NULL,
  238. .reset = NULL,
  239. .power_on = clock_on,
  240. .power_off = clock_off,
  241. .is_idle = NULL,
  242. .is_busy = NULL,
  243. .dump_info = NULL,
  244. .bypass = NULL,
  245. .build_cmdq = NULL,
  246. .set_lcm_utils = NULL,
  247. };