mtk-lk/platform/mt6885/mtk_dcm_autogen.c

/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2018. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#include <mtk_dcm.h>

#include <debug.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <arch/arm.h>
#include <arch/arm/mmu.h>
#include <arch/ops.h>
#include <target/board.h>
#include <platform/mt_reg_base.h>
#include <platform/mt_typedefs.h>
#include <platform/sync_write.h>

#include <mtk_dcm_autogen.h>

#define IOMEM(a) (a)
#define __raw_readl(addr)		DRV_Reg32(addr)
extern unsigned long mt_secure_call(unsigned long, unsigned long, unsigned long, unsigned long);
#define MTK_SIP_KERNEL_MCSI_NS_ACCESS	0x82000217
#define mcsi_reg_read(offset) \
		mt_secure_call(MTK_SIP_KERNEL_MCSI_NS_ACCESS, 0, offset, 0)
#define mcsi_reg_write(val, offset) \
		mt_secure_call(MTK_SIP_KERNEL_MCSI_NS_ACCESS, 1, offset, val)
#define reg_read(addr)	 __raw_readl(addr)
#define reg_write(addr, val)   mt_reg_sync_writel((val), ((void *)addr))

#define MCUSYS_SMC_WRITE(addr, val)  reg_write(addr, val)
#define MCSI_SMC_WRITE(addr, val)  mcsi_reg_write(val, (addr##_PHYS & 0xFFFF))
#define MCSI_SMC_READ(addr)  mcsi_reg_read(addr##_PHYS & 0xFFFF)
// ========== auto gen code 2019 0718 ====================
#define INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK ((0x1f << 12) | \
			(0x1 << 17) | \
			(0x1 << 18))
#define INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON ((0x10 << 12) | \
			(0x1 << 17) | \
			(0x0 << 18))
#define INFRACFG_AO_AXIMEM_BUS_DCM_REG0_OFF ((0x10 << 12) | \
			(0x0 << 17) | \
			(0x1 << 18))

bool dcm_infracfg_ao_aximem_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(INFRA_AXIMEM_IDLE_BIT_EN_0) &
		INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);

	return ret;
}

void dcm_infracfg_ao_aximem_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_aximem_bus_dcm'" */
		reg_write(INFRA_AXIMEM_IDLE_BIT_EN_0,
			(reg_read(INFRA_AXIMEM_IDLE_BIT_EN_0) &
			~INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_aximem_bus_dcm'" */
		reg_write(INFRA_AXIMEM_IDLE_BIT_EN_0,
			(reg_read(INFRA_AXIMEM_IDLE_BIT_EN_0) &
			~INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_AXIMEM_BUS_DCM_REG0_OFF);
	}
}

#define INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK ((0x1 << 0))
#define INFRACFG_AO_INFRA_BUS_DCM_REG0_ON ((0x1 << 0))
#define INFRACFG_AO_INFRA_BUS_DCM_REG0_OFF ((0x0 << 0))

bool dcm_infracfg_ao_infra_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(INFRA_BUS_DCM_CTRL) &
		INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);

	return ret;
}

void dcm_infracfg_ao_infra_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_infra_bus_dcm'" */
		reg_write(INFRA_BUS_DCM_CTRL,
			(reg_read(INFRA_BUS_DCM_CTRL) &
			~INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_infra_bus_dcm'" */
		reg_write(INFRA_BUS_DCM_CTRL,
			(reg_read(INFRA_BUS_DCM_CTRL) &
			~INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_INFRA_BUS_DCM_REG0_OFF);
	}
}

#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK ((0x1 << 8))
#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK ((0x1 << 8))
#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON ((0x1 << 8))
#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON ((0x0 << 8))
#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_OFF ((0x0 << 8))
#define INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_OFF ((0x1 << 8))

bool dcm_infracfg_ao_infra_conn_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MODULE_SW_CG_2_SET) &
		INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON);
	ret &= ((reg_read(MODULE_SW_CG_2_CLR) &
		INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK) ==
		(unsigned int) INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON);

	return ret;
}

void dcm_infracfg_ao_infra_conn_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_infra_conn_bus_dcm'" */
		reg_write(MODULE_SW_CG_2_SET,
			(reg_read(MODULE_SW_CG_2_SET) &
			~INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON);
		reg_write(MODULE_SW_CG_2_CLR,
			(reg_read(MODULE_SW_CG_2_CLR) &
			~INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK) |
			INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_infra_conn_bus_dcm'" */
		reg_write(MODULE_SW_CG_2_SET,
			(reg_read(MODULE_SW_CG_2_SET) &
			~INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_OFF);
		reg_write(MODULE_SW_CG_2_CLR,
			(reg_read(MODULE_SW_CG_2_CLR) &
			~INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK) |
			INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_OFF);
	}
}

#define INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK ((0xf << 0))
#define INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON ((0x0 << 0))
#define INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_OFF ((0xf << 0))

bool dcm_infracfg_ao_infra_rx_p2p_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(P2P_RX_CLK_ON) &
		INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);

	return ret;
}

void dcm_infracfg_ao_infra_rx_p2p_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_infra_rx_p2p_dcm'" */
		reg_write(P2P_RX_CLK_ON,
			(reg_read(P2P_RX_CLK_ON) &
			~INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK) |
			INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_infra_rx_p2p_dcm'" */
		reg_write(P2P_RX_CLK_ON,
			(reg_read(P2P_RX_CLK_ON) &
			~INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK) |
			INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_OFF);
	}
}

#define INFRACFG_AO_MTS_BUS_DCM_REG0_MASK ((0x1U << 31))
#define INFRACFG_AO_MTS_BUS_DCM_REG0_ON ((0x1U << 31))
#define INFRACFG_AO_MTS_BUS_DCM_REG0_OFF ((0x0 << 31))

bool dcm_infracfg_ao_mts_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(INFRA_BUS_DCM_CTRL) &
		INFRACFG_AO_MTS_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_MTS_BUS_DCM_REG0_ON);

	return ret;
}

void dcm_infracfg_ao_mts_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_mts_bus_dcm'" */
		reg_write(INFRA_BUS_DCM_CTRL,
			(reg_read(INFRA_BUS_DCM_CTRL) &
			~INFRACFG_AO_MTS_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_MTS_BUS_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_mts_bus_dcm'" */
		reg_write(INFRA_BUS_DCM_CTRL,
			(reg_read(INFRA_BUS_DCM_CTRL) &
			~INFRACFG_AO_MTS_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_MTS_BUS_DCM_REG0_OFF);
	}
}

#define INFRACFG_AO_PERI_BUS_DCM_REG0_MASK ((0x1 << 0))
#define INFRACFG_AO_PERI_BUS_DCM_REG0_ON ((0x1 << 0))
#define INFRACFG_AO_PERI_BUS_DCM_REG0_OFF ((0x0 << 0))

bool dcm_infracfg_ao_peri_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
		INFRACFG_AO_PERI_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_PERI_BUS_DCM_REG0_ON);

	return ret;
}

void dcm_infracfg_ao_peri_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_peri_bus_dcm'" */
		reg_write(PERI_BUS_DCM_CTRL,
			(reg_read(PERI_BUS_DCM_CTRL) &
			~INFRACFG_AO_PERI_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_peri_bus_dcm'" */
		reg_write(PERI_BUS_DCM_CTRL,
			(reg_read(PERI_BUS_DCM_CTRL) &
			~INFRACFG_AO_PERI_BUS_DCM_REG0_MASK) |
			INFRACFG_AO_PERI_BUS_DCM_REG0_OFF);
	}
}

#define INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK ((0x1 << 29) | \
			(0x1U << 31))
#define INFRACFG_AO_PERI_MODULE_DCM_REG0_ON ((0x1 << 29) | \
			(0x1U << 31))
#define INFRACFG_AO_PERI_MODULE_DCM_REG0_OFF ((0x0 << 29) | \
			(0x0 << 31))

bool dcm_infracfg_ao_peri_module_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
		INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);

	return ret;
}

void dcm_infracfg_ao_peri_module_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_peri_module_dcm'" */
		reg_write(PERI_BUS_DCM_CTRL,
			(reg_read(PERI_BUS_DCM_CTRL) &
			~INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK) |
			INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_peri_module_dcm'" */
		reg_write(PERI_BUS_DCM_CTRL,
			(reg_read(PERI_BUS_DCM_CTRL) &
			~INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK) |
			INFRACFG_AO_PERI_MODULE_DCM_REG0_OFF);
	}
}

#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3) | \
			(0x1 << 4) | \
			(0x1 << 5) | \
			(0x1 << 6))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK ((0xffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_MASK ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_ON ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3) | \
			(0x0 << 4) | \
			(0x1 << 5) | \
			(0x0 << 6))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_ON ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_ON ((0x44 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_ON ((0xc00000ff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_ON ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_ON ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_ON ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_ON ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_ON ((0x1f00000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_ON ((0xc0040180 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_ON ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_ON ((0x3 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_ON ((0xc000000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_ON ((0xc00000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_ON ((0x1f08000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_ON ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_ON ((0x20003040 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_ON ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_ON ((0x1000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_ON ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_ON ((0x10020f20 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_ON ((0x19000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_ON ((0x40a0818 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_ON ((0x370 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_ON ((0xc001c080 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_ON ((0x33000e01 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_ON ((0x180067e1 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_ON ((0x8c << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_ON ((0x20c0008 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_ON ((0xc00007e << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_ON ((0x80050006 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_ON ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_OFF ((0x0 << 0) | \
			(0x0 << 1) | \
			(0x0 << 2) | \
			(0x0 << 3) | \
			(0x0 << 4) | \
			(0x0 << 5) | \
			(0x0 << 6))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_OFF ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_OFF ((0x44 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_OFF ((0xc00000ff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_OFF ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_OFF ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_OFF ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_OFF ((0xffffffff << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_OFF ((0x1f00000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_OFF ((0xc0040180 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_OFF ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_OFF ((0x3 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_OFF ((0xc000000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_OFF ((0xc00000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_OFF ((0x1f08000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_OFF ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_OFF ((0x20003040 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_OFF ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_OFF ((0x1000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_OFF ((0x0 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_OFF ((0x10020f20 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_OFF ((0x19000 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_OFF ((0x40a0818 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_OFF ((0x370 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_OFF ((0xc001c080 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_OFF ((0x33000e01 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_OFF ((0x180067e1 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_OFF ((0x8c << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_OFF ((0x20c0008 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_OFF ((0xc00007e << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_OFF ((0x80050006 << 0))
#define INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_OFF ((0x0 << 0))

bool dcm_infracfg_ao_mem_dcm_emi_group_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(INFRA_EMI_DCM_CFG0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_ON);
	ret &= ((reg_read(INFRA_EMI_DCM_CFG1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_ON);
	ret &= ((reg_read(INFRA_EMI_DCM_CFG2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_ON);
	ret &= ((reg_read(TOP_CK_ANCHOR_CFG) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_ON);
	ret &= ((reg_read(INFRA_EMI_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_ON);
	ret &= ((reg_read(INFRA_EMI_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_ON);
	ret &= ((reg_read(INFRA_EMI_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_ON);
	ret &= ((reg_read(INFRA_EMI_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_ON);
	ret &= ((reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_ON);
	ret &= ((reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_ON);
	ret &= ((reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_ON);
	ret &= ((reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_ON);
	ret &= ((reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_ON);
	ret &= ((reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_ON);
	ret &= ((reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_ON);
	ret &= ((reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_ON);
	ret &= ((reg_read(INFRA_EMI_M3_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_ON);
	ret &= ((reg_read(INFRA_EMI_M3_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_ON);
	ret &= ((reg_read(INFRA_EMI_M3_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_ON);
	ret &= ((reg_read(INFRA_EMI_M3_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_ON);
	ret &= ((reg_read(INFRA_EMI_M4_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_ON);
	ret &= ((reg_read(INFRA_EMI_M4_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_ON);
	ret &= ((reg_read(INFRA_EMI_M4_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_ON);
	ret &= ((reg_read(INFRA_EMI_M4_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_ON);
	ret &= ((reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_ON);
	ret &= ((reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_ON);
	ret &= ((reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_ON);
	ret &= ((reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_ON);
	ret &= ((reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_0) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_ON);
	ret &= ((reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_1) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_ON);
	ret &= ((reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_2) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_ON);
	ret &= ((reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_3) &
		INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_MASK) ==
		(unsigned int) INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_ON);

	return ret;
}

void dcm_infracfg_ao_mem_dcm_emi_group(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infracfg_ao_mem_dcm_emi_group'" */
		reg_write(INFRA_EMI_DCM_CFG0,
			(reg_read(INFRA_EMI_DCM_CFG0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_ON);
		reg_write(INFRA_EMI_DCM_CFG1,
			(reg_read(INFRA_EMI_DCM_CFG1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_ON);
		reg_write(INFRA_EMI_DCM_CFG2,
			(reg_read(INFRA_EMI_DCM_CFG2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_ON);
		reg_write(TOP_CK_ANCHOR_CFG,
			(reg_read(TOP_CK_ANCHOR_CFG) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_ON);
		reg_write(INFRA_EMI_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_ON);
		reg_write(INFRA_EMI_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_ON);
		reg_write(INFRA_EMI_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_ON);
		reg_write(INFRA_EMI_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_ON);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_ON);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_ON);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_ON);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_ON);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_ON);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_ON);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_ON);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_ON);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_ON);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_ON);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_ON);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_ON);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_ON);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_ON);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_ON);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_ON);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_ON);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_ON);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_ON);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_ON);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_ON);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_ON);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_ON);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infracfg_ao_mem_dcm_emi_group'" */
		reg_write(INFRA_EMI_DCM_CFG0,
			(reg_read(INFRA_EMI_DCM_CFG0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_OFF);
		reg_write(INFRA_EMI_DCM_CFG1,
			(reg_read(INFRA_EMI_DCM_CFG1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_OFF);
		reg_write(INFRA_EMI_DCM_CFG2,
			(reg_read(INFRA_EMI_DCM_CFG2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_OFF);
		reg_write(TOP_CK_ANCHOR_CFG,
			(reg_read(TOP_CK_ANCHOR_CFG) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_OFF);
		reg_write(INFRA_EMI_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_OFF);
		reg_write(INFRA_EMI_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_OFF);
		reg_write(INFRA_EMI_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_OFF);
		reg_write(INFRA_EMI_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_OFF);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_OFF);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_OFF);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_OFF);
		reg_write(INFRA_EMI_M0M1_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M0M1_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_OFF);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_OFF);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_OFF);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_OFF);
		reg_write(INFRA_EMI_M2M5_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M2M5_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_OFF);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_OFF);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG17_OFF);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG18_OFF);
		reg_write(INFRA_EMI_M3_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M3_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG19_OFF);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG20_OFF);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG21_OFF);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG22_OFF);
		reg_write(INFRA_EMI_M4_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M4_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG23_OFF);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG24_OFF);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG25_OFF);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG26_OFF);
		reg_write(INFRA_EMI_M6M7_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_M6M7_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG27_OFF);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_0,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_0) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG28_OFF);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_1,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_1) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG29_OFF);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_2,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_2) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG30_OFF);
		reg_write(INFRA_EMI_SRAM_IDLE_BIT_EN_3,
			(reg_read(INFRA_EMI_SRAM_IDLE_BIT_EN_3) &
			~INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_MASK) |
			INFRACFG_AO_MEM_DCM_EMI_GROUP_REG31_OFF);
	}
}

#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK ((0x1 << 0) | \
			(0x1 << 1))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK ((0x1 << 2) | \
			(0x1f << 11))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK ((0x1 << 12))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_ON ((0x1 << 0) | \
			(0x1 << 1))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_ON ((0x1 << 2) | \
			(0x0 << 11))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_ON ((0x1 << 12))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_OFF ((0x1 << 0) | \
			(0x1 << 1))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_OFF ((0x0 << 2) | \
			(0x0 << 11))
#define INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_OFF ((0x0 << 12))

bool dcm_infra_ao_bcrm_infra_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
		INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_ON);
	ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
		INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK) ==
		(unsigned int) INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_ON);
	ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13) &
		INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK) ==
		(unsigned int) INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_ON);

	return ret;
}

void dcm_infra_ao_bcrm_infra_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infra_ao_bcrm_infra_bus_dcm'" */
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
			~INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK) |
			INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_ON);
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
			~INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK) |
			INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_ON);
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13) &
			~INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK) |
			INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infra_ao_bcrm_infra_bus_dcm'" */
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_0) &
			~INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_MASK) |
			INFRA_AO_BCRM_INFRA_BUS_DCM_REG0_OFF);
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_1) &
			~INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_MASK) |
			INFRA_AO_BCRM_INFRA_BUS_DCM_REG1_OFF);
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13) &
			~INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_MASK) |
			INFRA_AO_BCRM_INFRA_BUS_DCM_REG2_OFF);
	}
}

#define INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK ((0x1 << 0) | \
			(0x1f << 9))
#define INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK ((0x1 << 25))
#define INFRA_AO_BCRM_PERI_BUS_DCM_REG0_ON ((0x1 << 0) | \
			(0x0 << 9))
#define INFRA_AO_BCRM_PERI_BUS_DCM_REG1_ON ((0x1 << 25))
#define INFRA_AO_BCRM_PERI_BUS_DCM_REG0_OFF ((0x0 << 0) | \
			(0x0 << 9))
#define INFRA_AO_BCRM_PERI_BUS_DCM_REG1_OFF ((0x0 << 25))

bool dcm_infra_ao_bcrm_peri_bus_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
		INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK) ==
		(unsigned int) INFRA_AO_BCRM_PERI_BUS_DCM_REG0_ON);
	ret &= ((reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13) &
		INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK) ==
		(unsigned int) INFRA_AO_BCRM_PERI_BUS_DCM_REG1_ON);

	return ret;
}

void dcm_infra_ao_bcrm_peri_bus_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'infra_ao_bcrm_peri_bus_dcm'" */
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
			~INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK) |
			INFRA_AO_BCRM_PERI_BUS_DCM_REG0_ON);
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13) &
			~INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK) |
			INFRA_AO_BCRM_PERI_BUS_DCM_REG1_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'infra_ao_bcrm_peri_bus_dcm'" */
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_2) &
			~INFRA_AO_BCRM_PERI_BUS_DCM_REG0_MASK) |
			INFRA_AO_BCRM_PERI_BUS_DCM_REG0_OFF);
		reg_write(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13,
			(reg_read(VDNR_DCM_TOP_INFRA_PAR_BUS_u_INFRA_PAR_BUS_CTRL_13) &
			~INFRA_AO_BCRM_PERI_BUS_DCM_REG1_MASK) |
			INFRA_AO_BCRM_PERI_BUS_DCM_REG1_OFF);
	}
}

#define EMI_EMI_DCM_REG0_MASK ((0xff << 24))
#define EMI_EMI_DCM_REG1_MASK ((0xff << 24))
#define EMI_EMI_DCM_REG2_MASK ((0x1 << 13))
#define EMI_EMI_DCM_REG0_ON ((0x0 << 24))
#define EMI_EMI_DCM_REG1_ON ((0x0 << 24))
#define EMI_EMI_DCM_REG2_ON ((0x0 << 13))
#define EMI_EMI_DCM_REG0_OFF ((0xff << 24))
#define EMI_EMI_DCM_REG1_OFF ((0xff << 24))
#define EMI_EMI_DCM_REG2_OFF ((0x1 << 13))

bool dcm_emi_emi_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(EMI_CONM) &
		EMI_EMI_DCM_REG0_MASK) ==
		(unsigned int) EMI_EMI_DCM_REG0_ON);
	ret &= ((reg_read(EMI_CONN) &
		EMI_EMI_DCM_REG1_MASK) ==
		(unsigned int) EMI_EMI_DCM_REG1_ON);
	ret &= ((reg_read(EMI_THRO_CTRL0) &
		EMI_EMI_DCM_REG2_MASK) ==
		(unsigned int) EMI_EMI_DCM_REG2_ON);

	return ret;
}

void dcm_emi_emi_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'emi_emi_dcm'" */
		reg_write(EMI_CONM,
			(reg_read(EMI_CONM) &
			~EMI_EMI_DCM_REG0_MASK) |
			EMI_EMI_DCM_REG0_ON);
		reg_write(EMI_CONN,
			(reg_read(EMI_CONN) &
			~EMI_EMI_DCM_REG1_MASK) |
			EMI_EMI_DCM_REG1_ON);
		reg_write(EMI_THRO_CTRL0,
			(reg_read(EMI_THRO_CTRL0) &
			~EMI_EMI_DCM_REG2_MASK) |
			EMI_EMI_DCM_REG2_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'emi_emi_dcm'" */
		reg_write(EMI_CONM,
			(reg_read(EMI_CONM) &
			~EMI_EMI_DCM_REG0_MASK) |
			EMI_EMI_DCM_REG0_OFF);
		reg_write(EMI_CONN,
			(reg_read(EMI_CONN) &
			~EMI_EMI_DCM_REG1_MASK) |
			EMI_EMI_DCM_REG1_OFF);
		reg_write(EMI_THRO_CTRL0,
			(reg_read(EMI_THRO_CTRL0) &
			~EMI_EMI_DCM_REG2_MASK) |
			EMI_EMI_DCM_REG2_OFF);
	}
}

#define SUB_EMI_EMI_DCM_REG0_MASK ((0xff << 24))
#define SUB_EMI_EMI_DCM_REG1_MASK ((0xff << 24))
#define SUB_EMI_EMI_DCM_REG2_MASK ((0x1 << 13))
#define SUB_EMI_EMI_DCM_REG0_ON ((0x0 << 24))
#define SUB_EMI_EMI_DCM_REG1_ON ((0x0 << 24))
#define SUB_EMI_EMI_DCM_REG2_ON ((0x0 << 13))
#define SUB_EMI_EMI_DCM_REG0_OFF ((0xff << 24))
#define SUB_EMI_EMI_DCM_REG1_OFF ((0xff << 24))
#define SUB_EMI_EMI_DCM_REG2_OFF ((0x1 << 13))

bool dcm_sub_emi_emi_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(SUB_EMI_EMI_CONM) &
		SUB_EMI_EMI_DCM_REG0_MASK) ==
		(unsigned int) SUB_EMI_EMI_DCM_REG0_ON);
	ret &= ((reg_read(SUB_EMI_EMI_CONN) &
		SUB_EMI_EMI_DCM_REG1_MASK) ==
		(unsigned int) SUB_EMI_EMI_DCM_REG1_ON);
	ret &= ((reg_read(SUB_EMI_EMI_THRO_CTRL0) &
		SUB_EMI_EMI_DCM_REG2_MASK) ==
		(unsigned int) SUB_EMI_EMI_DCM_REG2_ON);

	return ret;
}

void dcm_sub_emi_emi_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'sub_emi_emi_dcm'" */
		reg_write(SUB_EMI_EMI_CONM,
			(reg_read(SUB_EMI_EMI_CONM) &
			~SUB_EMI_EMI_DCM_REG0_MASK) |
			SUB_EMI_EMI_DCM_REG0_ON);
		reg_write(SUB_EMI_EMI_CONN,
			(reg_read(SUB_EMI_EMI_CONN) &
			~SUB_EMI_EMI_DCM_REG1_MASK) |
			SUB_EMI_EMI_DCM_REG1_ON);
		reg_write(SUB_EMI_EMI_THRO_CTRL0,
			(reg_read(SUB_EMI_EMI_THRO_CTRL0) &
			~SUB_EMI_EMI_DCM_REG2_MASK) |
			SUB_EMI_EMI_DCM_REG2_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'sub_emi_emi_dcm'" */
		reg_write(SUB_EMI_EMI_CONM,
			(reg_read(SUB_EMI_EMI_CONM) &
			~SUB_EMI_EMI_DCM_REG0_MASK) |
			SUB_EMI_EMI_DCM_REG0_OFF);
		reg_write(SUB_EMI_EMI_CONN,
			(reg_read(SUB_EMI_EMI_CONN) &
			~SUB_EMI_EMI_DCM_REG1_MASK) |
			SUB_EMI_EMI_DCM_REG1_OFF);
		reg_write(SUB_EMI_EMI_THRO_CTRL0,
			(reg_read(SUB_EMI_EMI_THRO_CTRL0) &
			~SUB_EMI_EMI_DCM_REG2_MASK) |
			SUB_EMI_EMI_DCM_REG2_OFF);
	}
}

#define CHN0_EMI_CHN_EMI_DCM_REG0_MASK ((0xff << 24))
#define CHN0_EMI_CHN_EMI_DCM_REG0_ON ((0x0 << 24))
#define CHN0_EMI_CHN_EMI_DCM_REG0_OFF ((0xff << 24))

bool dcm_chn0_emi_chn_emi_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(CHN0_EMI_CHN_EMI_CONB) &
		CHN0_EMI_CHN_EMI_DCM_REG0_MASK) ==
		(unsigned int) CHN0_EMI_CHN_EMI_DCM_REG0_ON);

	return ret;
}

void dcm_chn0_emi_chn_emi_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'chn0_emi_chn_emi_dcm'" */
		reg_write(CHN0_EMI_CHN_EMI_CONB,
			(reg_read(CHN0_EMI_CHN_EMI_CONB) &
			~CHN0_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN0_EMI_CHN_EMI_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'chn0_emi_chn_emi_dcm'" */
		reg_write(CHN0_EMI_CHN_EMI_CONB,
			(reg_read(CHN0_EMI_CHN_EMI_CONB) &
			~CHN0_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN0_EMI_CHN_EMI_DCM_REG0_OFF);
	}
}

#define DRAMC_CH0_TOP5_DDRPHY_REG0_MASK ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH0_TOP5_DDRPHY_REG1_MASK ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x1 << 26))
#define DRAMC_CH0_TOP5_DDRPHY_REG2_MASK ((0x1 << 24))
#define DRAMC_CH0_TOP5_DDRPHY_REG3_MASK ((0x1 << 30))
#define DRAMC_CH0_TOP5_DDRPHY_REG4_MASK ((0x3 << 0))
#define DRAMC_CH0_TOP5_DDRPHY_REG0_ON ((0x0 << 8) | \
			(0x0 << 9) | \
			(0x0 << 10) | \
			(0x0 << 11) | \
			(0x0 << 12) | \
			(0x0 << 13) | \
			(0x0 << 14) | \
			(0x0 << 15) | \
			(0x0 << 16) | \
			(0x0 << 17) | \
			(0x0 << 19))
#define DRAMC_CH0_TOP5_DDRPHY_REG1_ON ((0x0 << 6) | \
			(0x0 << 7) | \
			(0x0 << 26))
#define DRAMC_CH0_TOP5_DDRPHY_REG2_ON ((0x0 << 24))
#define DRAMC_CH0_TOP5_DDRPHY_REG3_ON ((0x0 << 30))
#define DRAMC_CH0_TOP5_DDRPHY_REG4_ON ((0x0 << 0))
#define DRAMC_CH0_TOP5_DDRPHY_REG0_OFF ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH0_TOP5_DDRPHY_REG1_OFF ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x0 << 26))
#define DRAMC_CH0_TOP5_DDRPHY_REG2_OFF ((0x1 << 24))
#define DRAMC_CH0_TOP5_DDRPHY_REG3_OFF ((0x1 << 30))
#define DRAMC_CH0_TOP5_DDRPHY_REG4_OFF ((0x1 << 0))
#if 0
static unsigned int dramc_ch0_top5_rg_mem_dcm_idle_fsel_get(void)
{
	return (reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL2) >> 21) & 0x1f;
}
#endif
static void dramc_ch0_top5_rg_mem_dcm_idle_fsel_set(unsigned int val)
{
	reg_write(DRAMC_CH0_TOP5_MISC_CG_CTRL2,
		(reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL2) &
		~(0x1f << 21)) |
		(val & 0x1f) << 21);
}

bool dcm_dramc_ch0_top5_ddrphy_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL0) &
		DRAMC_CH0_TOP5_DDRPHY_REG0_MASK) ==
		(unsigned int) DRAMC_CH0_TOP5_DDRPHY_REG0_ON);
	ret &= ((reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL2) &
		DRAMC_CH0_TOP5_DDRPHY_REG1_MASK) ==
		(unsigned int) DRAMC_CH0_TOP5_DDRPHY_REG1_ON);
	ret &= ((reg_read(DRAMC_CH0_TOP5_MISC_DQSG_RETRY1) &
		DRAMC_CH0_TOP5_DDRPHY_REG2_MASK) ==
		(unsigned int) DRAMC_CH0_TOP5_DDRPHY_REG2_ON);
	ret &= ((reg_read(DRAMC_CH0_TOP5_MISC_APB) &
		DRAMC_CH0_TOP5_DDRPHY_REG3_MASK) ==
		(unsigned int) DRAMC_CH0_TOP5_DDRPHY_REG3_ON);
	ret &= ((reg_read(DRAMC_CH0_TOP5_MISC_CTRL2) &
		DRAMC_CH0_TOP5_DDRPHY_REG4_MASK) ==
		(unsigned int) DRAMC_CH0_TOP5_DDRPHY_REG4_ON);

	return ret;
}

void dcm_dramc_ch0_top5_ddrphy(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'dramc_ch0_top5_ddrphy'" */
		dramc_ch0_top5_rg_mem_dcm_idle_fsel_set(0x8);
		reg_write(DRAMC_CH0_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH0_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG0_ON);
		reg_write(DRAMC_CH0_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH0_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG1_ON);
		reg_write(DRAMC_CH0_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH0_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH0_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG2_ON);
		reg_write(DRAMC_CH0_TOP5_MISC_APB,
			(reg_read(DRAMC_CH0_TOP5_MISC_APB) &
			~DRAMC_CH0_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG3_ON);
		reg_write(DRAMC_CH0_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH0_TOP5_MISC_CTRL2) &
			~DRAMC_CH0_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG4_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'dramc_ch0_top5_ddrphy'" */
		dramc_ch0_top5_rg_mem_dcm_idle_fsel_set(0x0);
		reg_write(DRAMC_CH0_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH0_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG0_OFF);
		reg_write(DRAMC_CH0_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH0_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH0_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG1_OFF);
		reg_write(DRAMC_CH0_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH0_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH0_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG2_OFF);
		reg_write(DRAMC_CH0_TOP5_MISC_APB,
			(reg_read(DRAMC_CH0_TOP5_MISC_APB) &
			~DRAMC_CH0_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG3_OFF);
		reg_write(DRAMC_CH0_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH0_TOP5_MISC_CTRL2) &
			~DRAMC_CH0_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH0_TOP5_DDRPHY_REG4_OFF);
	}
}

#define CHN1_EMI_CHN_EMI_DCM_REG0_MASK ((0xff << 24))
#define CHN1_EMI_CHN_EMI_DCM_REG0_ON ((0x0 << 24))
#define CHN1_EMI_CHN_EMI_DCM_REG0_OFF ((0xff << 24))

bool dcm_chn1_emi_chn_emi_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(CHN1_EMI_CHN_EMI_CONB) &
		CHN1_EMI_CHN_EMI_DCM_REG0_MASK) ==
		(unsigned int) CHN1_EMI_CHN_EMI_DCM_REG0_ON);

	return ret;
}

void dcm_chn1_emi_chn_emi_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'chn1_emi_chn_emi_dcm'" */
		reg_write(CHN1_EMI_CHN_EMI_CONB,
			(reg_read(CHN1_EMI_CHN_EMI_CONB) &
			~CHN1_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN1_EMI_CHN_EMI_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'chn1_emi_chn_emi_dcm'" */
		reg_write(CHN1_EMI_CHN_EMI_CONB,
			(reg_read(CHN1_EMI_CHN_EMI_CONB) &
			~CHN1_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN1_EMI_CHN_EMI_DCM_REG0_OFF);
	}
}

#define DRAMC_CH1_TOP5_DDRPHY_REG0_MASK ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH1_TOP5_DDRPHY_REG1_MASK ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x1 << 26))
#define DRAMC_CH1_TOP5_DDRPHY_REG2_MASK ((0x1 << 24))
#define DRAMC_CH1_TOP5_DDRPHY_REG3_MASK ((0x1 << 30))
#define DRAMC_CH1_TOP5_DDRPHY_REG4_MASK ((0x3 << 0))
#define DRAMC_CH1_TOP5_DDRPHY_REG0_ON ((0x0 << 8) | \
			(0x0 << 9) | \
			(0x0 << 10) | \
			(0x0 << 11) | \
			(0x0 << 12) | \
			(0x0 << 13) | \
			(0x0 << 14) | \
			(0x0 << 15) | \
			(0x0 << 16) | \
			(0x0 << 17) | \
			(0x0 << 19))
#define DRAMC_CH1_TOP5_DDRPHY_REG1_ON ((0x0 << 6) | \
			(0x0 << 7) | \
			(0x0 << 26))
#define DRAMC_CH1_TOP5_DDRPHY_REG2_ON ((0x0 << 24))
#define DRAMC_CH1_TOP5_DDRPHY_REG3_ON ((0x0 << 30))
#define DRAMC_CH1_TOP5_DDRPHY_REG4_ON ((0x0 << 0))
#define DRAMC_CH1_TOP5_DDRPHY_REG0_OFF ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH1_TOP5_DDRPHY_REG1_OFF ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x0 << 26))
#define DRAMC_CH1_TOP5_DDRPHY_REG2_OFF ((0x1 << 24))
#define DRAMC_CH1_TOP5_DDRPHY_REG3_OFF ((0x1 << 30))
#define DRAMC_CH1_TOP5_DDRPHY_REG4_OFF ((0x1 << 0))
#if 0
static unsigned int dramc_ch1_top5_rg_mem_dcm_idle_fsel_get(void)
{
	return (reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL2) >> 21) & 0x1f;
}
#endif
static void dramc_ch1_top5_rg_mem_dcm_idle_fsel_set(unsigned int val)
{
	reg_write(DRAMC_CH1_TOP5_MISC_CG_CTRL2,
		(reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL2) &
		~(0x1f << 21)) |
		(val & 0x1f) << 21);
}

bool dcm_dramc_ch1_top5_ddrphy_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL0) &
		DRAMC_CH1_TOP5_DDRPHY_REG0_MASK) ==
		(unsigned int) DRAMC_CH1_TOP5_DDRPHY_REG0_ON);
	ret &= ((reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL2) &
		DRAMC_CH1_TOP5_DDRPHY_REG1_MASK) ==
		(unsigned int) DRAMC_CH1_TOP5_DDRPHY_REG1_ON);
	ret &= ((reg_read(DRAMC_CH1_TOP5_MISC_DQSG_RETRY1) &
		DRAMC_CH1_TOP5_DDRPHY_REG2_MASK) ==
		(unsigned int) DRAMC_CH1_TOP5_DDRPHY_REG2_ON);
	ret &= ((reg_read(DRAMC_CH1_TOP5_MISC_APB) &
		DRAMC_CH1_TOP5_DDRPHY_REG3_MASK) ==
		(unsigned int) DRAMC_CH1_TOP5_DDRPHY_REG3_ON);
	ret &= ((reg_read(DRAMC_CH1_TOP5_MISC_CTRL2) &
		DRAMC_CH1_TOP5_DDRPHY_REG4_MASK) ==
		(unsigned int) DRAMC_CH1_TOP5_DDRPHY_REG4_ON);

	return ret;
}

void dcm_dramc_ch1_top5_ddrphy(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'dramc_ch1_top5_ddrphy'" */
		dramc_ch1_top5_rg_mem_dcm_idle_fsel_set(0x8);
		reg_write(DRAMC_CH1_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH1_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG0_ON);
		reg_write(DRAMC_CH1_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH1_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG1_ON);
		reg_write(DRAMC_CH1_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH1_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH1_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG2_ON);
		reg_write(DRAMC_CH1_TOP5_MISC_APB,
			(reg_read(DRAMC_CH1_TOP5_MISC_APB) &
			~DRAMC_CH1_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG3_ON);
		reg_write(DRAMC_CH1_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH1_TOP5_MISC_CTRL2) &
			~DRAMC_CH1_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG4_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'dramc_ch1_top5_ddrphy'" */
		dramc_ch1_top5_rg_mem_dcm_idle_fsel_set(0x0);
		reg_write(DRAMC_CH1_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH1_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG0_OFF);
		reg_write(DRAMC_CH1_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH1_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH1_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG1_OFF);
		reg_write(DRAMC_CH1_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH1_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH1_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG2_OFF);
		reg_write(DRAMC_CH1_TOP5_MISC_APB,
			(reg_read(DRAMC_CH1_TOP5_MISC_APB) &
			~DRAMC_CH1_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG3_OFF);
		reg_write(DRAMC_CH1_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH1_TOP5_MISC_CTRL2) &
			~DRAMC_CH1_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH1_TOP5_DDRPHY_REG4_OFF);
	}
}

#define CHN2_EMI_CHN_EMI_DCM_REG0_MASK ((0xff << 24))
#define CHN2_EMI_CHN_EMI_DCM_REG0_ON ((0x0 << 24))
#define CHN2_EMI_CHN_EMI_DCM_REG0_OFF ((0xff << 24))

bool dcm_chn2_emi_chn_emi_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(CHN2_EMI_CHN_EMI_CONB) &
		CHN2_EMI_CHN_EMI_DCM_REG0_MASK) ==
		(unsigned int) CHN2_EMI_CHN_EMI_DCM_REG0_ON);

	return ret;
}

void dcm_chn2_emi_chn_emi_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'chn2_emi_chn_emi_dcm'" */
		reg_write(CHN2_EMI_CHN_EMI_CONB,
			(reg_read(CHN2_EMI_CHN_EMI_CONB) &
			~CHN2_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN2_EMI_CHN_EMI_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'chn2_emi_chn_emi_dcm'" */
		reg_write(CHN2_EMI_CHN_EMI_CONB,
			(reg_read(CHN2_EMI_CHN_EMI_CONB) &
			~CHN2_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN2_EMI_CHN_EMI_DCM_REG0_OFF);
	}
}

#define DRAMC_CH2_TOP5_DDRPHY_REG0_MASK ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH2_TOP5_DDRPHY_REG1_MASK ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x1 << 26))
#define DRAMC_CH2_TOP5_DDRPHY_REG2_MASK ((0x1 << 24))
#define DRAMC_CH2_TOP5_DDRPHY_REG3_MASK ((0x1 << 30))
#define DRAMC_CH2_TOP5_DDRPHY_REG4_MASK ((0x3 << 0))
#define DRAMC_CH2_TOP5_DDRPHY_REG0_ON ((0x0 << 8) | \
			(0x0 << 9) | \
			(0x0 << 10) | \
			(0x0 << 11) | \
			(0x0 << 12) | \
			(0x0 << 13) | \
			(0x0 << 14) | \
			(0x0 << 15) | \
			(0x0 << 16) | \
			(0x0 << 17) | \
			(0x0 << 19))
#define DRAMC_CH2_TOP5_DDRPHY_REG1_ON ((0x0 << 6) | \
			(0x0 << 7) | \
			(0x0 << 26))
#define DRAMC_CH2_TOP5_DDRPHY_REG2_ON ((0x0 << 24))
#define DRAMC_CH2_TOP5_DDRPHY_REG3_ON ((0x0 << 30))
#define DRAMC_CH2_TOP5_DDRPHY_REG4_ON ((0x0 << 0))
#define DRAMC_CH2_TOP5_DDRPHY_REG0_OFF ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH2_TOP5_DDRPHY_REG1_OFF ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x0 << 26))
#define DRAMC_CH2_TOP5_DDRPHY_REG2_OFF ((0x1 << 24))
#define DRAMC_CH2_TOP5_DDRPHY_REG3_OFF ((0x1 << 30))
#define DRAMC_CH2_TOP5_DDRPHY_REG4_OFF ((0x1 << 0))
#if 0
static unsigned int dramc_ch2_top5_rg_mem_dcm_idle_fsel_get(void)
{
	return (reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL2) >> 21) & 0x1f;
}
#endif
static void dramc_ch2_top5_rg_mem_dcm_idle_fsel_set(unsigned int val)
{
	reg_write(DRAMC_CH2_TOP5_MISC_CG_CTRL2,
		(reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL2) &
		~(0x1f << 21)) |
		(val & 0x1f) << 21);
}

bool dcm_dramc_ch2_top5_ddrphy_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL0) &
		DRAMC_CH2_TOP5_DDRPHY_REG0_MASK) ==
		(unsigned int) DRAMC_CH2_TOP5_DDRPHY_REG0_ON);
	ret &= ((reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL2) &
		DRAMC_CH2_TOP5_DDRPHY_REG1_MASK) ==
		(unsigned int) DRAMC_CH2_TOP5_DDRPHY_REG1_ON);
	ret &= ((reg_read(DRAMC_CH2_TOP5_MISC_DQSG_RETRY1) &
		DRAMC_CH2_TOP5_DDRPHY_REG2_MASK) ==
		(unsigned int) DRAMC_CH2_TOP5_DDRPHY_REG2_ON);
	ret &= ((reg_read(DRAMC_CH2_TOP5_MISC_APB) &
		DRAMC_CH2_TOP5_DDRPHY_REG3_MASK) ==
		(unsigned int) DRAMC_CH2_TOP5_DDRPHY_REG3_ON);
	ret &= ((reg_read(DRAMC_CH2_TOP5_MISC_CTRL2) &
		DRAMC_CH2_TOP5_DDRPHY_REG4_MASK) ==
		(unsigned int) DRAMC_CH2_TOP5_DDRPHY_REG4_ON);

	return ret;
}

void dcm_dramc_ch2_top5_ddrphy(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'dramc_ch2_top5_ddrphy'" */
		dramc_ch2_top5_rg_mem_dcm_idle_fsel_set(0x8);
		reg_write(DRAMC_CH2_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH2_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG0_ON);
		reg_write(DRAMC_CH2_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH2_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG1_ON);
		reg_write(DRAMC_CH2_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH2_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH2_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG2_ON);
		reg_write(DRAMC_CH2_TOP5_MISC_APB,
			(reg_read(DRAMC_CH2_TOP5_MISC_APB) &
			~DRAMC_CH2_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG3_ON);
		reg_write(DRAMC_CH2_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH2_TOP5_MISC_CTRL2) &
			~DRAMC_CH2_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG4_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'dramc_ch2_top5_ddrphy'" */
		dramc_ch2_top5_rg_mem_dcm_idle_fsel_set(0x0);
		reg_write(DRAMC_CH2_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH2_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG0_OFF);
		reg_write(DRAMC_CH2_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH2_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH2_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG1_OFF);
		reg_write(DRAMC_CH2_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH2_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH2_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG2_OFF);
		reg_write(DRAMC_CH2_TOP5_MISC_APB,
			(reg_read(DRAMC_CH2_TOP5_MISC_APB) &
			~DRAMC_CH2_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG3_OFF);
		reg_write(DRAMC_CH2_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH2_TOP5_MISC_CTRL2) &
			~DRAMC_CH2_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH2_TOP5_DDRPHY_REG4_OFF);
	}
}

#define CHN3_EMI_CHN_EMI_DCM_REG0_MASK ((0xff << 24))
#define CHN3_EMI_CHN_EMI_DCM_REG0_ON ((0x0 << 24))
#define CHN3_EMI_CHN_EMI_DCM_REG0_OFF ((0xff << 24))

bool dcm_chn3_emi_chn_emi_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(CHN3_EMI_CHN_EMI_CONB) &
		CHN3_EMI_CHN_EMI_DCM_REG0_MASK) ==
		(unsigned int) CHN3_EMI_CHN_EMI_DCM_REG0_ON);

	return ret;
}

void dcm_chn3_emi_chn_emi_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'chn3_emi_chn_emi_dcm'" */
		reg_write(CHN3_EMI_CHN_EMI_CONB,
			(reg_read(CHN3_EMI_CHN_EMI_CONB) &
			~CHN3_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN3_EMI_CHN_EMI_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'chn3_emi_chn_emi_dcm'" */
		reg_write(CHN3_EMI_CHN_EMI_CONB,
			(reg_read(CHN3_EMI_CHN_EMI_CONB) &
			~CHN3_EMI_CHN_EMI_DCM_REG0_MASK) |
			CHN3_EMI_CHN_EMI_DCM_REG0_OFF);
	}
}

#define DRAMC_CH3_TOP5_DDRPHY_REG0_MASK ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH3_TOP5_DDRPHY_REG1_MASK ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x1 << 26))
#define DRAMC_CH3_TOP5_DDRPHY_REG2_MASK ((0x1 << 24))
#define DRAMC_CH3_TOP5_DDRPHY_REG3_MASK ((0x1 << 30))
#define DRAMC_CH3_TOP5_DDRPHY_REG4_MASK ((0x3 << 0))
#define DRAMC_CH3_TOP5_DDRPHY_REG0_ON ((0x0 << 8) | \
			(0x0 << 9) | \
			(0x0 << 10) | \
			(0x0 << 11) | \
			(0x0 << 12) | \
			(0x0 << 13) | \
			(0x0 << 14) | \
			(0x0 << 15) | \
			(0x0 << 16) | \
			(0x0 << 17) | \
			(0x0 << 19))
#define DRAMC_CH3_TOP5_DDRPHY_REG1_ON ((0x0 << 6) | \
			(0x0 << 7) | \
			(0x0 << 26))
#define DRAMC_CH3_TOP5_DDRPHY_REG2_ON ((0x0 << 24))
#define DRAMC_CH3_TOP5_DDRPHY_REG3_ON ((0x0 << 30))
#define DRAMC_CH3_TOP5_DDRPHY_REG4_ON ((0x0 << 0))
#define DRAMC_CH3_TOP5_DDRPHY_REG0_OFF ((0x1 << 8) | \
			(0x1 << 9) | \
			(0x1 << 10) | \
			(0x1 << 11) | \
			(0x1 << 12) | \
			(0x1 << 13) | \
			(0x1 << 14) | \
			(0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 19))
#define DRAMC_CH3_TOP5_DDRPHY_REG1_OFF ((0x1 << 6) | \
			(0x1 << 7) | \
			(0x0 << 26))
#define DRAMC_CH3_TOP5_DDRPHY_REG2_OFF ((0x1 << 24))
#define DRAMC_CH3_TOP5_DDRPHY_REG3_OFF ((0x1 << 30))
#define DRAMC_CH3_TOP5_DDRPHY_REG4_OFF ((0x1 << 0))
#if 0
static unsigned int dramc_ch3_top5_rg_mem_dcm_idle_fsel_get(void)
{
	return (reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL2) >> 21) & 0x1f;
}
#endif
static void dramc_ch3_top5_rg_mem_dcm_idle_fsel_set(unsigned int val)
{
	reg_write(DRAMC_CH3_TOP5_MISC_CG_CTRL2,
		(reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL2) &
		~(0x1f << 21)) |
		(val & 0x1f) << 21);
}

bool dcm_dramc_ch3_top5_ddrphy_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL0) &
		DRAMC_CH3_TOP5_DDRPHY_REG0_MASK) ==
		(unsigned int) DRAMC_CH3_TOP5_DDRPHY_REG0_ON);
	ret &= ((reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL2) &
		DRAMC_CH3_TOP5_DDRPHY_REG1_MASK) ==
		(unsigned int) DRAMC_CH3_TOP5_DDRPHY_REG1_ON);
	ret &= ((reg_read(DRAMC_CH3_TOP5_MISC_DQSG_RETRY1) &
		DRAMC_CH3_TOP5_DDRPHY_REG2_MASK) ==
		(unsigned int) DRAMC_CH3_TOP5_DDRPHY_REG2_ON);
	ret &= ((reg_read(DRAMC_CH3_TOP5_MISC_APB) &
		DRAMC_CH3_TOP5_DDRPHY_REG3_MASK) ==
		(unsigned int) DRAMC_CH3_TOP5_DDRPHY_REG3_ON);
	ret &= ((reg_read(DRAMC_CH3_TOP5_MISC_CTRL2) &
		DRAMC_CH3_TOP5_DDRPHY_REG4_MASK) ==
		(unsigned int) DRAMC_CH3_TOP5_DDRPHY_REG4_ON);

	return ret;
}

void dcm_dramc_ch3_top5_ddrphy(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'dramc_ch3_top5_ddrphy'" */
		dramc_ch3_top5_rg_mem_dcm_idle_fsel_set(0x8);
		reg_write(DRAMC_CH3_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH3_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG0_ON);
		reg_write(DRAMC_CH3_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH3_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG1_ON);
		reg_write(DRAMC_CH3_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH3_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH3_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG2_ON);
		reg_write(DRAMC_CH3_TOP5_MISC_APB,
			(reg_read(DRAMC_CH3_TOP5_MISC_APB) &
			~DRAMC_CH3_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG3_ON);
		reg_write(DRAMC_CH3_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH3_TOP5_MISC_CTRL2) &
			~DRAMC_CH3_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG4_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'dramc_ch3_top5_ddrphy'" */
		dramc_ch3_top5_rg_mem_dcm_idle_fsel_set(0x0);
		reg_write(DRAMC_CH3_TOP5_MISC_CG_CTRL0,
			(reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL0) &
			~DRAMC_CH3_TOP5_DDRPHY_REG0_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG0_OFF);
		reg_write(DRAMC_CH3_TOP5_MISC_CG_CTRL2,
			(reg_read(DRAMC_CH3_TOP5_MISC_CG_CTRL2) &
			~DRAMC_CH3_TOP5_DDRPHY_REG1_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG1_OFF);
		reg_write(DRAMC_CH3_TOP5_MISC_DQSG_RETRY1,
			(reg_read(DRAMC_CH3_TOP5_MISC_DQSG_RETRY1) &
			~DRAMC_CH3_TOP5_DDRPHY_REG2_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG2_OFF);
		reg_write(DRAMC_CH3_TOP5_MISC_APB,
			(reg_read(DRAMC_CH3_TOP5_MISC_APB) &
			~DRAMC_CH3_TOP5_DDRPHY_REG3_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG3_OFF);
		reg_write(DRAMC_CH3_TOP5_MISC_CTRL2,
			(reg_read(DRAMC_CH3_TOP5_MISC_CTRL2) &
			~DRAMC_CH3_TOP5_DDRPHY_REG4_MASK) |
			DRAMC_CH3_TOP5_DDRPHY_REG4_OFF);
	}
}

#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3) | \
			(0x1 << 4) | \
			(0x1 << 5) | \
			(0x1 << 6) | \
			(0x1 << 16) | \
			(0x1 << 18))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK ((0xffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_ON ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_ON ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_ON ((0x0 << 0) | \
			(0x1 << 1) | \
			(0x0 << 2) | \
			(0x1 << 3) | \
			(0x1 << 4) | \
			(0x1 << 5) | \
			(0x1 << 6) | \
			(0x1 << 16) | \
			(0x1 << 18))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_ON ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_ON ((0x44 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_ON ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_ON ((0x6007fe0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_ON ((0x3f << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_ON ((0x3000c << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_ON ((0x200003c0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_ON ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_ON ((0x1000fc00 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_ON ((0x1000000 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_ON ((0xcfff0000 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_ON ((0x30008013 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_ON ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_ON ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_OFF ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_OFF ((0xffffffff << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_OFF ((0x0 << 0) | \
			(0x0 << 1) | \
			(0x0 << 2) | \
			(0x0 << 3) | \
			(0x0 << 4) | \
			(0x0 << 5) | \
			(0x0 << 6) | \
			(0x1 << 16) | \
			(0x1 << 18))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_OFF ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_OFF ((0x44 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_OFF ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_OFF ((0x6007fe0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_OFF ((0x3f << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_OFF ((0x3000c << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_OFF ((0x200003c0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_OFF ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_OFF ((0x1000fc00 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_OFF ((0x1000000 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_OFF ((0xcfff0000 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_OFF ((0x30008013 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_OFF ((0x0 << 0))
#define SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_OFF ((0x0 << 0))

bool dcm_sub_infracfg_ao_mem_dcm_emi_group_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(SUB_INFRA_EMI_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_DCM_CFG0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_DCM_CFG1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_DCM_CFG2) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M3_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M3_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M4_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M4_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_0) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_ON);
	ret &= ((reg_read(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_1) &
		SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK) ==
		(unsigned int) SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_ON);

	return ret;
}

void dcm_sub_infracfg_ao_mem_dcm_emi_group(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'sub_infracfg_ao_mem_dcm_emi_group'" */
		reg_write(SUB_INFRA_EMI_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_ON);
		reg_write(SUB_INFRA_EMI_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_ON);
		reg_write(SUB_INFRA_EMI_DCM_CFG0,
			(reg_read(SUB_INFRA_EMI_DCM_CFG0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_ON);
		reg_write(SUB_INFRA_EMI_DCM_CFG1,
			(reg_read(SUB_INFRA_EMI_DCM_CFG1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_ON);
		reg_write(SUB_INFRA_EMI_DCM_CFG2,
			(reg_read(SUB_INFRA_EMI_DCM_CFG2) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_ON);
		reg_write(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_ON);
		reg_write(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_ON);
		reg_write(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_ON);
		reg_write(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_ON);
		reg_write(SUB_INFRA_EMI_M3_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M3_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_ON);
		reg_write(SUB_INFRA_EMI_M3_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M3_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_ON);
		reg_write(SUB_INFRA_EMI_M4_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M4_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_ON);
		reg_write(SUB_INFRA_EMI_M4_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M4_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_ON);
		reg_write(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_ON);
		reg_write(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_ON);
		reg_write(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_ON);
		reg_write(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'sub_infracfg_ao_mem_dcm_emi_group'" */
		reg_write(SUB_INFRA_EMI_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG0_OFF);
		reg_write(SUB_INFRA_EMI_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG1_OFF);
		reg_write(SUB_INFRA_EMI_DCM_CFG0,
			(reg_read(SUB_INFRA_EMI_DCM_CFG0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG2_OFF);
		reg_write(SUB_INFRA_EMI_DCM_CFG1,
			(reg_read(SUB_INFRA_EMI_DCM_CFG1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG3_OFF);
		reg_write(SUB_INFRA_EMI_DCM_CFG2,
			(reg_read(SUB_INFRA_EMI_DCM_CFG2) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG4_OFF);
		reg_write(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG5_OFF);
		reg_write(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M0M1_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG6_OFF);
		reg_write(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG7_OFF);
		reg_write(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M2M5_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG8_OFF);
		reg_write(SUB_INFRA_EMI_M3_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M3_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG9_OFF);
		reg_write(SUB_INFRA_EMI_M3_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M3_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG10_OFF);
		reg_write(SUB_INFRA_EMI_M4_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M4_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG11_OFF);
		reg_write(SUB_INFRA_EMI_M4_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M4_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG12_OFF);
		reg_write(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG13_OFF);
		reg_write(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_M6M7_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG14_OFF);
		reg_write(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_0,
			(reg_read(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_0) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG15_OFF);
		reg_write(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_1,
			(reg_read(SUB_INFRA_EMI_VPU_IDLE_BIT_EN_1) &
			~SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_MASK) |
			SUB_INFRACFG_AO_MEM_DCM_EMI_GROUP_REG16_OFF);
	}
}

#define SSPM_SSPM_DCM_REG0_MASK ((0x1 << 8))
#define SSPM_SSPM_DCM_REG1_MASK ((0x1fffff << 0))
#define SSPM_SSPM_DCM_REG0_ON ((0x1 << 8))
#define SSPM_SSPM_DCM_REG1_ON ((0x1fbfff << 0))
#define SSPM_SSPM_DCM_REG0_OFF ((0x0 << 8))
#define SSPM_SSPM_DCM_REG1_OFF ((0x0 << 0))

bool dcm_sspm_sspm_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(SSPM_MCLK_DIV) &
		SSPM_SSPM_DCM_REG0_MASK) ==
		(unsigned int) SSPM_SSPM_DCM_REG0_ON);
	ret &= ((reg_read(SSPM_DCM_CTRL) &
		SSPM_SSPM_DCM_REG1_MASK) ==
		(unsigned int) SSPM_SSPM_DCM_REG1_ON);

	return ret;
}

void dcm_sspm_sspm_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'sspm_sspm_dcm'" */
		reg_write(SSPM_MCLK_DIV,
			(reg_read(SSPM_MCLK_DIV) &
			~SSPM_SSPM_DCM_REG0_MASK) |
			SSPM_SSPM_DCM_REG0_ON);
		reg_write(SSPM_DCM_CTRL,
			(reg_read(SSPM_DCM_CTRL) &
			~SSPM_SSPM_DCM_REG1_MASK) |
			SSPM_SSPM_DCM_REG1_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'sspm_sspm_dcm'" */
		reg_write(SSPM_MCLK_DIV,
			(reg_read(SSPM_MCLK_DIV) &
			~SSPM_SSPM_DCM_REG0_MASK) |
			SSPM_SSPM_DCM_REG0_OFF);
		reg_write(SSPM_DCM_CTRL,
			(reg_read(SSPM_DCM_CTRL) &
			~SSPM_SSPM_DCM_REG1_MASK) |
			SSPM_SSPM_DCM_REG1_OFF);
	}
}

#define AUDIO_AUD_MAS_AHB_CK_DCM_REG0_MASK ((0x1 << 29) | \
			(0x1 << 30))
#define AUDIO_AUD_MAS_AHB_CK_DCM_REG0_ON ((0x1 << 29) | \
			(0x1 << 30))
#define AUDIO_AUD_MAS_AHB_CK_DCM_REG0_OFF ((0x0 << 29) | \
			(0x0 << 30))

bool dcm_audio_aud_mas_ahb_ck_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(AUDIO_TOP_CON0) &
		AUDIO_AUD_MAS_AHB_CK_DCM_REG0_MASK) ==
		(unsigned int) AUDIO_AUD_MAS_AHB_CK_DCM_REG0_ON);

	return ret;
}

void dcm_audio_aud_mas_ahb_ck_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'audio_aud_mas_ahb_ck_dcm'" */
		reg_write(AUDIO_TOP_CON0,
			(reg_read(AUDIO_TOP_CON0) &
			~AUDIO_AUD_MAS_AHB_CK_DCM_REG0_MASK) |
			AUDIO_AUD_MAS_AHB_CK_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'audio_aud_mas_ahb_ck_dcm'" */
		reg_write(AUDIO_TOP_CON0,
			(reg_read(AUDIO_TOP_CON0) &
			~AUDIO_AUD_MAS_AHB_CK_DCM_REG0_MASK) |
			AUDIO_AUD_MAS_AHB_CK_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK ((0x1 << 17))
#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK ((0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 18) | \
			(0x1 << 21))
#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK ((0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 18))
#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON ((0x1 << 17))
#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON ((0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 18) | \
			(0x1 << 21))
#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON ((0x1 << 15) | \
			(0x1 << 16) | \
			(0x1 << 17) | \
			(0x1 << 18))
#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
			(0x0 << 16) | \
			(0x0 << 17) | \
			(0x0 << 18) | \
			(0x0 << 21))
#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
			(0x0 << 16) | \
			(0x0 << 17) | \
			(0x0 << 18))

bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
		MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
	ret &= ((reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
		MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
	ret &= ((reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
		MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);

	return ret;
}

void dcm_mp_cpusys_top_adb_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
			~MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
		reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
			(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
			~MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) |
			MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
		reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
			~MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) |
			MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
			~MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
		reg_write(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
			(reg_read(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
			~MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) |
			MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
		reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
			~MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) |
			MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
	}
}

#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK ((0x1 << 5))
#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK ((0x1 << 8))
#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK ((0x1 << 16))
#define MP_CPUSYS_TOP_APB_DCM_REG0_ON ((0x1 << 5))
#define MP_CPUSYS_TOP_APB_DCM_REG1_ON ((0x1 << 8))
#define MP_CPUSYS_TOP_APB_DCM_REG2_ON ((0x1 << 16))
#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))

bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
		MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
	ret &= ((reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
		MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
	ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
		MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);

	return ret;
}

void dcm_mp_cpusys_top_apb_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
			~MP_CPUSYS_TOP_APB_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_APB_DCM_REG0_ON);
		reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
			~MP_CPUSYS_TOP_APB_DCM_REG1_MASK) |
			MP_CPUSYS_TOP_APB_DCM_REG1_ON);
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
			~MP_CPUSYS_TOP_APB_DCM_REG2_MASK) |
			MP_CPUSYS_TOP_APB_DCM_REG2_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
			~MP_CPUSYS_TOP_APB_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
		reg_write(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
			~MP_CPUSYS_TOP_APB_DCM_REG1_MASK) |
			MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
			~MP_CPUSYS_TOP_APB_DCM_REG2_MASK) |
			MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
	}
}

#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK ((0x1 << 11))
#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON ((0x1 << 11))
#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11))

bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
		MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_bus_pll_div_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
		reg_write(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
			(reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
			~MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
		reg_write(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
			(reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
			~MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK ((0x1 << 0))
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON ((0x1 << 0))
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))

bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
		MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_core_stall_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
			~MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
			~MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))

bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MCSIC_DCM0) &
		MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_cpubiu_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
		reg_write(MP_CPUSYS_TOP_MCSIC_DCM0,
			(reg_read(MP_CPUSYS_TOP_MCSIC_DCM0) &
			~MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
		reg_write(MP_CPUSYS_TOP_MCSIC_DCM0,
			(reg_read(MP_CPUSYS_TOP_MCSIC_DCM0) &
			~MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11))

bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) &
		MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11))

bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) &
		MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF ((0x0 << 11))

bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG2) &
		MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG2,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG2) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG2,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG2) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF ((0x0 << 11))

bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG3) &
		MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG3,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG3) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG3,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG3) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON ((0x1 << 11))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF ((0x0 << 11))

bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG4) &
		MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG4,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG4) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
		reg_write(MP_CPUSYS_TOP_CPU_PLLDIV_CFG4,
			(reg_read(MP_CPUSYS_TOP_CPU_PLLDIV_CFG4) &
			~MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK ((0x1 << 4))
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON ((0x1 << 4))
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))

bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
		MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_fcm_stall_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
			~MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG7,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
			~MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0 << 31))

bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
		MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_last_cor_idle_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
		reg_write(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
			(reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
			~MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
		reg_write(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
			(reg_read(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
			~MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK ((0x1 << 1) | \
			(0x1 << 4))
#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON ((0x1 << 1) | \
			(0x1 << 4))
#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
			(0x0 << 4))

bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
		MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);

	return ret;
}

void dcm_mp_cpusys_top_misc_dcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
			~MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
		reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
			~MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) |
			MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
	}
}

#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK ((0x1 << 3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON ((0x1 << 3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
			(0x0 << 1) | \
			(0x0 << 2) | \
			(0x0 << 3))

bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
		MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
	ret &= ((reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
		MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
		(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);

	return ret;
}

void dcm_mp_cpusys_top_mp0_qdcm(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
		reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
			~MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) |
			MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
			~MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) |
			MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
		reg_write(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
			~MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) |
			MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
		reg_write(MP_CPUSYS_TOP_MP0_DCM_CFG0,
			(reg_read(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
			~MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) |
			MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
	}
}

#define CPCCFG_REG_EMI_WFIFO_REG0_MASK ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3))
#define CPCCFG_REG_EMI_WFIFO_REG0_ON ((0x1 << 0) | \
			(0x1 << 1) | \
			(0x1 << 2) | \
			(0x1 << 3))
#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
			(0x0 << 1) | \
			(0x0 << 2) | \
			(0x0 << 3))

bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
{
	bool ret = true;

	ret &= ((reg_read(CPCCFG_REG_EMI_WFIFO) &
		CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
		(unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);

	return ret;
}

void dcm_cpccfg_reg_emi_wfifo(int on)
{
	if (on) {
		/* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
		reg_write(CPCCFG_REG_EMI_WFIFO,
			(reg_read(CPCCFG_REG_EMI_WFIFO) &
			~CPCCFG_REG_EMI_WFIFO_REG0_MASK) |
			CPCCFG_REG_EMI_WFIFO_REG0_ON);
	} else {
		/* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
		reg_write(CPCCFG_REG_EMI_WFIFO,
			(reg_read(CPCCFG_REG_EMI_WFIFO) &
			~CPCCFG_REG_EMI_WFIFO_REG0_MASK) |
			CPCCFG_REG_EMI_WFIFO_REG0_OFF);
	}
}