;*****************************************************************************
;  Copyright Statement:
;  --------------------
;  This software is protected by Copyright and the information contained
;  herein is confidential. The software may not be copied and the information
;  contained herein may not be used or disclosed except with the written
;  permission of MediaTek Inc. (C) 2011
;
;*****************************************************************************
;;================================================
;; PURPOSE:     FPGA Bring Up
;; CREATE_DATE: 2014/11/17
;; NOTE:
;;================================================
; Specify Core Number
;=================================================

;;-> # Option: Serial Wire or Parallel JTAG
;; OPT_JTAG
;; 0: Parallel
;; 1: Serial Wire
&OPT_JTAG=0

;;-> # Option: Number of CPUs to be connected
;; OPT_NR_CPUS
&OPT_NR_CPUS=1

&NR_CPUS=1
; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600

;=================================================
; Initialize CPU
;=================================================
&WDT_TEST=0
if &WDT_TEST==0
(
	RESET
	SYSTEM.OPTION ENRESET ON
)

SYStem.Down
SYSTEM.RESET
SYSTEM.OPTION ENRESET ON
SYSTEM.OPTION RESBREAK OFF
SYSTEM.OPTION WAITRESET OFF
SYSTEM.JTAGCLOCK 10.MHz;

IF &OPT_JTAG==0
(
    SYStem.Config SWDP OFF
)
ELSE IF &OPT_JTAG==1
(
    SYStem.Config SWDP ON
)

SYSTEM.CPU CortexA7MPCore
;SYStem.CPU CORTEXA53;

SYStem.Config CORENUMBER &OPT_NR_CPUS
SYStem.Config COREBASE 0x80070000

;R-T Memory Access
;SYSTEM.MULTICORE MEMORYACCESSPORT 0
;SYSTEM.MULTICORE DEBUGACCESSPORT 1

;=================================================
; Attach and Stop CPU
;=================================================
SYStem.Up
MMU.OFF
D.S C15:0x1 0				; Turn off MMU

wait 200.us

SETUP.IMASKHLL ON
SETUP.IMASKASM ON

; Disable DABORT and PABORT breakpoint
TrOnchip.Set dabort off
TrOnchip.Set pabort off
TrOnchip.Set undef off
TrOnchip.Set irq off


; set_hw_breakpoint_by_def
; setting attribute of breakpoints
Break.Select Program OnChip
Break.Select Hll OnChip
Break.Select Spot OnChip
Break.Select Read OnChip
Break.Select Write OnChip

;
; board init
;
; Disable acinactm
;D.S c:0x1020011C %LE %LONG 0x1
;D.S c:0x1020011C %LE %LONG 0x1

;Disable acinactm
;d.s c:0x1020002c  %le %long 0x8
;d.s c:0x1020022c  %le %long 0x8


; Disable wdt
D.S c:0x10007000 %LE %LONG 0x22000000


;enable L2C 256KB
D.S SD:0x10200000 %LE %LONG 0x00000020 ;Enable L2C share SRAM, cluster 0


; init DRAM by cmm script (FPGA only)
do Rainier_FPGA_DDR.cmm

; board init
print "loading pre-loader image"
d.load.elf ../../bin/preloader.elf
; ABTC change the ouput folder
;d.load.elf ../../../../out/target/product/fpga6580/obj/PRELOADER_OBJ/bin/preloader.elf
;d.load.elf ../../../../out/target/product/fpga6580/obj/PRELOADER_OBJ/bin/preloader.elf /nocode

Y.SPATH.RESET ; reset all source path
Y.SPATH.SRD ../../platform/mt6580/src/init
Y.SPATH.SRD ../../platform/mt6580/src/core
Y.SPATH.SRD ../../platform/mt6580/src/drivers
Y.SPATH.SRD ../../platform/mt6580/src/security
Y.SPATH.SRD ../../custom/fpga6580/
;Y.SPATH.SRD ../../../protect-private/security/ASF/preloader


R.S T 0
;winclear
d.l
enddo