;*****************************************************************************
;  Copyright Statement:
;  --------------------
;  This software is protected by Copyright and the information contained
;  herein is confidential. The software may not be copied and the information
;  contained herein may not be used or disclosed except with the written
;  permission of MediaTek Inc. (C) 2011
;
;*****************************************************************************
;;================================================
;; PURPOSE:     FPGA Bring Up
;; CREATE_DATE: 2014/08/28
;; NOTE:
;;================================================
; Specify Core Number
;=================================================

&NR_CPUS=1
; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600

;=================================================
; Initialize CPU
;=================================================
&WDT_TEST=0
if &WDT_TEST==0
(
	RESET
	SYSTEM.OPTION ENRESET ON
)

SYSTEM.RESET
SYSTEM.OPTION ENRESET ON
SYSTEM.OPTION RESBREAK OFF
SYSTEM.OPTION WAITRESET OFF

SYSTEM.JTAGCLOCK 10.MHz;

;SYSTEM.CPU CortexA7MPCore
SYStem.CPU CORTEXA53;

;R-T Memory Access
SYSTEM.MULTICORE MEMORYACCESSPORT 0
SYSTEM.MULTICORE DEBUGACCESSPORT 1

;SYSTEM.MULTICORE COREBASE APB:0x80070000
;Setting Core debug register access
if &NR_CPUS==1
(
    SYStem.CONFIG CORENUMBER 1;
    SYStem.CONFIG COREBASE 0x80810000;
    SYStem.CONFIG CTIBASE 0x80820000;
)
else
(
    SYSTEM.CONFIG CORENUMBER 2;
    SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
    SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
)

;=================================================
; Attach and Stop CPU
;=================================================
SYStem.Up
wait 200.us

SETUP.IMASKHLL ON
SETUP.IMASKASM ON

;Disable acinactm
;d.s c:0x1020002c  %le %long 0x8
;d.s c:0x1020022c  %le %long 0x8



;D.S SD:0x00000000 %LE %LONG 0xEAFFFFFE
;D.S SD:0x10006000 %LE %LONG 0x0b160001
;D.S SD:0x100062A0 %LE %LONG 0x7C
;D.S SD:0x100062B0 %LE %LONG 0x7C


;enable L2C 256KB
D.S SD:0x10200000 %LE %LONG 0x00000100 ;Enable L2C share SRAM, cluster 0
D.S SD:0x10200000 %LE %LONG 0x00001100 ;Enable L2C share SRAM, cluster 0




; MSDC FPGA DTB: Card power(GPIO3), MSDC Bus 3.3V(GPIO2), MSDC Bus 1.8V(GPIO1) control
; Set GPIO direction
;D.S SD:0x10001E88 %LE %LONG 0xFF00
; Set GPIO output value
;D.S SD:0x10001E84 %LE %LONG 0x5500

; set_hw_breakpoint_by_def
; setting attribute of breakpoints
Break.Select Program OnChip
Break.Select Hll OnChip
Break.Select Spot OnChip
Break.Select Read OnChip
Break.Select Write OnChip

D.S C15:0x1 0				; Turn off MMU

; disable wdt (debug purpose)
D.S SD:0x10212000 %LE %LONG 0x22000000

; board init
print "loading pre-loader image"
d.load.elf ../../bin/preloader.elf
; ABTC change the ouput folder
;d.load.elf ../../../../out/target/product/mt6752_fpga/obj/PRELOADER_OBJ/bin/preloader.elf
;d.load.elf ../../../../out/target/product/mt6752_fpga/obj/PRELOADER_OBJ/bin/preloader.elf /nocode

Y.SPATH.RESET ; reset all source path
Y.SPATH.SRD ../../platform/mt6735/src/init
Y.SPATH.SRD ../../platform/mt6735/src/core
Y.SPATH.SRD ../../platform/mt6735/src/drivers
Y.SPATH.SRD ../../platform/mt6735/src/security
Y.SPATH.SRD ../../custom/fpga6735_64
;Y.SPATH.SRD ../../protect-private/security/ASF/preloader


Break.Select Program OnChip
Break.Select Hll OnChip
Break.Select Spot OnChip
Break.Select Read OnChip
Break.Select Write OnChip

R.S T 0
;winclear
d.l
enddo