link_descriptor.ld 1.3 KB

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  1. OUTPUT_ARCH(arm)
  2. ENTRY(_start)
  3. romBase = 0x00201000;
  4. ramBase = 0x00102180;
  5. pll_init_baseaddr = 0x00100100;
  6. MEMORY {
  7. ram : ORIGIN = ramBase, LENGTH = 0xBA80
  8. rom : ORIGIN = romBase, LENGTH = 0x1F000
  9. }
  10. SECTIONS {
  11. /* rom region */
  12. . = romBase;
  13. __boot_start = .;
  14. .start ALIGN(4) : {
  15. *(.text.start)
  16. }
  17. . = romBase + 0x01FC;
  18. .rom_info ALIGN(4) : {
  19. *(.data.rom_info)
  20. }
  21. .text ALIGN(4) : {
  22. *(.text)
  23. /* *(.text.*) for get .text.mt_pll_init */
  24. }
  25. .rodata ALIGN(4) : {
  26. *(.rodata)
  27. *(.rodata.*)
  28. }
  29. .data ALIGN(4) : {
  30. *(.data)
  31. *(.data.*)
  32. }
  33. .got ALIGN(4) : {
  34. *(.got)
  35. *(.got.*)
  36. }
  37. .pll_text pll_init_baseaddr : AT (ADDR(.got) + SIZEOF(.got))
  38. {
  39. Image$$PLL_INIT$$Base = . ;
  40. *(.text.mt_pll_init)
  41. Image$$PLL_INIT$$Limit = . ;
  42. }
  43. __load_start_pll_text = LOADADDR (.pll_text);
  44. __load_stop_pll_text = LOADADDR (.pll_text) + SIZEOF (.pll_text);
  45. __boot_end = .;
  46. /* ram region */
  47. . = ramBase;
  48. .bss ALIGN(16) : {
  49. _bss_start = .;
  50. *(.bss)
  51. *(.bss.*)
  52. *(COMMON)
  53. /* make _bss_end as 4 bytes alignment */
  54. . = ALIGN(4);
  55. _bss_end = .;
  56. }
  57. .secbuf ALIGN(4) : {
  58. _secbuf_start = .;
  59. *(.secbuf)
  60. _secbuf_end = .;
  61. }
  62. }