link_descriptor_fpga.ld 894 B

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  1. OUTPUT_ARCH(arm)
  2. ENTRY(_start)
  3. romBase = 0x00201000;
  4. ramBase = 0x00102180;
  5. MEMORY {
  6. ram : ORIGIN = ramBase, LENGTH = 0xBA80
  7. rom : ORIGIN = romBase, LENGTH = 0x1F000
  8. }
  9. SECTIONS {
  10. /* rom region */
  11. . = romBase;
  12. .start ALIGN(4) : {
  13. *(.text.start)
  14. }
  15. . = romBase + 0x01FC;
  16. .rom_info ALIGN(4) : {
  17. *(.data.rom_info)
  18. }
  19. .text ALIGN(4) : {
  20. *(.text)
  21. *(.text.*)
  22. }
  23. .rodata ALIGN(4) : {
  24. *(.rodata)
  25. *(.rodata.*)
  26. }
  27. .data ALIGN(4) : {
  28. *(.data)
  29. *(.data.*)
  30. }
  31. .got ALIGN(4) : {
  32. *(.got)
  33. *(.got.*)
  34. }
  35. __boot_end = .;
  36. /* ram region */
  37. . = ramBase;
  38. .bss ALIGN(16) : {
  39. _bss_start = .;
  40. *(.bss)
  41. *(.bss.*)
  42. *(COMMON)
  43. /* make _bss_end as 4 bytes alignment */
  44. . = ALIGN(4);
  45. _bss_end = .;
  46. }
  47. }