link_descriptor_trng.ld 1.8 KB

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  1. OUTPUT_ARCH(arm)
  2. ENTRY(_start)
  3. romBase = 0x00201000;
  4. bss1Base = 0x00100000;
  5. bss2Base = 0x00114C00;
  6. stackBase = 0x0011A400;
  7. /* log_sram_buf + bss1 should be less than 40 KB.*/
  8. MEMORY {
  9. bss1 : ORIGIN = 0x00100000, LENGTH = 0xA000
  10. rom : ORIGIN = 0x00201000, LENGTH = 0x3A000
  11. bss2 : ORIGIN = 0x00114C00, LENGTH = 0x5800
  12. stack : ORIGIN = 0x0011A400, LENGTH = 0xC00
  13. }
  14. SECTIONS {
  15. . = romBase;
  16. .start ALIGN(4) : {
  17. *(.text.start)
  18. } >rom
  19. . = romBase + 0x01FC;
  20. .rom_info ALIGN(4) : {
  21. *(.data.rom_info)
  22. } >rom
  23. .text ALIGN(4) : {
  24. *(.text)
  25. *(.text.*)
  26. } >rom
  27. .rodata ALIGN(4) : {
  28. *(.rodata)
  29. *(.rodata.*)
  30. } >rom
  31. .data ALIGN(4) : {
  32. *(.data)
  33. *(.data.*)
  34. } >rom
  35. .got ALIGN(4) : {
  36. *(.got)
  37. *(.got.*)
  38. } >rom
  39. .secbuf ALIGN(4) : {
  40. _secbuf_start = .;
  41. *(.secbuf)
  42. _secbuf_end = .;
  43. } >rom
  44. __boot_end = .;
  45. . = stackBase;
  46. .stack ALIGN(4) : {
  47. _stack_start = .;
  48. *(.stack)
  49. _stack_end = .;
  50. } >stack
  51. . = bss2Base;
  52. .bss2 ALIGN(16) : {
  53. _bss2_start = .;
  54. *(EXCLUDE_FILE(*circbuf.o *dramc_*.o *usb*.o *pcie.o) .bss)
  55. *(EXCLUDE_FILE(*circbuf.o *dramc_*.o *usb*.o *pcie.o) .bss.*)
  56. *(EXCLUDE_FILE(*circbuf.o *dramc_*.o *usb*.o *pcie.o) COMMON)
  57. /* make _bss2_end as 4 bytes alignment */
  58. . = ALIGN(4);
  59. _bss2_end = .;
  60. } >bss2
  61. . = bss1Base;
  62. .bss1 ALIGN(16) : {
  63. _bss1_start = .;
  64. *print.o (.log_sram_buf)
  65. *(*circbuf.o *dramc_*.o *usb*.o *pcie.o .bss)
  66. *(*circbuf.o *dramc_*.o *usb*.o *pcie.o .bss.*)
  67. *(*circbuf.o *dramc_*.o *usb*.o *pcie.o COMMON)
  68. /* make _bss_end as 4 bytes alignment */
  69. . = ALIGN(4);
  70. _bss1_end = .;
  71. } >bss1
  72. }