link_descriptor_trng.ld 1.8 KB

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  1. OUTPUT_ARCH(arm)
  2. ENTRY(_start)
  3. romBase = 0x00201000;
  4. bss1Base = 0x00100000;
  5. bss2Base = 0x00114C00;
  6. stackBase = 0x0011A400;
  7. /* log_sram_buf + bss1 should be less than 40 KB.*/
  8. MEMORY {
  9. bss1 : ORIGIN = 0x00100000, LENGTH = 0xA000
  10. rom : ORIGIN = 0x00201000, LENGTH = 0x3A000
  11. bss2 : ORIGIN = 0x00114C00, LENGTH = 0x5800
  12. stack : ORIGIN = 0x0011A400, LENGTH = 0xC00
  13. }
  14. SECTIONS {
  15. /* rom region */
  16. . = romBase;
  17. .start ALIGN(4) : {
  18. *(.text.start)
  19. }
  20. . = romBase + 0x01FC;
  21. .rom_info ALIGN(4) : {
  22. *(.data.rom_info)
  23. }
  24. .text ALIGN(4) : {
  25. *(.text)
  26. *(.text.*)
  27. }
  28. .rodata ALIGN(4) : {
  29. *(.rodata)
  30. *(.rodata.*)
  31. }
  32. .data ALIGN(4) : {
  33. *(.data)
  34. *(.data.*)
  35. }
  36. .got ALIGN(4) : {
  37. *(.got)
  38. *(.got.*)
  39. }
  40. .secbuf ALIGN(4) : {
  41. _secbuf_start = .;
  42. *(.secbuf)
  43. _secbuf_end = .;
  44. }
  45. __boot_end = .;
  46. /* stack region */
  47. . = stackBase;
  48. .stack ALIGN(4) : {
  49. _stack_start = .;
  50. *(.stack)
  51. _stack_end = .;
  52. }
  53. /* bss2 region */
  54. . = bss2Base;
  55. .bss2 ALIGN(16) : {
  56. _bss2_start = .;
  57. *(EXCLUDE_FILE(*circbuf.o *dramc_*.o *usb*.o *pcie.o) .bss)
  58. *(EXCLUDE_FILE(*circbuf.o *dramc_*.o *usb*.o *pcie.o) .bss.*)
  59. *(EXCLUDE_FILE(*circbuf.o *dramc_*.o *usb*.o *pcie.o) COMMON)
  60. /* make _bss2_end as 4 bytes alignment */
  61. . = ALIGN(4);
  62. _bss2_end = .;
  63. }
  64. /* bss1 region */
  65. . = bss1Base;
  66. .bss1 ALIGN(16) : {
  67. _bss1_start = .;
  68. *print.o (.log_sram_buf)
  69. *(*circbuf.o *dramc_*.o *usb*.o *pcie.o .bss)
  70. *(*circbuf.o *dramc_*.o *usb*.o *pcie.o .bss.*)
  71. *(*circbuf.o *dramc_*.o *usb*.o *pcie.o COMMON)
  72. /* make _bss_end as 4 bytes alignment */
  73. . = ALIGN(4);
  74. _bss1_end = .;
  75. }
  76. }